Optoelectronic device and method for manufacturing the same

Abstract

A method for manufacturing an optoelectronic device including a mode converter. The method has the following steps: manufacturing the optoelectronic device on a first silicon-on-insulator (SOI) wafer; and either: manufacturing the mode converter on a second SOI wafer; and bonding the mode converter to the first SOI wafer; or bonding the second SOI wafer to the first SOI wafer to form a combined wafer; and etching the mode converter into the combined wafer.

Description

Technical Field

[0001] The present invention relates to an optoelectronic device and a method for manufacturing the same. Background Art

[0002] In optoelectronic devices, there can be significant optical losses when a standard single-mode fiber (with a typical mode size of 10.6 μm at a wavelength of 1.55 μm) is coupled to a silicon waveguide, which can have mode sizes ranging from sub-micron to 3 μm (depending on the silicon-on-insulator (SOI) platform used) due to mode mismatch.

[0003] To minimize coupling losses, 13μm × 13μm silica waveguides have been used because the mode size matches that of standard single-mode optical fibers. A mode converter or taper is used to adiabatically transition the mode from the 13μm × 13μm waveguide to a smaller silica waveguide in the SOI platform. However, current solutions such as dual SOI mode converters have complex manufacturing processes that result in high optical losses and low device yields.

[0004] There is therefore a desire to provide a manufacturing process for mode converters having lower optical losses and with higher device yield. Summary of the invention

[0005] Therefore, in a first aspect, embodiments of the present invention provide a method of manufacturing an optoelectronic device including a mode converter, the method having the following steps:

[0006] Fabrication of optoelectronic devices on the first silicon-on-insulator (SOI) wafer;

[0007] and either:

[0008] On the second SOI wafer, a mode converter is fabricated, and

[0009] bonding the mode converter to the first SOI wafer;

[0010] or

[0011] bonding the second SOI wafer to the first SOI wafer to form a combined wafer;

[0012] and etching a mode converter into the combined wafer.

[0013] Such an approach results in a simpler manufacturing process and thus a higher manufacturing yield. In addition, the devices so manufactured have lower optical losses.

[0014] Optional features of embodiments of the invention will now be described. These may be applicable alone or in any combination with any aspect of the invention.

[0015] Multiple mode converters may be fabricated on the second SOI wafer or the combined wafer.

[0016] In a second aspect, an embodiment of the present invention provides a method of manufacturing an optoelectronic device including a mode converter, the method having the following steps:

[0017] On the first SOI wafer, manufacturing an optoelectronic device;

[0018] On the second SOI wafer, manufacturing a mode converter; and

[0019] The mode converter is bonded to the first SOI wafer.

[0020] Fabricating the mode converter on the second SOI wafer may include the following steps:

[0021] disposing a first photoresist over a portion of the device layer of the second SOI wafer; and

[0022] Exposed regions of the device layer are etched to form a mode converter.

[0023] The mode converter may be formed as a tapered waveguide which decreases in width in a direction parallel to the guiding direction of the waveguide.

[0024] Fabricating the mode converter on the second SOI wafer may include the steps of preparing the second SOI wafer for a microtransfer printing process. Preparing the second SOI wafer for a microtransfer printing process may include the steps of patterning a tether onto the mode converter; and removing an insulator layer between the mode converter and the silicon substrate of the second SOI wafer, thereby suspending the mode converter via the tether.

[0025] The step of manufacturing the mode converter on the second SOI wafer may be performed before or simultaneously with the step of manufacturing the optoelectronic device on the first SOI wafer.

[0026] Bonding the mode converter to the first wafer may be performed via a micro transfer printing process. The micro transfer printing process may include a plasma treatment step and an annealing step to bond the mode converter to the bonding area of ​​the first wafer.

[0027] Fabricating an optoelectronic device may include the following steps: fabricating an input waveguide and / or an output waveguide on a first SOI wafer.

[0028] The optoelectronic device may be an electro-optic modulator, a laser, or a detector, and fabricating the optoelectronic device may include the steps of etching a device cavity into a device layer of a first SOI wafer; and growing an optically active region in the device cavity. Fabricating the optoelectronic device may also include the steps of etching the grown optically active region in the device cavity to form an optically active waveguide. The optoelectronic device may be an electro-optic modulator or a detector, and fabricating the optoelectronic device may also include doping two or more regions of the optically active waveguide; and placing electrodes in electrical contact with respective doped regions of the optically active waveguide. The optoelectronic device may be referred to as a photonic integrated circuit (PIC).

[0029] Fabricating the optoelectronic device further includes the following step, performed before bonding the second wafer to the first wafer: disposing a cover layer over the optoelectronic device to expose one or more bonding regions for bonding the first wafer to the second wafer.

[0030] The method may further comprise the steps of manufacturing an additional mode converter on a second SOI wafer or on another SOI wafer and bonding the additional mode converter to the first SOI wafer.

[0031] In a third aspect, an embodiment of the present invention provides a method of manufacturing an optoelectronic device including a mode converter, the method having the following steps:

[0032] On the first SOI wafer, manufacturing an optoelectronic device;

[0033] bonding the second SOI wafer to the first SOI wafer to form a combined wafer; and

[0034] The mode converter is etched into the combined wafer.

[0035] Fabricating an optoelectronic device may include the following steps: fabricating an input waveguide and / or an output waveguide on a first SOI wafer.

[0036] The optoelectronic device may be an electro-optic modulator, a laser, a detector, an arrayed waveguide grating, an echelle grating, a Mach-Zehnder interferometer, a ring resonator, or any combination thereof.

[0037] The optoelectronic device may be an electro-optic modulator, a laser, or a detector, and fabricating the optoelectronic device may include the steps of etching a device cavity into a device layer of a first SOI wafer; and growing an optically active region in the device cavity. Fabricating the optoelectronic device may also include the steps of etching the grown optically active region in the device cavity to form an optically active waveguide. The optoelectronic device may be an electro-optic modulator, or a detector, and fabricating the optoelectronic device may include the steps of doping two or more regions of the optically active waveguide; and placing electrodes in electrical contact with respective doped regions of the optically active waveguide.

[0038] Fabricating the optoelectronic device may include the following steps performed prior to bonding the second wafer to the first wafer: disposing a capping layer over the optoelectronic device to expose one or more bonding regions for bonding the first wafer to the second wafer.

[0039] Before bonding the second SOI wafer to the first SOI wafer, the method may include etching a second cavity into a device layer of the second SOI wafer. Bonding the second SOI wafer to the first SOI wafer may include inverting the second SOI wafer and placing it on an upper surface of the first SOI wafer.

[0040] In another step, the silicon substrate of the second SOI wafer may be removed after the second SOI wafer is bonded to the first SOI wafer.

[0041] In another step, the buried oxide layer of the second SOI wafer may be removed after the second SOI wafer is bonded to the first SOI wafer.

[0042] The second SOI wafer may be bonded to the first SOI wafer via a wafer bonding process. The wafer bonding process may be a plasma assisted wafer bonding process. The wafer bonding process may include a step of annealing the first SOI wafer and the second SOI wafer. The annealing may be performed at a temperature of at least 250°C.

[0043] The method may include the step of etching a plurality of mode converters into the combined wafer.

[0044] In a fourth aspect, embodiments of the present invention provide an optoelectronic device comprising a mode converter manufactured according to the method of any preceding aspect.

[0045] Other aspects of the present invention provide: a computer program comprising code that, when run on a computer, causes the computer to perform the method of the first, second, or third aspect; a computer-readable medium storing the computer program, the computer program comprising code that, when run on a computer, causes the computer to perform the method of the first, second, or third aspect; and a computer system programmed to perform the method of the first, second, or third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0047] Figure 1A and 1B shows a top view and a cross-sectional view of an optoelectronic device including a mode converter;

[0048] Figure 2A and 2BA top view and a cross-sectional view of a variant optoelectronic device including a mode converter are shown;

[0049] Figure 3A and 3B A top view and a cross-sectional view of a variant optoelectronic device including a mode converter are shown;

[0050] Figure 4A and 4B A top view and a cross-sectional view of a variant optoelectronic device including a mode converter are shown;

[0051] Figures 5(i)–5(xvi)(B) show the Figure 1A and 1B Various stages of manufacturing optoelectronic devices for mode converters;

[0052] Figures 6(i)–6(viii)(B) show various fabrication stages for preparing optoelectronic devices for integration with mode converters;

[0053] 7(i)–7(v)(B) illustrate various fabrication stages in preparing a mode converter for integration with an optoelectronic device; and

[0054] Figures 8(i)(A)–8(ii)(B) show the integration process of the mode converter and optoelectronic devices. DETAILED DESCRIPTION

[0055] Aspects and embodiments of the present invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art.

[0056] Figure 1A and 1B A top view and a cross-sectional view of a photonic device 100 are shown, respectively. In general, the device 100 includes a 13 μm to 3 μm tapered waveguide 101a, which acts as a mode converter for light entering the device (on the left-hand edge). The light is converted from an optical mode of an input fiber (not shown) to a 3 μm optical mode supported by a 3 μm waveguide 102b. The light then enters an optoelectronic device 103 that includes a 3 μm waveguide.

[0057] The process is then reversed and as the light leaves the optoelectronic device 103, it is coupled into the 3μm tapered waveguide 102b, which is coupled into the 3μm to 13μm tapered waveguide 101b. The light is converted from the 3μm mode to the 13μm mode and then transmitted onward via the output fiber (not shown).

[0058] Figure 1B is along Figure 1A1-1 is a cross-sectional view taken along line A-A' of FIG. 1. This view shows the structure of the photonic device 100 in more detail. As can be seen, the tapered waveguides 101a and 10b are located atop a 3μm silicon slab 104. The slab is bounded on the underside (the distal end of the tapered waveguides) by a buried oxide layer 106. In this example, the buried oxide layer is formed of silicon dioxide and serves as a lower cladding for the 3μm silicon waveguides 102a and 102b. On the side of the buried oxide layer 106 opposite the waveguides is a silicon substrate 107.

[0059] As previously described, the optoelectronic device 103 may be: an electro-absorption modulator; a laser; a detector; an arrayed waveguide grating; an echelle grating; a Mach-Zehnder interferometer, a ring resonator, or any combination thereof. The optoelectronic device in this example is an electro-absorption modulator. In the example where the component is a laser, there may be only one output fiber, i.e., only waveguides 102b and 101b connected to the output fiber. Similarly, in the example where the component is a detector, there may be only one input fiber, i.e., only waveguides 101a and 102a.

[0060] Figure 2A and 2B A top view and a cross-sectional view of a variant photonic device 200 are shown. Figure 1A and 1B Where features are shared by the devices shown in FIG. , the same features are indicated by the same reference numerals. Figure 1A and 1B In contrast to the device 100 shown in FIG. 2 , light passing through the device 200 undergoes a two-stage mode conversion process.

[0061] As previously described, light enters the device 200 into the left hand side of the 13μm to 3μm tapered waveguide 101a. The light undergoes mode conversion and is provided into the 3μm to 1μm tapered waveguide 201a. In a second mode conversion step, the light is then converted to a mode supported by the 1μm waveguide 202a, which is optically connected to the 1μm based optoelectronic device 204. As previously described, the order is then reversed, with light coupled from the optoelectronic device 204 to the 1μm waveguide 202b, before first coupling to the 1μm to 3μm tapered waveguide 201b and then coupling to the 3μm to 13μm tapered waveguide 101b.

[0062] Figure 3A and 3B A top view and a cross-sectional view of a variant photonic device 300 are shown. Figure 1A and 1B Where features are shared by the devices shown in FIG. , the same features are indicated by the same reference numerals. Figure 1A and 1BIn contrast to the device 100 shown in FIG. 3 , light passing through the device 300 undergoes a two-stage mode conversion process.

[0063] As previously described, light enters the left hand side of the device 300 into the 13μm to 3μm tapered waveguide 101a. The light undergoes mode conversion and is provided into the 3μm to 800nm ​​tapered waveguide 301a. In a second mode conversion step, the light is then converted to a mode supported by the 800nm ​​waveguide 302a, which is optically connected to the 800nm ​​based optoelectronic device 304. As previously described, the order is then reversed, with light coupled from the optoelectronic device 304 to the 800nm ​​waveguide 302b, before first coupling to the 800nm ​​to 3μm tapered waveguide 201b and then coupling to the 3μm to 13μm tapered waveguide 101b.

[0064] Figure 4A and 4B A top view and a cross-sectional view of a variant photonic device 400 are shown. Figure 1A and 1B Where features are shared by the devices shown in FIG. , the same features are indicated by the same reference numerals. Figure 1A and 1B Compared to the device 400 shown in FIG. 3 , light passing through the device 300 undergoes a three-stage mode conversion process.

[0065] As previously described, light enters the device 400 into the left hand side of the 13μm to 3μm tapered waveguide 101a. The light undergoes mode conversion and is provided into the 3μm to 1.5μm tapered waveguide 402a. In a second mode conversion step, the light is provided to the 1.5μm to 220nm tapered waveguide 403a. In a third mode conversion step, the light is then converted to a mode supported by the 220nm waveguide 204a, which is optically connected to the 220nm based optoelectronic device 405. As previously described, the order is then reversed, with light coupled from the optoelectronic device 405 to the 220nm waveguide 404b, prior to being coupled to the 220nm to 1.5μm tapered waveguide 403b. Next, the light is coupled to the 1.5μm to 3μm tapered waveguide 402b, prior to being provided to the 3μm to 13μm tapered waveguide 101b.

[0066] Figures 5(i)–5(xvi)(B) show Figure 1A and 1B 5 (i) , a silicon-on-insulator wafer is provided. The wafer includes a silicon device layer 501, a buried oxide layer 106, and a silicon substrate 107. In this example, the silicon device layer is about 3 μm high, as measured from the uppermost surface of the buried oxide layer to the uppermost surface of the silicon device layer.

[0067] Next, in the step shown in FIG5(ii), a hard mask 502 is provided over a portion of the upper surface of the device layer, and a cavity 503 is etched through the silicon device layer 501 and also through the buried oxide layer 106. This etching may be performed in two steps, a first step using the buried oxide layer as an etch stop, and a second step using the silicon substrate as an etch stop. After this etching, a silicon cladding 505 is epitaxially grown from the silicon substrate, and a silicon germanium stack 504 is epitaxially grown on top of the silicon cladding. This is shown in FIG5(iii). The silicon cladding has a composition such that it serves as a bottom cladding of a waveguide subsequently formed by the silicon germanium stack 504. For example, the silicon cladding may have a composition such that the refractive index of the cladding is lower than the refractive index of the silicon germanium stack.

[0068] After providing the silicon germanium stack 504, it is planarized relative to the surrounding surface via a chemical mechanical planarization process. The result is shown in FIG5(iv). Next, the silicon device layer and a portion of the silicon germanium stack are etched to provide silicon ridge waveguides 102a and 102b at either end of the silicon germanium ridge waveguide 506 and couple them into the silicon germanium ridge waveguide 506. This is shown in FIGS5(v)(A) and 5(v)(B), where FIG5(v)(A) is a cross-section taken along line AA' in FIG5(B). As can be seen in FIGS5(v)(A) and 5(v)(B), the silicon germanium plate 507 is retained.

[0069] The etching is performed so as to provide a space x from the sidewalls of the cavity to the start of the tapered region to the 3 μm waveguide. This allows the bonding step discussed in detail below to be more flexible in terms of alignment. Part of the upper surface of the device is covered by a silicon dioxide cap 508 .

[0070] Subsequently, in a step whose results are shown in Figures 5(vi)(A) ​​and 5(vi)(B), doped regions are added to the silicon germanium ridge waveguide 506 and the plate 507. Figure 5(vi)(A) ​​is a cross-section taken along line AA' of Figure 5(vi)(B). As can be seen, the sidewalls of the silicon germanium ridge waveguide 506 are doped. On one side, a dopant of the p-type variety is used to provide a p-doped region 509 extending downward along the sidewall. On the other side, a dopant of the n-type variety is used to provide an n-doped region 511 extending downward along the sidewall. A vertical pin junction is thereby provided. A portion of the plate is heavily doped with a dopant of the p-type variety to provide a p+ doped region 510 in the plate. Similarly, a portion of the plate is heavily doped with a dopant of the n-type variety to provide an n+ doped region 513 in the plate.

[0071] Thereafter, a silicon dioxide layer 515 is provided on the exposed surface of the device, and vias are opened above the p+ doped region 510 and the n+ doped region 512. A metallization step is performed to provide a p-electrode 513 and an n-electrode 514 electrically connected to the p+ doped region 510 and the n+ doped region 512, respectively. The result is shown in Figures 5(vii)(A) ​​and (B), Figure 5(vii)(A) ​​being a cross-section along line A-A' of Figure 5(vii)(B). Next, in the steps shown in Figures 5(viii)(A) ​​and 5(viii)(B), a silicon nitride layer 516 is provided to cover the electrodes 513 and 514. As shown in Figure 5(viii)(B), a bonding region 517 located at the lateral end of the device is exposed. As previously described, Figure 5(viii)(A) ​​is a cross-sectional view along line A-A' in Figure 5(viii)(B).

[0072] Next, in the step shown in FIG. 5(ix)(A), a second SOI wafer is prepared. The second SOI wafer in this example has a 10 μm device layer 518 located above a buried oxide layer 519 supported by a substrate 520. A cavity 521 is etched, the cavity corresponding in position and size to the previously etched cavity 503. As previously described, FIG. 5(ix)(A) is a cross section along the line AA' shown in FIG. 5(ix)(B).

[0073] Subsequently, the second SOI wafer is bonded to the bonding area 517 of the first SOI wafer. The second SOI wafer is inverted and the 10 μm device layer 518 is placed in contact with the bonding area 517 of the first SOI wafer. A plasma assisted bonding process is used with an annealing temperature of at least 300°C. The result is shown in FIG5(x), where the 10 μm device layer 517 is bonded to the silicon device layer 501 of the first SOI wafer. The distance x between the sidewalls of the silicon nitride 516 and the 10 μm device layer 518 can be 1 mm or up to about 1 cm to facilitate bonding alignment.

[0074] After the wafer bonding step, the silicon substrate 520 is removed by a chemical mechanical planarization process or dry etching. The result is shown in Figure 5 (xi). Subsequently, in a step, the result of which is shown in Figure 5 (xii), the buried oxide layer 519 is removed by a chemical mechanical planarization process or wet etching. This then allows a hard mask 522 to be provided over a portion of the upper surface of the structure for the etching step used to produce the 13μm to 3μm tapered waveguide. Figure 5 (xiii) shows a cross section through the previously discussed line A-A' after the hard mask 522 has been provided.

[0075] The hard mask 522 is then patterned and a 13 μm to 3 μm tapered waveguide is etched. This is shown in Figures 5(xiv)(A) and 5(xiv)(B), where 5(xiv)(A) is a cross-section along line A-A' in 5(xiv)(B). The hard mask and silicon nitride layer 516 are then removed, after which a silicon dioxide top cladding 523 is deposited over at least the upper surface of the waveguide. This is shown in Figure 5(xv)(A), which is a cross-section along line A-A' of Figure 5(xv)(B). Note that the top cladding is omitted in Figure 5(xv)(B) for clarity. Next, in the step shown in Figure (xvi)(A), the silicon dioxide top cladding 523 over the p-electrode 513 and n-electrode 514 is removed to allow electrical contacts to be connected to the respective electrodes.

[0076] FIG6(i)-6(viii)(B) shows various manufacturing stages of preparing an optoelectronic device for integration with a mode converter. It corresponds to the steps shown in FIG5(i) to FIG5(vii) above. In the first step shown in FIG6(i), a silicon-on-insulator (SOI) wafer is provided. The SOI wafer includes a silicon device layer 501 located above a buried oxide layer 106. The buried oxide layer is between the silicon device layer 501 and the silicon substrate 107.

[0077] Next, in a step shown in FIG6(ii), a hard mask 502 is provided over a portion of the upper surface and a cavity 503 is etched through the silicon device layer and also through the buried oxide layer. This etching may be performed in two steps, a first step using the buried oxide layer as an etch stop, and a second step using the silicon substrate as an etch stop. After this etching, a silicon cladding 505 is grown from the silicon substrate, and a silicon germanium stack 504 is epitaxially grown on top of the silicon cladding. This is shown in FIG6(iii). The silicon cladding has a composition such that it serves as a bottom cladding of a waveguide subsequently formed by the silicon germanium stack 504. For example, the silicon cladding may have a composition such that the refractive index of the cladding is lower than the refractive index of the silicon germanium stack.

[0078] After providing the silicon germanium stack 504, it is planarized relative to the surrounding surface via a chemical mechanical planarization process. The result is shown in FIG6 (iv). Next, the silicon device layer and a portion of the silicon germanium stack are etched to provide silicon ridge waveguides 102a and 102b at either end of the silicon germanium ridge waveguide 506 and couple them into the silicon germanium ridge waveguide 506. This is shown in FIGS6 (v) (A) and 6 (v) (B), where FIG6 (v) (A) is a cross-section taken along line AA' in FIG6 (B). As can be seen in FIGS6 (v) (A) and 6 (v) (B), the silicon germanium plate 507 is retained.

[0079] The etching is performed so as to provide a space x from the sidewalls of the cavity to the start of the tapered region to the 3 μm waveguide. This allows the bonding step discussed in detail below to be more flexible in terms of alignment. Part of the upper surface of the device is covered by a silicon dioxide cap 508 .

[0080] Subsequently, in a step whose results are shown in Figures 6(vi)(A) ​​and 6(vi)(B), doped regions are added to the silicon germanium ridge waveguide 506 and the plate 507. Figure 6(vi)(A) ​​is a cross-section taken along line AA' of Figure 6(vi)(B). As can be seen, the sidewalls of the silicon germanium ridge waveguide 506 are doped. On one side, a dopant of the p-type variety is used to provide a p-doped region 509 extending downward along the sidewall. On the other side, a dopant of the n-type variety is used to provide an n-doped region 511 extending downward along the sidewall. A vertical pin junction is thereby provided. A portion of the plate is heavily doped with a dopant of the p-type variety to provide a p+ doped region 510 in the plate. Similarly, a portion of the plate is heavily doped with a dopant of the n-type variety to provide an n+ doped region 513 in the plate.

[0081] Thereafter, a silicon dioxide layer 515 is provided over the exposed surface of the device and vias are opened over the p+ doped region 510 and the n+ doped region 512. A metallization step is performed to provide a p-electrode 513 and an n-electrode 514 electrically connected to the p+ doped region 510 and the n+ doped region 512, respectively. The result is shown in Figures 6(vii)(A) ​​and (B), Figure 6(vii)(A) ​​being a cross-section of Figure 6(vii)(B) along line A-A'. After the electrodes have been provided, the bonding regions 517 at either end of the device are opened, as shown in Figure 6(viii)(B). The structure is then ready for integration with the mode converter fabricated with reference to Figures 7(i)-7(v)(B).

[0082] Figures 7(i)-7(v)(B) show various manufacturing stages for preparing a mode converter for integration with an optoelectronic device. In the first step shown in Figure 7(i), an SOI wafer is provided, which includes: a 10μm silicon device layer 701, a buried oxide layer 702, and a silicon substrate 703. Next, in the steps shown in Figure 7(ii)(A) ​​(cross-sectional view) and Figure 7(ii)(B) (top view), a silicon dioxide hard mask 704 is provided, and a photoresist 705 is provided on top of the hard mask 704 and patterned. The photoresist 705 has a triangular geometry to define a waveguide that tapers from a first width to a second width.

[0083] Etching is then performed, producing the structure shown in Figures 7(iii)(A) ​​and 7(iii)(B), where Figure 7(iii)(A) ​​is a cross-sectional view through the structure of Figure 7(iii)(B). The tapered waveguide 706 produced by the etching is shown. The photoresist has been removed. Further etching is performed to remove the hard mask and also the exposed areas of the buried oxide layer 702, i.e., those portions of the buried oxide layer that are not sandwiched between the waveguide 706 and the substrate 703. The results of this subsequent etching are shown in Figures 7(iv)(A) and 7(iv)(B), where Figure 7(iv) is a cross-sectional view through the structure of 7(iv)(B).

[0084] Next, photoresist tethers 707 are provided on the lateral sides and upper surface of the waveguide 706. This facilitates further etching, which removes the remaining buried oxide layer and leaves the waveguide 706 tethered to the silicon substrate 703 with only the photoresist tethers 707. The waveguide 706 can then be printed via a microtransfer printing process (e.g., by attaching to an elastomeric stamp).

[0085] Figures 8(i)(A)-8(ii)(B) show the integration process of the mode converter with the optoelectronic device. The waveguide 706 is printed via a microtransfer printing process to the bonding region 517 of the structure shown in Figure 6(viii)(B). Subsequently, in the steps shown in Figures 8(ii)(A) ​​and 8(ii)(B), a silicon dioxide top cladding layer 515 is disposed over the upper surface of the structure, and openings are formed in the cladding of the p-electrode 513 and the n-electrode 514.

[0086] The above steps, in particular the fabrication of the mode converter and the bonding to a separate structure, may be repeated to provide multiple mode conversion steps, such as Figures 2A-4B 5(ix)(A)-5(xii) , the inverted SOI wafer may be bonded to the structure and multiple etching steps may be performed to provide multiple mode converters. Each mode converter after the first is bonded to the previously bonded mode converter. Further alternatively, a single plate or mode converter may be bonded to the structure and multiple etching steps may be performed to provide multiple mode converters.

[0087] Although the present invention has been described in conjunction with the above exemplary embodiments, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the present invention set forth above are considered to be illustrative, rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0088] Features

[0089] 100 Photonic Devices

[0090] 101 13μm to 3μm tapered waveguide

[0091] 102 3μm waveguide

[0092] 103 Optoelectronic devices

[0093] 104 3μm silicon plate

[0094] 105 3μm waveguide silicon slab

[0095] 106 Buried Oxide

[0096] 107 Silicon substrate

[0097] 200 Photonic Devices

[0098] 201 3μm to 1μm tapered waveguide

[0099] 202 1μm waveguide

[0100] 203 1μm waveguide silicon slab

[0101] 204 Optoelectronic devices

[0102] 205 1μm silicon plate

[0103] 300 Photonic Devices

[0104] 301 3μm to 800nm ​​tapered waveguide

[0105] 302 800nm ​​waveguide

[0106] 302 800nm ​​waveguide silicon slab

[0107] 304 Optoelectronic Devices

[0108] 305 800nm ​​silicon board

[0109] 400 Photonic Devices

[0110] 402 3μm to 1.5μm tapered waveguide

[0111] 403 1.5μm-0.22μm tapered waveguide

[0112] 404 0.22μm tapered waveguide

[0113] 405 Optoelectronic Devices

[0114] 406 0.22μm tapered waveguide silicon slab

[0115] 407 0.22μm silicon plate

[0116] 501 Silicon device layer

[0117] 502 Hard Mask

[0118] 503 cavity

[0119] 504 Epitaxially grown silicon germanium

[0120] 505 Epitaxially grown silicon cladding

[0121] 506 SiGe Ridge Waveguide

[0122] 507 Silicon Germanium Plate

[0123] 508 Silica Cover

[0124] 509 P doped sidewall

[0125] 510 P+ doped plate

[0126] 511 N-doped sidewall

[0127] 512 N+ doped plate

[0128] 513 P electrode

[0129] 514 N electrode

[0130] 515 Silicon dioxide layer

[0131] 516 Silicon Nitride Layer

[0132] 517 Junction area

[0133] 518 10μm Silicon-on-Insulator

[0134] 519 buried oxide layer

[0135] 520 Silicon substrate

[0136] 521 cavity

[0137] 522 Hard Mask

[0138] 523 Silica cladding

[0139] 701 10μm silicon device layer

[0140] 702 buried oxide layer

[0141] 703 Silicon substrate

[0142] 704 Silicon Dioxide Hard Mask

[0143] 705 Photoresist

[0144] 706 Tapered Waveguide

[0145] 707 Photoresist Tether

Claims

1. A method of manufacturing an optoelectronic device comprising a mode converter, the mode converter comprising a tapered waveguide, the method comprising the following steps: Manufacturing the optoelectronic device on a first SOI wafer; On a second SOI wafer, manufacturing the mode converter; bonding the mode converter to the first SOI wafer; as well as manufacturing an additional mode converter on the second SOI wafer or on another SOI wafer and bonding the additional mode converter to the first SOI wafer; in, The first SOI wafer includes a first silicon substrate, a first buried oxide layer on the first silicon substrate, and a first silicon device layer on the first buried oxide layer; The manufacturing of the optoelectronic device comprises the following steps: etching a device cavity into the first silicon device layer; growing an optically active region in the device cavity, and fabricating a first waveguide in the first silicon device layer, the first waveguide being optically coupled to the optoelectronic device; The second SOI wafer includes a second silicon substrate, a second buried oxide layer on the second silicon substrate, and a second silicon device layer on the second buried oxide layer; Wherein, manufacturing the mode converter on the second SOI wafer comprises the steps of preparing the second SOI wafer for a micro transfer printing process; Wherein, preparing the second SOI wafer for the micro-transfer printing process comprises the following steps: etching the second silicon device layer to form the tapered waveguide; Etching and removing the portion of the second buried oxide layer that is not between the tapered waveguide and the second silicon substrate; patterning a tether onto the mode converter; and removing a second buried oxide layer between the tapered waveguide and the second silicon substrate, thereby suspending the tapered waveguide via the tether; The step of bonding the mode converter to the first SOI wafer comprises the following steps: micro-transfer printing the tapered waveguide onto the first silicon device layer such that the tapered waveguide is optically coupled to the first waveguide, and Therein, the tapered waveguide decreases in width in a direction parallel to the guiding direction of the tapered waveguide in a plan view.

2. The method according to claim 1, wherein manufacturing the mode converter on the second SOI wafer comprises the following steps: disposing a first photoresist over a portion of the second silicon device layer of the second SOI wafer; as well as Exposed regions of the second silicon device layer are etched to form the tapered waveguide. 3 . The method according to claim 1 , wherein the step of manufacturing the mode converter on the second SOI wafer is performed before or simultaneously with the step of manufacturing the optoelectronic device on the first SOI wafer.

4. The method of claim 1, wherein the micro transfer printing process comprises a plasma treatment step and an annealing step to bond the tapered waveguide to a bonding area of ​​the first wafer.

5. The method according to claim 1, wherein manufacturing the optoelectronic device comprises one or more of the following steps: An input waveguide and / or an output waveguide are fabricated on the first SOI wafer.

6. The method of claim 1, wherein the optoelectronic device comprises one or more of the following: an electro-optic modulator, a laser, a detector, an arrayed waveguide grating, an echelle grating, a Mach-Zehnder interferometer, a ring resonator.

7. The method of claim 1, wherein the optoelectronic device is an electro-optic modulator, a laser, or a detector.

8. The method according to claim 7, wherein manufacturing the optoelectronic device further comprises the following steps: A grown optically active region is etched in the device cavity to form an optically active waveguide.

9. The method of claim 8, wherein the optoelectronic device is an electro-optic modulator or detector, and manufacturing the optoelectronic device further comprises: doping two or more regions in the optically active waveguide; as well as Electrodes are disposed in electrical contact with respective doped regions of the optically active waveguide.

10. The method according to claim 1, wherein manufacturing the optoelectronic device further comprises the following steps, which are performed before bonding the second wafer to the first wafer: A capping layer is disposed over the optoelectronic device, thereby exposing one or more bonding areas for bonding the first wafer to the second wafer.

11. A method of manufacturing an optoelectronic device comprising a first mode converter, the mode converter comprising a tapered waveguide, the method comprising the following steps: On the first SOI wafer, manufacturing an optoelectronic device; bonding a second SOI wafer to the first SOI wafer to form a combined wafer; and etching a plurality of mode converters, including the first mode converter, into the combined wafer; in, The first SOI wafer includes a first silicon substrate, a first buried oxide layer on the first silicon substrate, and a first silicon device layer on the first buried oxide layer; The manufacturing of the optoelectronic device comprises the following steps: etching a first device cavity into the first silicon device layer; growing an optically active region in the first device cavity, and fabricating a first waveguide in the first silicon device layer, the first waveguide being optically coupled to the optoelectronic device; The second SOI wafer includes a second silicon substrate, a second buried oxide layer on the second silicon substrate, and a second silicon device layer on the second buried oxide layer; wherein, before the second SOI wafer is bonded to the first SOI wafer, the second SOI wafer is etched to form a second device cavity in the second silicon device layer, which corresponds to the first device cavity in position and size; Wherein, bonding the second SOI wafer to the first SOI wafer comprises the following steps: placing the second silicon device layer in contact with the first silicon device layer; wherein, after the second SOI wafer is bonded to the first SOI wafer, the second silicon substrate is removed, the second buried oxide layer is removed, and the second silicon device layer is etched to form the tapered waveguide, so that the tapered waveguide is optically coupled to the first waveguide; and Therein, the tapered waveguide decreases in width in a direction parallel to the guiding direction of the tapered waveguide in a plan view.

12. The method according to claim 11, wherein manufacturing the optoelectronic device comprises one or more of the following steps: An input waveguide and / or an output waveguide are fabricated on the first SOI wafer.

13. The method of claim 11, wherein the optoelectronic device comprises one or more of the following: an electro-optic modulator, a laser, a detector, an arrayed waveguide grating, an echelle grating, a Mach-Zehnder interferometer, a ring resonator.

14. The method of claim 11, wherein the optoelectronic device is an electro-optic modulator, a laser, or a detector.

15. The method according to claim 14, wherein manufacturing the optoelectronic device further comprises the following steps: A grown optically active region is etched in the first device cavity to form an optically active waveguide.

16. The method of claim 15, wherein the optoelectronic device is an electro-optical modulator or a detector, and manufacturing the optoelectronic device further comprises: doping two or more regions in the optically active waveguide; as well as Electrodes are disposed in electrical contact with respective doped regions of the optically active waveguide.

17. The method according to claim 11, wherein manufacturing the optoelectronic device further comprises the following steps, which are performed before bonding the second wafer to the first wafer: A capping layer is disposed over the optoelectronic device, thereby exposing one or more bonding areas for bonding the first wafer to the second wafer.

18. The method of claim 11, wherein bonding the second SOI wafer to the first SOI wafer comprises the following steps: The second SOI wafer is turned upside down and disposed on an upper surface of the first SOI wafer.

19. The method of claim 11, wherein bonding the second SOI wafer to the first SOI wafer is performed via a wafer bonding process.

20. The method of claim 19, wherein the wafer bonding process includes the step of annealing the first SOI wafer and the second SOI wafer.

21. An optoelectronic device comprising a mode converter manufactured according to the method of any preceding claim.

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