Vertical electron fuse element and method of making the same

Abstract

The present disclosure provides a vertical electronic fuse element and a method for manufacturing the vertical electronic fuse element. The vertical electronic fuse element has a fuse chain disposed on a semiconductor substrate. The material of the fuse chain and the material of the semiconductor substrate are the same. The vertical electronic fuse element also has a first lower anode / cathode region and a second lower anode / cathode region disposed on the semiconductor substrate. A lower portion of the fuse chain is sandwiched between the first lower anode / cathode region and the second lower anode / cathode region. The vertical electronic fuse element further has an upper anode / cathode region disposed on the fuse chain.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 16 / 922,628, filed July 7, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to an electronic fuse (e-fuse) element and a method of fabricating the same. In particular, the present disclosure relates to a vertical e-fuse element and a method of fabricating the same. BACKGROUND

[0003] Integrated circuit (IC) elements are typically fabricated with all the electronic interconnect components during the fabrication process. However, due to the high development cost, long fabrication time, and high cost of fabrication tools for forming such IC elements, users often require that the circuit can be configured or programmed in the field. Such a circuit is called programmable circuit, and it usually includes programmable links. The programmable links are electronic interconnects that are broken or created at selected electronic nodes by the user after the IC element has been fabricated and packaged for activating or deactivating the selected electronic nodes.

[0004] One of the programmable links is an electronic fuse (e-fuse) element. The e-fuse element is used in semiconductor integrated circuits for various applications, such as memory array redundancy, post-fabrication programming of circuits, and package identification coding. However, the fabrication of the e-fuse element using existing complementary metal-oxide-semiconductor (CMOS) technology requires multiple deposition and masking steps, which are expensive and time-consuming. Therefore, it is desirable to reduce the complexity of the processing steps involved in fabricating the integrated e-fuse element to reduce the cost and time of fabricating IC elements with e-fuses. Furthermore, it is desirable to minimize the footprint area occupied by the e-fuse element.

[0005] The above description of the background of the prior art is provided merely for better understanding of the present disclosure and should not be taken as an acknowledgement that the above description of the prior art is a correct and full description of the prior art relevant to the present disclosure. Furthermore, no admission is made that any of the above description of the prior art is part of the prior art relevant to the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a vertical electronic fuse element. The vertical electronic fuse element has a fuse link disposed on a semiconductor base. The material of the fuse link and the material of the semiconductor base are the same. The vertical electronic fuse element also has a first lower anode / cathode region and a second lower anode / cathode region disposed on the semiconductor base. A lower portion of the fuse link is sandwiched between the first lower anode / cathode region and the second lower anode / cathode region. The vertical electronic fuse element also has an upper anode / cathode region disposed on the fuse link.

[0007] In one embodiment, the upper anode / cathode region has a faceted portion. In one embodiment, the fuse link is doped with an n-type dopant. In one embodiment, the fuse link and the upper anode / cathode region are ring-shaped as viewed from a top view. In one embodiment, the vertical electronic fuse element further includes a suicide layer disposed on the first lower anode / cathode region, and a lower gap sub-layer disposed on the suicide layer, wherein the suicide layer and the fuse link are disposed apart by the lower gap sub-layer.

[0008] In one embodiment, the vertical electronic fuse element further includes a first fuse dielectric layer disposed on the first lower anode / cathode region, and a second fuse dielectric layer disposed on the second lower anode / cathode region, wherein the first lower anode / cathode region and the first fuse dielectric layer directly contact a first sidewall of the fuse link, and the second lower anode / cathode region and the second fuse dielectric layer directly contact a second sidewall of the fuse link. In one embodiment, the vertical electronic fuse element further includes a first conductive layer disposed on the first fuse dielectric layer, wherein the first conductive layer and the fuse link are disposed apart by the first fuse dielectric layer, and a second conductive layer disposed on the second fuse dielectric layer, wherein the second conductive layer and the fuse link are disposed apart by the second fuse dielectric layer.

[0009] Another embodiment of the present disclosure provides a vertical electronic fuse element. The vertical electronic fuse element has a ring-shaped fuse link disposed on a semiconductor base. The material of the ring-shaped fuse link and the material of the semiconductor base are the same. The vertical electronic fuse element also has a first lower anode / cathode region surrounded by a lower portion of the ring-shaped fuse link, and a second lower anode / cathode region disposed around the lower portion of the ring-shaped fuse link. The vertical electronic fuse element also has an upper anode / cathode region disposed on the ring-shaped fuse link.

[0010] In one embodiment, the upper anode / cathode region is annular, and the upper anode / cathode region directly contacts an upper surface of the annular fuse link. In one embodiment, the first lower anode / cathode region abuts an inner sidewall of the annular fuse link, and the second lower anode / cathode region abuts an outer sidewall of the annular fuse link. In one embodiment, the vertical electronic fuse element further includes a first silicide layer disposed on the first lower anode / cathode region, and a second silicide layer disposed on the second lower anode / cathode region, wherein the first silicide layer and the second silicide layer are disposed separately from the annular fuse link. In one embodiment, the vertical electronic fuse element further includes a first fuse dielectric layer disposed on an inner sidewall of the annular fuse link, wherein the first fuse dielectric layer extends over the first lower anode / cathode region, and a second fuse dielectric layer disposed on an outer sidewall of the annular fuse link, wherein the second fuse dielectric layer extends over the second lower anode / cathode region.

[0011] In one embodiment, the vertical electronic fuse element further includes a first conductive layer disposed on the first fuse dielectric layer, and a second conductive layer disposed on the second fuse dielectric layer, wherein the first conductive layer and the second conductive layer are disposed separately from the annular fuse link. In one embodiment, the vertical electronic fuse element further includes a lower gap sublayer disposed between the first lower anode / cathode region and the first fuse dielectric layer, and between the second lower anode / cathode region and the second fuse dielectric layer, and an upper gap sublayer covering the first fuse dielectric layer, the first conductive layer, the second fuse dielectric layer, and the second conductive layer.

[0012] Still another embodiment of the present disclosure provides a method of fabricating a vertical electronic fuse element. The method includes forming a mask layer on a semiconductor substrate, and etching the semiconductor substrate and using the mask layer as a mask to form a fuse link on the semiconductor substrate. The method also includes epitaxially growing a first lower anode / cathode region and a second lower anode / cathode region on the semiconductor substrate and adjacent to a lower portion of the fuse link. The fuse link is between the first lower anode / cathode region and the second lower anode / cathode region. The method further includes epitaxially growing an upper anode / cathode region to replace the mask layer.

[0013] In one embodiment, the mask layer has an overlapping annular shape with the fuse link from a top view. In one embodiment, forming the mask layer further comprises forming an annular structure on the semiconductor substrate; and forming a mask material to cover a portion of the semiconductor substrate exposed through the annular structure. Further, forming the mask layer comprises depositing an inner gap sub-layer and an outer gap sub-layer on the mask material, wherein an inner sidewall of the annular structure is covered by the inner gap sub-layer and an outer sidewall of the annular structure is covered by the outer gap sub-layer; and etching the mask material and using the inner gap sub-layer and the outer gap sub-layer as a mask to form the mask layer on the semiconductor substrate.

[0014] In one embodiment, the method further comprises implanting the fuse link with an n-type dopant; and removing the inner gap sub-layer and the outer gap sub-layer, which is performed after the implanting of the fuse link. In one embodiment, the method further comprises forming a first silicide layer on the first lower anode / cathode region and forming a second silicide layer on the second lower anode / cathode region; and forming a lower gap sub-layer to cover the first silicide layer and the second silicide layer, which is performed before the growing of the upper anode / cathode region. In one embodiment, the method further comprises forming a first fuse dielectric layer and a second fuse dielectric layer on the lower gap sub-layer and on each opposite sidewall of the fuse link; and forming a first conductive layer on the first fuse dielectric layer and forming a second conductive layer on the second fuse dielectric layer. Further, the method comprises forming an upper gap sub-layer to cover the first conductive layer and the second conductive layer, which is performed before the growing of the upper anode / cathode region.

[0015] The present disclosure provides vertical electronic fuse elements of various embodiments. The vertical electronic fuse element has a fuse link and a plurality of lower anode / cathode regions, wherein the fuse link and the lower anode / cathode regions are disposed on a semiconductor substrate, and a lower portion of the fuse link is sandwiched between the lower anode / cathode regions. The vertical electronic fuse element also has an upper anode / cathode region disposed on the fuse link. Since the fuse link is configured in a vertical direction between the lower anode / cathode regions and the upper anode / cathode region, the vertical electronic fuse element can be integrated with other semiconductor elements, such as a fin field effect transistor (FinFET) element, and the vertical electronic fuse element can be formed integrally with the FinFET element without additional processing steps.

[0016] The foregoing has outlined rather broadly the technical features of the technology in accordance with the present disclosure so that those skilled in the art can better understand the detailed description of the technology that follows. Additional features of the technology will be described hereinafter that form the subject of the claims of the technology. Those skilled in the art will appreciate the BRIEF DESCRIPTION OF DRAWINGS

[0017] For a fuller understanding of the present disclosure, reference is made to the detailed description of the technology in conjunction with the accompanying drawings in which like reference numerals refer to like elements in which:

[0018] Figure 1 A cross-sectional view of a vertical electronic fuse element according to some embodiments of the present disclosure.

[0019] Figure 2 A flow diagram of a method of fabricating a vertical electronic fuse element according to some embodiments of the present disclosure.

[0020] Figure 3 A top view of an intermediate stage of forming ring structures on a semiconductor substrate during fabrication of a vertical electronic fuse element according to some embodiments of the present disclosure.

[0021] Figure 4 A cross-sectional view of an intermediate stage of forming ring structures on a semiconductor substrate during fabrication of a vertical electronic fuse element according to some embodiments of the present disclosure.

[0022] Figure 5 A top view of an intermediate stage of forming a masking material during fabrication of a vertical electronic fuse element according to some embodiments of the present disclosure.

[0023] Figure 6 A cross-sectional view of an intermediate stage of forming a masking material during fabrication of a vertical electronic fuse element according to some embodiments of the present disclosure. Figure 5

[0024] Figure 7 A top view of an intermediate stage of depositing inner gap sub-layers and outer gap sub-layers during fabrication of a vertical electronic fuse element according to some embodiments of the present disclosure.

[0025] Figure 8 ​FIG. 6 is a cross-sectional view of a semiconductor substrate 100 along section line I-I' of FIG. 5, according to some embodiments of the present disclosure, at an intermediate stage during formation of a vertical electronic fuse element. Figure 7 FIG. 7 is a cross-sectional view of a semiconductor substrate 100 along section line I-I' of FIG. 6, according to some embodiments of the present disclosure, at an intermediate stage during formation of a vertical electronic fuse element.

[0026] Figure 9 FIG. 8 is a top view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure.

[0027] Figure 10 FIG. 9 is a cross-sectional view of a semiconductor substrate 100 along section line I-I' of FIG. 8, according to some embodiments of the present disclosure, at an intermediate stage during formation of a vertical electronic fuse element. Figure 9

[0028] Figure 11 FIG. 10 is a cross-sectional view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure.

[0029] Figure 12 FIG. 11 is a top view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure.

[0030] Figure 13 FIG. 12 is a cross-sectional view of a semiconductor substrate 100 along section line I-I' of FIG. 11, according to some embodiments of the present disclosure, at an intermediate stage during formation of a vertical electronic fuse element. Figure 12

[0031] FIG. 13 is a partial enlarged cross-sectional view of region A in FIG. 12, according to some embodiments of the present disclosure. Figure 14 FIG. 14 is a schematic view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure, of epitaxially growing a plurality of lower anode / cathode regions on the semiconductor substrate. Figure 13 Figure 14 FIG. 15 is a schematic view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure, of forming the inner gap sub-layers and the outer gap sub-layers.

[0032] Figure 15 FIG. 16 is a partial enlarged cross-sectional view of region A in FIG. 15, according to some embodiments of the present disclosure. Figure 13 Figure 15 FIG. 17 is a schematic view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure, of forming a plurality of silicide layers on the lower anode / cathode regions.

[0033] Figure 16 FIG. 18 is a partial enlarged cross-sectional view of region A in FIG. 17, according to some embodiments of the present disclosure. Figure 13 Figure 16 FIG. 19 is a schematic view of a semiconductor substrate 100 at an intermediate stage during formation of a vertical electronic fuse element, according to some embodiments of the present disclosure, of forming a plurality of fuse chains on the semiconductor substrate.​​​​

[0034] Figure 17 is a partial enlarged sectional view of the area A in Figure 13 , and Figure 17 is a schematic view of an intermediate stage of forming a lower gap sub-layer on the silicide layer during formation of the vertical electronic fuse element according to some embodiments of the present disclosure.

[0035] Figure 18 is a partial enlarged sectional view of the area A in Figure 13 , and Figure 18 is a schematic view of an intermediate stage of forming a plurality of fuse dielectric layers and a plurality of conductive layers on the lower gap sub-layer during formation of the vertical electronic fuse element according to some embodiments of the present disclosure.

[0036] Figure 19 is a partial enlarged sectional view of the area A in Figure 13 , and Figure 19 is a schematic view of an intermediate stage of forming an upper gap sub-layer on the fuse dielectric layers and the conductive layers during formation of the vertical electronic fuse element according to some embodiments of the present disclosure.

[0037] Figure 20 is a partial enlarged sectional view of the area A in Figure 13 , and Figure 20 is a schematic view of an intermediate stage of forming a plurality of dielectric layers to pass through the conductive layers during formation of the vertical electronic fuse element according to some embodiments of the present disclosure.

[0038] Figure 21 is a partial enlarged sectional view of the area A in Figure 13 , and Figure 21 is a schematic view of an intermediate stage of epitaxially growing an upper anode / cathode to replace the mask layer during formation of the vertical electronic fuse element according to some embodiments of the present disclosure.

[0039] In which, the reference signs are explained as follows:

[0040] 10: method

[0041] 100: vertical electronic fuse element

[0042] 101: semiconductor substrate

[0043] 101': semiconductor substrate

[0044] 101a: fuse chain

[0045] 101b: fuse chain

[0046] 101c: fuse chain

[0047] 101d: fuse link

[0048] 103a: cylindrical structure

[0049] 103b: cylindrical structure

[0050] 105a: ring structure

[0051] 105b: ring structure

[0052] 107: masking material

[0053] 107': masking layer

[0054] 110a: opening

[0055] 110b: opening

[0056] 113a1: inner gap sublayer

[0057] 113a2: outer gap sublayer

[0058] 113b1: inner gap sublayer

[0059] 113b2: outer gap sublayer

[0060] 120a: opening

[0061] 120b: opening

[0062] 130a1: recess

[0063] 130a2: recess

[0064] 130b1: recess

[0065] 130b2: recess

[0066] 130c: recess

[0067] 135: ion implantation process

[0068] 141a1: lower anode / cathode region

[0069] 141a2: lower anode / cathode region

[0070] 145a1: silicide layer

[0071] 145a2: silicide layer

[0072] 147: lower gap sublayer

[0073] 151a1: fuse dielectric layer

[0074] 151a11: fuse dielectric layer

[0075] 151a12: fuse dielectric layer

[0076] 151a2: fuse dielectric layer

[0077] 153a1: conductive layer

[0078] 153a11: conductive layer

[0079] 153a12: conductive layer

[0080] 153a2: conductive layer

[0081] 157: upper gap sublayer

[0082] 159: interlayer dielectric layer

[0083] 161: dielectric layer

[0084] 163: upper anode / cathode region

[0085] 165: dielectric layer

[0086] 167: conductive contact

[0087] A: area

[0088] BP: lower portion

[0089] S11: step

[0090] S13: step

[0091] S15: step

[0092] S17: step

[0093] S19: step

[0094] S21: step

[0095] S23: step

[0096] S25: step

[0097] S27: step

[0098] S29: step

[0099] S31: step

[0100] S33: step

[0101] SW1: sidewall

[0102] SW2: sidewall

[0103] SW3: inner sidewall

[0104] SW4: outer sidewall

[0105] TS: top surface DETAILED DESCRIPTION

[0106] The following description describes specific examples of components and configurations to simplify the present disclosure. These examples are merely intended to facilitate description of the disclosure. Thus, the disclosure is not limited to these implementations. For example, in describing a first component formed on a second component, the implementation can include a first and second component in direct contact, or can include additional components formed between the first and second components such that the first and second components are not in direct contact. Additionally, implementations of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. These repetitions are for the sake of simplicity and clarity and do not themselves imply a particular relationship between the various implementations and / or configurations discussed.

[0107] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0108] Figure 1 A cross-sectional schematic view of a vertical electronic fuse element 100 in accordance with some embodiments of the present disclosure is shown. As shown, the vertical electronic fuse element 100 includes a fuse link 101a and lower anode / cathode regions 141a1, 141a2 disposed on a semiconductor substrate 101', and an upper anode / cathode region 163 disposed on the fuse link 101a. Figure 1

[0109] In some embodiments, as shown, the two segments of the fuse link 101a are physically connected together as different parts of a continuous annular structure, which will be described in detail later. The fuse link 101a is also referred to as an annular fuse link. In this example, the lower anode / cathode region 414a1 is surrounded by a lower portion BP of the fuse link 101a, and as shown, the two segments of the lower anode / cathode region 141a2 are different parts of a continuous annular structure that surrounds the lower portion BP of the fuse link 101a. Figure 1 Figure 1

[0110] ​​​In some embodiments, the lower BP of fuse link 101a is sandwiched between lower anode / cathode regions 141a1 and 141a2. In particular, lower anode / cathode region 141a1 abuts sidewall SW1 of fuse link 101a, and lower anode / cathode region 141a2 abuts sidewall SW2 of fuse link 101a. Sidewall SW1 is also referred to as the inner sidewall of fuse link 101a. Sidewall SW2 is also referred to as the outer sidewall of fuse link 101a. Similarly, as shown in FIG. 1A, the two segments of upper anode / cathode region 163 can be different parts of a continuous annular structure. In some embodiments, upper anode / cathode region 136 directly contacts the upper surface TS of fuse link 101a. Figure 1

[0111] Further, vertical electronic fuse element 100 includes suicide layers 145a1, 145a2 disposed on lower anode / cathode regions 141a1, 141a2, and a lower gap sublayer 147 covering suicide layers 145a1, 145a2. In some embodiments, suicide layer 145a1 is disposed on lower anode / cathode region 141a1, and as shown in FIG. 1A, the two segments of suicide layer 145a2 are different parts of a continuous annular structure disposed on lower anode / cathode region 141a2, which is also a continuous annular structure. In some embodiments, suicide layers 145a1, 145a2 are conformally covered by lower gap sublayer 147, and suicide layers 145a1, 145a2 are disposed apart from sidewalls SW1, SW2 of fuse link 101a by lower gap sublayer 147. Figure 1

[0112] Still referring to FIG. 1A, vertical electronic fuse element 100 includes fuse dielectric layers 151a11, 151a12, 151a2 disposed on lower gap sublayer 147, and conductive layers 153a11, 153a12, 153a2 disposed on fuse dielectric layers 151a11, 151a12, 151a2. In some embodiments, fuse dielectric layers 151a11 and 151a12 are disposed on sidewall SW1 of fuse link 101a, and fuse dielectric layers 151a11 and 151a12 extend onto the portion of lower gap sublayer 147 that is surrounded by fuse link 101a. In some embodiments, as shown in FIG. 1A, the two segments of fuse dielectric layer 151a2 are physically connected together and disposed on sidewall SW2 of fuse link 101a, and fuse dielectric layer 151a2 extends onto the portion of lower gap sublayer 147 that surrounds fuse link 101a. Figure 1 Figure 1

[0113] ​​​​Similar to fuse dielectric layer 151a2, in accordance with some embodiments, the two segments of conductive layer 153a2 are physically connected together because they are different parts of a continuous ring-like structure. In some embodiments, conductive layers 153a11, 153a12, 153a2, fuse link 101a, and lower gap sub-layer 147 are separated by fuse dielectric layers 151a11, 151a12, 151a2.

[0114] In addition, vertical electronic fuse element 100 includes an upper gap sub-layer 157, an interlayer dielectric layer 159, and a dielectric layer 161. Upper gap sub-layer 157 covers conductive layers 153a11, 153a12, 153a2, interlayer dielectric layer 159 is disposed on upper gap sub-layer 157 and around upper anode / cathode region 163, and dielectric layer 161 penetrates interlayer dielectric layer 159 and upper gap sub-layer 157. In some embodiments, fuse dielectric layer 151a11 and conductive layer 153a11 are separated from fuse dielectric layer 151a12 and conductive layer 153a12 by dielectric layer 161. In some embodiments, dielectric layer 161 does not extend into silicide layers 145a1 and 145a2. In other words, a portion of lower gap sub-layer 147 is sandwiched between dielectric layer 161 and silicide layers 145a1, 145a2.

[0115] Further, vertical electronic fuse element 100 includes a conductive contact 167 and another dielectric layer 165. Conductive contact 167 is disposed on upper anode / cathode region 163, and interlayer dielectric layer 165 is disposed on dielectric layer 161 and interlayer dielectric layer 159 and around conductive contact 167. In some embodiments, as shown, the two segments of conductive contact 167 are physically connected together because they are different parts of a continuous ring-like structure. In some embodiments, conductive contact 167 is electrically connected to upper anode / cathode region 163. Figure 1

[0116] Figure 2 A flowchart of a method 10 for fabricating a vertical electronic fuse element 100 in accordance with some embodiments of the present disclosure is shown. Method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27, S29, S31, and S33. Steps S11 through S33 of method 10 are described in detail in conjunction with the following figures.

[0117] Figure 3 Figure 5 Figure 7 Figure 9 Figure 12 Top view schematic diagrams of various intermediate stages in forming a vertical electronic fuse element 100 in accordance with some embodiments are shown, and Figure 4 ,​​​​​Figure 6 、 Figure 8 、 Figure 10 、 Figure 11 and Figure 13 are cross-sectional schematic views of various intermediate stages in the formation of vertical electron fuse element 100 in accordance with some embodiments. It is to be understood that Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 、 Figure 11 and Figure 13 are cross-sectional schematic views along the cross-sectional line I-I’ of Figure 3 、 Figure 5 、 Figure 7 、 Figure 9 and Figure 12 .

[0118] As shown in Figure 3 and Figure 4 , a semiconductor substrate 101 is provided. Semiconductor substrate 101 can be a semiconductor wafer, such as a silicon wafer. Additionally or alternatively, semiconductor substrate 101 can include elementary semiconductor material, compound semiconductor material, and / or alloy semiconductor material. Examples of elementary semiconductor materials can include crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond, but are not limited thereto. Examples of compound semiconductor elements can include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, but are not limited thereto. Alloy semiconductor materials can include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, but are not limited thereto.

[0119] In some embodiments, semiconductor substrate 101 has an epitaxial layer. For example, semiconductor substrate 101 has an epitaxial layer that is grown on a bulk semiconductor. In some embodiments, semiconductor substrate 101 is a semiconductor-on-insulator substrate, which can have a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX) techniques, wafer bonding, or other suitable methods.

[0120] Still referring toFigure 3 and Figure 4 According to some embodiments, the cylindrical structures 103a, 103b are formed on the semiconductor substrate 101, and the ring-shaped structures 105a, 105b are formed to surround the cylindrical structures 103a, 103b, respectively. The corresponding steps are illustrated as step Sll in the method 10 shown in FIG. 1. Figure 2 Although only two cylindrical structures and two ring-shaped structures are illustrated, it should be understood that more than two cylindrical structures and more than two ring-shaped structures can be implemented in the vertical electron fuse element 100.

[0121] In some embodiments, the material of the cylindrical structures 103a, 103b includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), other applicable materials, or combinations thereof. Further, the cylindrical structures 103a, 103b can be formed by a deposition process and a patterning process. For example, a material layer (not shown) can be deposited on the semiconductor substrate 101, and the material layer can be patterned to form the cylindrical structures 103a, 103b.

[0122] The deposition process can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, other applicable processes, or combinations thereof. The patterning process can include a lithography process and a subsequent etching process. The lithography process can form a plurality of photoresist patterns (not shown) on an upper surface of the material layer. The lithography process can include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, developing photoresist, rising, and drying (e.g., hard baking). The etching process can be a dry etching process, a wet etching process, or combinations thereof.

[0123] In some embodiments, each sidewall of the cylindrical structures 103a, 103b is completely surrounded by the annular structures 105a, 105b, respectively, and each sidewall of the cylindrical structures 103a, 103b is in direct contact with the annular structures 105a, 105b, respectively. Some materials and processes used to form the annular structures 105a, 105b are similar to or the same as those used to form the cylindrical structures 103a, 103b, and are not repeated in detail herein. However, it should be understood that the materials of the annular structures 105a, 105b are different from those of the cylindrical structures 103a, 103b.

[0124] Then, as shown in FIG. 1C, according to some embodiments, the cylindrical structures 103a, 103b are removed to form openings 110a, 110b in the annular structures 105a, 105b, and a mask material 107 is formed on the semiconductor substrate 101 and on the annular structures 105a, 105b. The corresponding step is step S13 in the method 10 as shown in FIG. 1D. Figure 5 Figure 6 Figure 2

[0125] In some embodiments, the cylindrical structures 103a, 103b are removed by an etching process, such as a dry etching process. As mentioned previously, the materials of the cylindrical structures 103a, 103b are different from those of the annular structures 105a, 105b, and the materials are selected such that the etching selectivity of the cylindrical structures 103a, 103b with respect to the annular structures 105a, 105b is high. Thus, the cylindrical structures 103a, 103b can be removed by the etching process while the annular structures 105a, 105b can be left substantially intact, and the openings 110a, 110b exposing the semiconductor substrate 101 are obtained.

[0126] Some materials and processes used to form the mask material 107 are similar to or the same as those used to form the cylindrical structures 103a, 103b, and are not repeated in detail herein. In some embodiments, the material of the mask material 107 is different from that of the annular structures 105a, 105b. In some embodiments, the mask material 107 is formed by selectively growing or depositing a dielectric material on each of the upper surfaces of the annular structures 105a, 105b and on the portion of the semiconductor substrate 101 exposed through the annular structures 105a, 105b. In some embodiments, each sidewall of the annular structures 105a, 105b is partially exposed. That is, the portion of each sidewall of the annular structures 105a, 105b is not covered by the mask material 107. In some embodiments, the mask material 107 is formed by an epitaxial (epi) process.

[0127] ​​​Next, as shown in FIG. 1C, according to some embodiments, inner gap sub-layers 113al, 113bl and outer gap sub-layers 113a2, 113b2 are disposed on the mask material 107. The corresponding step is step S15 in the method 10 shown in FIG. 1D. In some embodiments, the inner gap sub-layers 113al, 113bl are deposited on and directly contact each inner sidewall SW3 of the ring structures 105a, 105b, and the outer gap sub-layers 113a2, 113b2 are deposited on and directly contact each outer sidewall SW4 of the ring structures 105a, 105b. Figure 7 Figure 8 Figure 2

[0128] Further, one opening 120a is surrounded by the inner gap sub 113al, and another opening 120b is surrounded by the inner gap sub 113bl. Some materials and processes used to form the inner gap sub-layers 113al, 113bl and the outer gap sub-layers 113a2, 113b2 are similar to or the same as those used to form the cylindrical structures 103a, 103b, and will not be described in detail herein. In some embodiments, the inner gap sub-layers 113al, 113bl and the outer gap sub-layers 113a2, 113b2 are formed simultaneously and from the same material. However, it should be understood that, according to some embodiments, the materials of the inner gap sub-layers 113al, 113bl and the outer gap sub-layers 113a2, 113b2 are different from the material of the mask material 107 and the material of the ring structures 105a, 105b.

[0129] Next, as shown in FIG. 1C, according to some embodiments, inner gap sub-layers 113al, 113bl and outer gap sub-layers 113a2, 113b2 are disposed on the mask material 107. The corresponding step is step S15 in the method 10 shown in FIG. 1D. In some embodiments, the inner gap sub-layers 113al, 113bl are deposited on and directly contact each inner sidewall SW3 of the ring structures 105a, 105b, and the outer gap sub-layers 113a2, 113b2 are deposited on and directly contact each outer sidewall SW4 of the ring structures 105a, 105b. Figure 9 Figure 10 Figure 2

[0130] ​​​​​​It should be appreciated that the portions of the ring structures 105a, 105b and the mask material 107 that are removed are the portions that are exposed (e.g., not covered) by the inner gap sub-layers 113a1, 113b1 and the outer gap sub-layers 113a2, 113b2. In some embodiments, the materials of the ring structures 105a, 105b, the mask material 107, the inner gap sub-layers 113a1, 113b1 and the outer gap sub-layers 113a2, 113b2 are selected such that the mask material 107 and the ring structures 105a, 105b are highly etch selective with respect to the inner gap sub-layers 113a1, 113b1 and the outer gap sub-layers 113a2, 113b2. Thus, the exposed portions of the ring structures 105a, 105b and the mask material 107 are removed by the etch process, while the inner gap sub-layers 113a1, 113b1 and the outer gap sub-layers 113a2, 113b2 can remain substantially intact.

[0131] Referring still to Figure 9 and Figure 10 , recesses 130a1, 130a2, 130b1, 130b2, 130c are formed in the semiconductor substrate 101 and on the semiconductor substrate 101'. In some embodiments, the recess 130a1 is surrounded by the fuse link 101a, and the fuse link 101a is surrounded by the recess 130a2. In some embodiments, the recess 130b1 is surrounded by the fuse link 101b, and the fuse link 101b is surrounded by the recess 130b2. Further, according to some embodiments, the recess 130c is formed between the fuse links 101c and 101d.

[0132] It should be appreciated that the fuse links 101a, 101b, 101c, 101d are formed from the semiconductor substrate 101. Thus, the material of the fuse links 101a, 101b, 101c, 101d is the same as the material of the semiconductor substrate 101 (e.g., the material of the semiconductor substrate 101'). Further, the mask layer 107' is formed from the mask material 107. In some embodiments, portions of the mask material 107 and the semiconductor substrate 101 around the outer gap sub-layers 113a2, 113b2 are not etched.

[0133] As shown in Figure 11 , according to some embodiments, after the recesses 130a1, 130a2, 130b1, 130b2, 130c are formed, an ion implantation process is performed to implant dopants into the fuse links 101a, 101b, 101c, 101d through the recesses 130a1, 130a2, 130b1, 130b2, 130c. The corresponding steps are illustrated in Figure 2Step S21 in the method 10 is shown. In some embodiments, the N-type dopant is implanted into the fuse link 101a, 101b, 101c, 101d, and the N-type dopant is, for example, phosphorous (P) or arsenic (As). In some other embodiments, the P-type dopant is implanted into the fuse link 101a, 101b, 101c, 101d, and the P-type dopant is, for example, boron (B), gallium (Ga), or indium (In). The conductive form of the fuse link 101a, 101b, 101c, 101d is dependent on the design requirements of the vertical electronic fuse element 100.

[0134] As Figure 12 and Figure 13 shown, according to some embodiments, after the ion implantation process 135 is performed, the inner gap sublayer 113a1, 113b1 and the outer gap sublayer 113a2, 113b2 are removed. In some embodiments, the inner gap sublayer 113a1, 113b1 and the outer gap sublayer 113a2, 113b2 are removed by an etching process. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

[0135] Figures 14 to 21 is a partial enlarged sectional view of the region A in Figure 13 illustrating various sequential intermediate stages of forming the vertical electronic fuse element 100 according to some embodiments. Although Figures 14 to 21 only a portion of the structure in Figure 12 and Figure 13 is shown, it should be understood that it is for ease of illustration; and other portions of the structure in Figure 12 and Figure 13 may have features similar to those illustrated in Figures 14 to 21 .

[0136] As Figure 14 shown, according to some embodiments, after the inner gap sublayer 113a1, 113b1 and the outer gap sublayer 113a2, 113b2 are removed, the lower anode / cathode region 141a1, 141a2 is epitaxially grown on the semiconductor substrate 101’ and adjacent to the fuse link 101a. The corresponding step is shown as step S23 in the method 10 as shown in Figure 2 In some embodiments, the lower anode / cathode region 141a1, 141a2 is epitaxially grown in the recess 130a1, 130a2, respectively.

[0137] As mentioned above, as Figure 14The two sections of the lower anode / cathode region 141a2 shown are two different parts of a continuous annular structure. In some embodiments, the lower anode / cathode region 141a1 is surrounded by the lower portion BP of the fuse chain 101a, and the lower portion BP of the fuse chain 101a is surrounded by the lower anode / cathode region 141a2. In some embodiments, the lower anode / cathode regions 141a1 and 141a2 are in direct contact with the opposite sidewalls SW1 and SW2 (e.g., the inner sidewall SW1 and the outer sidewall SW2) of the fuse chain 101a.

[0138] In some embodiments, a strained material is grown on the recesses 130a1 and 130a2 of the semiconductor substrate 101' through an epitaxial process to form lower anode / cathode regions 141a1 and 141a2. In some embodiments, the lower anode / cathode regions 141a1 and 141a2 include Ge, SiGe, InAs, InGaSa, InSb, GaAs, GaSb, InAlP, InP, or the like. The epitaxial process may include a rapid thermal chemical vapor deposition (RTCVD) process, an ultra-high vacuum chemical vapor deposition (UHVCVD) process, a molecular beam epitaxy (MBE) process, a metal-organic air chemical vapor deposition (MOCVD) process, or other applicable processes.

[0139] Next, as Figure 15 As shown, according to some embodiments, another inner gap sublayer 143a1 is formed on the sidewall SW1 of the fuse chain 101a and directly contacts the sidewall SW1 of the fuse chain 101a; and another outer gap sublayer 143a2 is formed on the sidewall SW2 of the fuse chain 101a and directly contacts the sidewall SW2 of the fuse chain 101a. In some embodiments, the inner gap sublayer 143a1 is formed on the lower anode / cathode region 141a1, and the outer gap sublayer 143a2 is formed on the lower anode / cathode region 141a2. After the inner gap sublayer 143a1 and the outer gap sublayer 143a2 are formed, the sidewalls SW1 and SW2 of the fuse chain 101a are completely covered.

[0140] In some embodiments, the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 are made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), other applicable material, or a combination thereof. In some embodiments, the material of the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 is different from the material of the mask layer 107'. Further, the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 can be formed by a CVD process, a PVD process, an ALD process, other applicable process, or a combination thereof.

[0141] As shown in FIG. 1C, according to some embodiments, after the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 are formed, a silicide layer 145a1, 145a2 is formed on the lower anode / cathode region 141a1, 141a2, respectively. The corresponding step is illustrated as step S25 in the method 10 as shown in FIG. 1D. In some embodiments, the silicide layer 145a1 is in direct contact with the inner gap sub-layer 143a1, and the silicide layer 145a2 is in direct contact with the outer gap sub-layer 143a2. Figure 16 Figure 2 As shown in FIG. 1C, according to some embodiments, after the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 are formed, a silicide layer 145a1, 145a2 is formed on the lower anode / cathode region 141a1, 141a2, respectively. The corresponding step is illustrated as step S25 in the method 10 as shown in FIG. 1D. In some embodiments, the silicide layer 145a1 is in direct contact with the inner gap sub-layer 143a1, and the silicide layer 145a2 is in direct contact with the outer gap sub-layer 143a2.

[0142] In some embodiments, the silicide layer 145a1, 145a2 is made of a metal silicide material, such as cobalt silicide, titanium silicide, tantalum silicide, nickel silicide, copper silicide, tungsten silicide, molybdenum silicide, or other applicable material. Further, the silicide layer 145a1, 145a2 can be formed by a silicidation process. In some embodiments, the silicidation process includes a metal material deposition process and an annealing process performed sequentially. In some embodiments, the deposition process of the silicidation process includes a PVD process, an ALD process, or other applicable process. In some embodiments, the annealing process of the silicidation process is performed at a temperature between about 400 °C and about 700 °C. After the annealing process, unreacted metal material is removed.

[0143] Then, as shown in FIG. 1E, according to some embodiments, the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 are removed, and a lower gap sub-layer 147 is formed to cover the silicide layer 145a1, 145a2. The corresponding step is illustrated as step S27 in the method 10 as shown in FIG. 1F. In some embodiments, the lower gap sub-layer 147 is in direct contact with the sidewalls SW1 and SW2 of the fuse link 101a. Figure 17 Figure 2 As shown in FIG. 1E, according to some embodiments, after the inner gap sub-layer 143a1 and the outer gap sub-layer 143a2 are formed, a silicide layer 145a1, 145a2 is formed on the lower anode / cathode region 141a1, 141a2, respectively. The corresponding step is illustrated as step S25 in the method 10 as shown in FIG. 1D. In some embodiments, the silicide layer 145a1 is in direct contact with the inner gap sub-layer 143a1, and the silicide layer 145a2 is in direct contact with the outer gap sub-layer 143a2.

[0144] ​​In some embodiments, the inner gap sublayer 143a1 and the outer gap sublayer 143a2 are removed by a selective etching process, such as a reactive ion etching (RIE) process. The removal of the inner gap sublayer 143a1 and the outer gap sublayer 143a2 exposes the sidewalls SW1 and SW2 of the fuse chain 101a, and a plurality of annular gaps (not shown) are formed between the silicide layers 145a1 and 145a2 and the fuse chain 101a. Then, the lower gap sublayer 147 is deposited on the silicide layers 145a1, 145a2, and some portions of the lower gap sublayer 147 extend into the annular gaps. Thus, the lower gap sublayer 147 is sandwiched between the silicide layers 145a1, 145a2 and the fuse chain 101a. In some embodiments, the sidewalls SW1, SW2 of the silicide layers 145a1, 145a2 and the fuse chain 101a are separated by the lower gap sublayer 147.

[0145] In some embodiments, the lower gap sublayer 147 is made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), other applicable materials, or a combination thereof. In addition, the lower gap sublayer 147 is formed by a directional deposition process, such as a high-density plasma (HDP) deposition process, a gas cluster ion beam (GCIB) deposition process, or other applicable deposition processes. The directional deposition process preferably deposits the material of the lower gap sublayer 147 on the exposed horizontal surfaces, but not on the lateral sidewalls. During a subsequent planarization process, such as a chemical mechanical polishing (CMP) process, the material of the lower gap sublayer 147 formed on the upper surfaces of the mask layer 107’ is removed.

[0146] Next, as shown in FIG. 1G, in accordance with some embodiments, fuse dielectric layers 151a1, 151a2 are formed on the lower gap sublayer 147, and conductive layers 153a1, 153a2 are formed on the fuse dielectric layers 151a1, 151a2. The corresponding steps are shown as step S29 in the method 10 shown in FIG. 1H. In some embodiments, some portions of the fuse dielectric layers 151a1, 151a2 extend onto the sidewalls SW1 and SW2 of the fuse chain 101a, and the conductive layers 153a1, 153a2 and the sidewalls SW1, SW2 of the fuse chain 101a are separated by the fuse dielectric layers 151a1, 151a2. Figure 18 Figure 2 Next, as shown in FIG. 1G, in accordance with some embodiments, fuse dielectric layers 151a1, 151a2 are formed on the lower gap sublayer 147, and conductive layers 153a1, 153a2 are formed on the fuse dielectric layers 151a1, 151a2. The corresponding steps are shown as step S29 in the method 10 shown in FIG. 1H. In some embodiments, some portions of the fuse dielectric layers 151a1, 151a2 extend onto the sidewalls SW1 and SW2 of the fuse chain 101a, and the conductive layers 153a1, 153a2 and the sidewalls SW1, SW2 of the fuse chain 101a are separated by the fuse dielectric layers 151a1, 151a2.​

[0147] Each fuse dielectric layer 151a1, 151a2 can be a single layer or multiple layers. In some embodiments, the fuse dielectric layer 151a1, 151a2 is silicon oxide, silicon nitride, silicon oxynitride (SiON), a dielectric material with high-k, or a combination thereof. In some embodiments, the fuse dielectric layer 151a1, 151a2 is deposited by a CVD process, a PVD process, an ALD process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin-on process, or other applicable processes.

[0148] Further, according to some embodiments, the conductive layer 153a1, 153a2 is made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. The conductive layer 153a1, 153a2 can be formed by a deposition process, such as a CVD process, a PVD process, an ALD process, an HDPCVD process, an MOCVD process, or a PECVD process.

[0149] After the materials of the fuse dielectric layer 151a1, 151a2 and the conductive layer 153a1, 153a2 are deposited, the excess materials of the fuse dielectric layer 151a1, 151a2 and the conductive layer 153a1, 153a2 are removed by a single etching process or multiple etching processes, such as a dry etching process. Thus, the respective upper surfaces of the fuse dielectric layer 151a1, 151a2 and the conductive layer 153a1, 153a2 are lower than the upper surface of the mask layer 107'. In some embodiments, the respective upper surfaces of the fuse dielectric layer 151a1, 151a2 and the conductive layer 153a1, 153a2 are lower than the upper surface of the fuse chain 101a, so that the sidewall SW1 and SW2 portions of the fuse chain 101a are exposed.

[0150] Next, as shown in FIG. 1G, according to some embodiments, an upper gap sub-layer 157 is formed to cover the fuse dielectric layer 151a1, 151a2 and the conductive layer 153a1, 153a2, and an interlayer dielectric layer 159 is formed on the upper gap sub-layer 157. The corresponding step is step S31 in the method 10 as shown in FIG. 1H. In some embodiments, the upper gap sub-layer 157 directly contacts the respective upper portions of the sidewall SW1 and SW2 of the fuse chain 101a. Some materials and processes used to form the upper gap sub-layer 157 are similar to or the same as those used to form the lower gap sub-layer 147, and detailed descriptions thereof are not repeated herein. Figure 19 Figure 2

[0151] ​​The interlayer dielectric layer 159 may be a single layer or multiple layers. In some embodiments, the material of the interlayer dielectric layer 159 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-dielectric materials, or other applicable dielectric materials. The interlayer dielectric layer 159 may be formed by a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes. Subsequently, a planarization process may be performed on the interlayer dielectric layer 159 until the upper surface of the mask layer 107' is exposed, and the planarization process is, for example, a CMP process.

[0152] like Figure 20 As shown, according to some embodiments, a dielectric layer 161 is formed to pass through an interlayer dielectric layer 159, an upper spacer layer 157, conductive layers 153a1 and 153a2, and fuse dielectric layers 151a1 and 151a2. The dielectric layer 161 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials; and the formation of the dielectric layer 161 may include forming a patterned mask (not shown) on... Figure 19 Structurally; etch the interlayer dielectric layer 159, the upper spacer layer 157, the conductive layers 153a1 and 153a2, and the filament dielectric layers 151a1 and 151a2 to form a plurality of openings (not shown) by using a patterned mask as a mask; deposit a dielectric material in the openings and on the interlayer dielectric layer 159 and the mask layer 107'; and polish the dielectric material until the upper surface of the mask layer 107' is exposed.

[0153] In some embodiments, during the etching process for forming dielectric layer 161, the lower spacer layer 147 is partially etched. Therefore, the lower surface of dielectric layer 161 may be lower than the upper surface of lower spacer layer 147. However, it should be understood that dielectric layer 161 does not penetrate through lower spacer layer 147. That is, dielectric layer 161 and silicide layers 145a1, 145a2 are separated by lower spacer layer 147. After dielectric layer 161 is formed, conductive layers 153a1, 153a2 and fuse dielectric layers 151a11, 151a12 are obtained.

[0154] like Figure 21 As shown, according to some embodiments, after the interlayer dielectric layer 161 is formed, an upper anode / cathode region 163 is epitaxially grown to replace the masking layer 107'. The corresponding steps are illustrated in... Figure 2Step S33 in method 10 shown. More specifically, according to some embodiments, is the removal of the masking layer 107', and the upper anode / cathode region 163 is epitaxially grown on the upper surface of the filament chain 101a.

[0155] In some embodiments, the mask layer 107' is removed by an etching process, such as a wet etching process. According to some embodiments, after the mask layer 107' is removed, the upper surface TS of the fuse chain 101a and the sidewalls of the interlayer dielectric layer 159 are exposed through an annular opening (not shown), and the upper anode / cathode region 163 is epitaxially grown within the annular opening. Some materials and processes used to form the upper anode / cathode region 163 are similar to or the same as those used to form the lower anode / cathode regions 141a1, 141a2, and their detailed description will not be repeated herein.

[0156] In some embodiments, the upper anode / cathode region 163 is in-situ doped with N-type or P-type dopant during its epitaxial growth. In some embodiments, the upper anode / cathode region 163 is not doped during its epitaxial growth. Instead, after the growth of the upper anode / cathode region 163, it is doped in a subsequent process, such as an ion implantation process. In particular, as Figure 21 As shown, according to some embodiments, during its epitaxial growth, the upper anode / cathode region 163 has multiple faceted ports due to the slower growth rate of the upper anode / cathode region 163 on the (111) orientation surface. In some embodiments, the upper anode / cathode region 163 is in direct contact with the upper surface TP of the fused chain 101a.

[0157] like Figure 1 As shown, according to some embodiments, after epitaxial growth in the upper anode / cathode region 163, an interlayer dielectric layer 165 is formed. Figure 21 Structurally, a conductive contact is formed in the interlayer dielectric layer 165 and on the upper anode / cathode region 163. In some embodiments, the conductive contact 167 covers and directly contacts the facet of the upper anode / cathode region 163. Some materials and processes used to form the interlayer dielectric layer 1654 are similar to or the same as those used to form the interlayer dielectric layer 159, and their detailed description will not be repeated herein.

[0158] In some embodiments, the conductive contact 167 is made of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, tungsten (W), a tungsten alloy, titanium (Ti), a titanium alloy, tantalum (Ta), a tantalum alloy, or a combination thereof. Alternatively, other applicable materials can be used. Further, the formation of the conductive contact 167 can include forming a patterned mask (not shown) on the interlayer dielectric layer 165, etching the interlayer dielectric layer 165 using the patterned mask as a mask to form an opening (not shown) to partially expose the upper anode / cathode region 163, depositing a material of the conductive contact 167 in the opening and on the interlayer dielectric layer 165, and polishing the material of the conductive contact 167 until the upper surface of the interlayer dielectric layer 165 is exposed. After the conductive contact 167 is formed, the vertical electronic fuse element 100 is obtained.

[0159] In the present disclosure, various embodiments of a vertical electronic fuse element 100 are provided. Since the fuse link 101a of the vertical electronic fuse element 100 is arranged in a vertical direction between the lower anode / cathode regions 141a1, 141a2 and the upper anode / cathode region 163, the vertical electronic fuse element 100 can be integrated with other semiconductor elements, such as a fin field effect transistor (FinFET) element, and the vertical electronic fuse element 100 can be formed integrally with the FinFET element without additional processing steps.

[0160] In an embodiment of the present disclosure, a vertical electronic fuse element is provided. The vertical electronic fuse element has a fuse link disposed on a semiconductor base. The material of the fuse link and the material of the semiconductor base are the same. The vertical electronic fuse element also has a first lower anode / cathode region and a second lower anode / cathode region disposed on the semiconductor base. A lower portion of the fuse link is sandwiched between the first lower anode / cathode region and the second lower anode / cathode region. The vertical electronic fuse element further has an upper anode / cathode region disposed on the fuse link.

[0161] In another embodiment of the present disclosure, a vertical electronic fuse element is provided. The vertical electronic fuse element has a ring-shaped fuse link disposed on a semiconductor base. The material of the ring-shaped fuse link and the material of the semiconductor base are the same. The vertical electronic fuse element also has a first lower anode / cathode region surrounded by a lower portion of the ring-shaped fuse link and a second lower anode / cathode region disposed around the lower portion of the ring-shaped fuse link. The vertical electronic fuse element further has an upper anode / cathode region disposed on the ring-shaped fuse link.

[0162] In yet another embodiment of the present disclosure, a method for fabricating a vertical electronic fuse element is provided. The method includes forming a mask layer on a semiconductor substrate, and etching the semiconductor substrate and using the mask layer as a mask to form a fuse chain on the semiconductor substrate. The method also includes epitaxially growing a first lower anode / cathode region and a second lower anode / cathode region on the semiconductor substrate and adjacent to a lower portion of the fuse chain. The fuse chain is located between the first lower anode / cathode region and the second lower anode / cathode region. The method further includes epitaxially growing an upper anode / cathode region to replace the mask layer.

[0163] The above-described embodiments of the present disclosure have some advantageous features. Since the fuse chain extends in a vertical direction between the lower anode / cathode regions and the upper anode / cathode region, the vertical electronic fuse element can be integrated with other semiconductor elements, such as a FinFET element, and the vertical electronic fuse element can be formed integrally with the FinFET element without additional processing steps.

[0164] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the

[0165] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the appended claims are intended to cover all such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A vertical electronic fuse element, comprising: A fuse chain is disposed on a semiconductor substrate, wherein the material of the fuse chain is the same as the material of the semiconductor substrate; A first lower anode / cathode region and a second lower anode / cathode region are disposed on the semiconductor substrate, wherein a lower portion of the fuse chain is sandwiched between the first lower anode / cathode region and the second lower anode / cathode region; and An upper anode / cathode region is located on this fuse chain. From a top view, the fused chain and the upper anode / cathode region are in a ring shape.

2. The vertical electronic fuse element as claimed in claim 1, wherein, The upper anode / cathode region has a face.

3. The vertical electronic fuse element as described in claim 1, wherein, The fused wire chain is doped with an n-type dopant.

4. The vertical electronic fuse element as described in claim 1, further comprising: A silicide layer is disposed on the first lower anode / cathode region; as well as A lower spacer layer is disposed on the silicide layer, wherein the silicide layer and the fuse chain are separated by the lower spacer layer.

5. The vertical electronic fuse element as described in claim 1, further comprising: A first fusible dielectric layer is disposed on the first lower anode / cathode region; as well as A second fuse dielectric layer is disposed on the second lower anode / cathode region, wherein the first lower anode / cathode region and the first fuse dielectric layer are in direct contact with a first sidewall of the fuse chain, and the second lower anode / cathode region and the second fuse dielectric layer are in direct contact with a second sidewall of the fuse chain.

6. The vertical electronic fuse element as described in claim 5, further comprising: A first conductive layer is disposed on the first fuse dielectric layer, wherein the first conductive layer and the fuse chain are separated through the first fuse dielectric layer; as well as A second conductive layer is disposed on the second fuse dielectric layer, wherein the second conductive layer and the fuse chain are separated by the second fuse dielectric layer.

7. A vertical electronic fuse element, comprising: A ring-shaped fuse chain is disposed on a semiconductor substrate, wherein the material of the ring-shaped fuse chain is the same as the material of the semiconductor substrate; A first lower anode / cathode region is surrounded by the lower part of the annular fused wire chain; A second lower anode / cathode region is disposed around the lower portion of the annular fuse chain; and An upper anode / cathode region is located on the annular fuse chain.

8. The vertical electronic fuse element as claimed in claim 7, wherein, The upper anode / cathode region is annular, and the upper anode / cathode region directly contacts an upper surface of the annular filament chain.

9. The vertical electronic fuse element as claimed in claim 7, wherein, The first lower anode / cathode region is adjacent to an inner wall of the annular fuse chain, and the second lower anode / cathode region is adjacent to an outer wall of the annular fuse chain.

10. The vertical electronic fuse element as claimed in claim 7, further comprising: A first silicide layer is disposed on the first lower anode / cathode region; as well as A second silicide layer is disposed on the second lower anode / cathode region, wherein the first silicide layer and the second silicide layer are disposed separately from the annular fused chain.

11. The vertical electronic fuse element as claimed in claim 7, further comprising: A first fuse dielectric layer is disposed on an inner sidewall of the annular fuse chain, wherein the first fuse dielectric layer extends over the first lower anode / cathode region; as well as A second fuse dielectric layer is disposed on an outer sidewall of the annular fuse chain, wherein the second fuse dielectric layer extends over the second lower anode / cathode region.

12. The vertical electronic fuse element as claimed in claim 11, further comprising: A first conductive layer is disposed on the first fuse dielectric layer; as well as A second conductive layer is disposed on the second fuse dielectric layer, wherein the first conductive layer and the second conductive layer are disposed separately from the annular fuse chain.

13. The vertical electronic fuse element as claimed in claim 12, further comprising: A gap sublayer is disposed between the first lower anode / cathode region and the first fuse dielectric layer, and between the second lower anode / cathode region and the second fuse dielectric layer; as well as An upper spacer layer covers the first fuse dielectric layer, the first conductive layer, the second fuse dielectric layer, and the second conductive layer.

14. A method for fabricating a vertical electronic fuse element, comprising: A masking layer is formed on a semiconductor substrate; The semiconductor substrate is etched and the masking layer is used as a mask to form a filament chain on the semiconductor substrate; Epitaxially growing a first lower anode / cathode region and a second lower anode / cathode region on the semiconductor substrate and adjacent to a lower portion of the fuse chain, wherein the fuse chain is located between the first lower anode / cathode region and the second lower anode / cathode region; and An upper anode / cathode region is epitaxially grown to replace the masking layer. From a top view, the masking layer and the fused chain have an overlapping annular shape.

15. The method for fabricating a vertical electronic fuse element as described in claim 14, wherein, The formation of this masking layer also includes: A ring structure is formed on the semiconductor substrate; A masking material is formed to cover a portion of the semiconductor substrate exposed through the ring structure; An inner spacer sublayer and an outer spacer sublayer are deposited on the masking material, wherein an inner sidewall of the annular structure is covered by the inner spacer sublayer, and an outer sidewall of the annular structure is covered by the outer spacer sublayer; and The masking material is etched and the inner and outer spacer sublayers are used as a mask to form the mask layer on the semiconductor substrate.

16. The method for fabricating a vertical electronic fuse element as described in claim 15, further comprising: The fused filament chain with an n-type dopant was implanted; as well as The removal of the inner spacer layer and the outer spacer layer is performed after the implantation of the fuse chain.

17. The method for fabricating a vertical electronic fuse element as described in claim 14, further comprising: A first silicide layer is formed on the first lower anode / cathode region and a second silicide layer is formed on the second lower anode / cathode region; as well as A gap sublayer is formed to cover the first silicide layer and the second silicide layer, which is performed before the growth of the upper anode / cathode region.

18. The method for fabricating a vertical electronic fuse element as described in claim 17, further comprising: A first fuse dielectric layer and a second fuse dielectric layer are formed on the lower spacer layer and on each of the opposite sidewalls of the fuse chain; A first conductive layer is formed on the first fuse dielectric layer and a second conductive layer is formed on the second fuse dielectric layer; and An upper spacer sublayer is formed to cover the first conductive layer and the second conductive layer, which is performed before the growth of the upper anode / cathode region.

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