Semiconductor package including stacked semiconductor chips

Abstract

The present application discloses a semiconductor package including stacked semiconductor chips. A semiconductor package includes a sub-semiconductor package arranged above a substrate. The sub-semiconductor package includes a sub-semiconductor chip having a chip pad on its upper surface, a sub-molding layer surrounding the sub-semiconductor chip, and a redistribution conductive layer connected to each chip pad and extending above the upper surface of the sub-molding layer. The redistribution conductive layer includes a signal redistribution conductive layer extending to the edge of the sub-molding layer and having a signal redistribution pad at its end, and a power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer. The semiconductor package also includes a sub-signal interconnector, a sub-power interconnector, and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate or the sub-semiconductor chip.

Description

Technical Field

[0001] The present patent document relates to a semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked in a vertical direction. Background Art

[0002] Even as electronic products become smaller in size, they require large-capacity data processing. Therefore, there is an increasing need to increase the integration of semiconductor devices used in these electronic products.

[0003] However, due to limitations in semiconductor integration technology, it is difficult to satisfy required functions using only a single semiconductor chip, and thus, a semiconductor package having a plurality of semiconductor chips embedded therein has been manufactured. Summary of the invention

[0004] In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package disposed above the substrate, wherein the sub-semiconductor package includes a sub-semiconductor chip having a chip pad on an upper surface thereof, a sub-molding layer surrounding a side surface of the sub-semiconductor chip, and a redistribution conductive layer connected to each chip pad and extending above the upper surface of the sub-molding layer, wherein the redistribution conductive layer includes a signal redistribution conductive layer extending to an edge of the sub-molding layer, having a signal redistribution pad at an end of the signal redistribution conductive layer, and the redistribution conductive layer includes a power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer; a sub-signal interconnector connecting the signal redistribution pad to the substrate; a sub-power interconnector extending in a vertical direction below the power redistribution conductive layer to connect the power redistribution conductive layer to the substrate; and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate or the sub-semiconductor chip.

[0005] In another embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package arranged above the substrate, wherein the sub-semiconductor package includes a sub-semiconductor chip having a chip pad on its upper surface, a sub-molding layer surrounding the side surface of the sub-semiconductor chip, and a redistribution conductive layer connected to each chip pad and extending to the edge of the sub-molding layer, wherein the redistribution conductive layer includes a signal redistribution conductive layer having a signal redistribution pad at an end thereof and a power redistribution conductive layer having a power redistribution pad at an end thereof; a sub-signal interconnector connecting the signal redistribution pad to the substrate; a sub-power interconnector extending in a vertical direction under a portion of the power redistribution conductive layer to connect the power redistribution conductive layer to the substrate, the portion of the power redistribution conductive layer being located between the power redistribution pad and the sub-semiconductor chip; and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate or the sub-semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 It is an example Figure 1 A plan view of a portion of a semiconductor package is shown, in which a first main chip stack, a second main chip stack, and interconnectors connecting the first main chip stack and the second main chip stack are omitted.

[0008] Figure 3 , Figure 4 and Figure 5 It is an example Figure 1 A cross-sectional view of a semiconductor package.

[0009] Figure 6 It is along Figure 2 A cross-sectional view taken along line A1-A1'.

[0010] Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure.

[0011] Figure 7B : is a diagram for explaining the effect of the semiconductor package according to the comparative example.

[0012] Figure 8 is a plan view illustrating a portion of a semiconductor package according to another embodiment of the present disclosure.

[0013] Fig. 9 It is along Figure 8 A cross-sectional view taken along line A2-A2'.

[0014] Fig.10 is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure.

[0015] Fig.11 It is an example Fig.10 A plan view of a portion of a semiconductor package is shown, in which a first main chip stack, a second main chip stack, and interconnectors connecting the first main chip stack and the second main chip stack are omitted.

[0016] Fig.12 It is an example Fig.10 A cross-sectional view of a semiconductor package.

[0017] Fig.13 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0018] Fig.14A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0019] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate the specific features of the described embodiments. When a specific example in the drawings or descriptions is presented with two or more layers in a multilayer structure, the relative positioning relationship of these layers as shown or the order in which these layers are arranged reflects the specific implementation of the described or illustrated example, and different relative positioning relationships or the order in which these layers are arranged may be possible. In addition, the described or illustrated examples of multilayer structures may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0021] In the following description of the embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period of execution of the process or algorithm.

[0022] Figure 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 It is an example Figure 1 A plan view of a portion of a semiconductor package is shown, in which a first main chip stack, a second main chip stack, and interconnectors connecting the first main chip stack and the second main chip stack are omitted. Figures 3 to 5 It is an example Figure 1 A cross-sectional view of a semiconductor package. Figure 1 and Figure 2 They are top views of a semiconductor package and its parts respectively. Figure 3 Mainly illustrates Figure 1 A first main signal interconnector and a second main signal interconnector. Figure 4 Mainly illustrates Figure 1 a first main power interconnector and a second main power interconnector. Figure 5 Mainly illustrates Figure 1 Sub-signal interconnectors and sub-power interconnectors.

[0023] Reference Figures 1 to 5The semiconductor package may include a substrate 100 , a sub-semiconductor package 110 disposed over the substrate 100 , and a first main chip stack 120 and a second main chip stack 130 disposed over the sub-semiconductor package 110 .

[0024] The substrate 100 may be a substrate for a semiconductor package having a circuit and / or a wiring structure for transmitting an electrical signal, such as a printed circuit board (PCB).

[0025] The substrate 100 may have an upper surface, a lower surface located on the opposite side of the upper surface, and a side surface connecting the upper surface and the lower surface. The sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 may be arranged above the upper surface of the substrate 100. The external connection terminal 140 that connects the semiconductor package to an external device may be arranged above the lower surface of the substrate 100. For reference, the upper surface and the lower surface described below are expressions indicating the relative positions of the various surfaces of the components, rather than indicating the absolute positions. For example, in the case where the illustrated semiconductor package is inverted, the surface on which the sub-semiconductor package 110 and the first main chip stack 120 and the second main chip stack 130 are arranged may be the lower surface of the substrate 100, and the surface on which the external connection terminal 140 is arranged may be the upper surface of the substrate 100.

[0026] The substrate 100 may include an upper surface substrate pad 102 and a lower surface substrate pad 104. The upper surface substrate pad 102 may be disposed on the upper surface of the substrate 100 to electrically connect the sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 to the substrate 100. The lower surface substrate pad 104 may be disposed on the lower surface of the substrate 100 to electrically connect the external connection terminal 140 to the substrate 100. For reference, the substrate pad may refer to a conductive element or terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 to other components. As an example, the upper surface substrate pad 102 may be a bonding finger for wire bonding, and the lower surface substrate pad 104 may be a ball pad for bonding with a solder ball. The upper surface substrate pad 102 and the lower surface substrate pad 104 may be connected to a circuit and / or wiring structure inside the substrate 100.

[0027] The upper surface substrate pad 102 may include a sub-signal upper surface substrate pad 102S, a sub-power upper surface substrate pad 102P, a first main upper surface substrate pad 102M1, and a second main upper surface substrate pad 102M2. Figure 5102P, but will be described in more detail later. In addition to the sub-power supply upper surface substrate pad 102P, the upper surface substrate pad 102 may be provided at two side edges of the substrate 100 that do not overlap with the sub-semiconductor package 110. For example, the upper surface substrate pad 102 may be provided at two side edges of the substrate 100 in the first direction. For reference, the first side of the two sides in the first direction may correspond to Figure 1 and Figure 2 The upper side and Figures 3 to 5 In addition, the second side of the two sides in the first direction may correspond to Figure 1 and Figure 2 The lower side and Figures 3 to 5 The right side of the substrate 100. The sub-signal upper surface substrate pad 102S may be disposed at each of the two side edges of the substrate 100 in the first direction and may be electrically connected to the sub-semiconductor package 110. The first main upper surface substrate pad 102M1 may be disposed at the first side edge of the substrate 100 in the first direction and may be electrically connected to the first main chip stack 120. The second main upper surface substrate pad 102M2 may be disposed at the second side edge of the substrate 100 in the first direction and may be electrically connected to the second main chip stack 130. At the first side edge of the substrate 100 in the first direction, one or more sub-signal upper surface substrate pads 102S and one or more first main upper surface substrate pads 102M1 may be disposed at the desired position in the desired number and may be arranged spaced apart from each other in the second direction. At the second side edge of the substrate 100 in the first direction, one or more sub-signal upper surface substrate pads 102S and one or more second main upper surface substrate pads 102M2 may be disposed at the desired position in the desired number and may be arranged spaced apart from each other in the second direction.

[0028] The sub-semiconductor package 110 may have a planar area smaller than the upper surface of the substrate 100. The sub-semiconductor package 110 may be disposed to expose at least two side edges of the substrate 100 in the first direction and / or the upper surface substrate pad 102. As an example, the sub-semiconductor package 110 may be disposed in a central area of ​​the substrate 100. The sub-semiconductor package 110 may be attached to the upper surface of the substrate 100 using an insulating adhesive material (not shown) such as a die attach film (DAF).

[0029] The sub-semiconductor package 110 may include a sub-semiconductor chip 114, a sub-mold layer 116 surrounding the lower surface and side surfaces of the sub-semiconductor chip 114, and a redistribution structure 118 formed over the upper surfaces of the sub-semiconductor chip 114 and the sub-mold layer 116. Figure 1 and Figure 2 In the plan view of FIG. 1 , for the convenience of description, the redistribution insulation layers 118A and 118C of the redistribution structure 118 are omitted.

[0030] The sub-semiconductor chip 114 may be a semiconductor chip that performs various functions required for the operation of the first main chip stack 120 and / or the second main chip stack 130. In the present embodiment, the first main chip stack 120 and the second main chip stack 130 may include a non-volatile memory such as a NAND flash memory. In this case, the sub-semiconductor chip 114 may include a storage controller to control the operation of the first main chip stack 120 and the second main chip stack 130. However, the present embodiment is not limited thereto, and the sub-semiconductor chip 114 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM), a non-volatile memory such as a NAND flash memory, a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM), or other various active elements or passive elements.

[0031] The sub-semiconductor chip 114 may have a lower surface facing the upper surface of the substrate 100, an upper surface located on the opposite side of the lower surface, and a side surface connecting the upper surface to the lower surface. In the present embodiment, the sub-semiconductor chip 114 may have four side surfaces. The four side surfaces may be located on both sides in the first direction and on both sides in the second direction, respectively. For reference, the first side of the two sides in the second direction may correspond to Figure 1 and Figure 2 The second side of the two sides in the second direction may correspond to Figure 1 and Figure 2 on the left side.

[0032] The sub-semiconductor chip 114 may be located in a central region of the sub-semiconductor package 110. This is to make the lengths of signal redistribution conductive layers 118B-S, which will be described later, as similar as possible to each other.

[0033] A plurality of sub-chip pads 115 may be disposed on the upper surface of the sub-semiconductor chip 114. The sub-semiconductor chip 114 may have a relatively small plane area, and the number of the sub-chip pads 115 may be relatively large. When the first main chip stack 120 and the second main chip stack 130 include a memory and the sub-semiconductor chip 114 includes a memory controller, the size of the sub-semiconductor chip 114 may be reduced as technology develops. On the other hand, a large number of sub-chip pads 115 corresponding to a large number of input / output signals may be required to connect the corresponding first main chip stack 120 and the second main chip stack 130 to the sub-semiconductor chip 114 through independent channels. In order to meet this requirement, the sub-chip pads 115 may be arranged along the edges of all sides of the sub-semiconductor chip 114. That is, the sub-chip pads 115 may be arranged along the first side edge and the second side edge of the sub-semiconductor chip 114 in the first direction and along the third side edge and the fourth side edge of the sub-semiconductor chip 114 in the second direction.

[0034] The sub-molding layer 116 may have an upper surface having a height substantially the same as that of the upper surface of the sub-semiconductor chip 114 while surrounding the side surface of the sub-semiconductor chip 114. Therefore, the sub-molding layer 116 may expose the upper surfaces of the sub-semiconductor chip 114 and the sub-chip pad 115. In the present embodiment, the sub-molding layer 116 may cover the lower surface of the sub-semiconductor chip 114. However, the present embodiment is not limited thereto. In another embodiment, the sub-molding layer 116 may have a lower surface having a height substantially the same as that of the lower surface of the sub-semiconductor chip 114. The sub-molding layer 116 may include various molding materials such as epoxy molding compound (EMC).

[0035] The redistribution structure 118 may extend onto the upper surface of the sub-mold layer 116 while being electrically connected to the sub-chip pad 115. In other words, the sub-semiconductor package 110 according to the present embodiment may be a fan-out package.

[0036] The redistribution structure 118 may include a first redistribution insulating layer 118A, a redistribution conductive layer 118B, and a second redistribution insulating layer 118C. The first redistribution insulating layer 118A may cover the upper surfaces of the sub-semiconductor chip 114 and the sub-molding layer 116. The first redistribution insulating layer 118A may have an opening exposing the sub-chip pad 115 and the sub-power interconnector 119 (to be described later). The redistribution conductive layer 118B may be formed above the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected to the sub-chip pad 115 and the sub-power interconnector 119 through the opening of the first redistribution insulating layer 118A. The redistribution conductive layer 118B may include a signal redistribution layer 118B-S and a power redistribution layer 118B-P (to be described later). The second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B, while having an opening exposing a portion of the signal redistribution conductive layer 118B-S. The first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include an insulating material such as an oxide, a nitride, or a nitride oxide. Alternatively, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include a resin material such as epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, or acrylate. The redistribution conductive layer 118B may include a metal material such as gold, copper, or a copper alloy.

[0037] The signal redistribution conductive layers 118B-S may be used for signal transmission between the sub-semiconductor chip 114 and other components. As an example, the signal redistribution conductive layers 118B-S may be used for signal exchange between the sub-semiconductor chip 114 and the first main chip stack 120, between the sub-semiconductor chip 114 and the second main chip stack 130, or between the sub-semiconductor chip 114 and the substrate 100.

[0038] The plurality of signal redistribution conductive layers 118B-S may extend toward both side edges of the sub-mold layer 116 in the first direction. For reference, a first side edge among the side edges of the sub-mold layer 116 in the first direction may face the first side edge of the substrate 100, and a second side edge among the side edges of the sub-mold layer 116 in the first direction may face the second side edge of the substrate 100. As an example, the signal redistribution conductive layers 118B-S connected to the sub-chip pads 115 disposed at the first and third side edges of the sub-semiconductor chip 114 in the first and second directions, respectively, may extend to the first side edge of the sub-mold layer 116 in the first direction. In addition, the signal redistribution conductive layers 118B-S connected to the sub-chip pads 115 disposed at the second and fourth side edges of the sub-semiconductor chip 114 in the first and second directions, respectively, may extend to the second side edge of the sub-mold layer 116 in the first direction. The signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the second direction may have a shape bent toward both side edges of the sub-mold layer 116 in the first direction. Furthermore, the signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the first direction may not necessarily be bent. However, in order to have a length similar to that of the signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the second direction, the signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the first direction may also have a bent shape. As a result, the signal redistribution conductive layers 118B-S may have a spiral shape centered on the sub-semiconductor chip 114. Through this connection scheme, variations in the length of the signal redistribution conductive layers 118B-S may be reduced.

[0039] Based on the arrangement of the signal redistribution conductive layers 118B-S, the ends of the signal redistribution conductive layers 118B-S may be arranged along the second direction at the respective edges of the sub-mold layer 116 in the first direction. The second redistribution insulating layer 118C may have an opening exposing the ends of the signal redistribution conductive layers 118B-S. The portions of the signal redistribution conductive layers 118B-S exposed by the openings of the second redistribution insulating layer 118C will be referred to as signal redistribution pads 118BP-S hereinafter. The signal redistribution conductive layers 118B-S may extend from the sub-chip pads 115, and each of the signal redistribution conductive layers 118B-S may have a linear portion having a relatively small width and a plate-shaped end portion having a relatively large width while being located at the end of the linear portion. The opening of the second redistribution insulating layer 118C may expose the plate-shaped end portion of the signal redistribution conductive layer 118B-S, and may have a planar area less than or equal to the planar area of ​​the plate-shaped end portion while overlapping the plate-shaped end portion. The signal redistribution pads 118BP-S may be disposed at both side edges in the first direction of the sub-molding layer 116. In addition, the signal redistribution pads 118BP-S may be arranged along the second direction at respective side edges of the sub-molding layer 116 in the first direction.

[0040] The signal redistribution pad 118BP-S may be electrically connected to the substrate 100, the first main chip stack 120, or the second main chip stack 130. Specifically, the signal redistribution pad 118BP-S electrically connected to the substrate 100 may be electrically connected to the sub-signal upper surface substrate pad 102S through the sub-signal interconnector 117. One end of the sub-signal interconnector 117 may be connected to the signal redistribution pad 118BP-S, and the other end of the sub-signal interconnector 117 may be connected to the sub-signal upper surface substrate pad 102S. The sub-signal upper surface substrate pad 102S at the first side edge of the substrate 100 may be connected to the signal redistribution pad 118BP-S at the first side edge of the sub-molding layer 116. The sub-signal upper surface substrate pad 102S at the second side edge of the substrate 100 may be connected to the signal redistribution pad 118BP-S at the second side edge of the sub-molding layer 116. A bonding wire may be used as the sub-signal interconnector 117. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the sub-signal interconnectors 117. Connection between the first main chip stack 120 and the signal redistribution pad 118BP-S or between the second main chip stack 130 and the signal redistribution pad 118BP-S will be described later.

[0041] The power redistribution conductive layers 118B-P may be used to supply power from the substrate 100 to the sub-semiconductor chip 114. Various levels of power supply voltage or ground voltage may be supplied to the sub-semiconductor chip 114 through the power redistribution conductive layers 118B-P. Figure 3 and Figure 4 The cross-sectional view is not shown, only the Figure 5 In the cross-sectional view of Figure 1 In the plan view of FIG. 1 , the power redistribution conductive layer 118B-P is not visible because it is covered by the first main chip stack 120 and the second main chip stack 130. Therefore, the power redistribution conductive layer 118B-P is not visible. Figure 2 and Figure 5 The following description describes the power redistribution conductive layer 118B-P and the sub-power interconnector 119 and the sub-power upper surface substrate pad 102P connected thereto. Figure 2 and Figure 5 Together with reference to the diagram shown along Figure 2 The cross section taken along the line A1-A1' Figure 6 .

[0042] Reference Figure 2 , Figure 5 and Figure 6 , the power redistribution conductive layer 118B-P may be connected to the sub-chip pad 115 and may extend above the upper surface of the sub-molding layer 116. The power redistribution conductive layer 118B-P may have a shorter length than the signal redistribution conductive layer 118B-S. That is, unlike the signal redistribution conductive layer 118B-S, the power redistribution conductive layer 118B-P may not extend to the edge of the sub-molding layer 116. The power redistribution conductive layer 118B-P may be substantially parallel to a portion of an adjacent signal redistribution conductive layer 118B-S. This may prevent an electrical short circuit between the power redistribution conductive layer 118B-P and the signal redistribution conductive layer 118B-S.

[0043] The power redistribution conductive layer 118B-P may be electrically connected to the sub-power upper surface substrate pad 102P of the substrate 100 using a sub-power interconnector 119 disposed below the power redistribution conductive layer 118B-P. The sub-power interconnector 119 may include a penetration electrode 119A and a connection electrode 119B. The penetration electrode 119A may penetrate the sub-mold layer 116. The upper surface of the penetration electrode 119A may be connected to the power redistribution conductive layer 118B-P, and the lower surface of the penetration electrode 119A may be connected to the connection electrode 119B. For reference, in Figure 5 In the cross-sectional view of FIG. 1 , it appears that the through electrode 119A penetrates the sub-semiconductor chip 114. However, in reality, Figure 5 The sub-semiconductor chip 114 is shown behind the through electrode 119A. Figure 2 Floor plan and Figure 6As shown in the cross-sectional view of FIG. 1 , the penetration electrode 119A may penetrate the sub-mold layer 116 by being spaced apart from the sub-semiconductor chip 114 by a predetermined distance. In a plan view, the penetration electrode 119A may be located at any position as long as it overlaps and connects with a portion of the power redistribution conductive layer 118B-P while being spaced apart from the sub-semiconductor chip 114 by a predetermined distance. The connection electrode 119B may be disposed in a space between the sub-mold layer 116 and the substrate 100. The upper surface of the connection electrode 119B may be connected to the penetration electrode 119A, and the lower surface of the connection electrode 119B may be connected to the sub-power upper surface substrate pad 102P. The penetration electrode 119A may be a through hole having a relatively small width, and the connection electrode 119B may be a solder ball or a metal bump having a width greater than the penetration electrode 119A. However, the present embodiment is not limited thereto, and various types of electrical interconnectors extending from the power redistribution conductive layer 118B-P to the sub-power upper surface substrate pad 102P in a vertical direction may be used as the sub-power interconnector 119. Although not shown, an additional insulating layer may be disposed between the sub-mold layer 116 and the connection electrode 119B. An opening may be formed in the additional insulating layer to expose the penetration electrode 119A to be connected to the connection electrode 119B.

[0044] In addition, the connection electrode 119B may be inserted in the space between the sub-semiconductor package 110 and the substrate 100 to support the sub-semiconductor package 110. The height of the connection electrode 119B may be substantially the same as the distance between the sub-molding layer 116 and the substrate 100. The connection electrode 119B may be disposed to overlap with each power redistribution conductive layer 118B-P. Therefore, a plurality of connection electrodes 119B may be disposed at predetermined intervals along the periphery of the sub-semiconductor chip 114, and thus, the connection electrode 119B may fully support the sub-semiconductor package 110. In addition, a dummy connection electrode 119B' that is not connected to the penetration electrode 119A may be additionally disposed above the lower surface of the sub-molding layer 116. The dummy connection electrode 119B' may prevent the sub-semiconductor package 110 from tilting in one direction, or may withstand the pressure generated when the first main chip stack 120 and the second main chip stack 130 are mounted above the sub-semiconductor package 110.

[0045] Refer to Figures 1 to 5 , the first main chip stack 120 may include a plurality of first main semiconductor chips 124. The first main semiconductor chips 124 may be formed above the sub-semiconductor package 110, and may be stacked in a vertical direction with respect to the upper surface of the substrate 100. Although the present embodiment illustrates a case where the first main chip stack 120 includes four first main semiconductor chips 124, the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first main chip stack 120 may be variously modified to one or more first main semiconductor chips 124.

[0046] As described above, each first master semiconductor chip 124 may include a NAND flash memory. However, the present disclosure is not limited thereto, and each first master semiconductor chip 124 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM) or a non-volatile memory such as a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM).

[0047] The first main semiconductor chip 124 may be stacked with a predetermined offset in a direction toward the second side in the first direction. Figure 1 The lower side and Figures 3 to 5 . Thus, a first main chip stack 120 having a stepped shape when viewed as a whole may be formed. The offset stacking direction of the first main semiconductor chips 124 may be referred to as a first offset direction. Based on this offset stacking, a first side edge of an upper surface of each of the remaining first main semiconductor chips 124 except the uppermost first main semiconductor chip 124 among the first main semiconductor chips 124 may be exposed without being covered by the first main semiconductor chip 124 directly thereon. For example, Figure 1 The upper side edge of the upper surface of each of the remaining first main semiconductor chips 124 in Figure 3 The left side edge of the upper surface of each of the remaining first main semiconductor chips 124 in the stack may be exposed. The first side edge of the upper surface of the uppermost first main semiconductor chip 124 may be exposed without being covered by the lowermost second main semiconductor chip 134 of the second main chip stack 130 (to be described later). The first chip pads 125 may be disposed on these exposed portions of the first main semiconductor chips 124. A plurality of first chip pads 125 may be arranged in a row in the second direction at the first side edge of the upper surface of each first main semiconductor chip 124. However, the present disclosure is not limited thereto, and the number and arrangement of the first chip pads 125 at the first side edge of the upper surface of each first main semiconductor chip 124 may be modified differently. For reference, since in Figure 1 The portion of the first master chip stack 120 hidden by the second master chip stack 130 is not shown in the plan view, so the remaining portion of the first master chip stack 120 (eg, the first side edge of the lowermost first master semiconductor chip 124) is shown.

[0048] Each first main semiconductor chip 124 may be attached to the directly underlying sub semiconductor package 110 or the first main semiconductor chip 124 using the first adhesive layer 122. The first adhesive layer 122 may be formed on a lower surface of each first main semiconductor chip 124 to have a shape overlapping the lower surface.

[0049] The first main chip stack 120 or the first main semiconductor chip 124 may have a smaller plane area than the sub-semiconductor package 110, and may have a larger plane area than the sub-semiconductor chip 114. The first main chip stack 120 may be disposed to expose at least the signal redistribution pads 118BP-S disposed at both side edges in the first direction of the sub-semiconductor package 110. When the signal redistribution pads 118BP-S are exposed, direct connection (i.e., connection without passing through the substrate 100) between the first main chip stack 120 and the sub-semiconductor package 110 may be performed.

[0050] The first main chip stack 120 may be connected to the substrate 100 and the sub-semiconductor package 110 through the first main interconnector 127. In the present embodiment, the first main chip stack 120 may be electrically connected to the substrate 100 to receive power required for the operation of the first main chip stack 120 from the substrate 100. In addition, the first main chip stack 120 may be electrically connected to the sub-semiconductor package 110 to exchange signals with the sub-semiconductor chip 114. The interconnector connecting the first main chip stack 120 and the substrate 100 among the first main interconnectors 127 will be referred to as the first main power interconnector 127P. In addition, the interconnector connecting the first main chip stack 120 and the sub-semiconductor package 110 among the first main interconnectors 127 will be referred to as the first main signal interconnector 127S.

[0051] Specifically, refer to Figure 1 and Figure 3 , the first main signal interconnector 127S may connect adjacent first chip pads 125 to each other in the vertical direction, and may connect the first chip pad 125 of the lowermost first main semiconductor chip 124 to the signal redistribution pad 118BP-S provided at the first side edge in the first direction of the sub-mold layer 116. Therefore, the first main semiconductor chips 124 may be electrically connected to each other, and the first main chip stack 120 may be electrically connected to the sub-semiconductor package 110. In this case, the signal redistribution pad 118BP-S connected to the first main signal interconnector 127S may be distinguished from the signal redistribution pad 118BP-S connected to the above-mentioned sub-signal interconnector 117.

[0052] In addition, specifically, refer to Figure 1 and Figure 4 , the first main power interconnector 127P may connect adjacent first chip pads 125 to each other in a vertical direction, and may connect the first chip pad 125 of the lowermost first main semiconductor chip 124 to the first main upper surface substrate pad 102M1 of the substrate 100. Therefore, the first main semiconductor chips 124 may be electrically connected to each other, and the first main chip stack 120 may be electrically connected to the substrate 100.

[0053] The first main interconnector 127 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the first main interconnector 127 .

[0054] The second main chip stack 130 may include a plurality of second main semiconductor chips 134. The second main semiconductor chips 134 may be formed above the first main chip stack 120 and may be stacked in a vertical direction. Although the present embodiment illustrates a case where the second main chip stack 130 includes four second main semiconductor chips 134, the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second main chip stack 130 may be modified differently to one or more second main semiconductor chips 134. In addition, even if the present embodiment discloses that the number of second main semiconductor chips 134 included in the second main chip stack 130 is the same as the number of first main semiconductor chips 124 included in the first main chip stack 120, it should be noted that these numbers may be different from each other in other embodiments.

[0055] As described above, each second main semiconductor chip 134 may include a NAND flash memory. However, the present disclosure is not limited thereto, and each second main semiconductor chip 134 may include a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM) or a non-volatile memory such as a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM). In the present embodiment, the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124. However, in another embodiment, the second main semiconductor chip 134 may be different from the first main semiconductor chip 124.

[0056] The second main semiconductor chips 134 may be stacked with a predetermined offset in a direction toward the first side in the first direction. Figure 1 The upper side and Figures 3 to 5 . Thus, a second main chip stack 130 having a stepped shape when viewed as a whole may be formed. The offset stacking direction of the second main semiconductor chips 134 may be referred to as a second offset direction. The second offset direction may be opposite to the first offset direction. Based on this offset stacking, the second side edge of the upper surface of each of the remaining second main semiconductor chips 134 except the uppermost second main semiconductor chip 134 among the second main semiconductor chips 134 may be exposed without being covered by the second main semiconductor chip 134 directly thereon. For example, Figure 1 The lower side edge of the upper surface of each of the remaining second main semiconductor chips 134 in Figure 3The right side edge of the upper surface of each of the remaining second main semiconductor chips 134 in the uppermost second main semiconductor chip 134 may be exposed. The uppermost second main semiconductor chip 134 may be in a state where its entire upper surface is exposed. The second chip pads 135 may be arranged on the exposed portions of the remaining second main semiconductor chips 134 other than the uppermost second main semiconductor chip 134, and the second chip pads 135 of the uppermost second main semiconductor chip 134 may also be arranged at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. A plurality of second chip pads 135 may be arranged in a row in the second direction at the second side edge of the upper surface of each second main semiconductor chip 134. However, the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 may be modified differently.

[0057] In the case where the second main semiconductor chips 134 are identical to the first main semiconductor chips 124 , each of the second main semiconductor chips 134 may correspond to a state in which each of the first main semiconductor chips 124 is rotated 180 degrees around one axis extending in a vertical direction.

[0058] Each second main semiconductor chip 134 may be attached to the second main semiconductor chip 134 directly below or the uppermost first main semiconductor chip 124 of the first main chip stack 120 using the second adhesive layer 132. The second adhesive layer 132 may be formed on the lower surface of each second main semiconductor chip 134 to have a shape overlapping the lower surface.

[0059] The second main chip stack 130 or the second main semiconductor chip 134 may have a smaller plane area than the sub-semiconductor package 110, and may have a larger plane area than the sub-semiconductor chip 114. The second main chip stack 130 may be disposed to expose at least the signal redistribution pads 118BP-S disposed at both side edges in the first direction of the sub-semiconductor package 110. When the signal redistribution pads 118BP-S are exposed, direct connection between the second main chip stack 130 and the sub-semiconductor package 110 (i.e., connection without passing through the substrate 100) may be performed.

[0060] The second main chip stack 130 may be connected to the substrate 100 and the sub-semiconductor package 110 through the second main interconnector 137. In the present embodiment, the second main chip stack 130 may be electrically connected to the substrate 100 to receive power required for the operation of the second main chip stack 130 from the substrate 100. In addition, the second main chip stack 130 may be electrically connected to the sub-semiconductor package 110 to exchange signals with the sub-semiconductor chip 114. The interconnector connecting the second main chip stack 130 and the substrate 100 among the second main interconnectors 137 will be referred to as the second main power interconnector 137P. In addition, the interconnector connecting the second main chip stack 130 to the sub-semiconductor package 110 among the second main interconnectors 137 will be referred to as the second main signal interconnector 137S.

[0061] Specifically, refer to Figure 1 and Figure 3 , the second main signal interconnector 137S may connect the adjacent second chip pads 135 to each other in the vertical direction, and may connect the second chip pad 135 and the signal redistribution pad 118BP-S of the lowermost second main semiconductor chip 134 disposed at the second side edge of the sub-mold layer 116 in the first direction. Therefore, the second main semiconductor chips 134 may be electrically connected to each other, and the second main chip stack 130 may be electrically connected to the sub-semiconductor package 110. In this case, the signal redistribution pad 118BP-S connected to the second main signal interconnector 137S may be distinguished from the signal redistribution pad 118BP-S connected to the above-mentioned sub-signal interconnector 117.

[0062] In addition, specifically, refer to Figure 1 and Figure 4 , the second main power interconnector 137P may connect the adjacent second chip pads 135 to each other in the vertical direction, and may connect the second chip pad 135 of the lowermost second main semiconductor chip 134 to the second main upper surface substrate pad 102M2 of the substrate 100. Therefore, the second main semiconductor chips 134 may be electrically connected to each other, and the second main chip stack 130 may be electrically connected to the substrate 100.

[0063] The second main interconnector 137 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the second main interconnector 137 .

[0064] For reference, in Figure 1 and Figure 2 In the plan view of FIG. 1 , for convenience of description, the sub-package interconnector 117, the first main interconnector 127 and the second main interconnector 137 are shown by solid lines and dotted lines. However, it should be noted that these solid lines and dotted lines do not reflect the actual shapes of these interconnectors 117, 127 and 137.

[0065] The sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 may be covered by a mold layer 150 formed over the substrate 100. The mold layer 150 may include various molding materials such as EMC.

[0066] The external connection terminal 140 may include a solder ball. However, the present disclosure is not limited thereto, and various conductive terminals such as a bump may be used as the external connection terminal 140.

[0067] In the above-mentioned semiconductor package, the first main chip stack 120 can be identified as a single semiconductor chip while being connected to the substrate 100 and the sub-semiconductor package 110 through the first main interconnector 127. In addition, the second main chip stack 130 can be identified as another single semiconductor chip different from the first main chip stack 120 while being connected to the substrate 100 and the sub-semiconductor package 110 through the second main interconnector 137. The sub-semiconductor chip 114 can be connected to the substrate 100 through the redistribution structure 118, the sub-signal interconnector 117, and the sub-power interconnector 119.

[0068] Specifically, the first main chip stack 120 can be connected to the sub-semiconductor chip 114 through the first main signal interconnector 127S, the signal redistribution pad 118BP-S and the signal redistribution conductive layer 118B-S, so that the signal exchange between the first main chip stack 120 and the sub-semiconductor chip 114 can be performed. The second main chip stack 130 can be connected to the sub-semiconductor chip 114 through the second main signal interconnector 137S, the signal redistribution pad 118BP-S and the signal redistribution conductive layer 118B-S, so that the signal exchange between the second main chip stack 130 and the sub-semiconductor chip 114 can be performed. The sub-semiconductor chip 114 can be connected to the substrate 100 through the signal redistribution conductive layer 118B-S, the signal redistribution pad 118BP-S and the sub-signal interconnector 117, so that the signal exchange between the sub-semiconductor chip 114 and the substrate 100 can be performed. The signals between the first main chip stack 120 and the sub-semiconductor chip 114 and / or the signals between the second main chip stack 130 and the sub-semiconductor chip 114 may be internal signals transmitted inside the semiconductor package. On the other hand, the signals between the sub-semiconductor chip 114 and the substrate 100 may be external signals transmitted outside the semiconductor package.

[0069] In addition, the first main chip stack 120 can be connected to the substrate 100 through the first main power interconnector 127P, and thus, various levels of power such as ground voltage and power supply voltage can be received from the substrate 100. The second main chip stack 130 can be connected to the substrate 100 through the second main power interconnector 137P, and thus, various levels of power such as ground voltage and power supply voltage can be received from the substrate 100. The sub-semiconductor chip 114 can be connected to the substrate 100 through the power redistribution conductive layer 118B-P and the sub-power interconnector 119, and thus, various levels of power such as ground voltage and power supply voltage can be received from the substrate 100.

[0070] Based on the above-mentioned semiconductor package, the following advantages can be obtained.

[0071] First, since the sub-chip pads 115 are arranged along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 can be arranged compared to the size of the sub-semiconductor chip 114. In addition, by redistributing the sub-chip pads 115 using the fan-out technology, the arrangement of the sub-chip pads 115 can be relatively free. For example, if the bonding wire is directly connected to the sub-chip pads 115, the arrangement of the sub-chip pads 115 may be limited due to physical limitations such as the size and moving radius of the wire capillary. On the other hand, as in the present embodiment, if the sub-chip pads 115 are redistributed by the fan-out technology, the design will not be affected by these limitations.

[0072] In addition, since some sub-chip pads 115 are redistributed to signal redistribution pads 118BP-S using fan-out technology, and the signal redistribution pads 118BP-S can be directly connected to the first main signal interconnector 127S and the second main signal interconnector 137S, direct signal exchange between the sub-semiconductor chip 114 and the first main chip stack 120 and the second main chip stack 130 can be performed.

[0073] Furthermore, since the sub-semiconductor package 110 that is larger than the first and second main chip stacks 120 and 130 is disposed below the first and second main chip stacks 120 and 130 using the fan-out technology, the first and second main chip stacks 120 and 130 can be stably formed. In a structure in which the first and second main chip stacks 120 and 130 are formed above the sub-semiconductor chip 114, if the sub-semiconductor chip 114 is smaller than the first and second main semiconductor chips 124 and 134, a problem may occur due to the inclination of the first and second main chip stacks 120 and 130. Such a problem does not occur by significantly increasing the area of ​​the sub-semiconductor chip 114 through the fan-out technology.

[0074] In addition, by adjusting the shape and / or arrangement of the signal redistribution conductive layer 118B-S, the sub-chip pad 115 and the signal redistribution pad 118BP-S are connected so that the signal redistribution conductive layer 118B-S has a similar length, and the operating characteristics of the semiconductor package can be ensured. For example, when there is a first channel connected from the first main chip stack 120 to the substrate 100 and a second channel connected from the second main chip stack 130 to the substrate 100, the path of the first channel and the path of the second channel can have similar lengths. Therefore, the transmission rate of the signal (e.g., data) can be prevented from becoming different from channel to channel to the greatest extent.

[0075] In addition, since the length of the power redistribution conductive layer 118B-P is shorter than the length of the signal redistribution conductive layer 118B-S and the sub-power interconnector 119 extending in the vertical direction from the power redistribution conductive layer 118B-P connects the power redistribution conductive layer 118B-P and the substrate 100, power can be easily supplied to the sub-semiconductor chip 114. In this case, the length of the power supply path from the substrate 100 to the sub-semiconductor chip 114 can be shortened, and therefore, the impedance of the power supply path can be reduced. This will refer to Fig. 7A and Figure 7B Further description.

[0076] Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure, Figure 7B 1 is a diagram for explaining the effect of the semiconductor package according to the comparative example. Figure 7B It is illustrated that the power redistribution conductive layer is extended to the edge of the sub-molding layer similar to the signal redistribution conductive layer and is connected to the substrate through bonding wires.

[0077] Reference Fig. 7A , a relatively short current path can be formed (see the dotted arrow), which passes through the power redistribution conductive layer 118B-P with a shorter length, the sub-power interconnector 119 connected to the point of the power redistribution conductive layer 118B-P, and the substrate 100.

[0078] On the other hand, referring to Figure 7B , a relatively long current path (see the dotted arrow) can be formed, which passes through the power redistribution conductive layer 118B-P' with a longer length, the bonding wire 117' connected to the end of the power redistribution conductive layer 118B-P', and the substrate 100'.

[0079] As a result, according to this embodiment, Fig. 7A As shown, a short current path can be formed, and therefore, the impedance of the power supply path can be reduced. Therefore, power supply can be facilitated.

[0080] In addition, in the above embodiment, a case where one power redistribution conductive layer 118B-P is connected to one sub-power interconnector 119 is described. However, the present disclosure is not limited thereto, and one power redistribution conductive layer 118B-P may be connected to two or more sub-power interconnectors at the same time. This will be referred to as Figure 8 and Fig. 9 Further description.

[0081] Figure 8 is a plan view illustrating a portion of a semiconductor package according to another embodiment of the present disclosure, Fig. 9 It is along Figure 8 Parts substantially the same as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0082] Reference Figure 8 and Fig. 9 , one power redistribution conductive layer 118B-P may overlap and connect with two sub-power interconnectors 219 - 1 and 219 - 2 at the same time.

[0083] One of the two sub-power interconnectors 219-1 and 219-2 that is relatively close to the sub-semiconductor chip 114 will be referred to as the first sub-power interconnector 219-1, and the other of the two sub-power interconnectors 219-1 and 219-2 that is relatively far from the sub-semiconductor chip 114 will be referred to as the second sub-power interconnector 219-2. The first sub-power interconnector 219-1 and the second sub-power interconnector 219-2 may be arranged to be spaced apart from each other at a predetermined interval. The first sub-power interconnector 219-1 and the second sub-power interconnector 219-2 may be arranged in series along one power redistribution conductive layer 118B-P.

[0084] The first sub power interconnector 219-1 may include a penetration electrode 219A-1 and a connection electrode 219B-1. Likewise, the second sub power interconnector 219-2 may include a penetration electrode 219A-2 and a connection electrode 219B-2.

[0085] Through this embodiment, from one power redistribution conductive layer 118B-P, a current path passing through the first sub-power interconnector 219-1 and another current path passing through the second sub-power interconnector 219-2 can be formed. That is, multiple current paths can be formed. Therefore, the inductance of the power supply path can be reduced, and therefore, it is more convenient to supply power between the sub-semiconductor package 110 and the substrate 100.

[0086] In the present embodiment, two sub-power interconnectors 219 - 1 and 219 - 2 are illustrated, but the present disclosure is not limited thereto. Three or more sub-power interconnectors may overlap and connect with one power redistribution conductive layer 118B-P at the same time.

[0087] Furthermore, in the above-mentioned embodiment, a case where the power redistribution conductive layer 118B-P is shorter than the signal redistribution conductive layer 118B-S is described. However, the present disclosure is not limited thereto, and the power redistribution conductive layer may have the same length or a similar length as the signal redistribution conductive layer. In this case, by using a sub-power interconnector connected to a point of the power redistribution conductive layer, the power supply path to the sub-semiconductor chip can be shortened. This will be referred to Figures 10 to 12 Described exemplarily.

[0088] Fig.10 is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure. Fig.11 It is an example Fig.10 A plan view of a portion of a semiconductor package is shown, in which a first main chip stack, a second main chip stack, and interconnectors connecting the first main chip stack and the second main chip stack are omitted. Fig.12 It is an example Fig.10 A cross-sectional view of a semiconductor package. Fig.11 The line A3-A3' shows Fig.12 . Specifically, Fig.12 The left part of 310 shows a case where the additional sub power interconnector 319' is connected to the first main upper surface substrate pad 302M1 together with the first main power interconnector 327P. Fig.12 The right part of 310 shows a case where the additional sub power source interconnector 319' is connected to the additional sub power source upper surface substrate pad 302P'. Detailed description of parts substantially the same as those of the above-described embodiment will be omitted.

[0089] Reference Figures 10 to 12 The semiconductor package may include a substrate 300 , a sub-semiconductor package 310 disposed over the substrate 300 , and a first main chip stack 320 and a second main chip stack 330 disposed over the sub-semiconductor package 310 .

[0090] The substrate 300 may include an upper surface substrate pad 302 and a lower surface substrate pad 304. Here, the upper surface substrate pad 302 may include a sub-signal upper surface substrate pad 302S, a sub-power upper surface substrate pad 302P, a first main upper surface substrate pad 302M1, and a second main upper surface substrate pad 302M2. The arrangement of the sub-signal upper surface substrate pad 302S, the sub-power upper surface substrate pad 302P, the first main upper surface substrate pad 302M1, and the second main upper surface substrate pad 302M2 may be the same as in the above-mentioned embodiment. In addition, in the present embodiment, the upper surface substrate pad 302 may also include an additional sub-power upper surface substrate pad 302P'. The additional sub-power upper surface substrate pad 302P' may be arranged on two edges of the substrate 300 in the first direction. The additional sub-power upper surface substrate pad 302P' may be connected to the power redistribution conductive layer 318B-P (to be described later) by wire bonding. For the convenience of description, in Fig.10 and Fig.11 In the figure, the additional sub-power supply upper surface substrate pad 302P′ is hatched with oblique lines, unlike other upper surface substrate pads 302. The lower surface substrate pad 304 can be used to connect to the external connection terminal 340.

[0091] The sub-semiconductor package 310 may include a sub-semiconductor chip 314 , a sub-mold layer 316 surrounding side and lower surfaces of the sub-semiconductor chip 314 , and a redistribution structure 318 formed over upper surfaces of the sub-semiconductor chip 314 and the sub-mold layer 316 .

[0092] The redistribution structure 318 may extend over the upper surface of the sub-mold layer 316 while being electrically connected to the sub-chip pad 315 of the sub-semiconductor chip 314. The redistribution structure 318 may include a first redistribution insulating layer 318A, a redistribution conductive layer 318B, and a second redistribution insulating layer 318C.

[0093] The redistribution conductive layer 318B may include a signal redistribution conductive layer 318B-S and a power redistribution conductive layer 318B-P. In the present embodiment, all the redistribution conductive layers 318B may extend toward both edges of the sub-mold layer 316 in the first direction, regardless of the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P. As an example, the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P connected to the sub-chip pad 315 disposed at the first side edge and the third side edge of the sub-semiconductor chip 314 in the first direction and the second direction, respectively, may extend toward the first side edge of the sub-mold layer 316 in the first direction. In addition, the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P connected to the sub-chip pad 315 disposed at the second side edge and the fourth side edge of the sub-semiconductor chip 314 in the first direction and the second direction, respectively, may extend toward the second side edge of the sub-mold layer 316 in the first direction. As a result, the redistribution conductive layer 318B may have a spiral shape centered on the sub-semiconductor chip 314. Through this connection method, variation in the length of the redistribution conductive layer 318B may be reduced.

[0094] Based on the above arrangement of the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P, the ends of the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P may be arranged along the second direction at the respective side edges in the first direction of the sub-molded layer 316. The ends of the signal redistribution conductive layer 318B-S exposed through the opening of the second redistribution insulating layer 318C will be referred to as signal redistribution pads 318BP-S. In addition, the ends of the power redistribution conductive layer 318B-P exposed through the opening of the second redistribution insulating layer 318C will be referred to as power redistribution pads 318BP-P hereinafter. As a result, the signal redistribution pads 318BP-S and the power redistribution pads 318BP-P may be provided at both side edges in the first direction of the sub-molded layer 316. In addition, the signal redistribution pads 318BP-S and the power redistribution pads 318BP-P may be arranged along the second direction at respective side edges in the first direction of the sub-mold layer 316. For convenience of description, unlike the signal redistribution pads 318BP-S, the power redistribution conductive layers 318B-P and the power redistribution pads 318BP-P are hatched with oblique lines.

[0095] The signal redistribution pad 318BP-S may be electrically connected to the substrate 300, the first main chip stack 320 or the second main chip stack 330. Specifically, the signal redistribution pad 318BP-S electrically connected to the substrate 300 may be electrically connected to the sub-signal upper surface substrate pad 302S through the sub-signal interconnector 317.

[0096] The power redistribution conductive layer 318B-P may be electrically connected to the substrate 300 .

[0097] First, the power redistribution conductive layer 318B-P may be electrically connected to the sub-power upper surface substrate pad 302P of the substrate 300 through the sub-power interconnector 319 disposed thereunder. In a plan view, the sub-power interconnector 319 may overlap and connect with the power redistribution conductive layer 318B-P at a predetermined point between the sub-semiconductor chip 314 and the power redistribution pad 318BP-P. The predetermined point may be closer to the sub-semiconductor chip 314 than the power redistribution pad 318BP-P. This is to shorten the power supply path between the substrate 300 and the sub-semiconductor chip 314. The sub-power interconnector 319 may include a penetration electrode 319A penetrating the sub-mold layer 316 and a connection electrode 319B between the sub-mold layer 316 and the substrate 300. The undescribed reference numeral 319B' may represent a dummy connection electrode.

[0098] In addition, the power redistribution conductive layer 318B-P may be electrically connected to the substrate 300 via an additional sub-power interconnector 319' connected to the power redistribution pad 318BP-P. In this case, the additional sub-power interconnector 319' may be electrically connected to the additional sub-power upper surface substrate pad 302P' of the substrate 300. Alternatively, the additional sub-power interconnector 319' may be connected to the first main upper surface substrate pad 302M1 and / or the second main upper surface substrate pad 302M2 together with the first main power interconnector 327P and / or the second main power interconnector 337P, rather than being connected to the additional sub-power upper surface substrate pad 302P' (refer to Fig.10 and Fig.11 The P1 part and Fig.12 ). When the first main upper surface substrate pad 302M1 and / or the second main upper surface substrate pad 302M2 supplies a power supply of a specific level such as a ground voltage, and the power supply of the specific level is commonly used for the sub-semiconductor chip 314, the sub-semiconductor chip 314 can receive the power supply of the specific level from the substrate 300 through the additional sub-power interconnector 319' connected to the first main upper surface substrate pad 302M1 and / or the second main upper surface substrate pad 302M2, the power redistribution pad 318BP-P and the power redistribution conductive layer 318B-P. The additional sub-power interconnector 319' can be a bonding wire having one end connected to the power redistribution pad 318BP-P and the other end connected to one of the additional sub-power upper surface substrate pad 302P', the first main upper surface substrate pad 302M1, and the second main upper surface substrate pad 302M2.

[0099] The structure of the first main chip stack 320 and the connection relationship between the substrate 300 and the first main chip stack 320 and the sub-semiconductor package 310 and the first main chip stack 320 may be substantially the same as in the above-mentioned embodiment. In addition, the structure of the second main chip stack 330 and the connection relationship between the substrate 300 and the second main chip stack 330 and the sub-semiconductor package 310 and the second main chip stack 330 may be substantially the same as in the above-mentioned embodiment. The undescribed reference numerals 324, 322, 325, 327 and 327S may respectively represent the first main semiconductor chip, the first adhesive layer, the first chip pad, the first main interconnector and the first main signal interconnector. In addition, the undescribed reference numerals 334, 332, 335, 337 and 337S may respectively represent the second main semiconductor chip, the second adhesive layer, the second chip pad, the second main interconnector and the second main signal interconnector.

[0100] The sub-semiconductor package 310 , the first main chip stack 320 , and the second main chip stack 330 may be covered by a mold layer 350 formed over the substrate 300 .

[0101] According to the present embodiment, a first current path from one power redistribution conductive layer 318B-P through the sub-power interconnector 319 and a second current path from the one power redistribution conductive layer 318B-P through the additional sub-power interconnector 319' can be formed. That is, multiple current paths and short current paths can be formed. As a result, the impedance and inductance of the power supply path can be reduced, and therefore, power supply between the sub-semiconductor package 310 and the substrate 300 can be facilitated.

[0102] According to the above-described embodiments of the present disclosure, a large-capacity and multifunctional semiconductor package can be realized by forming a main chip stack having one or more main semiconductor chips over a sub-semiconductor package, and power supply to the sub-semiconductor package can be facilitated.

[0103] Fig.13 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments is shown. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0104] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0105] Fig.14 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a path for data movement.

[0106] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0107] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0108] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0109] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0110] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0111] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined in the following claims.

[0112] CROSS-REFERENCE TO RELATED APPLICATIONS

[0113] This application claims priority to Korean Patent Application No. 10-2020-0084680, filed on Jul. 9, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: substrate; a sub-semiconductor package disposed above the substrate, wherein the sub-semiconductor package comprises a sub-semiconductor chip having a chip pad on an upper surface thereof, a sub-molding layer surrounding a side surface of the sub-semiconductor chip, and a redistribution conductive layer connected to each of the chip pads and extending above the upper surface of the sub-molding layer, wherein the redistribution conductive layer comprises a signal redistribution conductive layer extending to an edge of the sub-molding layer, an end of the signal redistribution conductive layer having a signal redistribution pad, and the redistribution conductive layer comprises a power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer; a sub-signal interconnector connecting the signal redistribution pad to the substrate; a sub-power interconnector extending in a vertical direction below the power redistribution conductive layer to connect the power redistribution conductive layer to the substrate; and At least one main semiconductor chip is formed over the sub-semiconductor package and is electrically connected to the substrate or the sub-semiconductor chip.

2. The semiconductor package according to claim 1, wherein The sub-power interconnector comprises: a penetrating electrode, an upper surface of which is connected to the power redistribution conductive layer, and the penetrating electrode penetrates the sub-molding layer; and A connection electrode is disposed between the sub-molding layer and the substrate, the connection electrode having an upper surface connected to the penetration electrode and a lower surface connected to the substrate.

3. The semiconductor package according to claim 2, further comprising: A dummy connection electrode is provided between the sub-mold layer and the substrate and is not connected to the penetration electrode.

4. The semiconductor package according to claim 1, wherein: The sub-signal interconnects include bonding wires.

5. The semiconductor package according to claim 1, wherein A power supply path is formed through the power redistribution conductive layer, the sub-power interconnector, and the substrate.

6. The semiconductor package according to claim 1, wherein One power redistribution conductive layer is connected to two or more sub-power interconnectors, wherein the two or more sub-power interconnectors are spaced apart from each other.

7. The semiconductor package according to claim 1, wherein: The chip pad is arranged along a first side edge and a second side edge of the sub-semiconductor chip in a first direction, and along a third side edge and a fourth side edge of the sub-semiconductor chip in a second direction, wherein the second direction is perpendicular to the first direction. The signal redistribution pads include a plurality of signal redistribution pads disposed at a first side edge and a second side edge of the sub-molding layer in the first direction. Wherein, the signal redistribution conductive layer comprises a plurality of signal redistribution conductive layers, wherein some of the signal redistribution conductive layers connected to the chip pads disposed at the first side edge and the third side edge of the sub-semiconductor chip in the first direction and the second direction extend toward the signal redistribution pads disposed at the first side edge of the sub-molding layer in the first direction, and The remaining signal redistribution conductive layers connected to the chip pads disposed at the second side edge and the fourth side edge of the sub-semiconductor chip in the first direction and the second direction extend toward the signal redistribution pads disposed at the second side edge of the sub-molding layer in the first direction.

8. The semiconductor package according to claim 7, wherein: The signal redistribution conductive layer forms a spiral shape centered on the sub-semiconductor chip.

9. The semiconductor package according to claim 7, wherein: The substrate includes substrate pads disposed at a first side edge and a second side edge of the substrate in the first direction, Wherein, the sub-signal interconnector comprises a plurality of sub-signal interconnectors, and The sub-signal interconnector connects the signal redistribution pad disposed at the first side edge of the sub-molding layer in the first direction to the substrate pad disposed at the first side edge of the substrate in the first direction, and connects the signal redistribution pad disposed at the second side edge of the sub-molding layer in the first direction to the substrate pad disposed at the second side edge of the substrate in the first direction.

10. The semiconductor package according to claim 1, wherein The at least one main semiconductor chip includes a memory, and the sub-semiconductor chip includes a memory controller.

11. The semiconductor package according to claim 1, wherein The substrate includes substrate pads disposed at a first side edge and a second side edge of the substrate in a first direction, and Wherein, the at least one main semiconductor chip comprises: at least one first master semiconductor chip connected to the substrate pad disposed at the first side edge of the substrate through a first master interconnector; and At least one second master semiconductor chip is connected to the substrate pad disposed at the second side edge of the substrate through a second master interconnector.

12. The semiconductor package according to claim 11, wherein The at least one first main semiconductor chip includes a plurality of first main semiconductor chips stacked offset from the first side edge of the substrate toward the second side edge of the substrate in the first direction, and The at least one second main semiconductor chip includes a plurality of second main semiconductor chips offset and stacked from the second side edge of the substrate toward the first side edge of the substrate in the first direction.

13. The semiconductor package according to claim 7, wherein: The at least one main semiconductor chip comprises: at least one first main semiconductor chip connected to the signal redistribution pad disposed at the first side edge of the sub-molding layer in the first direction through a first main interconnector; and At least one second main semiconductor chip is connected to the signal redistribution pad disposed at the second side edge of the sub-molding layer in the first direction through a second main interconnector.

14. The semiconductor package according to claim 13, wherein: The signal redistribution pad is not covered by the first main semiconductor chip and the second main semiconductor chip.

15. A semiconductor package, comprising: substrate; a sub-semiconductor package disposed above the substrate, wherein the sub-semiconductor package comprises a sub-semiconductor chip having a chip pad on an upper surface thereof, a sub-molding layer surrounding a side surface of the sub-semiconductor chip, and a redistribution conductive layer connected to each of the chip pads and extending to an edge of the sub-molding layer, wherein the redistribution conductive layer comprises a signal redistribution conductive layer having a signal redistribution pad at an end thereof and a power redistribution conductive layer having a power redistribution pad at an end thereof; a sub-signal interconnector connecting the signal redistribution pad to the substrate; a sub-power interconnector extending in a vertical direction under a portion of the power redistribution conductive layer to connect the power redistribution conductive layer to the substrate, the portion of the power redistribution conductive layer being located between the power redistribution pad and the sub-semiconductor chip; and At least one main semiconductor chip is formed over the sub-semiconductor package and is electrically connected to the substrate or the sub-semiconductor chip.

16. The semiconductor package according to claim 15, wherein: The sub power interconnector is disposed closer to the sub semiconductor chip than to the power redistribution pad.

17. The semiconductor package according to claim 15, further comprising: An additional sub-power interconnector connects the power redistribution pad to the substrate.

18. The semiconductor package according to claim 17, wherein: The additional sub-power interconnector includes bonding wires.

19. The semiconductor package according to claim 17, wherein: forming a first power supply path passing through the power redistribution conductive layer, the sub-power interconnector and the substrate, and Wherein, a second power supply path is formed passing through the power redistribution conductive layer, the power redistribution pad, the additional sub-power interconnector and the substrate.

20. The semiconductor package according to claim 15, wherein The chip pad is arranged along a first side edge and a second side edge of the sub-semiconductor chip in a first direction and along a third side edge and a fourth side edge of the sub-semiconductor chip in a second direction, wherein the second direction is perpendicular to the first direction. The signal redistribution pad includes a plurality of signal redistribution pads, and the power redistribution pad includes a plurality of power redistribution pads, and the signal redistribution pad and the power redistribution pad are arranged at a first side edge and a second side edge of the sub-molding layer in the first direction. Wherein, the signal redistribution conductive layer includes a plurality of signal redistribution conductive layers, and the power redistribution conductive layer includes a plurality of power redistribution conductive layers, wherein some of the signal redistribution conductive layers and some of the power redistribution conductive layers connected to the chip pads disposed at the first side edge and the third side edge of the sub-semiconductor chip in the first direction and the second direction extend toward the signal redistribution pads and the power redistribution pads disposed at the first side edge of the sub-molding layer in the first direction, and Wherein, the remaining signal redistribution conductive layers and the remaining power redistribution conductive layers connected to the chip pads arranged at the second side edge and the fourth side edge of the sub-semiconductor chip in the first direction and the second direction extend toward the signal redistribution pads and the power redistribution pads arranged at the second side edge of the sub-molding layer in the first direction.

21. The semiconductor package according to claim 20, wherein: The signal redistribution conductive layer and the power redistribution conductive layer form a spiral shape centered on the sub-semiconductor chip.

22. The semiconductor package according to claim 20, wherein The substrate includes a plurality of substrate pads disposed at a first side edge and a second side edge of the substrate in the first direction, Wherein, the sub-signal interconnector comprises a plurality of sub-signal interconnectors, and The sub-signal interconnector connects the signal redistribution pad disposed at the first side edge of the sub-molding layer in the first direction to the substrate pad disposed at the first side edge of the substrate in the first direction, and connects the signal redistribution pad disposed at the second side edge of the sub-molding layer in the first direction to the substrate pad disposed at the second side edge of the substrate in the first direction.

23. The semiconductor package according to claim 22, further comprising: an additional sub-power interconnector, the additional sub-power interconnector connecting the power redistribution pad to the substrate, Wherein, the additional sub-power interconnector connects the power redistribution pad arranged at the first side edge of the sub-molding layer in the first direction to the substrate pad arranged at the first side edge of the substrate in the first direction, and connects the power redistribution pad arranged at the second side edge of the sub-molding layer in the first direction to the substrate pad arranged at the second side edge of the substrate in the first direction.

24. The semiconductor package according to claim 23, wherein: The at least one main semiconductor chip comprises: at least one first main semiconductor chip connected to the substrate pad disposed at the first side edge of the substrate in the first direction through a first main interconnector; and at least one second main semiconductor chip connected to the substrate pad disposed at the second side edge of the substrate in the first direction through a second main interconnector, wherein at least one of the plurality of substrate pads disposed at the first side edge of the substrate in the first direction is commonly connected to the additional sub-power interconnector and the first main interconnector, and Wherein, at least one of the plurality of substrate pads disposed at the first side edge of the substrate in the second direction is commonly connected to the additional sub-power interconnector and the second main interconnector.

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