A method for preparing a solar cell and a solar cell

Abstract

The present invention discloses a method for preparing a solar cell and a solar cell. The method for preparing the solar cell comprises: locally forming a tunneling silicon oxide layer and an N-type doped polysilicon layer on the front side of a P-type silicon substrate, wherein the N-type doped polysilicon layer is stacked on the tunneling silicon oxide layer; immersing the P-type silicon substrate on which the tunneling silicon oxide layer and the N-type doped polysilicon layer are locally formed on the front side into an electroplating solution, and applying light of a set duration on the front side of the P-type silicon substrate to grow a front metal electrode on the N-type doped polysilicon layer, and etching away the metal remaining on the front side of the P-type silicon substrate, wherein the width of the front metal electrode is consistent with the width of the N-type doped polysilicon layer. The preparation method can avoid the alignment operation in the metal electrode preparation process, thereby effectively reducing the difficulty of the local passivation contact emitter preparation process.

Description

Technical Field

[0001] The invention relates to a method for preparing a solar cell and the solar cell. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a tunnel oxide passivated contact solar cell technology based on the principle of selective carriers. It prepares an ultra-thin layer of silicon oxide on the back of the cell, and then deposits a thin layer of doped silicon. The two together form a passivated contact structure, which effectively reduces surface recombination and metal contact recombination. However, since the doped silicon thin layer is mainly polycrystalline silicon, the optical absorption coefficient of polycrystalline silicon is larger than that of crystalline silicon. Therefore, this passivated contact structure is generally applied to the back of solar cells. If TOPCon is applied to the front of the solar cell, the light irradiated to the front of the crystalline silicon solar cell will be excessively absorbed in this layer of polycrystalline silicon film, thereby significantly reducing the light absorption of the crystalline silicon substrate in the absorption layer.

[0003] When TOPCon is applied to the front of a solar cell, in order to eliminate parasitic absorption of light, a local passivation contact / emitter structure is usually used, that is, tunneling silicon oxide and polysilicon thin films are deposited only in the metal gate area, but not in other areas. At present, the preparation of the local passivation contact / emitter structure is mainly to set a local tunneling oxide passivation layer and a polysilicon layer on the surface of the silicon substrate by masking, and to prepare the front metal electrode in the area where the tunneling oxide passivation layer and the polysilicon layer are located by screen printing technology. In the process of preparing the front metal electrode by screen printing technology, it is necessary to align it with the local tunneling oxide passivation layer and the polysilicon layer. However, due to the structural errors of the local tunneling oxide passivation layer and the polysilicon layer set by masking, it is difficult to achieve precise alignment by screen printing, resulting in a relatively difficult process for preparing the local passivation contact emitter. Summary of the invention

[0004] In view of this, the technical problem to be solved by the present invention is to provide a method for preparing a solar cell and a solar cell, which can avoid the alignment operation in the metal electrode preparation process, thereby effectively reducing the difficulty of the local passivation contact emitter preparation process.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a locally passivated contact emitter, comprising:

[0007] Step 101, locally forming a tunneling silicon oxide layer and an N-type doped polysilicon layer on the front surface of a P-type silicon substrate, wherein the N-type doped polysilicon layer is stacked on the tunneling silicon oxide layer;

[0008] Step 102, immersing the P-type silicon substrate on which the tunneling silicon oxide layer and the N-type doped polysilicon layer are locally formed on the front side into an electroplating solution, and applying light for a set time to the front side of the P-type silicon substrate to grow a front metal electrode on the N-type doped polysilicon layer, and etching away the metal remaining on the front side of the P-type silicon substrate, wherein the width of the front metal electrode is consistent with the width of the N-type doped polysilicon layer.

[0009] In a second aspect, an embodiment of the present invention provides a solar cell, which is prepared by using the preparation method provided according to the first aspect.

[0010] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: the method for preparing a solar cell provided by the embodiment of the present invention, by immersing a P-type silicon substrate with a tunneling silicon oxide layer and an N-type doped polysilicon layer locally formed on the front side into an electroplating solution, and applying light of a set length of time on the front side of the P-type silicon substrate, growing a front metal electrode on the N-type doped polysilicon layer, that is, using a light-induced electroplating method to grow a front metal electrode on the front N-type doped polysilicon layer, and a metal electrode can be grown on the front N-type doped polysilicon layer, because when a solar cell with a P-type substrate forming a PN junction is placed in an electroplating solution When light is applied to the N-type doped polysilicon layer on the front side of the emitter region, due to the photovoltaic effect of the solar cell, the photogenerated carriers are separated under the action of the built-in electric field, wherein the electrons gather on the N-type doped polysilicon layer, diffuse to the surface, and transfer the electrons to the metal ions in the electroplating solution, and the metal ions are reduced on the N-type doped polysilicon layer, thereby plating a layer of metal on the N-type doped polysilicon layer to form a metal electrode, that is, the N-type doped polysilicon layer is combined with the front metal electrode grown on the front N-type doped polysilicon layer by the light-induced electroplating method, so that the front metal electrode can be electronically realized during the growth process. The trace amount of metal grown on the P-type silicon substrate that is not covered by the tunneling silicon oxide layer and the N-type doped polysilicon layer can be removed by etching back technology, so that the process of preparing the front metal electrode can be prepared without the need to calibrate the local formation of the tunneling silicon oxide layer and the N-type doped polysilicon layer, thereby effectively reducing the difficulty of the local passivation contact emitter preparation process.

[0011] In addition, since the N-type doped polysilicon layer is combined with the front metal electrode grown on the front N-type doped polysilicon layer by a light-induced electroplating method, the front metal electrode can be electronically connected during the growth process without the need for an external electric field or an additional metal electrode seed layer, further reducing the process difficulty. The preparation method has simple steps and is easy to implement.

[0012] In addition, the tunneling silicon oxide layer and the N-type doped polysilicon layer are combined to grow a front metal electrode on the front N-type doped polysilicon layer through a light-induced electroplating method, so that the width of the front metal electrode can be consistent with the width of the N-type doped polysilicon layer, which can effectively avoid the loss of short-circuit current Isc and increase the open circuit voltage Voc. Therefore, the solar cell provided in the embodiment of the present invention can effectively improve the efficiency of the solar cell.

[0013] In addition, the front metal grown on the front N-type doped polysilicon layer by light-induced electroplating has the same width as the N-type doped polysilicon layer, which can reduce the series resistance of the solar cell and increase the fill factor of the solar cell, thereby further improving the efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic flow chart of a method for preparing a solar cell according to the present invention;

[0015] Figure 2 It is a schematic diagram of the structure of growing a tunneling silicon oxide layer on the front side of a P-type silicon substrate according to the present invention;

[0016] Figure 3 is a schematic diagram of a structure of forming an N-type doped polysilicon layer on a tunneling silicon oxide layer according to the present invention;

[0017] Figure 4 is a schematic diagram of a structure in which a patterned mask according to the present invention covers an N-type doped polysilicon layer;

[0018] Figure 5 is a plan view schematically showing a patterned mask according to the present invention;

[0019] Figure 6 is a schematic diagram of the structure after the N-type doped polysilicon layer in the area not covered by the mask is removed according to the present invention;

[0020] Figure 7 is a schematic diagram of the structure after removing the tunneling silicon oxide layer in the area not covered by the mask and the mask according to the present invention;

[0021] Figure 8 is a schematic diagram of a local passivation contact emitter metallization structure according to the present invention;

[0022] Fig. 9 is a schematic diagram of a local passivation contact emitter metallization structure as a copper electrode according to the present invention;

[0023] Fig.10 is a schematic diagram of a local passivation contact emitter metallization structure as a silver electrode according to the present invention;

[0024] Fig.11It is a schematic diagram of the process of growing a front metal electrode on a front N-type doped polysilicon layer according to the present invention;

[0025] Fig.12 is a schematic diagram of a local passivation contact emitter metallization structure of a nickel electrode and a copper electrode according to the present invention;

[0026] Fig.13 is a schematic diagram of a local passivation contact emitter metallization structure of a nickel electrode and a silver electrode according to the present invention;

[0027] Fig.14 It is a schematic diagram of the process of growing a front metal electrode on a front N-type doped polysilicon layer according to the present invention;

[0028] Fig.15 is a schematic diagram of a local passivation contact emitter metallization structure of a nickel electrode, a copper electrode and a silver electrode according to the present invention;

[0029] Fig.16 According to the present invention Figure 8 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0030] Fig.17 According to the present invention Fig. 9 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0031] Fig.18 According to the present invention Fig.10 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0032] Fig.19 According to the present invention Fig.12 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0033] Fig. 20 According to the present invention Fig.13 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0034] Fig.21 According to the present invention Fig.15 The structure shown is a schematic diagram of a structure in which a P+ type doping layer is formed on the back side;

[0035] Fig. 22 According to the present invention Figure 8 The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0036] Fig.23 According to the present invention Fig. 9The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0037] Fig.24 According to the present invention Fig.10 The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0038] Fig.25 According to the present invention Fig.12 The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0039] Fig.26 According to the present invention Fig.13 The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0040] Fig. 27 According to the present invention Fig.15 The structure shown is a schematic diagram of a structure in which a tunneling silicon oxide layer and a P-type doped polysilicon layer are sequentially formed on the back side;

[0041] Fig.28 According to the present invention Fig.16 The structure shown forms a schematic diagram of the back metal electrode structure;

[0042] Fig.29 According to the present invention Fig.17 The structure shown forms a schematic diagram of the back metal electrode structure;

[0043] Fig.30 According to the present invention Fig.18 The structure shown forms a schematic diagram of the back metal electrode structure;

[0044] Fig.31 According to the present invention Fig.19 The structure shown forms a schematic diagram of the back metal electrode structure;

[0045] Fig.32 According to the present invention Fig. 20 The structure shown forms a schematic diagram of the back metal electrode structure;

[0046] Fig.33 According to the present invention Fig.21 The structure shown forms a schematic diagram of the back metal electrode structure;

[0047] Fig.34 According to the present invention Fig. 22 The structure shown forms a schematic diagram of the back metal electrode structure;

[0048] Fig.35According to the present invention Fig.23 The structure shown forms a schematic diagram of the back metal electrode structure;

[0049] Fig.36 According to the present invention Fig.24 The structure shown forms a schematic diagram of the back metal electrode structure;

[0050] Fig.37 According to the present invention Fig.25 The structure shown forms a schematic diagram of the back metal electrode structure;

[0051] Fig.38 According to the present invention Fig.26 The structure shown forms a schematic diagram of the back metal electrode structure;

[0052] Fig.39 According to the present invention Fig. 27 The structure shown forms a schematic diagram of the back metal electrode structure.

[0053] The reference numerals are as follows:

[0054] 10-P-type silicon substrate; 20-tunneling silicon oxide layer; 30-N-type doped polysilicon layer; 40-front metal electrode; 41-metal nickel electrode; 42-metal copper electrode; 43-metal silver electrode; 50-mask; 60-P+ type doped layer; 70-P-type doped polysilicon layer; 80-back electrode. DETAILED DESCRIPTION

[0055] When TOPCon (Tunnel Oxide Passivated Contact) technology is applied to the front of the battery, in order to eliminate parasitic absorption of light, a local passivated contact / emitter structure is usually used, that is, the tunneling silicon oxide layer and the polysilicon layer are deposited only in the area where the metal gate line (metal electrode) is located, and not in other areas. This brings up a problem, how to make a localized (also called patterned) passivated contact / emitter structure. The first solution currently used to make a localized passivated contact / emitter structure is to use photolithography. Although it can achieve perfect graphics, the disadvantage is that it is very expensive and not suitable for industrialization. The second solution to make a localized passivated contact / emitter structure is to use a masking agent to make a patterned tunneling silicon oxide and polysilicon layer, and then use a screen printing process to prepare a metal electrode on the polysilicon layer. The advantage of the second solution is that it is suitable for industrialization, but the disadvantage is that it is difficult to make fine graphics. In the process of preparing metal electrodes using screen printing technology, due to the working principle of the screen printing process and the errors in graphics, the patterned polysilicon layer needs to be aligned with the screen printing for a second time, which increases the difficulty of the process. In addition, the production of metal electrodes by screen printing also requires the assistance of an external electric field, which increases the preparation process and preparation cost.

[0056] In order to solve the problems existing in the above-mentioned process of preparing metal electrodes, an embodiment of the present invention provides a method for preparing a solar cell. Figure 1 Schematic diagram of the main process of the preparation method of solar cells. Figure 1 As shown, the method for preparing the solar cell may include the following steps:

[0057] Step S101, forming a tunneling silicon oxide layer and an N-type doped polysilicon layer locally on the front surface of a P-type silicon substrate, wherein the N-type doped polysilicon layer is stacked on the tunneling silicon oxide layer;

[0058] Among them, the front side of the P-type silicon substrate refers to the side of the P-type silicon substrate facing the sunlight after the P-type silicon substrate is used to make a solar cell, that is, the light-receiving side of the P-type silicon substrate that receives sunlight. On the contrary, the back side of the P-type silicon substrate refers to the side facing away from the sunlight, that is, the backlight side opposite to the light-receiving side of the P-type silicon substrate.

[0059] For step S101, specific implementations may include:

[0060] First, a whole layer of tunneling silicon oxide layer 20 is grown on the front side of the P-type silicon substrate 10. The thickness of the tunneling silicon oxide layer 20 can be any value between 0.5 and 2 nm, for example, 0.5 nm, 0.7 nm, 0.9 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc. In a preferred embodiment, the width of the tunneling silicon oxide layer 20 is any value between 5 and 30 μm. In a more preferred embodiment, the width of the tunneling silicon oxide layer 20 is any value between 5 and 20 μm. This range of thickness and width can effectively reduce the lateral resistance and the light-shielding property of the tunneling silicon oxide layer 20 while ensuring that the solar cell preparation process is relatively simple. Among them, Figure 2 A schematic diagram of the structure of growing a tunneling silicon oxide layer on the front side of a P-type silicon substrate is shown.

[0061] Then, a whole layer of N-type doped polysilicon layer 30 is formed on the tunneling silicon oxide layer 20 grown on the front side, wherein the width of the N-type doped polysilicon layer 30 is consistent with the tunneling silicon oxide layer 20, which can effectively reduce the lateral resistance and the light shielding property of the N-type doped polysilicon layer 30 while further ensuring that the solar cell preparation process is relatively simple. Figure 3 A schematic structural diagram of forming an N-type doped polysilicon layer on a tunneling silicon oxide layer is shown.

[0062] Furthermore, a patterned mask 50 is disposed on the N-type doped polysilicon layer 30. The mask 50 may include: SiO x Thin film, SiN xThe schematic diagram of the structure in which the patterned mask 50 covers the N-type doped polysilicon layer 30 can be as shown in FIG. Figure 4 As shown; the plan view of the patterned mask 50 may be as shown Figure 5 As shown. Figure 4 As shown, the patterned masks 50 are spaced apart from each other, and the spacing between the tunneling silicon oxide layers 20 and the spacing between the N-type doped polysilicon layers 30 can be controlled by controlling the spacing between the patterned masks 50. The spacing between the tunneling silicon oxide layers 20 refers to the spacing between adjacent side surfaces of two adjacent tunneling silicon oxide layers 20; the spacing between the N-type doped polysilicon layers 30 refers to the spacing between adjacent side surfaces of two adjacent N-type doped polysilicon layers 30; and accordingly, the spacing between the metal electrodes 40 mentioned later refers to the spacing between adjacent side surfaces of two adjacent metal electrodes 40.

[0063] Then, the N-type doped polysilicon layer 30 in the area not covered by the mask 50 is removed by using an alkaline solution, wherein: Figure 6 A schematic diagram of the structure after removing the N-type doped polysilicon layer 30 in the area not covered by the mask 50 is shown; after removing the N-type doped polysilicon layer 30 in the area not covered by the mask 50, the width of the N-type doped polysilicon layer 30 in the area covered by the mask 50 can be 5 to 50 μm, for example, 5 μm, 10 μm, 12 μm, 15 μm, 17 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.

[0064] The alkaline solution is generally KOH, NaOH solution, etc., and its concentration and duration of action can be adjusted according to actual needs. For example, a KOH solution can be selected, wherein the ratio of KOH: deionized water is 3:11, the corrosion time is 5 minutes, and the corrosion temperature is 70°C.

[0065] After etching away the N-type doped polysilicon layer in the area not covered by the mask 50, an acid solution is used to remove the tunneling silicon oxide layer 20 in the area not covered by the mask 50, and the mask 50 is removed at the same time, wherein: Figure 7 The schematic diagram of the structure after removing the tunneling silicon oxide layer 20 and the mask 50 in the area not covered by the mask 50 is shown. After removing the tunneling silicon oxide layer 20 in the area not covered by the mask 50, the width of the tunneling silicon oxide layer 20 is consistent with that of the N-type doped polysilicon layer 30.

[0066] The acid solution is generally an HF solution, and the concentration and duration of the HF solution can be adjusted according to actual needs. For example, the ratio of HF to deionized water in the HF solution is 2:3, the corrosion time is greater than or equal to 10 seconds, and the corrosion temperature is room temperature.

[0067] Step S102, immersing the P-type silicon substrate with a tunneling silicon oxide layer and an N-type doped polysilicon layer locally formed on the front side into an electroplating solution, applying light for a set time to the front side of the P-type silicon substrate, growing a front metal electrode on the front side N-type doped polysilicon layer, and removing the residual metal on the front side of the P-type silicon substrate by etching, wherein the width of the front metal electrode is consistent with the width of the N-type doped polysilicon layer.

[0068] When the P-type silicon substrate 10 is immersed in the electroplating solution and light is applied to the front of the P-type silicon substrate for a set period of time, due to the photovoltaic effect of the solar cell, the photogenerated carriers are separated under the action of the built-in electric field, among which the electrons are gathered on the N-type doped polycrystalline silicon layer and diffused to the surface, and the metal ions in the electroplating solution are replaced by the electrons gathered on the surface of the N-type doped polycrystalline silicon layer into metal atoms and deposited on the surface of the N-type doped polycrystalline silicon layer, thereby plating a layer of metal on the N-type doped polycrystalline silicon layer to form a metal electrode.

[0069] Therefore, the set duration of the illumination can be in the order of milliseconds, seconds, etc. The specific set duration can be determined based on parameters such as the concentration of metal ions contained in the electroplating solution and the thickness of the metal electrode.

[0070] When a metal electrode is grown on the upper surface of the N-type doped polysilicon layer by a light-induced plating method, a small amount of metal will remain on the exposed P-type silicon substrate that is not covered by the N-type doped polysilicon layer and the tunneling silicon oxide layer. The metal remaining on the P-type silicon substrate is removed by an etch-back technique. The etch-back technique can use a physical method such as ion etching or a chemical method such as an etch-back solution to remove the metal remaining on the P-type silicon substrate. Due to the light-induced effect, the metal mainly forms a metal electrode on the N-type doped polysilicon layer, and there is only a trace amount of metal in the area outside the N-type doped polysilicon layer. Therefore, the etch-back technique generally acts on the P-type silicon substrate for a duration of milliseconds or seconds. In this case, the metal on the P-type silicon substrate can be removed without affecting the metal electrode on the N-type doped polysilicon layer 30.

[0071] Among them, when using the etching liquid to etch back the metal on the P-type silicon substrate 10, different etching liquids can be selected according to different metals. For example, for metal nickel, the optional etching liquid can be a mixed acid solution of nitric acid and hydrochloric acid, or a mixed solution formed by nitric acid and ferric chloride; for metal copper, the optional etching liquid can be a mixed solution of sulfuric acid and hydrogen peroxide; for metal silver, the optional etching liquid can be a hydrochloric acid solution or a HNO3 solution. It is worth noting that when using the etching liquid to etch back the metal on the P-type silicon substrate 10, the etching temperature, time, solution concentration and other parameters can be adjusted according to actual needs.

[0072] Through step S102, the following can be obtained: Figure 8 Schematic diagram of the locally passivated contact emitter metallization structure shown.

[0073] According to the difference in the types of the front metal electrode, step S102 can be implemented in several different ways.

[0074] When the front metal electrode is a metal, such as a metal copper electrode or a metal silver electrode, a first implementation of step S102 may include the following steps:

[0075] Step S2-11, immersing the P-type silicon substrate 10 with the tunneling silicon oxide layer 20 and the N-type doped polysilicon layer 30 partially formed on the front side into an electroplating solution containing copper ions or silver ions, and applying light for a set time to the front side of the P-type silicon substrate 10, growing a metal copper electrode or a metal silver electrode on the N-type doped polysilicon layer 30,

[0076] Step S2-12, removing the metal copper or metal silver on the P-type silicon substrate 10 by etching. The schematic diagram of the local passivation contact emitter metallization structure formed by the first implementation manner can be shown as follows: Fig. 9 and Fig.10 As shown. Due to the existence of the N-type doped polysilicon layer 30, the metallic copper or metallic silver grown by the light-induced electroplating method mainly exists in the N-type doped polysilicon layer 30, and the metallic copper or metallic silver grown on the N-type doped polysilicon layer 30 can be directly electrified under the light-induced electroplating method, that is, directly form a metal electrode without the need for a metal seed layer or an external electric field. In addition, since there is only a trace amount of metallic copper or metallic silver on the P-type silicon substrate 10, the etch-back technology can be used to remove the only trace amount of metallic copper or metallic silver on the P-type silicon substrate 10 by controlling the etch-back time (the time can be adjusted according to actual conditions), without having much effect on the metallic copper or metallic silver grown on the N-type doped polysilicon layer 30.

[0077] The front metal electrode is made of two metals, such as a nickel electrode and a copper electrode or a nickel electrode and a silver electrode. Fig.11 As shown, the second implementation of step S102 may include the following steps:

[0078] Step S1021, immersing a P-type silicon substrate having a tunneling silicon oxide layer and an N-type doped polysilicon layer partially formed on the front side into an electroplating solution containing nickel ions, and applying light for a set time to the front side of the P-type silicon substrate to grow a metal nickel electrode on the N-type doped polysilicon layer;

[0079] Generally, the total electrode height is controlled between 10 and 35 μm. The thickness of the metal nickel electrode 41 on the N-type doped polysilicon layer 30 is generally 1 to 2 μm, for example, 1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2 μm, etc.

[0080] Step S1022, removing the metal nickel on the P-type silicon substrate by etching;

[0081] Step S1023, immersing the P-type silicon substrate with the metal nickel electrode in an electroplating solution containing copper ions or silver ions, and applying light for a set time to the front of the P-type silicon substrate to grow a metal copper electrode or a metal silver electrode on the metal nickel electrode;

[0082] The thickness of the metal copper electrode 42 or the metal silver electrode 43 is generally any value between 8 and 34 μm. In a preferred embodiment, the thickness of the metal copper electrode 42 or the metal silver electrode 43 is between 10 and 15 μm.

[0083] Step S1024, removing the metal copper or metal silver on the P-type silicon substrate by etching.

[0084] The local passivation contact emitter metallization structure obtained through the above steps S1021 to S1024 can be as follows Fig.12 or Fig.13 shown.

[0085] For the front metal electrode, there are three kinds of metals, such as metal nickel electrode, metal copper electrode and metal nickel electrode. Fig.14 As shown, the third implementation of step S102 may include the following steps:

[0086] Step S1021', immersing the P-type silicon substrate with a tunneling silicon oxide layer and an N-type doped polysilicon layer partially formed on the front side into an electroplating solution containing nickel ions, and applying light for a set time to the front side of the P-type silicon substrate to grow a metal nickel electrode on the N-type doped polysilicon layer;

[0087] Step S1022', removing the metal nickel on the P-type silicon substrate by etching;

[0088] Step S1023', immersing the P-type silicon substrate with the metal nickel electrode in an electroplating solution containing copper ions, and applying light for a set time to the front of the P-type silicon substrate to grow a metal copper electrode on the metal nickel electrode;

[0089] Step S1024', removing the metal copper on the P-type silicon substrate by etching;

[0090] Step S1025', immersing the P-type silicon substrate superimposed with the metal nickel electrode and the metal copper electrode in an electroplating solution containing silver ions, and applying light for a set time to the front side of the P-type silicon substrate to grow a metal silver electrode on the metal copper electrode;

[0091] Step S1026 ′, removing the metallic silver on the P-type silicon substrate by etching.

[0092] In the third implementation, the thickness of the metal nickel electrode 41 is generally between 1 and 2 μm. The thickness of the metal copper electrode 42 is generally between 6 and 33 μm. The thickness of the metal silver electrode 43 is generally between 1 and 2 μm. In a preferred embodiment, the thickness of the metal copper electrode 42 is between 10 and 15 μm.

[0093] The optimized thickness of the metal electrode in the local passivation contact emitter metallization structure obtained by the third implementation is Ni / Cu / Ag=2 / 15 / 2.

[0094] The local passivation contact emitter metallization structure obtained by the third implementation can be as follows Fig.15 shown.

[0095] With respect to the second and third implementations described above, by adding a metal nickel electrode, the adhesion of the metal copper electrode or the metal silver electrode can be effectively improved, and the risk of the metal copper electrode or the metal silver electrode falling off can be effectively reduced.

[0096] In addition, the reason why back etching is performed after each photoinduced electroplating method is that, on the one hand, since the etching solution and etching conditions of each metal are different, a targeted back etching is performed after each photoinduced electroplating method to ensure the integrity of the back etching and avoid damage to the grown metal electrode; on the other hand, if the residual metal on the P-type silicon substrate is not etched back during the next photoinduced electroplating, the residual metal will form a metal seed layer during the next photoinduced electroplating, accelerating the metal growth rate in this area during photoinduction and increasing the difficulty of etching.

[0097] The first to third implementations can all make the spacing between the front metal electrodes 100 to 2000 μm. It is worth noting that the spacing between the front metal electrodes can be determined by the spacing between the N-type doped polysilicon layers 30 distributed on the front of the P-type silicon substrate 10, that is, the spacing between the N-type doped polysilicon layers 30 is also any value between 100 and 2000 μm, for example, 100 μm, 200 μm, 300 μm, 500 μm, 700 μm, 800 μm, 900 μm, 1000 μm, 1200 μm, 1500 μm, 1800 μm, 2000 μm.

[0098] Users can choose one of the above three implementation methods to prepare metal electrodes according to their needs, thereby improving the flexibility, selectivity and usability of the local passivation contact emitter preparation method.

[0099] The solar cell preparation method provided by the embodiment of the present invention immerses the P-type silicon substrate with a tunneling silicon oxide layer and an N-type doped polysilicon layer locally formed on the front side into an electroplating solution, and applies light of a set length of time on the front side of the P-type silicon substrate to grow a front metal electrode on the N-type doped polysilicon layer, that is, a light-induced electroplating method is used to grow a front metal electrode on the front N-type doped polysilicon layer, and a metal electrode can be grown on the front N-type doped polysilicon layer. This is because, when a solar cell chip with a P-type substrate forming a PN junction is placed in an electroplating solution, when the N-type doped polysilicon layer on the front side of the emitter region is When light is applied to the crystalline silicon layer, due to the photovoltaic effect of the solar cell, the photogenerated carriers are separated under the action of the built-in electric field, wherein the electrons gather on the N-type doped polysilicon layer, diffuse to the surface, and transfer the electrons to the metal ions in the plating solution, thereby reducing the metal ions on the N-type doped polysilicon layer, plating a layer of metal on the N-type doped polysilicon layer, and forming a metal electrode, that is, the N-type doped polysilicon layer is combined with the front metal electrode grown on the front N-type doped polysilicon layer by the light-induced electroplating method, so that the front metal electrode can be electronically realized during the growth process. The trace amount of metal grown on the P-type silicon substrate that is not covered by the tunneling silicon oxide layer and the N-type doped polysilicon layer can be removed by etching such as etch-back technology, so that the process of preparing the front metal electrode can be prepared without the need to calibrate the local formation of the tunneling silicon oxide layer and the N-type doped polysilicon layer, thereby effectively reducing the difficulty of the local passivation contact emitter preparation process.

[0100] In addition, since the N-type doped polysilicon layer is combined with the front metal electrode grown on the front N-type doped polysilicon layer by a light-induced electroplating method, the front metal electrode can be electronically connected during the growth process without the need for an external electric field or an additional metal electrode seed layer, further reducing the process difficulty. The preparation method has simple steps and is easy to implement.

[0101] In addition, the tunneling silicon oxide layer and the N-type doped polysilicon layer are combined to grow a front metal electrode on the front N-type doped polysilicon layer through a light-induced electroplating method, so that the width of the front metal electrode can be consistent with the width of the N-type doped polysilicon layer. This structure is applied to solar cells, which can effectively avoid the loss of short-circuit current Isc and increase the open-circuit voltage Voc. Therefore, the local passivated contact emitter obtained by the method for preparing a local passivated contact emitter provided in an embodiment of the present invention is applied to solar cells, which can effectively improve the efficiency of solar cells.

[0102] In addition, the front metal grown on the front N-type doped polysilicon layer by light-induced electroplating has the same width as the N-type doped polysilicon layer, which can reduce the series resistance of the solar cell and increase the fill factor of the solar cell, thereby further improving the efficiency of the solar cell.

[0103] In the solar cell preparation method provided in the embodiment of the present invention, in order to further improve the electronic induction of the metal electrode, the method may further include the following two specific implementation steps.

[0104] The first specific implementation method is: before the above step S102, it also includes forming a P+ type doping layer 60 on the back of the P-type silicon substrate 10. The step of forming the P+ type doping layer 60 on the back of the P-type silicon substrate 10 can be before the above step S101, or after the above step S101. Figure 8 The structure shown is formed after forming a P+ type doped layer on the back side. Fig.16 The structure shown; Fig. 9 The structure shown is formed after forming a P+ type doped layer on the back side. Fig.17 The structure shown; Fig.10 The structure shown is formed after forming a P+ type doped layer on the back side. Fig.18 The structure shown; Fig.12 The structure shown is formed after forming a P+ type doped layer on the back side. Fig.19 The structure shown; Fig.13 The structure shown is formed after forming a P+ type doped layer on the back side. Fig. 20 The structure shown; Fig.15 The structure shown is formed after forming a P+ type doped layer on the back side. Fig.21 It should be noted that the P+ type doped layer refers to a P type doped layer and the doping concentration is greater than the doping concentration of the P type silicon substrate.

[0105] The second specific implementation method is: before the above step S102, it also includes sequentially forming a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 on the back of the P-type silicon substrate 10. The step of sequentially forming the tunneling silicon oxide layer 20 and the P-type doped polysilicon layer 70 on the back of the P-type silicon substrate 10 can be before the above step S101 or after the above step S101. Figure 8 The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig. 22 The structure shown; Fig. 9 The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig.23 The structure shown; Fig.10 The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig.24 The structure shown; Fig.12 The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig.25 The structure shown; Fig.13The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig.26 The structure shown; Fig.15 The structure shown in the figure is formed after a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 are sequentially formed on the back side. Fig. 27 The structure shown.

[0106] By adding the first specific implementation or the second specific implementation before the step S102, the electronic induction of the metal electrode can be effectively improved, thereby ensuring the efficiency of the solar cell.

[0107] In the embodiment of the present invention, before or after the above step S102, N-type doping may be performed in the area outside the local passivation / metallization structure on the front side of the P-type silicon substrate 10 to form an N-type doped junction in the area outside the local passivation / metallization structure on the front side of the P-type silicon substrate 10. The dopant required to form the N-type doped junction may be introduced into the area outside the local passivation / metallization structure on the front side of the P-type silicon substrate 10 by ion implantation, diffusion, laser doping, etc.

[0108] In addition, the embodiment of the present invention provides a method for preparing a solar cell, which further includes the step of providing a back metal electrode. Specifically, a metal electrode is provided on the surface of a P+ type doped layer on the back of a P-type silicon substrate, or a back electrode is provided on the surface of a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 sequentially provided on the back of a P-type silicon substrate.

[0109] exist Fig.16 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.28 The structure shown; Fig.17 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.29 The structure shown; Fig.18 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.30 The structure shown; Fig.19 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.31 The structure shown; Fig. 20 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.32 The structure shown; Fig.21 The P+ doped layer 60 shown in the figure is provided with a back metal electrode 80 on its surface. Fig.33 The structure shown.

[0110] exist Fig. 22 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.34 The structure shown; Fig.23 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.35 The structure shown; Fig.24 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.36 The structure shown; Fig.25 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.37 The structure shown; Fig.26 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.38 The structure shown; Fig. 27 The tunneling silicon oxide layer 20 and the surface of the P-type doped polysilicon layer 70 are formed to form a back metal electrode 80. Fig.39 The structure shown.

[0111] Another aspect of the present invention also includes a solar cell prepared by the above solar cell preparation method.

[0112] The method for preparing a solar cell and the solar cell obtained therefrom provided by the present invention are described in detail with reference to several specific embodiments.

[0113] Example 1

[0114] Step (A1), providing a P-type silicon substrate 10.

[0115] Step (B1), growing a tunneling silicon oxide layer 20 with a thickness of 1 to 2 nm on the front side of the P-type silicon substrate 10 by a high temperature thermal oxidation method, Figure 2 The structure shown; preferably, the thickness of the tunneling silicon oxide layer 20 is 1.5 to 2 nm.

[0116] Step (C1), forming intrinsic polysilicon on the front tunneling silicon oxide layer 20 by LPCVD / PVD, then performing boron diffusion and annealing, and then forming an N-type doped polysilicon layer 30 with a thickness of 100 to 200 nm, to obtain Figure 3 In the structure shown in FIG. 1 , in a preferred embodiment, the thickness of the N-type doped polysilicon layer 30 is between 100 nm and 150 nm.

[0117] Step (D1), a patterned mask 50 is provided on the N-type doped polysilicon layer 30 to obtain Figure 4 The structure shown; the plane pattern of the mask 50 is as shown Figure 5 As shown. Mask 50 is SiOx 、SiN x Or one of the SiON films.

[0118] Step (E1), using an alkaline solution to remove the N-type doped polysilicon layer 30 in the area not covered by the mask 50, to obtain Figure 6 For example, an alkaline solution with a ratio of KOH to deionized water of 3:11 is used for corrosion for 5 minutes at a temperature of 70°C.

[0119] Step (F1), using HF solution to remove the tunneling silicon oxide layer 20 and the mask 50 in the area not covered by the mask 50, to obtain a patterned tunneling silicon oxide layer / N-type doped polysilicon layer with a width of W=5 μm and a spacing of L=100 μm, such as Figure 7 The structure shown.

[0120] Step (G1), the obtained step (F1) Figure 7 The structure shown in FIG. 1 is immersed in an electroplating solution, and light is irradiated on the front side of the P-type silicon substrate 10 having the N-type doped polysilicon layer 30, and a metal electrode 40 is grown on the front side of the N-type doped polysilicon layer 30. Then, a mixture of sulfuric acid and hydrogen peroxide is used to etch back the trace metal remaining on the front side of the P-type silicon substrate 10, and the trace metal except for the N-type doped polysilicon layer 30 region is removed, and the structure shown in FIG. 1 is shown in FIG. Figure 8 The structure shown.

[0121] Example 2

[0122] Step (A2) is consistent with step (A1) provided in Example 1.

[0123] In step (B2), a tunneling silicon oxide layer 20 is grown on the front surface of the P-type silicon substrate 10 by a nitric acid oxidation method.

[0124] Step (C2) forms intrinsic polysilicon on the front tunneling silicon oxide layer 20 by ion implantation, and then performs boron doping and annealing to form an N-type doped polysilicon layer 30.

[0125] Steps (D2) to (F2) are consistent with steps (D1) to (F1) provided in Example 1, except that in step (F2), a patterned tunneling silicon oxide layer / N-type doped polysilicon layer with a width of W=10 μm and a spacing of L=500 μm is obtained.

[0126] Add step (G02) after step (F2).

[0127] Step (G02), forming a P+ type doped layer on the back side of the P type silicon substrate 10.

[0128] Step (G2), immersing the structure obtained in step (G02) into an electroplating solution containing nickel ions, and irradiating the front side of the P-type silicon substrate 10 having the N-type doped polysilicon layer 30 with light, growing a metal nickel electrode 41 on the front side N-type doped polysilicon layer 30, and etching back the trace nickel on the front side of the P-type silicon substrate 10 with a mixed acid composed of nitric acid and hydrochloric acid to remove the trace metal nickel on the front side of the P-type silicon substrate 10; then continuing to immerse the P-type silicon substrate 10 on which the metal nickel electrode 41 has been grown into an electroplating solution containing copper ions, and irradiating the front side of the P-type silicon substrate 10 having the N-type doped polysilicon layer 30 with light, growing a metal copper electrode 42 on the metal nickel electrode 41, and etching back the trace copper on the front side of the P-type silicon substrate 10 with a mixed solution of sulfuric acid and hydrogen peroxide to remove the trace metal copper on the front side of the P-type silicon substrate 10, to obtain the structure as shown in FIG. Fig.19 The structure shown.

[0129] Example 3

[0130] Step (A3) to step (G03) of this embodiment are consistent with step (A2) to step (G02) provided in Example 2.

[0131] Step (G3), immersing the structure obtained in step (G03) into an electroplating solution containing nickel ions, and irradiating the front side of the P-type silicon substrate 10 with the N-type doped polysilicon layer 30 with light, growing a metal nickel electrode 41 on the front side N-type doped polysilicon layer 30, and etching back the trace nickel on the front side of the P-type silicon substrate 10 with a mixed acid composed of nitric acid and hydrochloric acid to remove the trace metal nickel on the front side of the P-type silicon substrate 10; then continuing to immerse the P-type silicon substrate 10 on which the metal nickel electrode 41 is grown into an electroplating solution containing copper ions, and irradiating the front side of the P-type silicon substrate 10 with light, growing a metal copper electrode 42 on the metal nickel electrode 41, and etching back the trace nickel on the front side of the P-type silicon substrate 10 with a mixed acid composed of sulfuric acid and hydrogen peroxide. Finally, the P-type silicon substrate 10 on which the metal nickel electrode 41 and the metal copper electrode are grown is immersed in an electroplating solution containing silver ions, and the front side of the P-type silicon substrate 10 having the N-type doped polysilicon layer 30 is irradiated with light, a metal silver electrode 43 is grown on the metal copper electrode 42, and the trace silver on the front side of the P-type silicon substrate 10 is etched back by using an HCI solution or an HNO3 solution to remove the trace metal silver on the front side of the P-type silicon substrate 10, thereby obtaining a Fig.21 The structure shown.

[0132] Example 4

[0133] The steps of this embodiment are consistent with the steps of Embodiment 2, except that an N-type doped polysilicon layer with a thickness of 200 μm is formed in step (C4); and a patterned tunneling silicon oxide layer / N-type doped polysilicon layer with a width of W=40 μm and a spacing of L=800 μm is obtained in step (F4).

[0134] Example 5

[0135] Steps (A5) to (F5) of this embodiment are consistent with those of Embodiment 3, except that an N-type doped polysilicon layer with a thickness of 150 μm is formed in step (C5); and a patterned tunneling silicon oxide layer / N-type doped polysilicon layer with a width of W = 20 μm and a spacing of L = 400 μm is obtained in step (F5).

[0136] Step (G05), forming a tunneling silicon oxide layer 20 and a P-type doped polysilicon layer 70 on the back side of the P-type silicon substrate 10.

[0137] Step (G5) is consistent with step (G2) of Example 2, and the following is obtained: Fig. 27 The structure shown.

[0138] Example 6

[0139] Steps (A6) to (G6) of this embodiment are consistent with those of Embodiment 3, except that in step (F5), a patterned tunneling silicon oxide layer / N-type doped polysilicon layer with a width of W=50 μm and a spacing of L=1000 μm is obtained.

[0140] Example 7

[0141] Step (A7) to step (G7) are consistent with step (A1) to step (G1) of Example 1; and new steps (H7) and (I7) are added after step (G7).

[0142] Step (H7), forming a P+ type doped layer on the back side of the P type silicon substrate 10.

[0143] Step (I7), prepare a back metal electrode 80 on the P+ type doped layer on the back side of the P type silicon substrate 10, and obtain Fig.28 The solar cell structure shown.

[0144] Example 8

[0145] Steps (A8) to (G8) are consistent with steps (A2) to (G2) of Example 2; and a new step (H8) is added after step (G8).

[0146] Step (H8), prepare a back metal electrode 80 on the P+ type doped layer on the back side of the P type silicon substrate 10, and obtain Fig.31 The solar cell structure shown.

[0147] Example 9

[0148] Steps (A9) to (G9) are consistent with steps (A3) to (G3) of Example 3; and a new step (H9) is added after step (G9).

[0149] Step (H9), prepare a back metal electrode 80 on the P+ type doped layer on the back side of the P type silicon substrate 10, and obtain Fig.33 The solar cell structure shown.

[0150] Example 10

[0151] Step (A10) to step (G10) are consistent with step (A5) to step (G5) of Example 5; and a new step (H10) is added after step (G10).

[0152] Step (H10), preparing a back metal electrode 80 on the P-type doped polysilicon layer 70 on the back of the P-type silicon substrate 10, Fig.39 The solar cell structure shown.

[0153] The introduction provided in the above steps is only used to help understand the method, structure and core idea of ​​the present invention. For ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also belong to the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: Step 101, locally forming a tunneling silicon oxide layer (20) and an N-type doped polysilicon layer (30) on the front surface of a P-type silicon substrate (10), wherein the N-type doped polysilicon layer (30) is stacked on the tunneling silicon oxide layer (20); Step 102, immersing the P-type silicon substrate (10) on which the tunneling silicon oxide layer (20) and the N-type doped polysilicon layer (30) are partially formed on the front side into an electroplating solution, and applying light for a set time to the front side of the P-type silicon substrate (10) to grow a front metal electrode (40) on the N-type doped polysilicon layer (30), and removing the metal remaining on the front side of the P-type silicon substrate (10) by etching, wherein the width of the front metal electrode is consistent with the width of the N-type doped polysilicon layer (30); The step 102 includes: Step 1021, immersing the P-type silicon substrate (10) having the tunneling silicon oxide layer (20) and the N-type doped polysilicon layer (30) locally formed on the front side into an electroplating solution containing nickel ions, applying light for a set time to the front side of the P-type silicon substrate (10), and growing a metal nickel electrode (41) on the N-type doped polysilicon layer (30); Step 1022, removing the residual metal nickel on the P-type silicon substrate (10) by etching back technology; Step 1023, immersing the P-type silicon substrate (10) having the metal nickel electrode (41) in an electroplating solution containing copper ions or an electroplating solution containing silver ions, and applying light for a set time to the front side of the P-type silicon substrate (10), so as to grow a metal copper electrode (42) or a metal silver electrode (43) on the metal nickel electrode (41); Step 1024, removing the metal copper or metal silver remaining on the P-type silicon substrate (10) by etching back technology; or, The step 102 includes: Step S1021', immersing the P-type silicon substrate (10) having the tunneling silicon oxide layer (20) and the N-type doped polysilicon layer (30) locally formed on the front side into an electroplating solution containing nickel ions, applying light for a set time to the front side of the P-type silicon substrate (10), and growing a metal nickel electrode (41) on the N-type doped polysilicon layer (30); Step S1022', removing the metal nickel remaining on the P-type silicon substrate (10) by etching back technology; Step S1023', immersing the P-type silicon substrate (10) having the metal nickel electrode (41) in an electroplating solution containing copper ions, and applying light for a set time to the front side of the P-type silicon substrate (10), so as to grow a metal copper electrode (42) on the metal nickel electrode (41); Step S1024', removing the metal copper remaining on the P-type silicon substrate (10) by etching back technology; Step S1025', immersing the P-type silicon substrate (10) on which the metal nickel electrode (41) and the metal copper electrode (42) are superimposed into an electroplating solution containing silver ions, and applying light for a set time to the front side of the P-type silicon substrate (10) to grow a metal silver electrode (43) on the metal copper electrode (42); Step S1026', removing the residual metallic silver on the P-type silicon substrate (10) by etching back technology.

2. The method for preparing a solar cell according to claim 1, characterized in that: The step 101 comprises: Step 1-1, growing a whole layer of tunneling silicon oxide layer (20) on the front side of the P-type silicon substrate (10); Step 1-2, forming a whole layer of N-type doped polysilicon layer (30) on the whole layer of the tunneling silicon oxide layer (20) grown on the front side; Step 1-3, providing a patterned mask (50) on the entire N-type doped polysilicon layer (30); Step 1-4, removing the N-type doped polysilicon layer (30) in the area not covered by the mask (50) using an alkaline solution; Step 1-5, using an acid solution to remove the tunneling silicon oxide layer (20) in the area not covered by the mask (50), and removing the mask (50).

3. The method for preparing a solar cell according to claim 2, characterized in that: The mask (50) in step 1-3 comprises: SiO x Thin film, SiN x Any of a thin film and a SiON thin film.

4. The method for preparing a solar cell according to claim 1, characterized in that: The tunneling silicon oxide layer (20) and the N-type doped polysilicon layer (30) formed in step 101 have a width of 5 to 50 μm.

5. The method for preparing a solar cell according to claim 1, characterized in that: Before step 102, the method further includes: A P+ type doping layer (60) is formed on the back side of the P type silicon substrate (10).

6. The method for preparing a solar cell according to claim 1, characterized in that: Before step 102, the method further includes: A tunneling silicon oxide layer (20) and a P-type doped polysilicon layer (70) are sequentially formed on the back side of the P-type silicon substrate (10).

7. A solar cell, characterized in that: The method is prepared according to any one of claims 1 to 6.

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