Memory system design for reducing signal integrity crosstalk using asymmetry

Abstract

An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system-on-chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to the parallel memory interface via parallel signal traces (dmi0, dq0-dq7) arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, for a majority of the parallel signal traces, the signal traces are arranged according to a variable spacing (b1>b2>b3>b4) between the parallel signal traces.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Non-Provisional Application No. 16 / 442,208, filed on June 14, 2019, entitled “MEMORY SYSTEM DESIGN FORSIGNAL INTEGRITY CROSSTALK REDUCTION WITH ASYMMETRY,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to integrated communication systems and, more particularly, to memory system designs for reducing signal integrity crosstalk using asymmetry. Background Art

[0004] Electrical connections exist at each level of the system hierarchy. The system hierarchy includes interconnections from active devices at the lowest system level all the way to system-level interconnections at the highest level. For example, interconnection layers can connect different devices on an integrated circuit together. As integrated circuits become more and more complex, a large number of interconnection layers are specified to provide electrical connections between devices. Recently, due to the large number of devices interconnected in modern electronic devices, the number of interconnection levels for circuit devices has increased significantly. The increased number of interconnection levels used to support the increased number of devices involves more intricate processes.

[0005] These interconnect layers can provide transmission line structures for interconnecting integrated circuit (IC) devices in high-frequency circuit designs. For example, high-frequency circuit designs can use transmission lines (e.g., traces) to support high-speed interfaces. Traditional interconnect traces are manufactured on printed circuit boards (PCBs) to support communication between devices on the PCB. For example, a system-on-chip (SoC) die can communicate with external memory using a parallel memory interface.

[0006] For example, the parallel memory interface may include a low power double data rate (LPDDR) memory interface configured in an LPDDR parallel interface with a single-ended data channel. The SI (signal integrity) of these parallel traces plays a vital role in LPDDR performance. Unfortunately, SI is affected by crosstalk (xtalk), ISI (inter-symbol interference) and reflections, as well as other sources of signal errors. Poor SI reduces the eye-aperture of SI, thereby reducing LPDDR performance. Traditionally, SI channels are designed using conventional substrates that rely on symmetrical wiring. Symmetrical wiring results in higher maximum crosstalk, thereby resulting in poor signal integrity. It is expected that signal wiring technology can reduce maximum crosstalk and improve SI while supporting higher performance (e.g., speed). Summary of the invention

[0007] An integrated circuit is described. An integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system-on-chip (SoC) die on the PCB. The IC may also include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to the parallel memory interface via parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing between the parallel signal traces for a majority of the parallel signal traces.

[0008] An integrated circuit is described. An integrated circuit (IC) can include a parallel memory interface having parallel signal traces spaced apart based on a non-uniform trace spacing. The spacing of the parallel signal traces can include a trace spacing between inner traces of the parallel signal traces that is greater than a trace spacing between outer traces of the parallel signal traces.

[0009] An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system-on-chip (SoC) die on the PCB. The IC may also include an external memory device coupled to a parallel memory interface of the SoC die via the PCB. The PCB may be arranged such that a trace spacing between inner parallel signal traces of the PCB is greater than a trace spacing between outer parallel signal traces of the PCB.

[0010] This has been a fairly broad overview of the features and technical advantages of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure may be easily used as a basis for modifying or designing other structures for achieving the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features (regarding its organization and method of operation) that are considered to be characteristic of the present disclosure, together with further objects and advantages, will be better understood from the following description when considered in conjunction with the accompanying drawings. However, it should be clearly understood that each of the accompanying drawings is provided for the purpose of illustration and description only and is not intended to be a limitation on the limits of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram of a memory subsystem showing a host system-on-chip (SoC) die communicatively coupled to an external memory device in accordance with aspects of the present disclosure.

[0013] Figure 2A and Figure 2B According to various aspects of the present disclosure, Figure 1 A schematic diagram of a memory subsystem showing the asymmetric spacing between printed circuit board (PCB) traces of a transmission line structure.

[0014] Figure 3A and Figure 3B is a block diagram of a memory subsystem including a memory package stacked on a host SoC die in a SoC-memory package-on-package (PKG-on-PKG) configuration with internal signal integrity channels in accordance with aspects of the present disclosure.

[0015] Figure 4A A byte is shown in a conventional substrate with symmetrical routing of traces shown in a transmission line structure footprint.

[0016] Figure 4B According to various aspects of the present disclosure, Figure 4A The same transmission line structure footprint of one byte in a memory substrate with asymmetric routing of traces.

[0017] Figure 5A and Figure 5B Shown in Figure 4A The transmission line structure of the embodiment of the present invention covers a byte in a conventional substrate with symmetrical routing of traces.

[0018] Fig. 6A and Figure 6BAccording to various aspects of the present disclosure, Figure 4A The same transmission line structure footprint of one byte in a memory substrate with asymmetric routing of traces.

[0019] Fig. 7A and Figure 7B is a graph illustrating capacitive coupling and inductive coupling to adjacent traces due to conventional symmetrical routing and asymmetrical routing in accordance with aspects of the present disclosure.

[0020] Figure 8 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed.

[0021] Fig. 9 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION

[0022] In conjunction with the accompanying drawings, the detailed description set forth below is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. For the purpose of providing a thorough understanding of the various concepts, the detailed description includes specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0023] As described herein, the use of the term "and / or" is intended to mean an "inclusive or", and the use of the term "or" is intended to mean an "exclusive or". As described herein, the term "exemplary" used throughout this specification means "used as an example, instance, or illustration", and should not be interpreted as being preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" used throughout this specification means "connected, whether directly or indirectly through an intermediate connection (e.g., a switch), an electrical connection, a mechanical connection, or other means", and is not necessarily limited to a physical connection. In addition, the connection can be such a connection that objects are permanently connected or releasably connected. The connection can be made through a switch. As described herein, the term "close" used throughout this specification means "adjacent, very close, adjacent, or close". As described herein, the term "on" used throughout this specification means "directly on" in some configurations and "indirectly on" in other configurations.

[0024] Electrical connections exist at each level of the system hierarchy. Specifically, interconnection layers connect different devices on an integrated circuit (IC) together. As integrated circuits become more and more complex, a large number of interconnection layers are specified to support electrical connections between different devices. Recently, due to the large number of devices interconnected in modern electronic devices, the number of interconnection levels for circuit devices has increased significantly. The increased number of interconnection levels used to support the increased number of devices involves more intricate processes.

[0025] These interconnect layers can provide transmission line structures for interconnecting integrated circuit (IC) devices in high-frequency circuit designs. For example, high-frequency circuit designs can use transmission lines (e.g., traces) to support high-speed interfaces. Traditional interconnect traces are manufactured on printed circuit boards (PCBs) to support communication between devices on the PCB. For example, a system-on-chip (SoC) die can communicate with an external memory (e.g., dynamic random access memory (DRAM)) via parallel traces on the PCB. Specifically, the PCB traces can interconnect the SoC package (PKG) to a memory (e.g., DRAM) package on the PCB. Alternatively, the DRAM package can be stacked on the SoC package in a package-on-package (PoP) configuration. These different configurations all rely on parallel memory interfaces to support communication.

[0026] One type of parallel memory interface is low power double data rate (LPDDR) memory. LPDDR can be configured as a parallel interface with a single-ended data channel from the SoC to the DRAM. The SI (signal integrity) of these parallel traces plays a critical role in LPDDR performance. SI channels for external memory as well as PoP systems are used. Unfortunately, signal integrity is affected by crosstalk (xtalk), ISI (inter-symbol interference) and reflections, as well as other sources of signal degradation.

[0027] Poor signal integrity typically reduces the eye opening of the SI channel, thus reducing LPDDR performance. Traditionally, SI channels are designed using conventional substrates that rely on symmetrical routing. Symmetric routing results in higher maximum crosstalk, thus resulting in poor signal integrity. Aspects of the present disclosure provide a redesigned LPDDR new substrate (PKG and / or PCB), which results in lower maximum crosstalk, thereby resulting in improved signal integrity and higher performance (e.g., speed).

[0028] According to one aspect of the present disclosure, an integrated circuit includes a parallel memory interface having multiple parallel traces spaced apart based on uneven trace spacing. It should be understood that the term "layer" includes a film and should not be interpreted as indicating a vertical thickness or a horizontal thickness unless otherwise specified. As described herein, the term "substrate" may refer to a substrate of a cut wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms "chip" and "die" may be used interchangeably unless such interchange is implausible.

[0029] In the following SoC and external memory device examples, symmetrical routing results in higher maximum crosstalk, resulting in poor signal quality. Aspects of the present disclosure provide a redesigned LPDDR substrate (PKG and / or PCB) that provides lower maximum crosstalk, thereby providing improved signal integrity at higher operating frequencies.

[0030] According to one aspect of the present disclosure, an integrated circuit includes a parallel memory interface having a plurality of parallel traces spaced apart based on non-uniform trace spacing. The non-uniform trace spacing can be arranged to have a trace spacing between inner parallel traces greater than a trace spacing between outer parallel traces. For example, a first non-uniform trace spacing between an inner parallel trace and a closest trace is greater than a second non-uniform trace spacing between any two other parallel traces.

[0031] Figure 1 is a block diagram of a memory subsystem 100 showing a host system-on-chip (SoC) die communicatively coupled to an external memory device, in accordance with aspects of the present disclosure. Figure 1 A side view of a low power memory subsystem according to aspects of the present disclosure is shown, showing a SoC die 110 (e.g., a host SoC die) coupled to an external memory device 140 on a printed circuit board (PCB) 102. This aspect of the present disclosure applies asymmetric spacing between PCB traces of a memory link. The example relates to a next generation low power double data rate (DDR) (e.g., low power double data rate (LPDDR)) interface implementation in a mobile or computing system chipset. Figure 2A PCB traces of a signal integrity channel 150 between the SoC die 110 and the external memory device 140 are further shown.

[0032] Figure 2A It is a further illustration according to various aspects of the present disclosure Figure 1Schematic diagram 200 of a memory subsystem of a SoC with asymmetric spacing between printed circuit board (PCB) traces of a transmission line structure. Representatively, the SoC die 110 includes a parallel memory interface 220 (e.g., an LPDDR (4 / 4X / 5) interface) for communicating between the SoC die 110 and an external memory device (e.g., a dynamic random access memory (DRAM) receiver (RX)) 240. Although shown as volatile DRAM memory, it should be appreciated that the external memory device can be composed of volatile memory devices and / or non-volatile memory (NVM) devices (e.g., NAND / NOR based flash memory). The SoC die 110 is also coupled to a power distribution network (PDN) 202.

[0033] exist Figure 2A In this example, Figure 1 The external memory device 140 is shown as a DRAM RX (e.g., memory RX 240), which is communicatively coupled to the parallel memory interface 220 of the SoC die 110. The memory RX 240 is communicatively coupled to the parallel memory interface 220 through a SoC package (PKG) trace (e.g., SoC PKG trace 222), a PCB trace 230, and a memory (e.g., DRAM) PKG trace 242. In this example, the SoC PKG trace 222, the PCB trace 230, and the memory PKG trace 242 are collectively referred to as a signal integrity (SI) channel 250 (e.g., a transmission line structure).

[0034] Figure 2B An X16 channel configuration of an SI channel 250 (e.g., a transmission line structure) is shown. The X16 channel configuration of the SI channel 250 includes a first data (DQ) bus (e.g., a first DQ X8 bus 200 or a first data byte channel) and a second data (DQ) bus 270 (e.g., a second DQ X8 bus 270 or a second data byte channel). The X16 channel configuration of the SI channel 250 also includes a command address (CA) bus 280 between the first DQ X8 bus 260 and the second data (DQ) bus 270, although other channel configurations are also contemplated. In this example, a parallel memory interface 220 for communicating between the SoC die 110 and an external memory device 140 (e.g., a memory RX 240) operates at a high operating speed (e.g., a 2133 / 3200MHz input / output (I / O) operating speed).

[0035] In operation, data (or stimulus) from the parallel memory interface 220 travels from the transmitter (TX) of the parallel memory interface 220 through the SoC PKG trace 222 to the PCB trace 230, to the memory PKG trace 242, and then to the memory RX 240. In this example, the memory RX 240 includes an on-die termination (ODT). Therefore, the SoC PKG trace 222, the PCB trace 230, and the memory PKG trace 242 are collectively shown as a SI channel 250. Typically, the spacing between the SoC PKG trace 222, the PCB trace 230, and the memory PKG trace 242 is symmetrical.

[0036] Figure 3A is a block diagram of a memory subsystem 300 according to various aspects of the present disclosure, showing a memory device package 340 (e.g., a DRAM package) stacked on a host SoC die package 310 in a system-on-chip SoC-DRAM package-on-package (PKG-on-PKG) configuration with an internal SI channel 350. Figure 3A A side view of a memory subsystem 300 (e.g., a low power memory subsystem) according to aspects of the present disclosure is shown showing a SoC die package 310 (e.g., a host SoC die package) with stacked memory device packages 340 (e.g., a DRAM package) on a PCB 102. This aspect of the present disclosure applies asymmetric spacing between traces of an internal SI channel 350. This example also relates to a parallel memory (e.g., LPDDR) interface implementation for a mobile or computing system chipset. Figure 3B Further shown in FIG. 3 are traces of an internal SI channel 350 between the SoC die package 310 and the memory device package 340 .

[0037] Figure 3B It is a further illustration according to various aspects of the present disclosure Figure 3A Schematic diagram of the memory subsystem of the SoC die package 310 to illustrate the asymmetric spacing between the traces of the internal transmission line structure. The SoC die package 310 also includes a parallel memory interface 220 (e.g., an LPDDR (4 / 4X / 5) interface) for communicating between the SoC die package 310 and a memory device package 340 (e.g., a dynamic random access memory (DRAM) receiver (RX) 360). Although shown as a volatile DRAM memory, it should be recognized that the external memory device can be composed of volatile memory devices and / or non-volatile (NVM) memory devices (e.g., NAND / NOR based flash memory).

[0038] Typically, the spacing between the SoC PKG traces 222 and the memory PKG traces 242 is symmetrical. Specifically, conventional knowledge requires that the SI channels be designed and manufactured using conventional substrates. These conventional substrates rely on symmetrical routing (e.g., uniform spacing) between the traces of the internal SI channel 350. Unfortunately, the symmetrical routing of the traces of the internal SI channel 350 results in higher maximum crosstalk, resulting in poor SI. As a result, designing the spacing between the traces of the internal SI channel 350 using conventional symmetrical routing typically results in poor signal integrity.

[0039] Reference again Figure 2B , before reaching the memory PKG trace 242 (e.g., DRAM PKG trace) and finally reaching the DRAM RX 240, the SI channel 250 is configured as a SoC-DRAM SI external channel, outside the SoC PKG trace 222 and on the PCB trace 230. It can also be used Figure 2B The SI channel 250 is configured as an X16 channel Figure 3A and Figure 3B 350 in the internal SI channel. In this configuration, the spacing between the traces of the first DQ X8 bus 260, the CA bus 280, and the second data (DQ) bus 270 is symmetrical. Aspects of the present disclosure seek to redesign LPDDR substrates (e.g., PKG and / or PCB) with lower maximum crosstalk, thereby having improved signal integrity performance (e.g., speed).

[0040] Figure 4A A byte in a conventional substrate 400 with symmetrical routing of traces in a transmission line structure footprint (e.g., X×Y) is shown. In this example, the signal traces of the conventional substrate 400 include data mask inversion (DMI) bits and data (dq) bits (e.g., dmi0, dq0–dq7) carried by the signal traces of the conventional substrate 400. Representatively, the symmetrical routing of the conventional substrate means that the spacing (e.g., a1) between the traces is uniform. In this symmetrical routing configuration of the conventional substrate 400, the maximum crosstalk (Xtalk) between all bits limits the eye opening and data rate of the SI channel. In this configuration, the inner traces (e.g., dq2, dq3, dq4) of the conventional substrate 400 experience increased crosstalk because they are surrounded by more aggressor lines. In contrast, the outer traces (e.g., dmi0 and dq7) of the conventional substrate are exposed to less crosstalk due to the reduced number of aggressor lines.

[0041] Figure 4B According to various aspects of the present disclosure, Figure 4A4. A byte in a memory substrate 450 with asymmetric routing of traces in the same transmission line structure footprint of the memory substrate 450. In this example, the signal traces of the memory substrate 450 also include data mask inversion (DMI) bits and data (dq) bits (e.g., dmi0, dq0–dq7) carried by the signal traces of the memory substrate 450. Compared to symmetric routing, the asymmetric routing of the memory substrate 450 means that the spacing between the traces (e.g., b1>b2>b3>b4) is not uniform (e.g., uneven trace spacing). In this asymmetric routing configuration of the memory substrate 450, the maximum crosstalk (Xtalk) between all bits is reduced. In this example, the minimum uneven trace spacing (e.g., b4) is equal to the distance between the parallel signal trace (e.g., dmi0 / dq7) farthest from the center (e.g., dq3) of the parallel memory interface and the second farthest parallel signal trace (e.g., dq0 / dq6).

[0042] According to aspects of the present disclosure, the reduced crosstalk provided by the asymmetric routing of the memory substrate 450 improves the eye opening and data rate of the SI channel. In this configuration, the increased spacing between the inner traces of the memory substrate 450 experience reduced crosstalk by increasing isolation from the aggressor wires. In contrast, the outer traces of the memory substrate 450, which are exposed to less crosstalk due to the reduced number of aggressor wires, include reduced trace spacing. Figure 4A and Figure 4B As shown, for all traces of the conventional substrate 400 and the memory substrate 450, the trace width and characteristic impedance (Z0) are the same.

[0043] Figure 5A and Figure 5B Shown in Figure 4A A transmission line structure of FIG. 500 covers a byte in a conventional substrate 500 with symmetrical routing of traces. Figure 5B As shown, the signal traces (1 (dmi0), 2, ..., 5 (dq3), ..., 9 (dq7)) of the conventional substrate 500 follow a symmetrical routing, in which the spacing (e.g., a1) between the traces is uniform. In this symmetrical routing configuration of the conventional substrate 500, the total spacing width (X) of the transmission line footprint is a multiple of the spacing a1 (e.g., X=8*a1).

[0044] Fig. 6A and Figure 6B According to various aspects of the present disclosure, Figure 4AA byte in a memory substrate 600 with asymmetric routing of traces in the same transmission line structure footprint of the memory substrate 600. In this example, the signal traces of the memory substrate 600 also include data mask inversion (DMI) bits and data (dq) bits (e.g., 1 (dmi0), 2, ..., 5 (dq3), ..., 9 (dq7)) carried by the signal traces of the memory substrate 600. Compared to symmetric routing, the asymmetric routing of the memory substrate 600 means that the spacing between traces (e.g., b1>b2>b3>b4) is variable (e.g., variable spacing provided between parallel signal traces of the longest leg). In this asymmetric routing configuration of the memory substrate 600, the total spacing width (X) of the transmission line footprint is the sum of the variable spacing (e.g., X=2*(b1+b2+b3+b4)=8*a1). In this example, the spacing (z) between trace 5 and trace 6 is greater than the spacing (y) between trace 1 and trace 2. In addition, the pitch (z) of the memory substrate is greater than the pitch (x) between the traces 5 and 6 of the conventional substrate 500 (e.g., z>x>y). That is, the pitch (z) is the same as b1, the pitch (y) is the same as b4, and the pitch (x) is the same as a1. It should be appreciated that in the pitch (x), x is a lowercase x and should not be confused with an uppercase X, which is the total pitch width.

[0045] Fig. 7A and Figure 7B is a graph showing capacitive coupling and inductive coupling to adjacent traces due to conventional symmetrical routing and asymmetrical routing according to aspects of the present disclosure. Fig. 7A and Figure 7B In FIG. 1 , the NEXT_1 signal corresponds to the crosstalk experienced by a corner trace (eg, dmi0), and the NEXT_5 signal corresponds to the crosstalk experienced by a middle trace (eg, dq3). Fig. 7A and Figure 7B As shown, the difference (delta) between the inductive / capacitive coupling experienced by traces formed using asymmetric routing and symmetric routing is significant. For example, the differential capacitive / inductive coupling for a corner trace (e.g., dmi0) shown by the NEXT_1 signal is significant (=-41.642–(-43.056)=1.416dB). Similarly, the difference between the capacitive / inductive coupling for an intermediate trace (e.g., dq3) shown by the NEXT_5 signal is significant (=-41.480–(-40.057)=-1.423dB).

[0046] exist Fig. 7A In the figure, the method for using according to various aspects of the present disclosure is shown. Fig. 6A and Figure 6B700 of the capacitance / inductance coupling curve of the asymmetric routing shown in FIG. The capacitance / inductance coupling curve 700 shows that the asymmetric routing (e.g., variable spacing) results in uniform capacitance coupling and inductance coupling between adjacent traces. By comparing the NEXT_1 signal and the NEXT_5 signal, it can be seen that the asymmetric routing reduces the maximum limit crosstalk applied to the middle dq3 trace. That is, the crosstalk applied to the middle trace (e.g., dq3) is significantly reduced (e.g., reduced by 1.42 dB).

[0047] In addition, the uniform capacitive and inductive coupling between adjacent traces significantly increases the crosstalk imposed on the corner traces (e.g., dmi0) (e.g., 1.416 dB). Overall, the maximum limiting crosstalk of the full byte of asymmetrical routing is significantly reduced (e.g., by 1.42 dB). The reduction in maximum limiting crosstalk improves signal integrity and system performance. It should be recognized that crosstalk depends on spacing, but is not a linear function of spacing.

[0048] Figure 7B Shows the Figure 5A and Figure 5B Capacitance / inductance coupling graph 750 for conventional symmetrical routing is shown in . Capacitance / inductance coupling graph 750 shows that symmetrical routing (e.g., uniform spacing) results in uneven capacitive coupling and inductive coupling between adjacent traces, resulting in uneven crosstalk on the traces. By comparing the NEXT_1 signal and the NEXT_5 signal, it can be seen that the symmetrical routing increases the maximum crosstalk applied to the middle dq3 trace. This maximum crosstalk is caused by the coupling effect applied to the middle trace (e.g., dq3) from both sides. This maximum crosstalk limits the total eye opening / data rate for transmitting bytes using symmetrical routing. In contrast, because the corner traces have only one adjacent trace (e.g., dq0 and dq6), the corner traces experience the least crosstalk.

[0049] The redesigned memory substrate using asymmetric routing according to aspects of the present disclosure results in lower maximum crosstalk. This lower maximum crosstalk improves signal integrity and translates into a larger eye opening for the transmission line structure of the entire system. For example, the larger eye opening provides additional timing margin, which enables a parallel memory interface (e.g., LPDDR) to have higher performance (e.g., speed). In addition, the larger eye opening provides additional timing margin, which makes it possible to reduce expensive on-die decoupling capacitors (decap) for the same performance.

[0050] Various aspects of the present disclosure reduce the worst case crosstalk in the same footprint (e.g., area), resulting in overall higher performance (e.g., speed). These techniques are applicable to current LPDDR4 / 4X / 5 memory interfaces and future products. Although described with reference to LPDDR, various aspects of the present disclosure may be applicable to other parallel interfaces, such as DDR and graphics DDR (GDDR). In addition, various aspects of the present disclosure are not limited to PCB / PKG routing, but can be extended to routing on the die.

[0051] Figure 8 8 is a block diagram illustrating an exemplary wireless communication system 800 in which aspects of the present disclosure may be advantageously employed. For purposes of illustration, Figure 8 Three remote units 820, 830, and 850 and two base stations 840 are shown. It will be appreciated that the wireless communication system can have more remote units and base stations. Remote units 820, 830, and 850 include IC devices 825A, 825C, and 825B, which include asymmetric routing of disclosed signal traces. It will be appreciated that other devices can also include the disclosed improved signal trace spacing, such as base stations, switching equipment, and network equipment. Figure 8 Forward link signals 880 from base station 840 to remote units 820, 830, and 850, and reverse link signals 890 from remote units 820, 830, and 850 to base station 840 are shown.

[0052] exist Figure 8 , remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit (such as a meter reading device), an automotive electronic system, or other device that stores or retrieves data or computer instructions, or a combination thereof. Although Figure 8 Remote units according to aspects of the present disclosure are shown, but the present disclosure is not limited to these exemplary shown units.Aspects of the present disclosure may be suitably employed in a wide variety of devices, including the disclosed improved signal trace spacing.

[0053] Fig. 99 is a block diagram of a design workstation for circuit, layout, and logic design of semiconductor components, such as the improved signal trace spacing disclosed above. The design workstation 900 includes a hard disk 901, which contains operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 900 also includes a display 902 to facilitate the design of a circuit 910 or a signal trace 912. A storage medium 904 is provided for tangibly storing the design of the circuit 910 or the signal trace 912. The design of the circuit 910 or the signal trace 912 can be stored on the storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. In addition, the design workstation 900 includes a drive device 903 for receiving input from the storage medium 904 or writing output to the storage medium 904.

[0054] The data recorded on the storage medium 904 may specify a logic circuit configuration, pattern data for a lithography mask, or mask pattern data for a serial write tool such as electron beam lithography. The data may also include logic verification data, such as a timing diagram or a network circuit associated with a logic simulation. Providing the data on the storage medium 904 facilitates designing the circuit 910 or signal trace 912 by reducing the number of processes used to design a semiconductor wafer.

[0055] For firmware and / or software implementations, the methods can be implemented with modules (e.g., programs, functions, etc.) that perform the functions described herein. A machine-readable medium that tangibly embodies instructions can be used to implement the methods described herein. For example, software code can be stored in a memory and executed by a processor unit. The memory can be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to a type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a specific type of memory or a specific number of memories, or to the type of medium on which the memory is stored.

[0056] If implemented in firmware and / or software, the function can be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. Storage media can be available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or other media that can be used to store desired program codes in the form of instructions or data structures and can be accessed by a computer. The disc and disk used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy discs and blue-ray discs, wherein the discs usually reproduce data magnetically, and the discs reproduce data optically with lasers. The above combination should also be included in the scope of computer-readable media.

[0057] In addition to being stored on a computer-readable medium, instructions and / or data may be provided as signals on a transmission medium included in the communication device. For example, the communication device may include a transceiver with signals indicating instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0058] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made here without departing from the technology of the present disclosure defined by the appended claims. For example, relational terms such as "above..." and "below..." are used relative to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, then "above..." becomes "below...", and vice versa. In addition, if facing the side, "above..." and "below..." can refer to the side of the substrate or electronic device. In addition, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods and steps described in the specification. As will be readily understood by those of ordinary skill in the art from the present disclosure, according to the present disclosure, processes, machines, manufactures, material compositions, components, methods or steps that currently exist or will be developed later to perform functions substantially the same as the corresponding configurations described herein or to achieve substantially the same results can be utilized. Accordingly, the appended claims are intended to include these processes, machines, manufactures, material compositions, components, methods or steps within their scope.

[0059] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and steps have generally been described above according to their functions. Whether this function is implemented as hardware or software depends on specific application and the design constraints imposed on the entire system. The technician can implement the described function in different ways for each specific application, but this realization decision should not be interpreted as causing a departure from the scope of the present disclosure.

[0060] The various illustrative logical blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors with a DSP core, or any other such configuration.

[0061] The steps of the method or algorithm described in conjunction with the present disclosure can be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module can reside in a RAM, flash memory, ROM, EPROM, EEPROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium can be integrated into the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In an alternative, the processor and the storage medium can reside in a user terminal as discrete components.

[0062] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media and communication media, and communication media include any media that facilitates the transfer of computer programs from one place to another. Storage media may be any available media that can be accessed by a general or special-purpose computer. As an example and not limitation, such computer-readable media may include RAM, ROM, EPROM, EEPROM, CD-ROM, or other optical disk storage devices, disk storage devices, or other magnetic storage devices, or any other media that can be used to carry or store specific program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. In addition, any connection is properly referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where discs usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0063] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to the widest scope consistent with the principles and novel features disclosed herein.

[0064] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure defined by the appended claims. For example, relational terms such as "above..." and "below..." are used relative to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, then "above..." becomes "below...", and vice versa. In addition, if facing the side, "above..." and "below..." can refer to the side of the substrate or electronic device. In addition, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods and steps described in the specification. As will be readily understood by those of ordinary skill in the art from the present disclosure, according to the present disclosure, processes, machines, manufactures, material compositions, components, methods or steps that currently exist or are to be developed later to perform functions substantially the same as the corresponding configurations described herein or to achieve substantially the same results can be utilized. Accordingly, the appended claims are intended to include these processes, machines, manufactures, material compositions, components, methods or steps within their scope.

Claims

1. An integrated circuit, comprising: Printed circuit board PCB; a package substrate interconnected on the PCB, the package substrate comprising parallel signal traces arranged in an asymmetric wiring; a system-on-chip (SoC) die interconnected on the package substrate, the SoC die comprising a parallel memory interface coupled to the parallel signal traces of the package substrate via a package interconnect; as well as A memory device package is on the SoC die and coupled to the parallel memory interface of the SoC die through the parallel signal traces of the package substrate in the asymmetric routing arrangement, wherein variable spacing is provided between the parallel signal traces for a majority of the parallel signal traces for the longest legs of an internal signal integrity channel. 2 . The integrated circuit of claim 1 , wherein a trace spacing between inner ones of the parallel signal traces is greater than a trace spacing between outer ones of the parallel signal traces.

3. The integrated circuit of claim 2, wherein a first uneven trace spacing between an inner trace and a closest trace in the parallel signal traces is greater than a second uneven trace spacing between any two other traces in the parallel signal traces.

4. The integrated circuit of claim 1, wherein a minimum uneven trace spacing is equal to a distance between a signal trace farthest from a center of the parallel memory interface and a signal trace next farthest from the parallel signal traces.

5. The integrated circuit of claim 1 , wherein the parallel memory interface comprises a plurality of channels, and each channel comprises a first data byte channel and a second data byte channel, the first data byte channel and the second data byte channel comprising uneven trace spacings b1, b2, b3, and b4, wherein b1>b2>b3>b4.

6. The integrated circuit of claim 1, wherein the parallel memory interface comprises a low power double data rate (LPDDR) memory interface.

7. The integrated circuit of claim 1, wherein the memory device package comprises a volatile memory device and / or a non-volatile memory (NVM) device.

8. The integrated circuit according to claim 1 is integrated into a mobile phone, a set-top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a handheld personal communication system (PCS) unit, a portable data unit, a fixed location data unit and / or an automotive electronic system.

9. An integrated circuit comprising: a package substrate including parallel signal traces in an asymmetric wiring arrangement; a die interconnected on the package substrate and having a parallel memory interface coupled to the parallel signal traces of the package substrate through a package interconnect, wherein the parallel signal traces of the package substrate are spaced apart based on a non-uniform trace spacing, wherein for a majority of the parallel signal traces of the longest branch of the internal signal integrity channel, a trace spacing between inner traces in the parallel signal traces is greater than a trace spacing between outer traces in the parallel signal traces; as well as A memory device package is stacked on the die and coupled to the parallel memory interface of the die through the asymmetric wiring of the package substrate.

10. The integrated circuit of claim 9, wherein a first non-uniform trace spacing between an inner trace and a closest signal trace in the parallel signal traces is greater than a second non-uniform trace spacing between any two other traces in the parallel signal traces.

11. The integrated circuit of claim 9, wherein a minimum uneven trace spacing b4 is equal to a distance between a trace of the parallel signal traces that is farthest from a center of the parallel memory interface and a trace of the parallel signal traces that is next farthest from a center of the parallel memory interface.

12. The integrated circuit of claim 9, wherein the parallel memory interface comprises a plurality of channels, and each channel comprises a first data byte channel and a second data byte channel, the first data byte channel and the second data byte channel comprising uneven trace spacings b1, b2, b3, and b4, wherein b1>b2>b3>b4.

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