Semiconductor chip and semiconductor package including the semiconductor chip

Abstract

A semiconductor chip and a semiconductor package including the semiconductor chip are provided. A semiconductor chip may include: a main body portion including a front surface and a rear surface; a through electrode that penetrates the main body portion; and a rear connection electrode that is disposed above the rear surface of the main body portion and connected to the through electrode, wherein the through electrode includes a power through electrode for transmitting a power voltage and a ground through electrode for transmitting a ground voltage, and the rear connection electrode includes a power rear connection electrode connected to the power through electrode and a ground rear connection electrode connected to the ground through electrode; and one power rear connection electrode is connected to two or more power through electrodes, and one ground rear connection electrode is connected to two or more ground through electrodes.

Description

Technical Field

[0001] The patent document relates to semiconductor technology, and more particularly, to a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip. Background Art

[0002] Electronic products require a large amount of data processing, while the size of these electronic products is reduced. Therefore, the semiconductor chips used in such electronic products are also required to have a thin thickness and a small size. In addition, semiconductor packages in which a plurality of semiconductor chips are embedded have been manufactured.

[0003] A plurality of semiconductor chips may be connected to each other through a through-hole that passes through each semiconductor chip and provides an electrical connection path. Summary of the invention

[0004] In one embodiment, a semiconductor chip may include: a main body portion including a front surface and a rear surface; a through-electrode that penetrates the main body portion; and a rear connection electrode that is arranged above the rear surface of the main body portion and connected to the through-electrode, wherein the through-electrode includes a power through-electrode for transmitting a power voltage and a ground through-electrode for transmitting a ground voltage, and the rear connection electrode includes a power rear connection electrode connected to the power through-electrode and a ground rear connection electrode connected to the ground through-electrode; and one power rear connection electrode is connected to two or more power through-electrodes, and one ground rear connection electrode is connected to two or more ground through-electrodes.

[0005] In another embodiment, a semiconductor package may include: a first semiconductor chip; and a second semiconductor chip stacked in a vertical direction with the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip includes: a main body portion including a front surface and a rear surface; a through-electrode that penetrates the main body portion; and a rear connection electrode that is arranged above the rear surface of the main body portion and connected to the through-electrode, wherein the through-electrode includes a power through-electrode for transmitting a power supply voltage and a ground through-electrode for transmitting a ground voltage, and the rear connection electrode includes a power rear connection electrode connected to the power through-electrode and a ground rear connection electrode connected to the ground through-electrode; and one power rear connection electrode is connected to two or more power through-electrodes, and one ground rear connection electrode is connected to two or more ground through-electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 and Figure 2 is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure.

[0007] Figure 3is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 4 and Figure 5 is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0009] Figure 6 is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0010] Figure 7 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

[0011] Figure 8 A block diagram illustrating an exemplary electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0012] Fig. 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described embodiments. When a specific example with two or more layers is presented in a multilayer structure in the drawings or descriptions, the relative positioning relationship of these layers or the arrangement order of these layers shown reflects the specific implementation of the described or illustrated example, and different relative positioning relationships or arrangement orders of these layers are possible. In addition, the described or illustrated examples of multilayer structures may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0015] Figure 1 and Figure 2 is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure. For example, Figure 1 is a plan view showing the rear surface of the semiconductor chip of the present embodiment, and Figure 2 It is along Figure 1 A cross-sectional view taken along line A1-A1′.

[0016] Reference Figure 1 and Figure 2 The semiconductor chip 100 of the present embodiment may include a body portion 110 , a wiring portion 120 , a through electrode 130 , a rear connection electrode 140 , and a front connection electrode 150 .

[0017] The main body portion 110 may be formed of a semiconductor material such as silicon or germanium, and may have a plate shape defined by a front surface 111, a rear surface 112, and a side surface connecting them to each other. As an example, the main body portion 110 may have a plate shape having a rectangular planar shape. The front surface 111 of the main body portion 110 may mean an active surface on which an integrated circuit (not shown) having various functions is formed. In this case, the integrated circuit may be implemented in various ways according to the type of the semiconductor chip 100. For example, when the semiconductor chip 100 includes a volatile memory such as a DRAM (dynamic random access memory) and an SRAM (static RAM) or a non-volatile memory such as a NAND flash memory, an RRAM (resistance RAM), a PRAM (phase change RAM), an MRAM (magnetoresistive RAM), and a FRAM (ferroelectric RAM), the integrated circuit may include a memory array having a plurality of memory cells. The rear surface 112 of the main body portion 110 may mean a surface opposite to the front surface 111.

[0018] The wiring portion 120 may be formed on the front surface 111 of the body portion 110. Although not shown, the wiring portion 120 may include a wiring structure electrically connected to the integrated circuit formed on the front surface 111 of the body portion 110 and an insulating layer filling the remaining area where the wiring structure is not formed.

[0019] The through electrode 130 may be formed in the body portion 110. The through electrode 130 may have a column shape extending from the front surface 111 of the body portion 110 to the rear surface 112 and penetrating the body portion 110. As an example, the through electrode 130 may be a TSV (Through Silicon Via). The through electrode 130 may include various conductive materials. As an example, the through electrode 130 may include a metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru) and cobalt (Co) or a compound of such a metal. Although not shown, an insulating liner for insulating the through electrode 130 and the body portion 110 may be interposed between the through electrode 130 and the body portion 110. In addition, although not shown, a barrier metal layer for preventing the diffusion of the metal forming the through electrode 130 may be formed to surround the sidewall of the through electrode 130. One end of the through electrode 130 may be connected to the wiring portion 120, and the other end of the through electrode 130 may be connected to the rear connection electrode 140.

[0020] In the present embodiment, in a plan view, the through-electrodes 130 may be arranged along the first direction and the second direction. In this case, the through-electrodes 130 may include a signal through-electrode 130S for transmitting a signal, a ground through-electrode 130G for transmitting a ground voltage, and a power through-electrode 130P for transmitting a power voltage. The signal through-electrode 130S may be disposed in a central region C in the second direction, and the ground through-electrode 130G and the power through-electrode 130P may be disposed in two edge regions E1 and E2 in the second direction. The reason for such an arrangement may be to effectively reduce the warpage of the semiconductor chip 100, and will be further described in the corresponding section.

[0021] Here, the two edge regions E1 and E2 in the second direction may refer to regions whose distance from both sides of the semiconductor chip 100 in the second direction is less than the width of the semiconductor chip 100 in the second direction. In addition, the central region C may be a region between the two edge regions E1 and E2 in the second direction. For ease of description, one of the two edge regions E1 and E2 in the second direction (e.g., a region located on the left side in a plan view) will be referred to as a first edge region E1, and the other of the two edge regions E1 and E2 in the second direction (e.g., a region located on the right side in a plan view) will be referred to as a second edge region E2.

[0022] A plurality of signal through electrodes 130S arranged in a matrix along the first direction and the second direction may be disposed in the central region C. As shown in FIG.

[0023] A plurality of power through electrodes 130P arranged in a row along the first direction may be provided in the first edge region E1. A plurality of power through electrodes 130P arranged in a row along the first direction will be referred to as a column of the power through electrodes 130P. One or more columns of power through electrodes 130P may be provided in the first edge region E1. A plurality of columns of the power through electrodes 130P may be provided to be spaced apart from each other in the second direction. In the present embodiment, in the first edge region E1, a first column P1 of the power through electrodes 130P and a second column P2 of the power through electrodes 130P may be provided to be spaced apart from each other in the second direction.

[0024] In addition, a plurality of ground penetration electrodes 130G arranged in a row along the first direction may be provided in the first edge region E1. A plurality of ground penetration electrodes 130G arranged in a row along the first direction will be referred to as a column of ground penetration electrodes 130G. One or more columns of ground penetration electrodes 130G may be provided in the first edge region E1. A plurality of columns of ground penetration electrodes 130G may be provided to be spaced apart from each other in the second direction. In the present embodiment, in the first edge region E1, a first column G1 of the ground penetration electrodes 130G and a second column G2 of the ground penetration electrodes 130G may be provided to be spaced apart from each other in the second direction.

[0025] Specifically, in the present embodiment, the columns of the power through electrodes 130P and the columns of the ground through electrodes 130G may be alternately arranged along the second direction. As an example, the first column P1 of the power through electrodes 130P, the first column G1 of the ground through electrodes 130G, the second column P2 of the power through electrodes 130P, and the second column G2 of the ground through electrodes 130G may be arranged in sequence from left to right in the second direction. This can increase the capacitance between the power rear connection electrode 140P and the ground rear connection electrode 140G to be described later by increasing the relative area between them. This will be further described in the corresponding section.

[0026] In addition, the power supply through-electrode 130P may be further disposed at each of the two sides in the second direction of some of the power supply through-electrodes 130P included in the column of the power supply through-electrodes 130P. These power supply through-electrodes 130P that are not included in the column of the power supply through-electrodes 130P but are disposed on one or both sides thereof will be referred to as side power supply through-electrodes 130P-S. As an example, in the column of the power supply through-electrodes 130P, the power supply through-electrodes 130P disposed next to the side power supply through-electrodes 130P-S and the power supply through-electrodes 130P that are not disposed next to the side power supply through-electrodes 130P-S may be alternately arranged in the first direction. For example, as Figure 1 As shown, in the column of the power through electrodes 130P, the side power through electrodes 130P-S may be disposed at both sides of the even-numbered power through electrodes 130P in the first direction.

[0027] In addition, the ground through-electrode 130G may be further disposed at each of the two sides in the second direction of some of the ground through-electrodes 130G included in the column of the ground through-electrodes 130G. These ground through-electrodes 130G that are not included in the column of the ground through-electrodes 130G but disposed on one or both sides thereof will be referred to as side ground through-electrodes 130G-S. As an example, in the column of the ground through-electrodes 130G, the ground through-electrodes 130G disposed next to the side ground through-electrodes 130G-S and the ground through-electrodes 130G that are not disposed next to the side ground through-electrodes 130G-S may be arranged alternately in the first direction. Here, when two side power supply through-electrodes 130P-S are disposed on both sides of the even-numbered power supply through-electrodes 130P in the first direction in the column of the power supply through-electrodes 130P, the side ground through-electrodes 130G-S may be disposed on both sides of the odd-numbered ground through-electrodes 130G in the first direction in the column of the ground through-electrodes 130G. This can make the area in which the side power supply through-electrodes 130P-S are formed and the area in which the side ground through-electrodes 130G-S are formed alternately formed with each other. As another example, if the side power supply through-electrodes 130P-S are arranged on both sides of the odd-numbered power supply through-electrodes 130P in the first direction in the column of the power supply through-electrodes 130P, the side ground through-electrodes 130G-S can be arranged on both sides of the even-numbered ground through-electrodes 130G in the first direction in the column of the ground through-electrodes 130G. In this case, by increasing the relative area between them and reducing the distance between them, the capacitance between the power supply rear connection electrode 140P and the ground rear connection electrode 140G, which will be described later, can be further increased. The side power supply through-electrodes 130P-S and the side ground through-electrodes 130G-S can be arranged alternately along the first direction between the column of the power supply through-electrodes 130P and the column of the ground through-electrodes 130G.

[0028] In the first edge region E1, the arrangement of the columns of the power through electrodes 130P and the side power through electrodes 130P-S adjacent thereto may be repeated along the second direction. For example, the arrangement of the first column P1 of the power through electrodes 130P and the side power through electrodes 130P-S adjacent thereto may be the same as the arrangement of the second column P2 of the power through electrodes 130P and the side power through electrodes 130P-S adjacent thereto. In addition, in the first edge region E1, the arrangement of the columns of the ground through electrodes 130G and the side ground through electrodes 130G-S adjacent thereto may be repeated along the second direction. For example, the arrangement of the first column G1 of the ground through electrodes 130G and the side ground through electrodes 130G-S adjacent thereto may be the same as the arrangement of the second column G2 of the ground through electrodes 130G and the side ground through electrodes 130G-S adjacent thereto.

[0029] A plurality of power penetration electrodes 130P and a plurality of ground penetration electrodes 130G may also be disposed in the second edge region E2. Here, the power penetration electrodes 130P and the ground penetration electrodes 130G in the second edge region E2 may be arranged symmetrically with the power penetration electrodes 130P and the ground penetration electrodes 130G in the first edge region E1 and the central region C is interposed therebetween. Therefore, as an example, in the second edge region E2, the first column P1 of the power penetration electrodes 130P and the side power penetration electrodes 130P-S adjacent thereto, the first column G1 of the ground penetration electrodes 130G and the side ground penetration electrodes 130G-S adjacent thereto, the second column P2 of the power penetration electrodes 130P and the side power penetration electrodes 130P-S adjacent thereto, and the second column G2 of the ground penetration electrodes 130G and the side ground penetration electrodes 130G-S adjacent thereto may be disposed sequentially in the second direction from right to left.

[0030] The rear connection electrode 140 may be formed above the rear surface 111 of the main body portion 110. The rear connection electrode 140 may be used to connect the through-electrode 130 to another component (not shown) to be located above the semiconductor chip 100, for example, another semiconductor chip. As an example, the rear connection electrode 140 may be a conductive bump. In this case, the rear connection electrode 140 may include a laminated structure of a metal body 142 and a wetting layer 144, the metal body 142 being connected to the through-electrode 130, and the wetting layer 144 being formed above the metal body 142 and being connected to another component (not shown), for example, a solder layer of another semiconductor chip. The metal body 142 may include various metals such as copper, and the wetting layer 144 may include a metal capable of wetting the solder material, such as nickel. However, the present embodiment is not limited thereto, and the layered structure, material, etc. of the rear connection electrode 140 may be modified in various ways.

[0031] The rear connection electrodes 140 may include a signal rear connection electrode 140S connected to the signal through electrode 130S, a power rear connection electrode 140P connected to the power through electrode 130P, and a ground rear connection electrode 140G connected to the ground through electrode 130G.

[0032] The signal rear connection electrode 140S may be formed to overlap and connect with each signal through electrode 130S. That is, the signal rear connection electrode 140S and the signal through electrode 130S may correspond one to one. Therefore, the signal rear connection electrode 140S may be arranged in a matrix along the first direction and the second direction in the central area C. On the other hand, the power supply rear connection electrode 140P may be formed to be connected to two or more power supply through electrodes 130P at the same time, and the ground rear connection electrode 140G may be formed to be connected to two or more ground through electrodes 130G at the same time. In this case, there are the following advantages.

[0033] The wiring portion 120 including various metals may exist on the front surface 111 of the semiconductor chip 100, while the wiring portion 120 may not exist on the rear surface 112 of the semiconductor chip 100. Therefore, due to the difference in thermal expansion coefficient between the rear surface 112 and the front surface 111, the phenomenon of bending of the semiconductor chip 100 may occur. As the area occupied by the wiring portion 120 in the semiconductor chip 100 increases and as the thickness of the semiconductor chip 100 decreases, this phenomenon may be aggravated. When a semiconductor package is realized by stacking a plurality of semiconductor chips, this warping may cause various problems such as poor connection between semiconductor chips. In the present embodiment, because the power supply rear connection electrode 140P overlaps with two or more power supply through electrodes 130P, and the grounding rear connection electrode 140G overlaps with two or more grounding through electrodes 130G, the degree of metal material formation on the rear surface 112 can be increased. Therefore, the warping of the semiconductor chip 100 can be reduced and / or prevented. Specifically, by arranging these power supply rear connection electrodes 140P and ground rear connection electrodes 140G in the first edge region E1 and the second edge region E2, the warping of the semiconductor chip 100 can be more effectively reduced and / or prevented. This is because the warping intensifies from the center to the edge. In addition, because the power supply rear connection electrode 140P is connected to two or more power supply through electrodes 130P to form a power distribution network (PDN), and similarly, the ground rear connection electrode 140G is connected to two or more ground through electrodes 130G to form a PDN, power supply can be performed stably. In addition, when the power supply rear connection electrode 140P and the ground rear connection electrode 140G whose side surfaces face each other and are spaced apart from each other form a capacitor, as the capacitance of the capacitor increases, power supply can be performed more stably. In the following, the arrangement of the power supply rear connection electrode 140P and the ground rear connection electrode 140G that are more suitable for the capacitance increase will be described.

[0034] Return to reference Figure 1 and Figure 2, the power rear connection electrode 140P may overlap and connect with the column of the power through electrode 130P and the side power through electrode 130P-S adjacent thereto. In the present embodiment, in each of the first edge region E1 and the second edge region E2, two power rear connection electrodes 140P may be connected to the first column P1 of the power through electrode 130P and the side power through electrode 130P-S adjacent thereto, and the second column P2 of the power through electrode 130P and the side power through electrode 130P-S adjacent thereto, respectively. Therefore, the power rear connection electrode 140P may have a shape combined with a line portion extending in the first direction and a protruding portion protruding from the line portion to both sides in the second direction. A plurality of protruding portions of the power rear connection electrode 140P may be arranged along the first direction. Therefore, the power rear connection electrode 140P may have a shape in which a cross shape is repeated along the first direction as a whole.

[0035] In addition, the grounded rear connection electrode 140G may overlap and connect with the column of the grounded penetration electrode 130G and the side grounded penetration electrode 130G-S adjacent thereto. In the present embodiment, in each of the first edge region E1 and the second edge region E2, two grounded rear connection electrodes 140G may be connected to the first column G1 of the grounded penetration electrode 130G and the side grounded penetration electrode 130G-S adjacent thereto, and the second column G2 of the grounded penetration electrode 130G and the side grounded penetration electrode 130G-S adjacent thereto, respectively. Therefore, the grounded rear connection electrode 140G may have a shape in which a line portion extending in the first direction and a protruding portion protruding from the line portion to both sides in the second direction are combined. A plurality of protruding portions of the grounded rear connection electrode 140G may be arranged along the first direction. Therefore, the grounded rear connection electrode 140G may have a shape in which a cross shape is repeated along the first direction as a whole.

[0036] In this case, the power rear connection electrodes 140P and the ground rear connection electrodes 140G may be alternately arranged along the second direction. In this case, the opposing area between the power rear connection electrodes 140P and the ground rear connection electrodes 140G may increase, and thus, the capacitance therebetween may increase.

[0037] In addition, the protruding portion of the power rear connection electrode 140P and the protruding portion of the ground rear connection electrode 140G may be alternately arranged along the first direction. That is, the protruding portion of the ground rear connection electrode 140G may be disposed between the protruding portions of the power rear connection electrode 140P adjacent to each other in the first direction, and the protruding portion of the power rear connection electrode 140P may be disposed between the protruding portions of the ground rear connection electrode 140G adjacent to each other in the first direction. In this case, since the relative area between the power rear connection electrode 140P and the ground rear connection electrode 140G is further increased and the distance between the power rear connection electrode 140P and the ground rear connection electrode 140G is reduced, the capacitance therebetween may be further increased.

[0038] The front connection electrode 150 may be formed over the front surface 111 of the semiconductor chip 100 and further, may be formed over the wiring portion 120. The front connection electrode 150 may be used to electrically connect with another component such as another semiconductor chip or a substrate located under the semiconductor chip 100.

[0039] The front connection electrode 150 may be electrically connected to the wiring portion 120. Also, the front connection electrode 150 may be electrically connected to the through electrode 130 through the wiring portion 120.

[0040] The front connection electrode 150 may include a metal body 152 and a solder layer 154 formed over the metal body 152. The metal body 152 may include various metals such as copper. The solder layer 154 may be combined with the wetting layer in a manner of being wetted in the wetting layer. As an example, when a plurality of semiconductor chips 100 are stacked in a direction perpendicular to the front surface 111 or the rear surface 112 of the body portion 110, the solder layer 154 of one semiconductor chip 100 among the plurality of semiconductor chips 100 may be bonded to the wetting layer 144 of another semiconductor chip 100 located below the one semiconductor chip 100. This will be described later with reference to Figure 3 The metal body 152 may have a column shape, and the solder layer 154 may have a spherical shape. However, the present embodiment is not limited thereto, and the layer structure, material, etc. of the front connection electrode 150 may be modified in various ways.

[0041] According to the semiconductor chip 100 described above, a warping phenomenon of the semiconductor chip 100 may be reduced and / or prevented, and operation characteristics of the semiconductor chip 100 may be improved by stably supplying power.

[0042] Furthermore, even if the semiconductor chip 100 of the above embodiment has a thin thickness, the semiconductor chip 100 can be prevented from warping. Therefore, a semiconductor package in which a plurality of semiconductor chips 100 are stacked can be easily realized. Figure 3 Describe this.

[0043] Figure 3 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0044] Reference Figure 3 , the semiconductor package according to the present embodiment may include a substrate 200 and a plurality of semiconductor chips 210, 220, 230, and 240 stacked in a vertical direction above the substrate 200. In the present embodiment, four semiconductor chips 210, 220, 230, and 240 are stacked, but the present disclosure is not limited thereto, and the number of semiconductor chips stacked in the vertical direction may be modified in various ways. For ease of description, the four semiconductor chips 210, 220, 230, and 240 are referred to as a first semiconductor chip 210, a second semiconductor chip 220, a third semiconductor chip 230, and a fourth semiconductor chip 240 according to the distance from the substrate 200.

[0045] The substrate 200 may be a substrate of a semiconductor package having a circuit and / or wiring structure for electrical signal transmission, such as a printed circuit board (PCB). The substrate 200 may have an upper surface on which a plurality of semiconductor chips 210, 220, 230, and 240 are disposed, and a lower surface on which an external connection terminal 250 for connecting the semiconductor package to the outside is disposed and arranged opposite to the upper surface. When the plurality of semiconductor chips 210, 220, 230, and 240 are memory chips, the substrate 200 may be a base substrate including a logic circuit that supports the operation of these memory chips (e.g., reading data from the memory chip or writing data to the memory chip).

[0046] Each of the first to third semiconductor chips 210 to 230, except for the fourth semiconductor chip 240 located at the uppermost portion of the first to fourth semiconductor chips 210 to 240, may be identical to the semiconductor chips of the above embodiments (see Figure 1 and Figure 2100) in. That is, the first semiconductor chip 210 may include a body portion 211 having a front surface and a rear surface, a wiring portion 212 disposed above the front surface of the body portion 211, a through electrode 213 penetrating the body portion 211, a rear connection electrode 214 disposed above the rear surface of the body portion 211 and connected to the through electrode 213, and a front connection electrode 215 above the wiring portion 212. The second semiconductor chip 220 may include a body portion 221 having a front surface and a rear surface, a wiring portion 222 disposed above the front surface of the body portion 221, a through electrode 223 penetrating the body portion 221, a rear connection electrode 224 disposed above the rear surface of the body portion 221 and connected to the through electrode 223, and a front connection electrode 225 above the wiring portion 222. The third semiconductor chip 230 may include a body portion 231 having a front surface and a rear surface, a wiring portion 232 disposed above the front surface of the body portion 231, a through electrode 233 penetrating the body portion 231, a rear connection electrode 234 disposed above the rear surface of the body portion 231 and connected to the through electrode 233, and a front connection electrode 235 above the wiring portion 232. Because the fourth semiconductor chip 240 is located at the uppermost portion, it may not include the through electrode and the rear connection electrode. That is, as shown in the figure, the fourth semiconductor chip 240 may include a body portion 241 having a front surface and a rear surface, a wiring portion 242 disposed above the front surface of the body portion 241, and a front connection electrode 245 disposed above the wiring portion 242.

[0047] The first semiconductor chip 210 to the fourth semiconductor chip 240 may be arranged so that the front surfaces of the main body parts 211, 221, 231 and 241 face the upper surface of the substrate 200. Therefore, the front connection electrode 215 of the first semiconductor chip 210 may be connected to the substrate 200. The rear connection electrode 214 of the first semiconductor chip 210 may be connected to the front connection electrode 225 of the second semiconductor chip 220. The rear connection electrode 224 of the second semiconductor chip 220 may be connected to the front connection electrode 235 of the third semiconductor chip 230. The rear connection electrode 234 of the third semiconductor chip 230 may be connected to the front connection electrode 245 of the fourth semiconductor chip 240. Therefore, electrical connection from the substrate 200 to the first semiconductor chip 210 to the fourth semiconductor chip 240 may be made, and thus a signal may be transmitted or power may be provided. In this case, since the warpage of the first semiconductor chip 210 to the fourth semiconductor chip 240 is reduced, such electrical connection may be facilitated.

[0048] The spaces between the first semiconductor chip 210 and the substrate 200, between the first semiconductor chip 210 and the second semiconductor chip 220, between the second semiconductor chip 220 and the third semiconductor chip 230, and between the third semiconductor chip 230 and the fourth semiconductor chip 240 may be filled with a filling material 260. The filling material 260 may be formed by flowing an underfill material into the space by capillary action and then curing the underfill material.

[0049] In addition, the substrate 200 and the first to fourth semiconductor chips 210 to 240 may be surrounded by a mold layer 270. That is, the mold layer 270 may be formed to cover the first to fourth semiconductor chips 210 to 240 on the upper surface of the substrate 200. The mold layer 270 may include various molding materials such as EMC (Epoxy Molding Compound).

[0050] According to the semiconductor package of the present embodiment, warpage of the semiconductor chip can be reduced and / or prevented, and thus, connection failure between the semiconductor chips caused by the warpage can be prevented. As a result, a semiconductor package including a plurality of semiconductor chips can be realized.

[0051] Figure 4 and Figure 5 is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure. Specifically, Figure 4 is a plan view showing the rear surface of the semiconductor chip of the present embodiment, and Figure 5 is along Figure 4 The cross-sectional view taken along the line A2-A2′ of FIG. 1 is omitted from the detailed description. Figure 1 and Figure 2 The components in the embodiments are basically the same.

[0052] Reference Figure 4 and Figure 5The semiconductor chip 300 of the present embodiment may include a body portion 310 having a front surface 311 and a rear surface 312, a wiring portion 320 formed above the front surface 311 of the body portion 310, a through electrode 330 penetrating the body portion 310, a rear connection electrode 340 formed above the rear surface 312 of the body portion 310 and connected to the through electrode 330, and a front connection electrode 350 formed above the wiring portion 320 and electrically connected to the wiring portion 320. The through electrode 330 may include a signal through electrode 330S, a power through electrode 330P, and a ground through electrode 330G. The rear connection electrode 340 may include a signal rear connection electrode 340S, a power rear connection electrode 340P, and a ground rear connection electrode 340G. In addition, the rear connection electrode 340 may include a stacked structure of a metal body 342 and a wetting layer 344. The front connection electrode 350 may include a stacked structure of a metal body 352 and a solder layer 354.

[0053] In addition, the semiconductor chip 300 may further include a dummy rear connection electrode 360 ​​formed above the rear surface 312 of the main body portion 310. The lower surface of the dummy rear connection electrode 360 ​​may not be connected to the through electrode 330. In addition, the upper surface of the dummy rear connection electrode 360 ​​may not be connected to other components. That is, the dummy rear connection electrode 360 ​​may be in a floating state and may not provide an electrical connection. The dummy rear connection electrode 360 ​​may have a function of further preventing the warping phenomenon of the semiconductor chip 300 by adding a metal material on the rear surface 312 of the main body portion 310.

[0054] In a plan view, the dummy rear connection electrode 360 ​​may be formed to have various shapes at a position that does not overlap with the through electrode 330. Specifically, in the present embodiment, the dummy rear connection electrode 360 ​​may be formed along the entire edge of the semiconductor chip 300 outside the region where the through electrode 330 is arranged. In this case, the warping at the edge of the semiconductor chip 300 can be further prevented from deepening. In addition, the dummy rear connection electrode 360 ​​may have the same structure as the rear connection electrode 340. For example, the dummy rear connection electrode 360 ​​may include a metal body 362 and a wetting layer 364 formed above the metal body 362. However, the present embodiment is not limited thereto, and the layered structure, material, etc. of the dummy rear connection electrode 360 ​​may be modified differently from the rear connection electrode 340.

[0055] Figure 6 is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure. Figure 1 and Figure 2 The components of the embodiments are basically the same.

[0056] Reference Figure 6The semiconductor chip 400 of the present embodiment may include a body portion 410 having a front surface 411 and a rear surface 412, a wiring portion 420 formed above the front surface 411 of the body portion 410, a through electrode 430 penetrating the body portion 410, a rear connection electrode 440 formed above the rear surface 412 of the body portion 410 and connected to the through electrode 430, and a front connection electrode 450 formed above the wiring portion 420 and electrically connected to the wiring portion 420. The through electrode 430 may include a signal through electrode 430S, a power through electrode 430P, and a ground through electrode 430G. The rear connection electrode 440 may include a signal rear connection electrode 440S, a power rear connection electrode 440P, and a ground rear connection electrode 440G. In addition, the rear connection electrode 440 may include a stacked structure of a metal body 442 and a wetting layer 444. The front connection electrode 450 may include a stacked structure of a metal body 452 and a solder layer 454.

[0057] In addition, an insulating layer 470 filling spaces between the rear connection electrodes 440 (ie, 440S, 440G, and 440P) may be further formed over the rear surface 412 of the semiconductor chip 400 . That is, the rear connection electrodes 440 may be embedded in the insulating layer 470 .

[0058] The insulating layer 470 may be formed by depositing an insulating material covering the rear surface 412 of the semiconductor chip 400 on which the rear connection electrode 440 is formed according to a method such as chemical vapor deposition (CVD), and performing a planarization process (e.g., chemical mechanical polishing (CMP)) until the upper surface of the rear connection electrode 440 is exposed. Thus, the insulating layer 470 may have an upper surface located at substantially the same level as the upper surface of the rear connection electrode 440. The upper surface of the rear connection electrode 440 may be exposed through the insulating layer 470, and the side surface of the rear connection electrode 440 may be surrounded by the insulating layer 470. The insulating layer 470 may include silicon oxide, silicon nitride, or a combination thereof.

[0059] According to the present embodiment, a plurality of semiconductor chips 400 may be stacked. Figure 7 Describe this.

[0060] Figure 7 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. Figure 3 The components of the embodiments are basically the same.

[0061] Reference Figure 7The semiconductor package of the present embodiment may include a substrate 500 and a first semiconductor chip 510 , a second semiconductor chip 520 , a third semiconductor chip 530 , and a fourth semiconductor chip 540 stacked in a vertical direction over the substrate 500 .

[0062] The substrate 500 may include an upper surface on which the first to fourth semiconductor chips 510 to 540 are disposed, and a lower surface on which external connection terminals 550 for connecting the semiconductor package to the outside are disposed while being opposite to the upper surface.

[0063] Each of the first to third semiconductor chips 510 to 530 may be connected to the semiconductor chip 510. Figure 6 That is, the first semiconductor chip 510 may include a body portion 511 having a front surface and a rear surface, a wiring portion 512 formed over the front surface of the body portion 511, a through electrode 513 penetrating the body portion 511, a rear connection electrode 514 formed over the rear surface of the body portion 511 and connected to the through electrode 513, an insulating layer 517 formed over the rear surface of the body portion 511 and filling a space between the rear connection electrodes 514, and a front connection electrode 515 formed over the wiring portion 512. The second semiconductor chip 520 may include a body portion 521 having a front surface and a rear surface, a wiring portion 522 formed over the front surface of the body portion 521, a through electrode 523 penetrating the body portion 521, a rear connection electrode 524 formed over the rear surface of the body portion 521 and connected to the through electrode 523, an insulating layer 527 formed over the rear surface of the body portion 521 and filling a space between the rear connection electrodes 524, and a front connection electrode 525 formed over the wiring portion 522. The third semiconductor chip 530 may include a body portion 531 having a front surface and a rear surface, a wiring portion 532 formed over the front surface of the body portion 531, a through electrode 533 penetrating the body portion 531, a rear connection electrode 534 formed over the rear surface of the body portion 531 and connected to the through electrode 533, an insulating layer 537 formed over the rear surface of the body portion 531 and filling a space between the rear connection electrodes 534, and a front connection electrode 535 formed over the wiring portion 532. Because the fourth semiconductor chip 540 is located at the uppermost part, it may not include a through electrode and a rear connection electrode. That is, as shown in the figure, the fourth semiconductor chip 540 may include a main body 541 having a front surface and a rear surface, a wiring part 542 formed above the front surface of the main body 541, and a front connection electrode 545 formed above the wiring part 542.

[0064] The spaces between the first semiconductor chip 510 and the substrate 500, between the first semiconductor chip 510 and the second semiconductor chip 520, between the second semiconductor chip 520 and the third semiconductor chip 530, and between the third semiconductor chip 530 and the fourth semiconductor chip 540 may be filled with a filling material 560. In this case, since a portion of these spaces is in a state where the insulating layers 517, 527, and 537 are formed therein, the filling material 560 may fill the remaining portions of these spaces except for the insulating layers 517, 527, and 537. Therefore, the process of forming the filling material 560 may be facilitated.

[0065] The first to fourth semiconductor chips 510 to 540 may be surrounded by a mold layer 570 formed over an upper surface of the substrate 500 .

[0066] According to the above embodiments of the present disclosure, a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip capable of reducing defects and improving operation characteristics thereof may be provided.

[0067] Figure 8 A block diagram of an exemplary electronic system is shown, which includes a memory card 7800 employing at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0068] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or stored in response to a read / write request from the host 7830 .

[0069] Fig. 9 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 providing a data movement path.

[0070] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0071] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state drive (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0072] The electronic system 8710 may further include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna, or a wired or wireless transceiver.

[0073] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0074] If electronic system 8710 represents equipment capable of performing wireless communications, electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0075] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined by the following claims.

[0076] CROSS-REFERENCE TO RELATED APPLICATIONS

[0077] This application claims priority to Korean Patent Application No. 10-2020-0087380, filed on Jul. 15, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor chip, comprising: a main body portion, the main body portion comprising a front surface and a rear surface; A penetrating electrode, wherein the penetrating electrode penetrates the main body portion; as well as a rear connection electrode disposed over the rear surface of the body portion and connected to the through electrode, The through-electrodes include power through-electrodes for transmitting power voltage and ground through-electrodes for transmitting ground voltage. The rear connection electrode includes a power rear connection electrode connected to the power through electrode and a ground rear connection electrode connected to the ground through electrode, and A power rear connecting electrode is simultaneously connected to two or more power through-electrodes, and a ground rear connecting electrode is simultaneously connected to two or more ground through-electrodes, The power supply through-electrode comprises a plurality of power supply through-electrodes arranged in a row along a first direction to form a column of power supply through-electrodes, The power rear connection electrode includes a line portion extending in the first direction to overlap with the column of the power through electrodes, The ground through-electrode includes a plurality of ground through-electrodes arranged in a row along the first direction to form a column of ground through-electrodes, and The ground post connection electrode includes a line portion extending in the first direction to overlap with the column of the ground through electrodes, wherein the power rear connecting electrode and the ground rear connecting electrode face each other in a second direction intersecting the first direction, The power supply through-electrode further comprises a side power supply through-electrode, which is arranged on one or more sides of the column of the power supply through-electrode in the second direction. The power rear connection electrode further includes a protruding portion protruding from its line portion in the second direction to overlap with the side power penetration electrode, The ground through-electrodes further include side ground through-electrodes disposed on one or more sides of the column of the ground through-electrodes in the second direction, and The ground rear connection electrode further includes a protruding portion protruding from a line portion thereof in the second direction to overlap with the side ground through electrode.

2. The semiconductor chip according to claim 1, in, The through-electrodes include signal through-electrodes for transmitting signals, and The rear connection electrode includes a signal rear connection electrode connected to the signal through electrode.

3. The semiconductor chip according to claim 2, wherein: A signal post-connect electrode is connected to a signal through-electrode.

4. The semiconductor chip according to claim 2, wherein: The main body portion includes a central area and edge areas arranged on both sides of the central area, The signal penetration electrode and the signal post-connection electrode are arranged in the central area, The power supply through electrode and the power supply rear connection electrode are arranged in the edge region, and The ground through electrode and the ground rear connection electrode are disposed in the edge region so as not to overlap with the power through electrode and the power rear connection electrode.

5. The semiconductor chip according to claim 1, wherein: The power rear connection electrode includes a plurality of power rear connection electrodes, and the ground rear connection electrode includes a plurality of ground rear connection electrodes, and The plurality of power rear connection electrodes and the plurality of ground rear connection electrodes are alternately arranged along the second direction.

6. The semiconductor chip according to claim 1, wherein: The protruding portion of the power rear connection electrode and the protruding portion of the ground rear connection electrode face each other in the first direction.

7. The semiconductor chip according to claim 6, wherein: The protruding portion of the power rear connecting electrode includes a plurality of protruding portions of the power rear connecting electrode, the protruding portion of the ground rear connecting electrode includes a plurality of protruding portions of the ground rear connecting electrode, and The plurality of protruding portions of the power rear connection electrode and the plurality of protruding portions of the ground rear connection electrode are alternately arranged along the first direction.

8. The semiconductor chip according to claim 1, further comprising: A dummy rear connection electrode is formed over the rear surface of the body portion and is disposed not to be connected to the through electrode.

9. The semiconductor chip according to claim 8, wherein: The dummy rear connection electrode is formed along the entire edge of the main body portion.

10. The semiconductor chip according to claim 8, wherein: The dummy rear connection electrode has the same layer structure as the rear connection electrode.

11. The semiconductor chip according to claim 1, wherein: The rear connection electrode comprises a plurality of rear connection electrodes, and Wherein, the semiconductor chip further includes: An insulating layer is formed over the rear surface of the body portion and fills spaces between the plurality of rear connection electrodes.

12. The semiconductor chip according to claim 1, further comprising: A front connection electrode is disposed over the front surface of the body portion and connected to the through electrode.

13. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip, the second semiconductor chip being stacked vertically with the first semiconductor chip, Wherein, each of the first semiconductor chip and the second semiconductor chip comprises: a main body portion, the main body portion comprising a front surface and a rear surface; a penetrating electrode, the penetrating electrode penetrating the main body portion; and a rear connection electrode disposed over the rear surface of the body portion and connected to the through electrode, The through-electrodes include power through-electrodes for transmitting power voltage and ground through-electrodes for transmitting ground voltage. The rear connection electrode includes a power rear connection electrode connected to the power through electrode and a ground rear connection electrode connected to the ground through electrode, and One power rear connecting electrode is simultaneously connected to two or more power through electrodes, and one ground rear connecting electrode is simultaneously connected to two or more ground through electrodes.

14. The semiconductor package according to claim 13, wherein: Each of the first semiconductor chip and the second semiconductor chip further includes: a front connection electrode disposed above the front surface of the body portion and connected to the through electrode, and Wherein the rear connection electrodes of the first semiconductor chip and the front connection electrodes of the second semiconductor chip are connected to each other.

15. The semiconductor package according to claim 14, further comprising: A filling material fills a space between the first semiconductor chip and the second semiconductor chip.

16. The semiconductor package according to claim 15, wherein: The first semiconductor chip further includes an insulating layer formed over the rear surface of the body portion of the first semiconductor chip and filling a space between the rear connection electrodes of the first semiconductor chip, and The filling material fills the remaining space between the first semiconductor chip and the second semiconductor chip except the insulating layer.

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