A hafnium oxide-based ferroelectric capacitor and a preparation method thereof

Abstract

The present invention relates to a hafnium oxide-based ferroelectric capacitor and a preparation method thereof. The ferroelectric capacitor includes, from bottom to top in sequence, a first bottom electrode (4), a second bottom electrode (5), a hafnium oxide-based ferroelectric thin film (6b), a first top electrode (7), a second top electrode (8), and a substrate (9) which are stacked layer by layer; the first bottom electrode (4) and the second top electrode (8) are conductive layers; the second bottom electrode (5) and the first top electrode (7) are electrodes. Both the second bottom electrode (5) and the first top electrode (7) are HfNx (0 < x ≤ 1.1), and the second bottom electrode (5) and the first top electrode (7) have the same thickness; the substrate includes: silicon, a CMOS addressing, selection, and logic control circuit (1), a metal electrode, and an interlayer dielectric (2). The ferroelectric capacitor of the present invention has good miniaturization and excellent ferroelectric properties.

Description

[0001] This application is a divisional application of a patent application entitled "A Hafnium Oxide-Based Ferroelectric Capacitor and Its Preparation Method". The application date of the original application is March 26, 2019, and the application number is 201910233614.7. Technical Field

[0002] The invention belongs to the field of integrated circuit technology, relates to an integration process of a ferroelectric memory, and specifically relates to a hafnium oxide-based ferroelectric capacitor and a preparation method thereof. Background Art

[0003] Ferroelectric RAM (FRAM) is a very promising type of next-generation memory technology and has always been the focus of attention. FRAM has the characteristics of non-volatility, low power consumption, resistance to erase and write fatigue, fast read and write speed, and strong radiation resistance. It has been widely used in RFID, instrumentation, PLC control, medical equipment and other fields. It integrates ferroelectric capacitors (including bottom electrodes, ferroelectric thin film materials and top electrodes) into complementary metal oxide semiconductor (CMOS) addressing, selection and logic control circuits, and uses the bistable polarization characteristics of ferroelectric thin film materials to achieve data "0" and "1" storage. Therefore, the quality of ferroelectric thin film materials and their ferroelectric capacitors directly determines the performance of ferroelectric memory, and its integration process is closely related to the production and commercialization prospects of ferroelectric memory.

[0004] At present, most commercial FRAMs use lead zirconate titanate (PZT) thin film materials, and the bottom / top electrodes of their ferroelectric capacitor structures are made of metals such as Pt, Ir, IrO2 and SrRO3. PZT-based FRAM has limited ability to be scaled down proportionally, and is currently still stuck at the 130nm process, resulting in low storage density and limited applications. The main reasons include the following four points: (1) PZT thin films have obvious size effects, and their ferroelectric properties degrade sharply when the thickness is less than 70nm; (2) The three-dimensional preparation process of PZT thin films and their ferroelectric capacitors is limited, and cannot meet the requirements of smaller CMOS process integration technology; (3) Inert metals such as Pt, Ir, and IrO2 are difficult to etch, making it difficult to obtain high-vertical capacitor structures to increase integration density; (4) The crystallization annealing temperature of PZT thin films is high, which is also difficult to meet the requirements of smaller CMOS process integration technology. Therefore, it is urgent to develop ferroelectric capacitor structures and process preparation technologies that are compatible with standard CMOS processes.

[0005] Hafnium oxide-based ferroelectric thin film materials (FE-HfO2) are considered to be the next generation of ferroelectric memory materials due to their compatibility with CMOS processes, good miniaturization, low crystallization annealing temperature, and mature three-dimensional deposition processes. The ferroelectric capacitor structure based on FE-HfO2 and its preparation technology are expected to solve the bottleneck problem of PZT-based FRAM. Unlike PZT, in addition to its uses such as conductivity, inducing crystal nucleation and grain growth, and optimizing interfaces, the constraint effect of the electrode has a great influence on the ferroelectric properties of FE-HfO2. This is mainly due to the structural characteristics of FE-HfO2: Under normal pressure conditions, HfO2 mainly exists in three crystal structures, namely, the monoclinic phase at room temperature, the tetragonal phase in the medium temperature zone, and the cubic phase in the high temperature zone. The ferroelectricity of HfO2 thin films mainly originates from the non-centrosymmetric metastable orthorhombic phase (Pca21). Therefore, promoting and stabilizing the Pca21 ferroelectric phase is the basis for realizing the application of HfO2-based ferroelectric films and their devices. The confinement of electrodes is considered to be one of the main methods to stabilize the ferroelectric phase of HfO2-based thin films. At present, nitride electrodes represented by TiN and TaN are the most commonly used electrodes in FE-HfO2, and FRAM based on TiN / FE-HfO2 / TiN and TaN / FE-HfO2 / TaN ferroelectric capacitors have shown good application prospects. However, during crystallization annealing, HfO2 films are prone to react with TiN and TaN electrodes to form interface layers and element diffusion, resulting in degradation of the electrical properties of the film; when the thickness of the HfO2 film is further reduced, these effects will become more prominent. On the other hand, although ferroelectric capacitors such as Pt / FE-HfO2 / Pt, Ir / FE-HfO2 / Ir, Au / FE-HfO2 / Au, and W / FE-HfO2 / W also exhibit good ferroelectric properties, inert metals such as Pt, Ir, and Au are difficult to etch, and the leakage current of the W / FE-HfO2 / W ferroelectric capacitor is relatively large.

[0006] Based on the above problems, the hafnium oxide-based ferroelectric capacitor structure and preparation process with good process compatibility, excellent ferroelectric properties and high electrical reliability still need to be developed. Summary of the invention

[0007] (I) Purpose of the invention

[0008] The object of the present invention is to provide a hafnium oxide-based ferroelectric capacitor with good miniaturization and a preparation method thereof.

[0009] (II) Technical solution

[0010] In order to solve the above problems, the first aspect of the present invention provides a hafnium oxide-based ferroelectric capacitor, comprising a first bottom electrode (4), a second bottom electrode (5), a hafnium oxide-based ferroelectric film (6b), a first top electrode (7), a second top electrode (8) and a substrate (9) which are stacked in sequence from bottom to top;

[0011] The first-layer bottom electrode (4) and the second-layer top electrode (8) are conductive layers;

[0012] The second-layer bottom electrode (5) and the first-layer top electrode (7) are electrodes;

[0013] Both the second-layer bottom electrode (5) and the first-layer top electrode (7) are HfNx (0 < x ≤ 1.1), with a thickness of 5 - 20 nm; the second-layer bottom electrode (5) and the first-layer top electrode (7) have the same thickness;

[0014] The substrate includes: silicon, CMOS addressing, selection, and logic control circuits (1), metal electrodes, and interlayer dielectrics (2).

[0015] Optionally, the hafnium oxide-based ferroelectric capacitor further includes: a diffusion barrier layer (3a) or an adhesion layer (3b).

[0016] Optionally, the thickness of the first-layer bottom electrode (4) and the second-layer top electrode (8) is 10 - 150 nm;

[0017] The first-layer bottom electrode (4) and the second-layer top electrode (8) are respectively any one of polysilicon, TiN, W, Cu, Ni, Ru, and Co.

[0018] Optionally, the hafnium oxide-based ferroelectric thin film (6b) is doped with one or more of zirconium, aluminum, silicon, yttrium, strontium, lanthanum, lutetium, gadolinium, scandium, neodymium, germanium, and nitrogen elements, with a thickness of 3 - 20 nm.

[0019] Optionally, multi-layer interlayer dielectrics (2) and multi-layer metal electrodes are sequentially and overlappingly deposited on the CMOS addressing, selection, and logic control circuits (1).

[0020] To achieve the above object, the present invention also provides a method for manufacturing a hafnium oxide-based ferroelectric capacitor, including: forming a diffusion barrier layer (3a) or an adhesion layer (3b) on a pre-prepared substrate (9);

[0021] Forming a first-layer bottom electrode (4) on the diffusion barrier layer (3a) or the adhesion layer (3b);

[0022] Forming a second-layer bottom electrode (5) on the first-layer bottom electrode (4);

[0023] Forming a doped hafnium oxide thin film (6a) with a thickness of 3 - 20 nm on the second-layer bottom electrode (5);

[0024] Forming a first-layer top electrode (7) on the doped hafnium oxide thin film (6a);

[0025] Forming a second-layer top electrode (8) on the first-layer top electrode (7);

[0026] Annealing the device structure formed through the above steps to crystallize the doped hafnium oxide film (6a) to form a hafnium oxide-based ferroelectric film (6b) to obtain a hafnium oxide-based ferroelectric capacitor;

[0027] When the ferroelectric capacitor is embedded before the back-end multi-layer metal wiring process, the preparation of the substrate includes the following steps: preparing CMOS addressing, selection and logic control circuits (1) on a silicon substrate;

[0028] Depositing a layer of interlayer dielectric (2) on the CMOS addressing, selection and logic control circuit (1);

[0029] The interlayer dielectric (2) is planarized to obtain the substrate (9).

[0030] Optionally, the diffusion barrier layer (3a) or the bonding layer (3b) is made of any one or two of Ti, Ta, TiN and TaN, and has a thickness of 10-100 nm;

[0031] The diffusion barrier layer (3a) or the bonding layer (3b), the first bottom electrode (4), the second bottom electrode (5), the first top electrode (7) and the second top electrode (8) are all formed by deposition using a magnetron sputtering method.

[0032] Optionally, the doped hafnium oxide film (6a) is formed by deposition using an atomic layer deposition process.

[0033] Optionally, the annealing is performed in a high vacuum or inert gas environment, the annealing temperature is 400° C.-1000° C., and the annealing time is 1-300 s.

[0034] In addition, the present invention also provides another method for preparing a hafnium oxide-based ferroelectric capacitor, comprising: forming a diffusion barrier layer (3a) or an adhesive layer (3b) on a pre-prepared substrate (9);

[0035] forming a first bottom electrode (4) on the diffusion barrier layer (3a) or the bonding layer (3b);

[0036] forming a second bottom electrode (5) on the first bottom electrode (4);

[0037] forming a doped hafnium oxide film (6a) with a thickness of 3-20 nm on the second bottom electrode (5);

[0038] forming a first top electrode (7) on the doped hafnium oxide film (6a);

[0039] forming a second layer of top electrode (8) on the first layer of top electrode (7);

[0040] Annealing the device structure formed through the above steps to crystallize the doped hafnium oxide film (6a) to form a hafnium oxide-based ferroelectric film (6b) to obtain a hafnium oxide-based ferroelectric capacitor;

[0041] When the ferroelectric capacitor is embedded after the back-end multi-layer metal wiring process, the preparation of the substrate includes the following steps: preparing CMOS addressing, selection and logic control circuits (1) on a silicon substrate;

[0042] Depositing multiple layers of interlayer dielectrics (2) and multiple layers of metal electrodes sequentially and overlappingly on the CMOS addressing, selection and logic control circuit (1);

[0043] After the last interlayer dielectric layer is deposited, the last interlayer dielectric layer is planarized to obtain the substrate (9);

[0044] The diffusion barrier layer (3a) or bonding layer (3b) is made of any one or two of Ti, Ta, TiN and TaN, and has a thickness of 10-100 nm; the diffusion barrier layer (3a) or bonding layer (3b), the first bottom electrode (4), the second bottom electrode (5), the first top electrode (7) and the second top electrode (8) are all formed by magnetron sputtering deposition;

[0045] The doped hafnium oxide film (6a) is formed by deposition using an atomic layer deposition process;

[0046] The annealing is performed in a high vacuum or inert gas environment, the annealing temperature is 400° C.-1000° C., and the annealing time is 1-300 seconds.

[0047] (III) Beneficial effects

[0048] The above technical solution of the present invention has the following beneficial technical effects:

[0049] (1) Hafnium oxide-based ferroelectric thin films are used, which have good miniaturization properties and can maintain excellent ferroelectric properties when the thickness is less than 10 nm. This can meet the needs of proportional reduction of the ferroelectric memory integration process and increase storage capacity.

[0050] (2) The ferroelectric capacitor structure of double-layer bottom electrode + hafnium oxide-based ferroelectric film + double-layer top electrode is adopted. The second bottom electrode and the first top electrode in direct contact with the hafnium oxide-based ferroelectric film are nitride electrodes (HfNx), which can ensure stable ferroelectric performance. Compared with TiN or TaN electrodes, the double-layer electrode structure of low-resistivity conductive layer / HfNx can reduce the resistivity of the entire bottom / top electrode, meeting the requirements of high-speed, low-power ferroelectric memory.

[0051] (3) HfNx is used as the upper and lower electrodes in direct contact with the hafnium oxide-based ferroelectric film. Compared with TiN and TaN electrodes, HfNx is a nitride electrode with higher thermal stability and a better interface with the hafnium oxide-based ferroelectric film. In addition, there is no diffusion of other metal elements during the crystallization annealing process, which can achieve better electrical reliability.

[0052] (4) All electrode materials and hafnium oxide-based ferroelectric films used are materials commonly used in standard CMOS processes, and the deposition and etching processes are mature and have good compatibility with CMOS processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of a structure obtained by preparing a diffusion barrier layer or an adhesive layer on a substrate according to an embodiment of the present invention;

[0055] Figure 2 The present invention provides a process flow for preparing hafnium oxide-based ferroelectric capacitors;

[0056] Figure 3 According to an embodiment of the present invention Figure 1 A schematic diagram of the structure obtained by preparing a double-layer bottom electrode structure based on the structure of;

[0057] Figure 4 According to an embodiment of the present invention Figure 2 Schematic diagram of the structure obtained by preparing a doped hafnium oxide film based on the structure of;

[0058] Figure 5 According to an embodiment of the present invention Figure 3 A schematic diagram of the structure obtained by preparing a double-layer top electrode structure based on the structure of;

[0059] Figure 6 This is a hafnium oxide-based ferroelectric capacitor prepared according to an embodiment of the present invention.

[0060] Reference numerals:

[0061] 1: CMOS addressing, selection and logic control circuit; 2: interlayer dielectric; 3a: diffusion barrier layer; 3b: bonding layer; 4: first bottom electrode; 5: second bottom electrode; 6a: doped hafnium oxide film; 6b: hafnium oxide-based ferroelectric film; 7: first top electrode; 8: second top electrode; 9: substrate; 10: bottom electrode; 11: top electrode; 12a: hafnium oxide-based capacitor structure; 12b: hafnium oxide-based ferroelectric capacitor structure. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0063] Figure 1 It is a schematic structural diagram of a hafnium oxide-based ferroelectric capacitor according to an embodiment of the present invention.

[0064] like Figure 1 As shown, a hafnium oxide-based ferroelectric capacitor includes a first bottom electrode 4, a second bottom electrode 5, a hafnium oxide-based ferroelectric film 6b (formed by annealing 6a), a first top electrode 7 and a second top electrode 8 stacked in sequence from bottom to top; the first bottom electrode 4 and the second top electrode 8 are conductive layers; the second bottom electrode 5 and the first top electrode 7 are electrodes.

[0065] The first bottom electrode 4 and the second top electrode 8 are metal electrode materials with low resistivity and a thickness of 10-150 nm. It should be noted that the thickness of the first bottom electrode 4 and the second top electrode 8 can be the same or different, and the embodiment of the present invention does not limit this.

[0066] The first bottom electrode 4 and the second top electrode 8 are respectively any one of polysilicon, TiN, W, Cu, Ni, Ru and Co. It should be noted that the first bottom electrode 4 and the second top electrode 8 do not necessarily have to be made of the same metal electrode material and have the same thickness.

[0067] The second bottom electrode 5 and the first top electrode 7 are both hafnium nitride HfNx, wherein 0

[0068] The hafnium oxide-based ferroelectric film 6b is doped with one or more of zirconium, aluminum, silicon, yttrium, strontium, lanthanum, lutetium, gadolinium, scandium, neodymium, germanium, and nitrogen, and has a thickness of 3-20 nm.

[0069] An embodiment of the present invention provides a method for preparing a hafnium oxide-based ferroelectric capacitor, such as Figure 2 As shown, the following steps are included:

[0070] S0, preparing a substrate 9;

[0071] Among them, the substrate 9 is a CMOS addressing, selection and logic control circuit 1 prepared on p-type lightly doped silicon, and an interlayer dielectric 2 is deposited and a flattening process is completed. It can be completed in two ways, one is based on the front-end process, that is, the ferroelectric capacitor is embedded before the back-end multi-layer metal wiring process, and the first layer of interlayer dielectric deposition and flattening process is completed after the CMOS addressing, selection and logic control circuit is prepared, and the other is based on the back-end process, that is, the ferroelectric capacitor is embedded after the back-end multi-layer metal wiring process, and after the CMOS addressing, selection and logic control circuit and the multi-layer metal wiring process are completed, the last layer of interlayer dielectric is deposited and the flattening process is completed.

[0072] Specifically, when the ferroelectric capacitor is embedded before the back-end multi-layer metal wiring process, the preparation of the substrate includes the following steps: preparing a CMOS addressing, selection and logic control circuit 1 on a silicon substrate; depositing a layer of interlayer dielectric 2 on the CMOS addressing, selection and logic control circuit 1; and flattening the interlayer dielectric 2 to obtain the substrate 9.

[0073] When the ferroelectric capacitor is embedded after the back-end multi-layer metal wiring process, the preparation of the substrate includes the following steps: preparing a CMOS addressing, selection and logic control circuit 1 on a silicon substrate; depositing multiple layers of interlayer dielectrics 2 and multiple layers of metal electrodes on the CMOS addressing, selection and logic control circuit 1 in sequence and overlapping, that is, first depositing a layer of interlayer dielectric 2, then depositing a layer of metal electrode, and so on. After the last layer of interlayer dielectric is deposited, the last layer of interlayer dielectric is flattened to obtain the substrate 9. The total number of layers of interlayer dielectric 2 and metal electrode is 2-14 layers. For example, when the total number of layers of interlayer dielectric 2 and metal electrode is 4 layers, the structure is from bottom to top: CMOS addressing, selection and logic control circuit 1, interlayer dielectric 2, metal electrode, interlayer dielectric 2, metal electrode.

[0074] S1, forming a diffusion barrier layer 3a or a bonding layer 3b on a substrate 9;

[0075] S2, forming a first bottom electrode 4 on the diffusion barrier layer 3a or the bonding layer 3b;

[0076] The diffusion barrier layer or bonding layer is made of any one or two of Ti, Ta, TiN and TaN, and has a thickness of 10-100 nm.

[0077] S3, forming a second bottom electrode 5 on the first bottom electrode 4;

[0078] S4, forming a doped hafnium oxide film 6a with a thickness of 3-20 nm on the second bottom electrode 5;

[0079] S5, forming a first top electrode 7 on the doped hafnium oxide film 6a;

[0080] S6, forming a second top electrode 8 on the first top electrode 7;

[0081] S7, annealing the device structure formed by steps S1-S6 to crystallize the doped hafnium oxide film 6a to form a hafnium oxide-based ferroelectric film 6b, thereby completing the preparation of the hafnium oxide-based ferroelectric capacitor.

[0082] Wherein, annealing is carried out in a high vacuum or inert gas environment, the annealing temperature is 400° C.-1000° C., and the annealing time is 1-300 s.

[0083] Example 1

[0084] An embodiment of the present invention provides a method for preparing a hafnium oxide-based ferroelectric capacitor, comprising the following steps:

[0085] 1) Based on the front-end process, that is, the ferroelectric capacitor is embedded before the back-end multi-layer metal wiring process, after preparing the CMOS addressing, selection and logic control circuit, the CMOS addressing, selection and logic control circuit 1 is prepared on the p-type lightly doped silicon, the interlayer dielectric 2 is deposited and the planarization process is completed.

[0086] 2) Using magnetron sputtering method, 10 nm Ti and 50 nm TiN are deposited on substrate 9 as diffusion barrier layer 3a or bonding layer 3b (such as Figure 1 shown);

[0087] 3) A first bottom electrode 4 made of W material is deposited on the diffusion barrier layer 3a or the bonding layer 3b by magnetron sputtering, with a thickness of 50 nm, wherein the first bottom electrode 4 serves as the main conductive layer of the hafnium oxide-based ferroelectric capacitor.

[0088] 4) A HfN0.5 film with a thickness of 10 nm is deposited on the first bottom electrode 4 by a magnetron sputtering method as the second bottom electrode 5, so that the doped hafnium oxide film 6a is induced to form a ferroelectric phase during the crystallization annealing process. The first bottom electrode 4 and the second bottom electrode 5 together serve as the bottom electrode 10 of the ferroelectric capacitor (such as Figure 3 shown);

[0089] 5) Atomic layer deposition is used to deposit an aluminum-doped hafnium oxide film 6a on the second bottom electrode 5, with a doping content of 4.8% and a thickness of 10 nm (e.g. Figure 4 shown);

[0090] 6) A HfN0.5 film with a thickness of 10 nm is deposited on the doped hafnium oxide film 6a by magnetron sputtering as the first top electrode 7, so that the doped hafnium oxide film 6a is induced to form a ferroelectric phase during the crystallization annealing process.

[0091] 7) A second top electrode 8 of W material is deposited on the first top electrode 7 by a magnetron sputtering method, with a thickness of 50 nm, and the second top electrode 8 serves as the main conductive layer of the ferroelectric capacitor. The first top electrode 7 and the second top electrode 8 together serve as the top electrode 11 of the ferroelectric capacitor, and a preliminarily formed hafnium oxide-based capacitor structure 12a (such as Figure 5 shown).

[0092] 8) The hafnium oxide-based capacitor structure shown in 12a is subjected to crystallization annealing at a temperature of 700° C. for 60 seconds in a high vacuum, so that the doped hafnium oxide film 6a is crystallized to generate a ferroelectric phase, i.e., it has ferroelectric properties, and forms a hafnium oxide-based ferroelectric film 6b, thereby obtaining a hafnium oxide-based ferroelectric capacitor structure 12b (such as Figure 6 As shown in FIG. 1 , the hafnium oxide-based ferroelectric capacitor structure 12b is formed by annealing 12a. The crystallization annealing process is preferably rapid thermal annealing (RTA).

[0093] Example 2

[0094] An embodiment of the present invention provides a method for preparing a hafnium oxide-based ferroelectric capacitor, comprising the following steps:

[0095] 1) Based on the back-end process, that is, the ferroelectric capacitor is embedded in the back-end multi-layer metal wiring process, after the CMOS addressing, selection and logic control circuit and the multi-layer metal wiring process are completed, the CMOS addressing, selection and logic control circuit 1 is prepared on the p-type lightly doped silicon, the interlayer dielectric 2 is deposited and the planarization process is completed.

[0096] 2) Using magnetron sputtering method, 10 nm Ta and 80 nm TaN are deposited on substrate 9 as diffusion barrier layer 3a or bonding layer 3b (eg Figure 1 shown);

[0097] 3) A first bottom electrode 4 made of Cu material is deposited on the diffusion barrier layer 3a or the bonding layer 3b by magnetron sputtering, with a thickness of 100 nm, wherein the first bottom electrode 4 serves as the main conductive layer of the hafnium oxide-based ferroelectric capacitor.

[0098] 4) A 5 nm thick HfN1.1 thin film is deposited on the first bottom electrode 4 by magnetron sputtering as the second bottom electrode 5. The first bottom electrode 4 and the second bottom electrode 5 together serve as the bottom electrode 10 of the ferroelectric capacitor (eg Figure 3 shown);

[0099] 5) A zirconium-doped hafnium oxide film 6a is deposited on the second bottom electrode 5 by atomic layer deposition process, with a doping amount of 50%, i.e., forming Hf0.5Zr0.5O2 with a thickness of 8nm (e.g., Figure 4 shown);

[0100] 6) A HfN1.1 film with a thickness of 5 nm is deposited on the doped hafnium oxide film 6a by magnetron sputtering as the first top electrode 7, so that the doped hafnium oxide film 6a forms a ferroelectric phase during the crystallization annealing process.

[0101] 7) A second top electrode 8 of Cu material is deposited on the first top electrode 7 by a magnetron sputtering method, with a thickness of 150 nm. The second top electrode 8 serves as the main conductive layer of the ferroelectric capacitor. The first top electrode 7 and the second top electrode 8 together serve as the top electrode 11 of the ferroelectric capacitor, and a preliminarily formed hafnium oxide-based capacitor structure 12a (such as Figure 5 shown).

[0102] 8) The hafnium oxide-based capacitor structure shown in 12a is subjected to crystallization annealing at a temperature of 400° C. for 300 seconds in a high vacuum, so that the doped hafnium oxide film 6a is crystallized to generate a ferroelectric phase, i.e., it has ferroelectric properties, and forms a hafnium oxide-based ferroelectric film 6b, thereby obtaining a hafnium oxide-based ferroelectric capacitor structure 12b (such as Figure 6 The crystallization annealing process is preferably rapid thermal annealing (RTA).

[0103] Example 3

[0104] An embodiment of the present invention provides a method for preparing a hafnium oxide-based ferroelectric capacitor, comprising the following steps:

[0105] 1) Based on the front-end process, that is, the ferroelectric capacitor is embedded before the back-end multi-layer metal wiring process, after preparing the CMOS addressing, selection and logic control circuit, the CMOS addressing, selection and logic control circuit 1 is prepared on the p-type lightly doped silicon, the interlayer dielectric 2 is deposited and the planarization process is completed.

[0106] 2) Using magnetron sputtering technology, 10 nm Ti and 20 nm TiN are deposited on the substrate 9 as a diffusion barrier layer 3a or a bonding layer 3b (eg Figure 1 shown);

[0107] 3) A Co material is deposited on the diffusion barrier layer 3a or the bonding layer 3b by magnetron sputtering process as the first bottom electrode 4 with a thickness of 100 nm, wherein the first bottom electrode 4 serves as the main conductive layer of the hafnium oxide-based ferroelectric capacitor.

[0108] 4) A 20 nm thick HfN film is deposited on the first bottom electrode 4 by a magnetron sputtering process as the second bottom electrode 5, so that the doped hafnium oxide film 6a forms a ferroelectric phase during the crystallization annealing process. The first bottom electrode 4 and the second bottom electrode 5 together serve as the bottom electrode 10 of the ferroelectric capacitor (such as Figure 3 shown);

[0109] 5) Atomic layer deposition is used to deposit a silicon-doped hafnium oxide film 6a on the second bottom electrode 5, with a doping content of 4.4% and a thickness of 5 nm (e.g. Figure 4 shown);

[0110] 6) A 20 nm thick HfN film is deposited on the doped hafnium oxide film 6a by chemical vapor deposition as the first top electrode 7. The second electrode 5 uses hafnium nitride to enable the doped hafnium oxide film 6a to form a ferroelectric phase during the crystallization annealing process.

[0111] 7) A second top electrode 8 of Ru material is deposited on the first top electrode 7 by magnetron sputtering method, with a thickness of 100 nm, and the second top electrode 8 serves as the main conductive layer of the ferroelectric capacitor. The first top electrode 7 and the second top electrode 8 together serve as the top electrode 11 of the ferroelectric capacitor, and a preliminarily formed hafnium oxide-based capacitor structure 12a (such as Figure 5 shown).

[0112] 8) The hafnium oxide-based capacitor structure shown in 12a is subjected to crystallization annealing at a temperature of 1000° C. for 1 second in an inert gas (such as N2, Ar and other chemically inactive gases) to crystallize the doped hafnium oxide film 6a to generate a ferroelectric phase, i.e., to have ferroelectric properties, to form a hafnium oxide-based ferroelectric film 6b, thereby obtaining a hafnium oxide-based ferroelectric capacitor structure 12b (such as a bottom electrode 10, a hafnium oxide-based ferroelectric film 6b and a top electrode 11). Figure 6 The crystallization annealing process is preferably rapid thermal annealing (RTA).

[0113] The beneficial effects of the embodiments of the present invention are described below:

[0114] The present invention adopts hafnium oxide-based ferroelectric film. On the one hand, it has been widely used in CMOS integration process as a gate dielectric material, and the process is very mature, so it can reduce the integration process difficulty of the ferroelectric memory and reduce the production cost; on the other hand, it has good miniaturization, and can still maintain excellent ferroelectricity when the thickness is less than 10nm, which can meet the requirements of proportional reduction of the ferroelectric memory integration process and improve the storage capacity. In addition, hafnium-based nitride electrodes (HfNx) are used as upper and lower electrodes directly in contact with the hafnium oxide-based ferroelectric film. Compared with TiN and TaN electrodes, HfNx is a nitride electrode with higher thermal stability, and has a better interface with the hafnium oxide-based ferroelectric film. There is no diffusion of other metal elements during the crystallization annealing process, so better electrical reliability can be obtained; and the use of electrodes with lower resistivity as the conductive layer can reduce the resistivity of the entire bottom / top electrode, meeting the requirements of high-speed and low-power ferroelectric memory.

[0115] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A hafnium oxide-based ferroelectric capacitor, characterized in that: It includes a first bottom electrode (4), a second bottom electrode (5), a hafnium oxide-based ferroelectric thin film (6b), a first top electrode (7), a second top electrode (8), and a substrate (9) that are stacked in sequence from bottom to top; The first bottom electrode (4) and the second top electrode (8) are conductive layers; The second bottom electrode (5) and the first top electrode (7) are electrodes; Both the second bottom electrode (5) and the first top electrode (7) are HfNx (0 < x ≤ 1.1), and the thickness is 5 - 20 nm; the thicknesses of the second bottom electrode (5) and the first top electrode (7) are the same; The substrate includes: silicon, a CMOS addressing, selection, and logic control circuit (1), a metal electrode, and an interlayer dielectric (2); On the CMOS addressing, selection, and logic control circuit (1), multiple layers of interlayer dielectrics (2) and multiple layers of metal electrodes are deposited sequentially and overlappingly.

2. The hafnium oxide-based ferroelectric capacitor according to claim 1, characterized in that: The hafnium oxide-based ferroelectric capacitor further includes: a diffusion barrier layer (3a) or an adhesion layer (3b).

3. The hafnium oxide-based ferroelectric capacitor according to claim 1, characterized in that: The thicknesses of the first bottom electrode (4) and the second top electrode (8) are 10 - 150 nm; The first bottom electrode (4) and the second top electrode (8) are respectively any one of polysilicon, TiN, W, Cu, Ni, Ru, and Co.

4. The hafnium oxide-based ferroelectric capacitor according to claim 1, characterized in that: The hafnium oxide-based ferroelectric thin film (6b) is doped with one or more of zirconium, aluminum, silicon, yttrium, strontium, lanthanum, lutetium, gadolinium, scandium, neodymium, germanium, and nitrogen elements, and the thickness is 3 - 20 nm.

5. A method for preparing a hafnium oxide-based ferroelectric capacitor, characterized in that: It includes: Forming a diffusion barrier layer (3a) or an adhesion layer (3b) on a pre-prepared substrate (9); Forming a first bottom electrode (4) on the diffusion barrier layer (3a) or the adhesion layer (3b); Forming a second bottom electrode (5) on the first bottom electrode (4); Forming a doped hafnium oxide thin film (6a) with a thickness of 3 - 20 nm on the second bottom electrode (5); Forming a first top electrode (7) on the doped hafnium oxide thin film (6a); Forming a second top electrode (8) on the first top electrode (7); Annealing the device structure formed through the above steps to crystallize the doped hafnium oxide thin film (6a) to form a hafnium oxide-based ferroelectric thin film (6b), thereby obtaining a hafnium oxide-based ferroelectric capacitor; When the ferroelectric capacitor is embedded after the back-end multi-layer metal wiring process, the preparation of the substrate includes the following steps: preparing a CMOS addressing, selection, and logic control circuit (1) on a silicon substrate; Sequentially and overlappingly depositing multiple layers of interlayer dielectrics (2) and multiple layers of metal electrodes on the CMOS addressing, selection, and logic control circuit (1); After the deposition of the last layer of interlayer dielectric is completed, performing planarization treatment on the last layer of interlayer dielectric to obtain the substrate (9); The diffusion barrier layer (3a) or the adhesion layer (3b) is any one or two of Ti, Ta, TiN, and TaN, and the thickness is 10 - 100 nm; the diffusion barrier layer (3a) or the adhesion layer (3b), the first bottom electrode (4), the second bottom electrode (5), the first top electrode (7), and the second top electrode (8) are all deposited by magnetron sputtering; The doped hafnium oxide film (6a) is formed by deposition using an atomic layer deposition process; The annealing is performed in a high vacuum or inert gas environment, the annealing temperature is 400° C.-1000° C., and the annealing time is 1-300 seconds.

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