Semiconductor wafer and method for manufacturing semiconductor chip

Abstract

A semiconductor chip (1) includes: a rectangular circuit forming area (CA1) arranged on the semiconductor chip (1); an electronic circuit formed in the circuit forming area (CA1); a first sealing ring (SR1) formed along four outer peripheries of the circuit forming area (CA1) in a manner surrounding the outer periphery of the circuit forming area (CA1); and a second sealing ring (SR2) formed in parallel with the first sealing ring (SR1) on the remaining outer peripheries of the four outer peripheries of the circuit forming area (CA1) except for at least one outer periphery.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor chip, and to a method for manufacturing a semiconductor wafer and a semiconductor chip suitable for changing a dicing line according to, for example, a user's request while maintaining the effect of preventing circuit degradation by a sealing ring. Background Art

[0002] In each semiconductor chip cut out from a semiconductor wafer, a sealing ring made of copper (Cu), aluminum (Al), etc. is formed in a manner that surrounds the pattern of the electronic circuit and the outer periphery of the circuit formation area where various functional blocks are arranged. Through this sealing ring, for example, it is difficult for moisture to penetrate into the circuit from the periphery of the cut portion of the semiconductor chip, thereby suppressing the degradation of signal transmission inside the circuit. As a result, the reliability of the semiconductor chip is improved.

[0003] Patent document 1 discloses a technique related to a sealing ring. Specifically, in Patent document 1, a double sealing ring is formed so as to surround the outer periphery of a circuit forming area. Thus, for example, even if the outer sealing ring is damaged due to fragmentation during cutting, the inner sealing ring can prevent the inside of the circuit from being damaged.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent document 1: International Publication No. 2012 / 095907. Summary of the invention

[0007] However, in the future, semiconductor wafer manufacturers may foresee not cutting semiconductor wafers with circuit patterns formed thereon into semiconductor chips, but providing semiconductor wafers intact to customers (users) who have slicers (devices for cutting). Furthermore, semiconductor wafer manufacturers may foresee providing semiconductor wafers with common circuit patterns formed thereon to multiple customers.

[0008] Here, when semiconductor chips are cut out from a semiconductor wafer by dicing, chipping may occur in the semiconductor chip. The chipping refers to a notch, crack, etc. at the dicing cut of the chip end surface. Usually, even if chipping occurs, it can be tolerated depending on the degree of chipping.

[0009] For example, when the reflective liquid crystal display device is formed using the semiconductor chip, the reflective liquid crystal display device is not packaged, but is formed by bonding the semiconductor chip to glass. That is, the end face (cutting cut) of the semiconductor chip is exposed. Therefore, depending on the degree of cracking on the end face of the semiconductor chip, it is possible that a defect occurs when assembling the liquid crystal, or that the circuit deteriorates due to moisture absorption at the cracked part.

[0010] Here, the performance of the slicer, design constraints (e.g., the allowable amount of chipping formed on the end surface of the semiconductor chip), etc., vary from user to user, so the cutting conditions of the semiconductor wafer, specifically, the width of the cutting line of the semiconductor wafer, vary depending on the user. In particular, when the semiconductor chip is used to form a reflective liquid crystal display device, the cutting conditions of the semiconductor wafer may need to be changed depending on the difference in the liquid crystal assembly method, the difference in the use method of the reflective liquid crystal display device, etc.

[0011] However, when designing multiple semiconductor wafers with different cutting line widths to meet the requirements of multiple users, there is a problem of increased design cost. On the other hand, when cutting a common semiconductor wafer under different cutting conditions, it is possible to cut across the cutting line, in which case there is a possibility that the sealing ring will be damaged.

[0012] The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor wafer and a semiconductor chip, which can change the dicing line according to user's request, for example, while maintaining the effect of preventing circuit degradation by the seal ring.

[0013] A semiconductor chip in one embodiment of the present invention includes: a rectangular circuit forming area arranged on the semiconductor chip; an electronic circuit formed in the circuit forming area; a first sealing ring formed along each of the four outer peripheries of the circuit forming area in a manner surrounding the outer periphery of the circuit forming area; and a second sealing ring formed in parallel with the first sealing ring on the remaining outer peripheries of the circuit forming area other than at least one of the four outer peripheries.

[0014] A method for manufacturing a semiconductor chip in one embodiment of the present invention uses a semiconductor wafer, the semiconductor wafer comprising: a plurality of rectangular circuit forming areas divided into a matrix on the semiconductor wafer; an electronic circuit formed in each of the circuit forming areas; a first sealing ring formed along each of the four outer peripheries of the circuit forming area in a manner surrounding the outer periphery of each of the circuit forming areas; and a second sealing ring formed in parallel with the first sealing ring on the remaining outer periphery other than at least one of the four outer peripheries of each of the circuit forming areas. In the method for manufacturing the semiconductor chip, the semiconductor chip is cut out by cutting along any one of a first cutting line and a second cutting line, the first cutting line being defined by a first sealing ring disposed between adjacent circuit forming areas, and the second cutting line being defined by using at least the second sealing ring of the first sealing ring and the second sealing ring disposed between adjacent circuit forming areas.

[0015] According to the present embodiment, it is possible to provide a semiconductor wafer and a method for manufacturing a semiconductor chip that can maintain the effect of preventing circuit degradation by the seal ring and can change the dicing line used for dicing according to user's request, for example. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic plan view of the semiconductor wafer in the first embodiment.

[0017] Figure 2 will be formed in Figure 1 The diagram is a schematic enlarged plan view of a plurality of semiconductor chips of a semiconductor wafer.

[0018] Figure 3 It is a schematic cross-sectional view of the seal ring and its surrounding area.

[0019] Figure 4 It is a schematic plan view of the seal ring and its surrounding area.

[0020] Figure 5 This is a schematic plan view showing the circuit arrangement of a semiconductor chip used for forming a liquid crystal display device.

[0021] Figure 6 Yes Figure 5 An enlarged plan view of a portion of a semiconductor chip is shown.

[0022] Figure 7 is used Figure 5 A schematic perspective view of a liquid crystal display device formed by the semiconductor chip shown.

[0023] Figure 8 This is a schematic plan view showing an enlarged view of a plurality of semiconductor chips formed on a semiconductor wafer in the second embodiment.

[0024] Fig. 9 This is a schematic plan view showing an enlarged view of a plurality of semiconductor chips formed on a semiconductor wafer in the third embodiment. DETAILED DESCRIPTION

[0025] (Implementation Method 1)

[0026] Figure 1 1 is a schematic plan view of the semiconductor wafer 1 in the first embodiment. Figure 1 As shown, in a semiconductor wafer 1, a plurality of rectangular regions (hereinafter referred to as semiconductor chips 10) cut out as semiconductor chips 10 are formed (divided) into a matrix shape. The semiconductor wafer 1 is cut along a cutting line (more specifically, a center line of the cutting line) to cut out a plurality of semiconductor chips 10.

[0027] Figure 2is formed on a plurality of semiconductor wafers 1 (in Figure 2 In the example of FIG. 4 , there are four) semiconductor chips 10 which are enlarged and schematically shown in plan view. Figure 2 As shown, each semiconductor chip 10 includes a rectangular circuit forming region CA1 , a seal ring (first seal ring) SR1 , and a seal ring (second seal ring) SR2 .

[0028] In the circuit forming region CA1 of each semiconductor chip 10 , an electronic circuit pattern and various functional blocks are arranged.

[0029] The sealing rings SR1 are formed along the four outer peripheries of the circuit forming area CA1 so as to surround the outer periphery of the circuit forming area CA1. Hereinafter, the sealing rings SR1 formed along the upper side, the lower side, the right side, and the left side of the paper (the positive side in the y-axis direction, the negative side in the y-axis direction, the positive side in the x-axis direction, and the negative side in the x-axis direction based on the circuit forming area CA1) of the four outer peripheries of the circuit forming area CA1 are referred to as sealing rings SR1_U, SR1_D, SR1_R, and SR1_L, respectively.

[0030] The upper right corner T1_UR is formed by the respective ends of the sealing rings SR1_U and SR1_R formed along the upper side and the right side of the circuit forming area CA1. The upper left corner T1_UL is formed by the respective ends of the sealing rings SR1_U and SR1_L formed along the upper side and the left side of the circuit forming area CA1. The lower right corner T1_DR is formed by the respective ends of the sealing rings SR1_D and SR1_R formed along the lower side and the right side of the circuit forming area CA1. The lower left corner T1_DL is formed by the respective ends of the sealing rings SR1_D and SR1_L formed along the lower side and the left side of the circuit forming area CA1.

[0031] The seal ring SR2 is formed on two sides of the four outer peripheries of the circuit forming region CA1, which are located outside the circuit forming region CA1 compared to the seal ring SR1 and are formed in parallel with the seal ring SR1. Figure 2 In the example, the sealing ring SR2 is formed as sealing rings SR2_U and SR2_R on two sides on the upper and right sides of the paper surface (the positive side in the y-axis direction and the positive side in the x-axis direction based on the circuit forming area CA1) of the four outer peripheries of the circuit forming area CA1.

[0032] In addition, the seal ring SR2 is formed so as to be in contact with a portion of the seal ring SR1. Figure 2 In the example, the seal ring SR2 is formed from the lower right end T2_DR to the corner T1_DR of the seal ring SR1, and is also formed from the upper left end T2_UL to the corner T1_UL of the seal ring SR1. Therefore, the corners T1_DR and T1_UL have a T-shape in a plan view.

[0033] Here, two types of cut lines DL1 and DL2 are defined between adjacent semiconductor chips 10 by seal rings SR1 and SR2. Specifically, cut line DL1 is defined between adjacent semiconductor chips 10 by a set of seal rings SR1 facing each other. Cut line DL2 is defined between adjacent semiconductor chips 10 by a set of seal rings SR1 and SR2 facing each other. Figure 2 In the example, the width of the cutting line DL1 is greater than the width of the cutting line DL2.

[0034] Thus, in the semiconductor wafer 1 on which a common circuit pattern is formed, a plurality of semiconductor chips 10 can be cut out along any one of two different dicing lines DL1 and DL2 (more specifically, center lines CL1 and CL2 of the dicing lines DL1 and DL2 ).

[0035] Here, the performance and design constraints of the slicer vary from user to user, so the cutting conditions of the semiconductor wafer (specifically, the width of the cutting line of the semiconductor wafer) vary from user to user. In the semiconductor wafer 1 of this embodiment, the cutting line for cutting can be changed according to such user requirements.

[0036] For example, even if user U1 requires a semiconductor wafer having a wider dicing line width than user U2, it is not necessary to prepare semiconductor wafers having different dicing line widths for users U1 and U2, and a common semiconductor wafer 1 can be provided. In this case, user U1 only needs to cut a plurality of semiconductor chips 10 from semiconductor wafer 1 along dicing lines DL1 having a wider width. In addition, user U2 only needs to cut a plurality of semiconductor chips 10 from semiconductor wafer 1 along dicing lines DL2 having a narrower width.

[0037] In this way, in the semiconductor wafer 1 of the present embodiment, a plurality of sealing rings SR1 and SR2 are formed on each of the plurality of semiconductor chips 10 formed in a matrix. That is, in the semiconductor wafer 1 of the present embodiment, a plurality of different cutting lines DL1 and DL2 are defined between adjacent semiconductor chips 10. Thus, in the semiconductor wafer 1 of the present embodiment, a plurality of semiconductor chips 10 can be cut out along any one of the two different cutting lines DL1 and DL2. That is, in the semiconductor wafer 1 of the present embodiment, the cutting line used for cutting can be changed according to the user's requirements. In addition, even when cutting is performed along any one of the cutting lines DL1 and DL2, since at least the sealing ring SR1 remains, the effect of preventing circuit degradation by the sealing ring SR1 can be maintained.

[0038] In addition, in the semiconductor wafer 1 of the present embodiment, even when dicing is performed along either of the dicing lines DL1 and DL2, the size of each semiconductor chip 10 does not change. Therefore, even when dicing is performed along either of the dicing lines DL1 and DL2, the number of semiconductor chips 10 cut out from the semiconductor wafer 1 does not change.

[0039] In the present embodiment, the seal ring SR2 is formed on two sides, upper and right, of the four outer peripheries of the circuit forming region CA1 in each semiconductor chip 10 , but the present invention is not limited thereto and the seal ring SR2 may be formed on any two sides.

[0040] In addition, the width of the cutting line DL1 extending in the x-axis direction (the length in the y-axis direction) and the width of the cutting line DL1 extending in the y-axis direction (the length in the x-axis direction) can be set to any length. Similarly, the width of the cutting line DL2 extending in the x-axis direction (the length in the y-axis direction) and the width of the cutting line DL2 extending in the y-axis direction (the length in the x-axis direction) can be set to any length.

[0041] Figure 3 2 is a schematic cross-sectional view of the seal ring SR1 and its surrounding area. In addition, since the cross-sectional structure of the seal ring SR2 is the same as that of the seal ring SR1, its description is omitted.

[0042] like Figure 3 As shown, the sealing ring SR1 is formed in the height direction (z-axis direction) by metals M1 to M5 stacked on the silicon substrate of the semiconductor chip 1, a contact C1 connecting the silicon substrate and the metal M1, and through holes V1 to V4 connecting the metals M1 to M5.

[0043] Figure 4 1 is a schematic plan view of the seal rings SR1 and SR2 and the dummy pattern DM arranged around them. Figure 4 In the example of FIG. 1 , only the wiring layer of the metal M1 is shown, but the wiring layers of the metals M2 to M5 also have basically the same structure as the wiring layer of the metal M1.

[0044] Here, the contact and through hole used in each semiconductor chip 10 are usually determined to have a uniform minimum width so as to satisfy design constraints. However, the seal rings SR1 and SR2 are not subject to such design constraints and are formed so as to surround the outer periphery of the circuit forming area CA1 in a plan view. The T-shaped corner of the seal ring SR1 is also formed without being bound by design constraints.

[0045] In addition, if Figure 3 and Figure 4As shown, a dummy pattern DM is formed in an area where a circuit pattern is not formed in the peripheral area of ​​the sealing rings SR1 and SR2. A dummy pattern DM is also formed in the area surrounded by the sealing rings SR1 and SR2. Thus, even when cutting along any of the cutting lines DL1 and DL2, the coverage (distribution of metal) of each semiconductor chip 10 can be made uniform. In addition, in reality, the dummy pattern DM is formed in the wiring layer of the metals M1 to M5, and is not formed in the layer where the contact or through hole is formed.

[0046] In addition, due to the different widths of the sealing rings SR1 and SR2, the center line CL1 of the cutting line DL1 may enter the area surrounded by the sealing rings SR1 and SR2. In this case, when cutting is performed along the center line CL1 of the cutting line DL1, the cutting may enter the area surrounded by the sealing rings SR1 and SR2. However, even in this case, since the dummy pattern DM formed in the area surrounded by the sealing rings SR1 and SR2 does not generate steps inside or outside the area, high-precision cutting can be achieved.

[0047] In addition, TEG (Test Element Group) and alignment marks may be formed in the area surrounded by the seal rings SR1 and SR2. Thus, compared with the case where TEG or alignment marks are formed inside the seal ring SR1, signal noise generated by light incident on them can be blocked by the seal ring SR1.

[0048] (Application Examples)

[0049] Next, use Figures 5 to 8 , an example in which each semiconductor chip 10 cut out from the semiconductor wafer 1 is used to form a liquid crystal display device is described.

[0050] Figure 5 1 is a schematic plan view showing a semiconductor chip 10 for forming a liquid crystal display device as a semiconductor chip 10a. Figure 6 Yes Figure 5 A portion of a semiconductor chip 10a is shown in an enlarged plan view.

[0051] In addition, in this example, the width of the cutting line DL1 between the semiconductor chips 10 adjacent in the y-axis direction (the cutting line DL1 extending in the x-axis direction) is 200um, and the width of the cutting line DL1 between the semiconductor chips 10 adjacent in the x-axis direction (the cutting line DL1 extending in the y-axis direction) is 400um. In addition, in this example, the width of the cutting line DL2 between the semiconductor chips 10 adjacent in the y-axis direction (the cutting line DL2 extending in the x-axis direction) is 100um, and the width of the cutting line DL2 between the semiconductor chips 10 adjacent in the x-axis direction (the cutting line DL2 extending in the y-axis direction) is 100um.

[0052] First, a pixel area PA1 in which a plurality of pixels are arranged in a matrix is ​​provided in the central portion of the circuit formation area CA1 of the semiconductor chip 10 a .

[0053] A horizontal driver HD1 for driving a plurality of pixels in the horizontal direction (x-axis direction) is arranged in the area below the pixel area PA1 (the area on the negative side in the y-axis direction with respect to the pixel area PA1). In contrast, no circuit is arranged in the area above the pixel area PA1 (the area on the positive side in the y-axis direction with respect to the pixel area PA1), and there is sufficient margin.

[0054] In the left area of ​​the pixel area PA1 (the area on the negative side of the x-axis direction based on the pixel area PA1), a plurality of pads PD are arranged along the outer periphery of the circuit forming area CA1, and a plurality of input and output ports IO are arranged opposite to the plurality of pads PD. In addition, in the left area and right area of ​​the pixel area PA1 (the area on the positive side of the x-axis direction based on the pixel area PA1), vertical drivers VD1 and VD2 for driving a plurality of pixels in the vertical direction (y-axis direction) are arranged respectively. Here, the circuit is laid in the left area of ​​the pixel area PA1, and there is no surplus, but there is surplus in the right area of ​​the pixel area PA1.

[0055] In addition, a sealing area SA1 (see FIG. 1 ) is provided in an area surrounding the pixel area PA1 in the circuit formation area CA1. Figure 7 ). In the sealing area SA1, spacer balls are scattered together with the sealant. Then, a common electrode with light transmittance, that is, glass CE, is arranged on the semiconductor chip 10a. As a result, a gap is formed between the semiconductor chip 10a and the glass CE arranged on the upper surface of the semiconductor chip 10a. Liquid crystal is filled and sealed between the electrodes of the plurality of pixels P arranged on the semiconductor chip 10a and the glass CE, thereby forming a reflective liquid crystal display device.

[0056] As described above, the sealing area SA1 is provided in the area surrounding the pixel area PA1 in the circuit formation area CA1. The sealing area SA1 may also include vertical drivers VD1, VD2, horizontal driver HD1, etc. Here, in the area on the right side of the pixel area PA1, the area of ​​the vertical driver VD2 is smaller than the area of ​​the sealing area SA1. Therefore, in the area on the right side of the pixel area PA1, a gap is generated between the vertical driver VD2 and the chip end.

[0057] The size of the sealing area SA1 varies depending on the user who assembles the reflective liquid crystal display device. For example, since the user U1 can reduce the size of the sealing area SA1, a wide cutting line is required. On the other hand, the user U2 needs a larger sealing area SA1, but can also reduce the width of the cutting line. In this case, the user U1 only needs to cut a plurality of semiconductor chips 10a from the semiconductor wafer 1 along the wide cutting line DL1. On the other hand, the user U2 only needs to cut a plurality of semiconductor chips 10a from the semiconductor wafer 1 along the narrow cutting line DL2.

[0058] In addition, Patent Document 1 does not disclose or suggest the case where a common semiconductor wafer is cut under different cutting conditions. Therefore, if a common semiconductor wafer is cut under different cutting conditions in the related art, it is possible that the cutting line is crossed and the sealing ring is damaged in this case. That is, in the related art, it is not possible to cut a common semiconductor wafer under different cutting conditions. In the semiconductor wafer 1 of this embodiment, such a problem can be solved.

[0059] (Implementation Method 2)

[0060] Figure 8 The semiconductor wafer 2 formed in the second embodiment is a plurality of (in Figure 8 1 is an enlarged schematic plan view of four semiconductor chips 20 in the example.

[0061] In setting Figure 2 In each semiconductor chip 10 of the semiconductor wafer 1 shown in FIG. 1 , the seal ring SR2 is formed on two sides of the four outer peripheries of the circuit forming area CA1. Figure 8 In each semiconductor chip 20 of the semiconductor wafer 2 shown, the seal ring SR2 is formed only on one side among the four outer peripheral sides of the circuit forming area CA1.

[0062] exist Figure 8 In the example, the seal ring SR2 is formed as the seal ring SR2_R only on one side on the right side of the paper (the positive side in the x-axis direction with respect to the circuit formation area CA1) among the four outer peripheries of the circuit formation area CA1.

[0063] In addition, the seal ring SR2 is formed so as to be in contact with a portion of the seal ring SR1. Figure 8 In the example, the seal ring SR2 is formed from one end T2_UR of the seal ring SR2_R to the corner T1_UR of the seal ring SR1, and is also formed from the other end T2_DR of the seal ring SR2_R to the corner T1_DR of the seal ring SR1. Therefore, the corners T1_UR and T1_DR have a T-shape in a plan view.

[0064] Thus, between adjacent semiconductor chips 20, two types of cut lines DL1 and DL2 are defined by the sealing rings SR1 and SR2. Specifically, the cut line DL1 is defined by the set of opposite sealing rings SR1 between adjacent semiconductor chips 20. The cut line DL2 is defined by the set of opposite sealing rings SR1 and SR2 (or SR1 and SR1) between adjacent semiconductor chips 20. Figure 8 In the example, the widths of the cutting lines DL1 and DL2 extending in the y-axis direction are different, but the widths of the cutting lines DL1 and DL2 extending in the x-axis direction are the same.

[0065] The other structures of the semiconductor wafer 2 are the same as those of the semiconductor wafer 1 , and thus the description thereof will be omitted.

[0066] Thus, in the semiconductor wafer 2 of the present embodiment, a plurality of sealing rings SR1 and SR2 are formed on each of the plurality of semiconductor chips 20 formed in a matrix. That is, in the semiconductor wafer 2 of the present embodiment, a plurality of different cutting lines DL1 and DL2 are defined between adjacent semiconductor chips 20. Thus, in the semiconductor wafer 2 of the present embodiment, a plurality of semiconductor chips 20 can be cut out along any one of the two different cutting lines DL1 and DL2. That is, in the semiconductor wafer 3 of the present embodiment, the cutting line used for cutting can be changed according to the user's requirements. In addition, even when cutting is performed along any one of the cutting lines DL1 and DL2, since at least the sealing ring SR1 remains, the effect of preventing circuit degradation by the sealing ring SR1 can be maintained.

[0067] In the present embodiment, the seal ring SR2 is described as an example in which the seal ring SR2 is formed on one right side among the four outer peripheries of the circuit forming area CA1 in each semiconductor chip 20 , but the present invention is not limited thereto and the seal ring SR2 may be formed on any side.

[0068] In addition, in this embodiment, the case where the sealing ring SR2 is formed only on one side of the four outer peripheries of the circuit forming area CA1 in each semiconductor chip 20 is described as an example, but it is not limited to this. It can also be formed on two sides as in the case of embodiment 1, or it can be formed on any three sides.

[0069] (Implementation 3)

[0070] Fig. 9 The semiconductor wafer 3 formed in the third embodiment is a plurality of (in Fig. 9 1 is an enlarged schematic plan view of four semiconductor chips 30 in the example.

[0071] In setting Figure 2 In each semiconductor chip 10 of the semiconductor wafer 1 shown in FIG. 1 , the seal ring SR2 is formed along two sides of the four outer peripheries of the circuit forming area CA1. Fig. 9 In each semiconductor chip 30 of the semiconductor wafer 3 shown in the figure, the seal ring SR2 is formed along all of the four outer peripheries of the circuit forming region CA1 so as to surround the outer periphery of the circuit forming region CA1.

[0072] In addition, the seal ring SR2 is formed so as to be in contact with a portion of the seal ring SR1. Fig. 9 In the example of FIG. 1 , seal rings are further formed from the four corners of the seal ring SR1 to the four corners of the seal ring SR2. Thus, a T-shaped or cross-shaped seal is formed around the corners.

[0073] Thus, two types of scribe lines DL1 and DL2 are defined between adjacent semiconductor chips 30 by the seal rings SR1 and SR2. Specifically, scribe line DL1 is defined between adjacent semiconductor chips 30 by a set of opposing seal rings SR1. Slice line DL2 is defined between adjacent semiconductor chips 30 by a set of opposing seal rings SR2.

[0074] The other structures of the semiconductor wafer 3 are the same as those of the semiconductor wafer 1 , and thus the description thereof will be omitted.

[0075] In this way, in the semiconductor wafer 3 of the present embodiment, a plurality of sealing rings SR1 and SR2 are formed on each of the plurality of semiconductor chips 30 formed in a matrix. That is, in the semiconductor wafer 3 of the present embodiment, a plurality of different cutting lines DL1 and DL2 are defined between adjacent semiconductor chips 30. Thus, in the semiconductor wafer 3 of the present embodiment, a plurality of semiconductor chips 30 can be cut out along any one of the two different cutting lines DL1 and DL2. That is, in the semiconductor wafer 3 of the present embodiment, the cutting line used for cutting can be changed according to the user's requirements. In addition, even when cutting is performed along any one of the cutting lines DL1 and DL2, since at least the sealing ring SR1 remains, the effect of preventing circuit degradation by the sealing ring SR1 can be maintained.

[0076] This application claims the benefit of priority based on Japanese patent application No. 2019-112648, filed on June 18, 2019, the disclosure of which is incorporated herein in its entirety.

[0077] Industrial Applicability

[0078] The present invention can be preferably applied to the manufacture of semiconductor chips used in liquid crystal display devices.

[0079] Explanation of symbols

[0080] 1 Semiconductor wafer

[0081] 2 Semiconductor wafer

[0082] 3 Semiconductor wafers

[0083] 10. Semiconductor Chip

[0084] 10a Semiconductor chip

[0085] 20 Semiconductor Chip

[0086] 30 Semiconductor Chip

[0087] CA1 circuit formation area

[0088] C1 Contact

[0089] CE Glass

[0090] CL1, CL2 center line

[0091] DL1 Cutting Line

[0092] DL2 Cutting Line

[0093] DM dummy pattern

[0094] HD1 Horizontal Driver

[0095] IO Input and Output Ports

[0096] M1~M5 Metal

[0097] P Pixel

[0098] PA1 Pixel Area

[0099] PD Pad

[0100] SA1 Sealing area

[0101] SR1 seal

[0102] SR2 seal

[0103] SR1_U, SR1_D, SR1_R, SR1_L sealing ring

[0104] SR2_U, SR2_R sealing ring

[0105] T1_UR, T1_UL, T1_DR, T1_DL corner

[0106] T2_UR, T2_UL, T2_DR Ends (corners)

[0107] V1~V4 through hole

[0108] VD1, VD2 vertical drivers

Claims

1. A semiconductor wafer, comprising: A plurality of rectangular circuit forming areas are divided into a matrix on a semiconductor wafer; An electronic circuit is formed in each of the circuit forming regions; A first sealing ring is formed along each of four outer peripheries of the circuit forming area in a manner of surrounding the outer periphery of each of the circuit forming areas; a second seal ring formed in parallel with the first seal ring on the remaining outer peripheries other than at least one outer periphery of the four outer peripheries of each of the circuit forming regions; a first cutting line defined by a first sealing ring disposed between adjacent circuit forming areas; as well as The second cutting line is defined by using at least the second sealing ring of the first sealing ring and the second sealing ring disposed between the adjacent circuit forming areas.

2. The semiconductor wafer according to claim 1, wherein: The second seal ring is formed to be in contact with a portion of the first seal ring.

3. The semiconductor wafer according to claim 1 or 2, wherein: A dummy pattern is formed in a region surrounded by the first seal ring and the second seal ring.

4. A method for manufacturing a semiconductor chip, wherein the semiconductor chip uses a semiconductor wafer, and the semiconductor wafer comprises: A plurality of rectangular circuit forming areas are divided into a matrix on a semiconductor wafer; An electronic circuit is formed in each of the circuit forming regions; A first sealing ring is formed along each of four outer peripheries of the circuit forming area in a manner of surrounding the outer periphery of each of the circuit forming areas; a second seal ring formed in parallel with the first seal ring on the remaining outer peripheries other than at least one outer periphery of the four outer peripheries of each of the circuit forming regions; a first cutting line defined by a first sealing ring disposed between adjacent circuit forming areas; as well as The second cutting line is defined by using at least the second sealing ring of the first sealing ring and the second sealing ring disposed between the adjacent circuit forming areas, In the method for manufacturing the semiconductor chip, Semiconductor chips are cut out by cutting along any one of the first cutting line and the second cutting line.

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