Wiring congestion prediction method and wiring congestion prediction system

Abstract

The present invention provides a wiring congestion prediction method, including dividing a circuit to obtain at least two circuit blocks, wherein the circuit block includes a module and a port, calculating the connection complexity of the circuit block, wherein the connection complexity is a quantitative relationship between the number of modules and the number of ports in the circuit block, comparing the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity, dividing the circuit into circuit blocks, and then calculating the connection complexity of the circuit block, and then comparing the connection complexity of the circuit block with the complexity threshold to determine the congestion level of the circuit block, and the wiring congestion level of each part of the circuit can be estimated without performing an initial layout of the circuit, optimizing the circuit layout according to the wiring congestion level, and reducing the probability of wiring congestion. The present invention also provides a layout congestion prediction system for implementing the layout congestion prediction method.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a wiring congestion prediction method and a wiring congestion prediction system. Background Art

[0002] The physical implementation process of the automated design of a Field Programmable Gate Array (FPGA) includes: 1. placing all circuit modules in legal positions according to chip resources; 2. utilizing chip interconnection resources to physically connect all circuit modules.

[0003] As electronic circuits used in FPGAs become more and more complex, when the logic of some circuits is very complex or the overall layout and routing resources of the chip are tight, layout and routing congestion will occur. Routing congestion will cause multiple wire nets to occupy limited hotspot resources, and the router can only solve routing conflicts by routing in a roundabout way, thus affecting the timing quality of the chip design, and in more serious cases, even causing routing failures.

[0004] Currently, the congested area is estimated through the global routing method, but the global routing method can only be calculated and iterated based on the existing initial layout. Although global routing can predict local congested areas, it cannot give prediction results at the beginning of layout, and the initial layout has an important impact on the quality of the final layout; the calculation of bus network length and layout utilization is simple and efficient, but they are only an assessment of the average level of congestion of the entire circuit routing, and cannot be specific to local hot spots.

[0005] Therefore, it is necessary to provide a novel wiring congestion prediction method and wiring congestion prediction system to solve the above problems existing in the prior art. Summary of the invention

[0006] The purpose of the present invention is to provide a wiring congestion prediction method and a wiring congestion prediction system to predict the wiring congestion degree of each part of the circuit before the initial layout, optimize the circuit layout according to the wiring congestion degree, and reduce the probability of wiring congestion.

[0007] To achieve the above-mentioned purpose, the routing congestion prediction method of the present invention is applied to the physical implementation process of FPGA circuit layout, including:

[0008] Dividing the circuit to obtain at least two circuit blocks, wherein the circuit block includes a module and a port;

[0009] Calculating the connection complexity of the circuit block, where the connection complexity is a quantitative relationship between the number of the modules and the number of the ports in the circuit block;

[0010] The connection complexity is compared with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity.

[0011] The beneficial effects of the wiring congestion estimation method are: dividing the circuit to obtain at least two circuit blocks, the circuit block includes a module and a port, calculating the connection complexity of the circuit block, the connection complexity is the quantitative relationship between the number of modules and the number of ports in the circuit block, comparing the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity, dividing the circuit into circuit blocks, and then calculating the connection complexity of the circuit blocks, and then comparing the connection complexity of the circuit blocks with the complexity threshold to determine the congestion level of the circuit blocks, estimating the wiring congestion level of each part of the circuit without performing an initial layout of the circuit, optimizing the circuit layout according to the wiring congestion level, and reducing the probability of wiring congestion.

[0012] Optionally, dividing the circuit to obtain at least two circuit blocks includes:

[0013] The circuit is divided according to the hierarchical relationship information of the circuit to obtain at least two primary split units, wherein the primary split units include modules. The beneficial effect is that the hierarchical relationship information of the circuit is the initial attribute of the circuit, which facilitates the division of the circuit.

[0014] Optionally, dividing the circuit to obtain at least two circuit blocks further includes:

[0015] Determining whether the size of the primary split unit is smaller than a circuit block size threshold;

[0016] If it is determined that the size of the primary split unit is smaller than the circuit block size threshold, the primary split unit is used as the circuit block;

[0017] If it is determined that the size of the primary split unit is greater than the circuit block size threshold, the primary split unit is recursively divided to obtain at least two circuit blocks whose sizes are both less than or equal to the circuit block size threshold. The beneficial effect is that the size of the primary split unit is determined to improve the accuracy of the estimated congestion level and avoid the situation where the individual primary split units are too large and affect the estimation of the congestion level.

[0018] Optionally, calculating the connection complexity of the circuit block includes:

[0019] Recursively splitting the circuit block to obtain at least two sub-circuit blocks whose sizes are both smaller than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes a module and a port;

[0020] Counting the number of the modules and the number of the ports in each of the sub-circuit blocks;

[0021] Performing linear fitting with the number of the modules and the number of the ports in each of the sub-circuit blocks as coordinates to obtain a straight line;

[0022] The first connection complexity calculation formula Calculate the connection complexity of the circuit block, where r represents the connection complexity of the circuit block, G i represents the number of modules in the i-th sub-circuit block, represents the average value of the number of modules in all the sub-circuit blocks, E i represents the number of ports in the i-th sub-circuit block, Represents the average value of the number of ports in all the sub-circuit blocks. Its beneficial effect is that: the circuit block is recursively split until the sub-circuit block is less than or equal to the sub-circuit block threshold, and then the internal connection of the circuit block can be well reflected by fitting a straight line, accurately reflecting the connection complexity.

[0023] Optionally, calculating the connection complexity of the circuit block includes:

[0024] Recursively splitting the circuit block to obtain at least two sub-circuit blocks whose sizes are both less than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes a module, a port, and a wire net, wherein the modules are connected through the wire net, and the module and the port are connected through the wire net;

[0025] Counting the number of the modules and the number of the ports in each of the sub-circuit blocks;

[0026] The second connection complexity calculation formula The connection complexity of the circuit block is calculated, wherein r represents the connection complexity of the circuit block, E represents the total number of ports of all the sub-circuit blocks, G represents the total number of modules of all the sub-circuit blocks, and P represents the total number of pins of all the modules. The beneficial effect is that the connection complexity of the circuit block can be quickly obtained without fitting a straight line, and the data processing efficiency is high.

[0027] Optionally, the routing congestion estimation method further includes treating the pins of the immovable macromodules in the circuit block as ports of the circuit block. The beneficial effect is that it is easy to avoid the problem of the number of immovable macromodules and pin imbalance in the circuit.

[0028] Optionally, the circuit is divided to obtain at least two circuit blocks, and further includes the circuit block size threshold selection step, wherein the circuit block size threshold selection step includes obtaining the circuit block size threshold according to the scale of the top-level circuit of the circuit. The beneficial effect is that the scale of the top-level circuit of the circuit includes circuits of all levels described below, so obtaining the circuit block size threshold according to the scale of the top-level circuit of the circuit can avoid taking too long due to the excessively large scale of the circuit, and can also improve the accuracy of the estimation of the routing congestion degree when the circuit scale is small.

[0029] Optionally, before dividing the circuit, the following steps are included:

[0030] According to the ratio of the area of ​​the basic logic unit in the FPGA to the area of ​​the movable macro module, the movable macro module in the circuit is converted into a corresponding number of logic units. The beneficial effect is that it is easy to balance the movable macro modules in the circuit to avoid them being too large and affecting the estimation of the wiring congestion degree.

[0031] The present invention also provides a wiring congestion prediction system, which includes a division unit, a connection complexity calculation unit and a comparison unit. The division unit is used to divide the circuit to obtain at least two circuit blocks, and the circuit block includes a module and a port. The connection complexity calculation unit is used to calculate the connection complexity of the circuit block, and the connection complexity is a quantitative relationship between the number of modules and the number of ports in the circuit block. The comparison unit is used to compare the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity.

[0032] The beneficial effects of the wiring congestion prediction system are as follows: the division unit is used to divide the circuit to obtain at least two circuit blocks, the circuit block includes a module and a port, the connection complexity calculation unit is used to calculate the connection complexity of the circuit block, the connection complexity is the quantitative relationship between the number of modules and the number of ports in the circuit block, the comparison unit is used to compare the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity, the circuit is divided into circuit blocks, and then the connection complexity of the circuit blocks is calculated, and then the congestion level of the circuit blocks is determined by comparing the connection complexity of the circuit blocks with the complexity threshold, and the wiring congestion level of each part of the circuit can be estimated without the need for initial layout of the circuit, thereby reducing the probability of congestion in subsequent wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural block diagram of the wiring congestion prediction system of the present invention;

[0034] Figure 2 A flowchart of a wiring congestion estimation method in some embodiments of the present invention;

[0035] Figure 3 A flow chart of calculating the connection complexity of a circuit block in some embodiments of the present invention;

[0036] Figure 4 Schematic diagram of circuit blocks in some embodiments of the present invention;

[0037] Figure 5 The flowchart is a flowchart of calculating the connection complexity of a circuit block in some other embodiments of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0039] In view of the problems existing in the prior art, an embodiment of the present invention provides a wiring congestion prediction system. Figure 1 The wiring congestion estimation system 100 includes a division unit 101, a connection complexity calculation unit 102 and a comparison unit 103. The division unit 101 is used to divide the circuit to obtain at least two circuit blocks, and the circuit block includes a module and a port. The connection complexity calculation unit 102 is used to calculate the connection complexity of the circuit block, and the connection complexity is a quantitative relationship between the number of modules and the number of ports in the circuit block. The comparison unit 103 is used to compare the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity.

[0040] Figure 2 FIG. 1 is a flowchart of a method for estimating wiring congestion in some embodiments of the present invention. Figure 2 The routing congestion prediction method is implemented by the routing congestion prediction system. The routing congestion prediction method is applied to the physical implementation process of FPGA circuit layout, including the following steps:

[0041] S1: Divide the circuit to obtain at least two circuit blocks, where the circuit block includes a module and a port;

[0042] S2: Calculate the connection complexity of the circuit block, where the connection complexity is a quantitative relationship between the number of the modules and the number of the ports in the circuit block;

[0043] S3: Compare the connection complexity with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity.

[0044] In some embodiments, dividing the circuit to obtain at least two circuit blocks includes:

[0045] The circuit is divided according to the hierarchical relationship information of the circuit to obtain at least two primary split units, wherein the primary split units include modules.

[0046] In some embodiments, dividing the circuit to obtain at least two circuit blocks further includes:

[0047] Determining whether the size of the primary split unit is smaller than a circuit block size threshold;

[0048] If it is determined that the size of the primary split unit is smaller than the circuit block size threshold, the primary split unit is used as the circuit block;

[0049] If it is determined that the size of the primary split unit is greater than the circuit block size threshold, the primary split unit is recursively divided to obtain at least two circuit blocks whose sizes are both less than or equal to the circuit block size threshold. The size of the processing split unit includes the number of modules.

[0050] Figure 3 FIG. 1 is a flow chart for calculating the connection complexity of a circuit block in some embodiments of the present invention. Figure 3 , the calculation of the connection complexity of the circuit block comprises the following steps:

[0051] S11: recursively split the circuit block to obtain at least two sub-circuit blocks whose sizes are both smaller than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes a module and a port;

[0052] S12: Counting the number of the modules and the number of the ports in each of the sub-circuit blocks;

[0053] S13: performing linear fitting with the number of the modules and the number of the ports in each of the sub-circuit blocks as coordinates to obtain a straight line;

[0054] S14: Calculate the complexity of the first connection using the formula Calculate the connection complexity of the circuit block, where r represents the connection complexity of the circuit block, G i represents the number of modules in the i-th sub-circuit block, represents the average value of the number of modules in all the sub-circuit blocks, E i represents the number of ports in the i-th sub-circuit block, represents the average value of the number of ports in all the sub-circuit blocks. The size of the circuit block includes the number of modules.

[0055] In some embodiments, the structure of the sub-circuit block is the same as the composition of the circuit block, both include at least one module and at least one port. When including at least two modules, both also include at least two wire networks, which are used for connecting between the modules and between the modules and the ports.

[0056] Figure 4 Schematic diagram of circuit blocks in some embodiments of the present invention. Figure 4 The circuit block includes 5 modules 200, 9 wire nets 300 and 7 ports 400. The wire nets 300 are used for connecting the modules 200 and connecting the modules 200 to the ports 400. The circuit blocks are connected through the ports 400, wherein the number of wire nets 300 connected to the modules 200 is the number of pins of the modules 200.

[0057] For example, the circuit is recursively split to obtain m sub-circuit blocks, the number of modules of the first sub-circuit block is G1, the number of modules of the second sub-circuit block is G2, the number of modules of the third sub-circuit block is G3, etc. The number of modules of the mth sub-circuit block is G m , the number of ports of the first sub-circuit block is E1, the number of ports of the second sub-circuit block is E2, the number of ports of the third sub-circuit block is E3... the number of ports of the mth sub-circuit block is E m , taking the number of modules of the sub-circuit module as the horizontal coordinate and the number of ports of the sub-circuit module as the vertical coordinate, the following coordinates can be formed: (G1, E1), (G2, E2), (G3, E3)... (G m 、E m ), for coordinates (G1, E1), (G2, E2), (G3, E3)...(G m 、E m ) is linearly fitted to obtain a straight line. Wherein, m is a natural number greater than or equal to i, and i is a natural number greater than or equal to 1 and less than or equal to m.

[0058] Figure 5 FIG. 1 is a flow chart of calculating the connection complexity of a circuit block in some other embodiments of the present invention. Figure 5 , the calculation of the connection complexity of the circuit block comprises the following steps:

[0059] S21: recursively split the circuit block to obtain at least two sub-circuit blocks whose sizes are both smaller than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes a module, a port, and a wire network, wherein the modules are connected through the wire network, and the modules and the ports are connected through the wire network;

[0060] S22: Counting the number of the modules and the number of the ports in each of the sub-circuit blocks;

[0061] S23: The second connection complexity calculation formula Calculate the connection complexity of the circuit block, where r represents the connection complexity of the circuit block, E represents the total number of ports of all the sub-circuit blocks, G represents the total number of modules of all the sub-circuit blocks, and P represents the total number of pins of all the modules. The recursive splitting is to split a circuit block into at least two first intermediate blocks, and then continue to split the first intermediate block whose size is greater than the sub-circuit block size threshold to obtain at least two second intermediate blocks, and the first intermediate block whose size is less than or equal to the sub-circuit block size threshold is used as the sub-circuit block; continue to split the second intermediate block whose size is greater than the sub-circuit block size threshold to obtain at least two third intermediate blocks, if the size of the third intermediate blocks is less than or equal to the sub-circuit block size threshold, then stop splitting, if the size of any of the third intermediate blocks is greater than the sub-circuit block size threshold, then continue splitting.

[0062] In some embodiments, the routing congestion estimation method further includes treating the pins of the immovable macromodules in the circuit block as ports of the circuit block. The immovable macromodules in the circuit block include a serializer (SERializer), a deserializer (DESerializer), a high-speed serial computer expansion bus standard interface (Peripheral Component Interconnect Express, PCIE), a double data rate synchronous dynamic random access memory (Double Data Rate, DDR), etc.

[0063] In some embodiments, the circuit is divided to obtain at least two circuit blocks, and further includes the circuit block size threshold selection step, wherein the circuit block size threshold selection step includes obtaining the circuit block size threshold according to the size of the top-level circuit of the circuit.

[0064] In some embodiments, before dividing the circuit, the following steps are included:

[0065] According to the ratio of the area of ​​the basic logic unit in the FPGA to the area of ​​the movable macro module, the movable macro module in the circuit is converted into a corresponding number of logic units. The movable macro module in the circuit includes a digital signal processing module (Digital Signal Processor, DSP), a memory module (ERAM)

[0066] In some embodiments, the division and the recursive splitting may both use a clustering algorithm (cluster) or a minimum cut algorithm (min-cut), or other methods may be used to split the circuit, which is not specifically limited herein.

[0067] In some embodiments, the complexity threshold includes a first complexity threshold, a second complexity threshold, a third complexity threshold and a fourth complexity threshold, and the congestion level includes a first level congestion level, a second level congestion level, a third level congestion level, a fourth level congestion level and a fifth level congestion level. When the connection complexity is greater than or equal to the first complexity threshold, the circuit block is judged to be at the first level of congestion; when the connection complexity is less than the first complexity threshold and greater than or equal to the second complexity threshold, the circuit block is judged to be at the second level of congestion; when the connection complexity is less than the second complexity threshold and greater than or equal to the third complexity threshold, the circuit block is judged to be at the third level of congestion; when the connection complexity threshold is less than the third complexity threshold and greater than or equal to the fourth complexity threshold, the circuit block is judged to be at the fourth level of congestion; and when the connection complexity threshold is less than the fourth complexity threshold, the circuit block is judged to be at the fifth level of congestion. Optionally, the first complexity threshold is 0.85, the second complexity threshold is 0.7, the third complexity threshold is 0.55, and the fourth complexity threshold is 0.4.

[0068] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A routing congestion estimation method, applied to the physical implementation process of FPGA circuit layout, characterized in that: include: Dividing the circuit to obtain at least two circuit blocks, wherein the circuit block includes a module and a port; Calculating the connection complexity of the circuit block, where the connection complexity is a quantitative relationship between the number of the modules and the number of the ports in the circuit block, includes: The circuit block is recursively split to obtain at least two sub-circuit blocks whose sizes are both less than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes modules and ports; the number of the modules and the number of the ports in each sub-circuit block are counted; a linear fit is performed with the number of the modules and the number of the ports in each sub-circuit block as coordinates to obtain a straight line; and a first connection complexity calculation formula is used to calculate the connection complexity. , calculate the connection complexity of the circuit block, where r represents the connection complexity of the circuit block, Indicates the number of modules in the sub-circuit block, represents the average value of the number of modules in all the sub-circuit blocks, Indicates the number of ports in the sub-circuit block, represents the average value of the number of ports in all the sub-circuit blocks; n represents the total number of the sub-circuit blocks in the circuit block; Or, recursively split the circuit block to obtain at least two sub-circuit blocks whose sizes are both less than or equal to the sub-circuit block size threshold, the sub-circuit block comprising modules, ports and wire nets, the modules are connected through the wire nets, and the modules and the ports are connected through the wire nets; counting the number of the modules and the number of the ports in each of the sub-circuit blocks; calculating the complexity of the second connection using the formula , calculating the connection complexity of the circuit block, wherein r represents the connection complexity of the circuit block, E represents the total number of ports of all the sub-circuit blocks, G represents the total number of modules of all the sub-circuit blocks, and P represents the total number of pins of all the modules; The size of a sub-circuit block is the number of modules contained in the sub-circuit block; The connection complexity is compared with a preset complexity threshold to determine the congestion level of the circuit block corresponding to the connection complexity.

2. The method for estimating routing congestion according to claim 1, characterized in that: The circuit is divided to obtain at least two circuit blocks, including: The circuit is divided according to the hierarchical relationship information of the circuit to obtain at least two primary split units, wherein the primary split units include modules.

3. The method for estimating routing congestion according to claim 2, characterized in that: The step of dividing the circuit to obtain at least two circuit blocks further includes: Determining whether the size of the primary split unit is smaller than a circuit block size threshold; If it is determined that the size of the primary split unit is smaller than the circuit block size threshold, the primary split unit is used as the circuit block; If it is determined that the size of the primary split unit is greater than the circuit block size threshold, recursively split the primary split unit to obtain at least two circuit blocks whose sizes are both less than or equal to the circuit block size threshold; The size of the primary split unit is the number of the modules included in the primary split unit, and the size of the circuit block is the number of the modules included in the circuit block.

4. The method for estimating wiring congestion according to claim 3, characterized in that: The method further includes considering the pins of the macromodules that cannot be moved in the circuit block as ports of the circuit block.

5. The method for estimating wiring congestion according to claim 3, characterized in that: The method of dividing the circuit to obtain at least two circuit blocks also includes the circuit block size threshold selection step, and the circuit block size threshold selection step includes obtaining the circuit block size threshold according to the scale of the top-level circuit of the circuit.

6. The method for estimating routing congestion according to claim 1, characterized in that: Before dividing the circuit, include: According to the ratio of the area of ​​the basic logic unit in the FPGA to the area of ​​the movable macro module, the movable macro modules in the circuit are converted into a corresponding number of logic units.

7. A wiring congestion prediction system, characterized in that: Used to implement the wiring congestion estimation method according to any one of claims 1 to 6, the wiring congestion estimation system comprises a division unit, a connection complexity calculation unit and a comparison unit, the division unit is used to divide the circuit to obtain at least two circuit blocks, the circuit block comprises a module and a port, the connection complexity calculation unit is used to calculate the connection complexity of the circuit block, the connection complexity is a quantitative relationship between the number of modules and the number of ports in the circuit block, and the comparison unit is used to compare the connection complexity with a preset complexity threshold to determine the congestion degree of the circuit block corresponding to the connection complexity; The method for calculating the connection complexity of the circuit block includes: The circuit block is recursively split to obtain at least two sub-circuit blocks whose sizes are both less than or equal to a sub-circuit block size threshold, wherein the sub-circuit block includes modules and ports; the number of the modules and the number of the ports in each sub-circuit block are counted; a linear fit is performed with the number of the modules and the number of the ports in each sub-circuit block as coordinates to obtain a straight line; and a first connection complexity calculation formula is used to calculate the connection complexity. , calculate the connection complexity of the circuit block, where r represents the connection complexity of the circuit block, Indicates the number of modules in the sub-circuit block, represents the average value of the number of modules in all the sub-circuit blocks, Indicates the number of ports in the sub-circuit block, represents the average value of the number of ports in all the sub-circuit blocks; n represents the total number of the sub-circuit blocks in the circuit block; Or, recursively split the circuit block to obtain at least two sub-circuit blocks whose sizes are both less than or equal to the sub-circuit block size threshold, the sub-circuit block comprising modules, ports and wire nets, the modules are connected through the wire nets, and the modules and the ports are connected through the wire nets; counting the number of the modules and the number of the ports in each of the sub-circuit blocks; calculating the complexity of the second connection using the formula , calculating the connection complexity of the circuit block, wherein r represents the connection complexity of the circuit block, E represents the total number of ports of all the sub-circuit blocks, G represents the total number of modules of all the sub-circuit blocks, and P represents the total number of pins of all the modules; The size of the sub-circuit block is the number of modules included in the sub-circuit block.

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