Nonvolatile memory device including a string of memory cells

Abstract

A nonvolatile memory device is provided which includes a memory cell string using a resistance change material. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction, a plurality of gates and a plurality of insulators alternately arranged in the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor-oxide including a mixture of a semiconductor material including the semiconductor layer and a transition metal oxide.

Description

Technical Field

[0001] This disclosure relates to vertical nonvolatile storage devices comprising strings of storage cells. Background Technology

[0002] Non-volatile memory devices, as semiconductor memory devices, include multiple memory cells that retain data even when the power supply to them is cut off, and the stored data can be reused when power is supplied. Non-volatile memory devices can be used in cellular phones, digital cameras, portable digital assistants (PDAs), mobile computing devices, fixed computing devices, and other devices.

[0003] Recently, research has been conducted on using three-dimensional (or vertical) NAND (or VNAND) structures in chips to form next-generation neuromorphic computing platforms or neural networks. Specifically, this may involve techniques for achieving high density and low power consumption while allowing random access to memory cells. Summary of the Invention

[0004] Other aspects will be set forth in part in the description which follows, and will also be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0005] According to one embodiment, a non-volatile memory device includes: a plurality of memory cell strings, each of the plurality of memory cell strings including a semiconductor layer, a plurality of gates and a plurality of insulators, a gate insulating layer and a resistance-changing layer. The semiconductor layer includes a first semiconductor material and extends in a first direction. The semiconductor layer includes a first surface and a second surface opposite to the first surface. Each of the plurality of gates and the plurality of insulators extends in a second direction perpendicular to the first direction, and the plurality of gates and the plurality of insulators are alternately arranged in the first direction. The gate insulating layer extends in the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer. The resistance-changing layer extends in the first direction on the second surface of the semiconductor layer. The resistance-changing layer includes: a metal semiconductor oxide comprising a second semiconductor material and a transition metal oxide, the metal semiconductor oxide having charge trapping sites in the band gap of the oxide of the second semiconductor material.

[0006] In some embodiments, the metal semiconductor oxide in the resistance-changing layer may have inversion defects caused by site reversal between the second semiconductor material and the transition metal oxide.

[0007] In some embodiments, the band gap of the transition metal oxide can be smaller than that of the oxide of the second semiconductor material.

[0008] For example, in some embodiments, the band gap of the transition metal oxide can be less than about 4.5 eV.

[0009] For example, in some embodiments, the band gap of the transition metal oxide can be less than about 3.5 eV.

[0010] In some implementations, the first semiconductor material and the second semiconductor material can be the same.

[0011] In some embodiments, the first semiconductor material and the second semiconductor material may be different from each other, and the metal semiconductor oxide of the resistance-changing layer may include both the first semiconductor material and the second semiconductor material.

[0012] In some embodiments, the transition metal oxide may include at least one selected from Ta₂O₅, BaO, and TiO₂, and the metal semiconductor oxide may include Ta silicate, Ba silicate, Ti silicate, and TaGe. x O y BaGe x O y and TiGe x O y At least one of them.

[0013] In some embodiments, the first semiconductor material of the semiconductor layer may include at least one selected from Si, Ge, indium gallium zinc oxide (IGZO) and GaAs.

[0014] In some implementations, the ratio of the second semiconductor material to the resistance-changing layer can be from about 20 at.% to about 80 at.%.

[0015] Furthermore, in some embodiments, the ratio of the second semiconductor material to the resistance-changing layer can be from about 40 at.% to about 60 at.%.

[0016] In some implementations, the ratio of the second semiconductor material to the resistance-changing layer can be substantially constant over a deviation of about 10% throughout the entire region of the resistance-changing layer.

[0017] In some implementations, the thickness of the resistance-changing layer in the second direction can be from about 0.1 nm to about 2.0 nm.

[0018] Furthermore, in some embodiments, the thickness of the resistance-changing layer in the second direction can be from about 0.3 nm to about 1.5 nm.

[0019] Furthermore, in some embodiments, the thickness of the resistance-changing layer in the second direction can be from about 0.5 nm to about 1.0 nm.

[0020] In some implementations, the thickness of the resistance-changing layer can be substantially constant over the entire area of ​​the resistance-changing layer extending along the first direction, within a deviation of about 10%.

[0021] In some implementations, a memory cell may be defined by one of the plurality of gates, a portion of a gate insulating layer adjacent to the gate in a second direction, a portion of a semiconductor layer adjacent to the gate in a second direction, and a portion of a resistance-varying layer adjacent to the gate in a second direction. The plurality of memory cells may be arranged in a vertically stacked structure in each memory cell string.

[0022] In some embodiments, the non-volatile memory device may further include: control logic configured to, in a programming mode, apply a current-on voltage only to the semiconductor layer of unselected memory cells in the plurality of memory cell strings, and a resistance-varying layer to apply a current-on voltage only to the selected memory cells in the plurality of memory cell strings; and a bit line configured to apply a programming voltage to the selected memory cells.

[0023] In some implementations, the resistance-changing layer can be configured such that, in response to a positive programming voltage being applied to a selected memory cell via a bit line, the resistance of one or more regions of the resistance-changing layer corresponding to the selected memory cell decreases because electrons are trapped in charge traps in the one or more regions of the resistance-changing layer, and in response to a negative programming voltage being applied to the selected memory cell via a bit line, the resistance of the one or more regions of the resistance-changing layer corresponding to the selected memory cell increases because electrons are decapitated from charge traps in the one or more regions of the resistance-changing layer.

[0024] In some implementations, the positive programming voltage can be about 10V or less.

[0025] Furthermore, in some implementations, the positive programming voltage can be in the range of approximately 5V to approximately 8V.

[0026] In some implementations, in response to a decrease in the resistance of one or more regions of the resistance-changing layer, the direction of the current flowing through one or more regions of the resistance-changing layer may be the same as the first direction in which the resistance-changing layer extends.

[0027] In some implementations, the one or more regions of the resistance variation layer may have at least three different resistance states.

[0028] In some implementations, the resistance state of one or more regions of the resistance variation layer can be selected by adjusting the current applied to one or more regions of the resistance variation layer.

[0029] In some embodiments, the resistance-varying layer can be formed such that: in response to a positive programming voltage being applied to a selected memory cell via a bit line, oxygen vacancies can move toward the interface between the semiconductor layer and the resistance-varying layer in one or more regions of the resistance-varying layer corresponding to the selected memory cell; and in response to a negative programming voltage being applied to the selected memory cell via a bit line, oxygen vacancies move away from the interface between the semiconductor layer and the resistance-varying layer in the one or more regions of the resistance-varying layer corresponding to the selected memory cell.

[0030] In some embodiments, the resistance-changing layer can be formed such that: in response to oxygen vacancies moving toward the interface between the semiconductor layer and the resistance-changing layer in one or more regions of the resistance-changing layer, thereby increasing the density of oxygen vacancies at the interface between the semiconductor layer and the resistance-changing layer, the resistance of the one or more regions of the resistance-changing layer decreases; and in response to oxygen vacancies moving away from the interface between the semiconductor layer and the resistance-changing layer in one or more regions of the resistance-changing layer, thereby decreasing the density of oxygen vacancies at the interface between the semiconductor layer and the resistance-changing layer, the resistance of the one or more regions of the resistance-changing layer increases.

[0031] In some implementations, the resistance state of the resistance-changing layer can be configured to vary according to the phenomenon in which electrons are trapped in or decaptured from charge traps defined by oxygen vacancies.

[0032] According to one embodiment, a non-volatile memory device includes: a substrate; a plurality of bit lines above the substrate, the plurality of bit lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a plurality of gates and a plurality of insulators alternately stacked on the substrate in a third-direction upward perpendicular to the top surface of the substrate; and a plurality of pillars spaced apart from each other on the substrate. Each corresponding pillar of the plurality of pillars is electrically connected to a corresponding bit line of the plurality of bit lines. Each of the plurality of pillars extends in a third-direction upward through a corresponding via defined in the alternately stacked plurality of gates and the plurality of insulators. Each of the plurality of pillars includes a resistance-varying layer extending in a third-direction upward, a semiconductor layer surrounding the resistance-varying layer, and a gate insulating layer surrounding the semiconductor layer. The resistance-varying layer includes a metal semiconductor oxide having a resistance that varies according to a voltage applied thereto, and the resistance-varying layer includes charge trapping sites.

[0033] In some embodiments, in at least one of the plurality of pillars, the gate insulating layer may directly contact the first surface of the semiconductor layer, the resistance changing layer may directly contact the second surface of the semiconductor layer opposite to the first surface of the semiconductor layer, and the gate insulating layer may extend between the plurality of gates and the semiconductor layer.

[0034] In some implementations, the thickness of the resistance-changing layer can be from about 0.3 nm to about 1.5 nm.

[0035] In some embodiments, the metal semiconductor oxide of the resistance-changing layer may include a semiconductor material and a transition metal oxide. The transition metal oxide may include at least one selected from Ta₂O₅, BaO, and TiO₂. The semiconductor material may include at least one selected from Si, Ge, indium gallium zinc oxide (IGZO), and GaAs.

[0036] In some implementations, the ratio of semiconductor material to transition metal oxide in the resistance-changing layer can be from about 20 at.% to about 80 at.%. Attached Figure Description

[0037] The above and other aspects, features, and effects of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 This is a block diagram of a memory system according to one embodiment;

[0039] Figure 2 According to one embodiment Figure 1 A block diagram of the storage device shown in the figure;

[0040] Figure 3 According to one embodiment Figure 1 The block diagram of the memory cell array shown in the figure;

[0041] Figure 4 It is a circuit diagram of the equivalent circuit corresponding to the memory block according to one embodiment;

[0042] Figure 5 This is a schematic perspective view of the physical structure corresponding to a storage block according to one embodiment;

[0043] Figure 6A According to one embodiment, in the XZ plane Figure 5 A cross-sectional view of the storage block;

[0044] Figure 6B According to one embodiment, in the YZ plane Figure 5 A cross-sectional view of the storage block;

[0045] Figure 7A and Figure 7C This is a programming mode for non-volatile memory devices according to one embodiment. Figure 4 The circuit diagram of the equivalent circuit of the memory block;

[0046] Figure 7B and Figure 7D This is according to one embodiment of the erase mode of a non-volatile storage device. Figure 4 The circuit diagram of the equivalent circuit of the memory block;

[0047] Figure 8 This is a schematic diagram illustrating the movement of current in a resistance variation layer in a programming mode according to one embodiment.

[0048] Figure 9 This is a circuit diagram of a circuit in the read mode of a memory block according to one embodiment;

[0049] Figure 10 It is a diagram used to describe the movement of current in a selected memory cell in a read mode according to one embodiment;

[0050] Figure 11 This is a schematic cross-sectional view of a structure for testing the operation of a memory cell according to one embodiment;

[0051] Figure 12 It is used for based on Figure 11 The graph shows the X-ray photoelectron spectroscopy (XPS) data of the mixture between the semiconductor material of the semiconductor layer and the transition metal oxide of the resistance-changing layer in the structure of the memory cell.

[0052] Figure 13 It is a graph showing the current-voltage behavior of a plurality of memory cell structures including metal semiconductor oxides obtained in experiments according to one embodiment.

[0053] Figure 14 It is a graph showing the current-voltage behavior of memory cells including metal-semiconductor-oxide-semiconductor (MSO) memory, which is obtained through... Figure 13 Curve graph recognition;

[0054] Figure 15 and Figure 16 It is a graph showing the current-voltage behavior of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment.

[0055] Figure 17 This is a comparison table between the characteristics of a memory cell comprising a metal semiconductor oxide according to one embodiment and the characteristics of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment.

[0056] Figure 18 This is a comparison diagram between the resistance distribution of a memory cell comprising a metal semiconductor oxide according to one embodiment and the resistance distribution of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment.

[0057] Figure 19A and Figure 19B These are graphs showing the cumulative probability of the resistance distribution of a memory cell comprising a metal semiconductor oxide according to one embodiment and the resistance distribution of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment.

[0058] Figures 20A to 20C It is a density of states (DOS) plot comparing the characteristics of a metal semiconductor oxide according to one embodiment and the characteristics of a metal semiconductor oxide according to a comparative embodiment.

[0059] Figure 21 This is a diagram showing the bandgap distribution of a candidate transition metal oxide for generating a resistance-changing layer of a metal semiconductor oxide according to one embodiment.

[0060] Figure 22 Is Figure 11 The diagram shows the current-voltage behavior of the memory cell structure as the thickness of the transition metal oxide increases;

[0061] Figure 23 This illustrates the gradual thickness variation of the transition metal oxide. Figure 11 The table shows the characteristic changes of the storage cells;

[0062] Figure 24 This is a schematic diagram of the structure of the storage device according to a comparative embodiment;

[0063] Figure 25 It is based on the comparative implementation method. Figure 24 A schematic cross-sectional view of the structure of a storage cell of a storage device is shown in the figure;

[0064] Figure 26A and Figure 26B This is a conceptual diagram illustrating an example of the principle of resistance change operation in a resistance change layer of a memory cell according to one embodiment; and

[0065] Figure 27 This is a schematic block diagram of a neuromorphic device including a storage device according to one embodiment. Detailed Implementation

[0066] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the accompanying drawings to illustrate aspects. As used herein, the term “and / or” includes any and all combinations of one or more related enumerated items. Expressions such as “at least one of…”, when present after an element in a column, modify the entire column of elements, not individual elements within that column. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, and a combination thereof” can be interpreted to cover any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0067] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values. Furthermore, when the words “approximately” and “substantially” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather that the range of shapes (latitude) is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it will be understood that these values ​​and shapes should be construed as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​or shapes.

[0068] The following description, with reference to the accompanying drawings, details a vertical non-volatile storage device comprising a string of memory cells. In the drawings, the same reference numerals denote the same elements, and the dimensions of the elements may be exaggerated for clarity and ease of explanation. The embodiments described below are merely examples, and various modifications can be made based on these embodiments.

[0069] In the following text, it will be understood that when an element is referred to as being "on" or "above" another element, the element may be directly on or above the other element, directly to the left or right of the other element, or there may also be intervening elements therebetween. As used herein, the singular terms "a" and "an" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when a component "comprises" or "contains" an element, unless otherwise specified, the component may further include other elements, without excluding other elements.

[0070] The term "described" and other equivalent qualifiers may correspond to either singular or plural indicators. Unless the order of operations included in a method is explicitly described or there is a contrary description, the operations may be performed in the appropriate order.

[0071] Furthermore, terms used in this specification, such as “…unit”, “module”, etc., indicate a unit that processes at least one function or movement, and that unit may be implemented by hardware or software or by a combination of hardware and software.

[0072] The connecting lines or connectors shown in the various diagrams are intended to represent functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0073] All examples and example terms are used only to describe the present disclosure in detail, and the disclosure is not limited to the examples and example terms unless they are defined within the scope of the claims.

[0074] Figure 1 This is a block diagram of a memory system 10 according to one embodiment.

[0075] Reference Figure 1 According to one embodiment, the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 can perform control operations regarding the memory device 200. For example, the memory controller 100 can provide the memory device 200 with an address (ADD) and a command (CMD) to perform programming (or writing), reading, and erasing operations on the memory device 200. Furthermore, data for programming operations and data read out can be sent and received between the memory controller 100 and the memory device 200. The memory device 200 can provide a pass / fail signal (P / F) to the memory controller 100 based on the reading results of the read data. The memory controller 100 can refer to the pass / fail signal (P / F) and thus control the write and read operations of the memory cell array 210.

[0076] Storage device 200 may include a memory cell array 210 and a voltage generator 220. The memory cell array 210 may include a plurality of memory cells arranged in a region where multiple word lines and multiple bit lines intersect. The memory cell array 210 may include non-volatile memory cells for storing data in a non-volatile manner, and may include flash memory cells as non-volatile memory cells, such as a NAND flash memory array or a NOR flash memory array. Embodiments of this disclosure will be described below, wherein the memory cell array 210 includes a flash memory array 210, and thus, storage device 200 is a non-volatile storage device.

[0077] The memory controller 100 may include a write / read controller 110, a voltage controller 120, and a data determiner 130.

[0078] The write / read controller 110 can generate address ADD and command CMD for performing programming / reading and erasing operations on the memory cell array 210. Furthermore, the voltage controller 120 can generate voltage control signals for controlling at least one voltage level used in the non-volatile memory device 200. For example, the voltage controller 120 can generate voltage control signals for controlling the voltage level of word lines used to read data from or program data on the memory cell array 210.

[0079] The data determiner 130 can determine the data read from the storage device 200. For example, to determine the data read from a storage cell, the data determiner 130 can determine the number of enabled and / or disabled cells among the storage cells. As an example of operation, when a programming operation is performed on the plurality of storage cells, the state of the data in the storage cells can be determined by using a desired and / or alternatively predetermined read voltage, thereby determining whether the programming operation was successfully completed on all cells.

[0080] Storage device 200 may include a memory cell array 210 and a voltage generator 220. As described above, the memory cell array 210 may include non-volatile memory cells. For example, the memory cell array 210 may include flash memory cells. Furthermore, flash memory cells may be implemented in various forms. For example, the memory cell array 210 may include three-dimensional (or vertical) NAND (or VNAND) memory cells.

[0081] Figure 2 According to one embodiment Figure 1 A block diagram of the storage device 200 is shown. (Refer to...) Figure 2 The storage device 200 may further include a line decoder 230, an input / output circuit 240, and control logic 250.

[0082] The memory cell array 210 can be connected to one or more string select lines SSL, multiple word lines WL1…WLm-1, WLm, one or more common source lines CSL, and multiple bit lines BL1, BL2…BLn. A voltage generator 220 can generate one or more word line voltages V1, V2…Vi, and these word line voltages V1 to Vi can be provided to the row decoder 230. Signals used for programming / reading / erasing operations can be applied to the memory cell array 210 via bit lines BL1 to BLn.

[0083] Furthermore, the data to be programmed can be provided to the memory cell array 210 via the input / output circuit 240, and the data read can be provided to an external device (e.g., a memory controller) via the input / output circuit 240. Figure 1(Memory controller 100 in the memory). Control logic 250 can provide various control signals related to memory operations to the line decoder 230 and voltage generator 220.

[0084] According to the decoding operation of the line decoder 230, word line voltages V1 to Vi can be provided to various lines SSL, WL1 to WLm, and CSL. For example, word line voltages V1 to Vi can include string select voltage, word line voltage, and ground select voltage. The string select voltage can be provided to one or more string select lines SSL, the word line voltage can be provided to one or more word lines WL1 to WLm, and the ground select voltage can be provided to one or more common source lines CSL.

[0085] Figure 3 yes Figure 1 A block diagram of the memory cell array 210 is shown. (Refer to...) Figure 3 The storage cell array 210 may include multiple storage blocks BLK1, BLK2...BLKz. Each of the storage blocks BLK1 to BLKz may have a three-dimensional structure (or a vertical structure). For example, each of the storage blocks BLK1 to BLKz may include a structure extending upwards in a first to third direction. For example, each of the storage blocks BLK1 to BLKz may include multiple strings of storage cells extending in a second direction. Furthermore, the multiple strings of storage cells may be arranged two-dimensionally upwards in the first and third directions. Each string of storage cells may be connected to a bit line BL, a string select line SSL, a word line WL, and a common source line CSL. Therefore, each of the storage blocks BLK1 to BLKz may be connected to the multiple bit lines BL, the multiple string select lines SSL, the multiple word lines WL, and the multiple common source lines CSL. (Refer to...) Figure 4 The storage blocks BLK1 to BLKz are described in further detail.

[0086] Figure 4 This is a circuit diagram of the equivalent circuit corresponding to a memory block according to one embodiment. For example, in Figure 4 It shows Figure 3 One of the storage blocks BLK1 to BLKz in the storage cell array 210. (Refer to...) Figure 3 and Figure 4 Each of the memory blocks BLK1 to BLKz may include multiple memory cell strings CS11 to CSkn. The multiple memory cell strings CS11 to CSkn may be arranged two-dimensionally in both row and column directions to form rows and columns. Each memory cell string CS11 to CSkn may include multiple memory cells MC and multiple string select transistors SST. The memory cells MC and string select transistors SST in each memory cell string CS11 to CSkn may be stacked in the height direction.

[0087] The rows of the plurality of memory cell strings CS11 to CSkn can be connected to multiple string select lines SSL1 to SSLk respectively. For example, the string select transistors SST of memory cell strings CS11 to CS1n can be connected together to string select line SSL1. The string select transistors SST of memory cell strings CSk1 to CSkn can be connected together to string select line SSLk.

[0088] Furthermore, the columns of the plurality of memory cell strings CS11 to CSkn can be connected to the plurality of bit lines BL1 to BLn respectively. For example, the memory cell MC and the string selection transistor SST of memory cell strings CS11 to CSk1 can be connected together to bit line BL1, and the memory cell MC and the string selection transistor SST of memory cell strings CS1n to CSkn can be connected together to bit line BLn.

[0089] Furthermore, the rows of the plurality of memory cell strings CS11 to CSkn can be respectively connected to the plurality of common source lines CSL1 to CSLk. For example, the string selection transistors SST of the plurality of memory cell strings CS11 to CS1n can be connected together to the common source line CSL1, and the string selection transistors SST of the plurality of memory cell strings CSk1 to CSkn can be connected together to the common source line CSLk.

[0090] Memory cells MC located at the same height from the substrate (or string select transistor SST) can be connected to a single word line WL, and memory cells MC located at different heights from the substrate (or string select transistor SST) can be connected to the multiple word lines WL1 to WLm respectively.

[0091] Figure 4 The storage block shown is an example. This disclosure is not limited to... Figure 4 The memory block is shown in the diagram. For example, the number of rows of the plurality of memory cell strings CS11 to CSkn can be increased or decreased. When the number of rows of the plurality of memory cell strings CS11 to CSkn changes, the number of string select lines connected to the rows of memory cell strings CS11 to CSkn and the number of memory cell strings CS11 to CSkn connected to a bit line can also change. When the number of rows of memory cell strings CS11 to CSkn changes, the number of common source lines connected to the rows of memory cell strings CS11 to CSkn can also change. Furthermore, the number of columns of the plurality of memory cell strings CS11 to CSkn can be increased or decreased. When the number of columns of memory cell strings CS11 to CSkn changes, the number of bit lines connected to the columns of memory cell strings CS11 to CSkn and the number of memory cell strings CS11 to CSkn connected to a string select line can also change.

[0092] The height of each memory cell string CS11 to CSkn can be increased or decreased. For example, the number of memory cells MC stacked in each memory cell string CS11 to CSkn can be increased or decreased. When the number of memory cells MC stacked in each memory cell string CS11 to CSkn changes, the number of word lines WL can also change. For example, the number of string select transistors SST provided to each memory cell string CS11 to CSkn can be increased. When the number of string select transistors SST provided to each memory cell string CS11 to CSkn changes, the number of string select lines or the number of common source lines can also change. When the number of string select transistors SST increases, the string select transistors SST can be stacked in the same shape as the memory cell MC stack.

[0093] For example, write and read operations can be performed on each row of memory cell strings CS11 to CSkn. Memory cell strings CS11 to CSkn can be selected for each row by a common source line CSL, and memory cell strings CS11 to CSkn can be selected for each row by a string selection line SSL. Furthermore, within the selected rows of memory cell strings CS11 to CSkn, write and read operations can be performed on each page. For example, a page can be a row of memory cells MC connected to a word line WL. Within the selected rows of memory cell strings CS11 to CSkn, memory cells MC can be selected for each page by a word line WL.

[0094] Each memory cell MC in each memory cell string CS11 to CSkn can correspond to a circuit in which transistors and resistors are connected in parallel. For example, Figure 5 This is a schematic perspective view of the physical structure corresponding to a storage block according to one embodiment. Figure 6A In the XZ plane Figure 5 A cross-sectional view of the storage block. Figure 6B In the YZ plane Figure 5 A cross-sectional view of the storage block.

[0095] Reference Figure 5 , Figure 6A and Figure 6B The memory block may include a substrate 501. Substrate 501 may include silicon material doped with a first type of impurity. For example, substrate 501 may include silicon material doped with p-type impurities. Substrate 501 may be, for example, a p-type well (e.g., a pocket p-well). Hereinafter, it is assumed that substrate 501 includes p-type silicon. However, substrate 501 is not limited to p-type silicon.

[0096] The doped region 510 may be formed in the upper region of the substrate 501. For example, the doped region 510 may have a second type, which is electrically opposite to the first type of the substrate 501. For example, the doped region 510 may be n-type. Hereinafter, it is assumed that the doped region 510 is n-type. However, the doped region 510 is not limited to n-type. The doped region 510 may become a common source line.

[0097] A plurality of gates 531 extending in the horizontal direction and a plurality of insulators 532 extending in the horizontal direction may be alternately arranged on the substrate 501. In other words, the plurality of gates 531 and the plurality of insulators 532 may be alternately stacked in a vertical direction orthogonal to the horizontal direction. For example, the gates 531 may comprise at least one of a metallic material (e.g., copper, silver, etc.) and silicon with a high concentration of doping, and the plurality of insulators 532 may comprise silicon oxide. However, the plurality of gates 531 and the plurality of insulators 532 are not limited thereto. Each gate 531 may be connected to one of a word line WL and a string select line SSL.

[0098] Furthermore, the memory block may include a plurality of pillars 520 that vertically penetrate the plurality of gates 531 and the plurality of insulators 532 arranged alternately in a vertical direction. Each pillar 520 may include multiple layers in a horizontal direction. According to one embodiment, the outermost layer of the pillar 520 may include a gate insulating layer 521. For example, the gate insulating layer 521 may include silicon oxide. The gate insulating layer 521 may be conformally deposited on the plurality of gates 531 and the plurality of insulators 532 and may extend in a vertical direction.

[0099] Furthermore, the semiconductor layer 522 may be conformally deposited along the surface of the gate insulating layer 521 and may extend in the vertical direction. According to one embodiment, the semiconductor layer 522 may include a silicon material doped with a first type of impurity. The semiconductor layer 522 may include a silicon material doped with impurities of the same type as those on the substrate 501. For example, when the substrate 501 includes a silicon material doped with p-type impurities, the semiconductor layer 522 may also include a silicon material doped with p-type impurities. Alternatively, the semiconductor layer 522 may include materials such as Ge, indium gallium zinc oxide (IGZO), or GaAs.

[0100] The resistance variation layer 523 can be conformally deposited along the surface of the semiconductor layer 522 and can extend in the vertical direction. The resistance variation layer 523 can be formed by thinly depositing a metal semiconductor oxide along the surface of the semiconductor layer 522, the metal semiconductor oxide comprising a mixture of semiconductor materials and transition metal oxide materials. According to one embodiment, the resistance variation layer 523 may comprise a material having a resistance that varies according to a voltage applied thereto. Depending on the voltage applied thereto, the resistance variation layer 523 can change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state.

[0101] The metal-semiconductor oxide in the resistance-changing layer 523 may have antisite defects due to site inversion between the semiconductor material and the transition metal. Charge traps formed due to these antisite defects can provide a resistance change in the resistance-changing layer 523. For example, the resistance of the resistance-changing layer 523 can decrease when electrons are trapped in charge traps formed due to antisite defects, and increase when electrons are de-trapped from these charge traps. Furthermore, multiple mobile oxygen vacancies distributed in the metal-semiconductor oxide of the resistance-changing layer 523 can also provide a resistance change. For example, the resistance state of the resistance-changing layer 523 can be easily changed based on the phenomenon where electrons are trapped in or de-trapped from charge traps formed by oxygen vacancies.

[0102] The transition metal oxide constituting the resistance changing layer 523 may include, for example, Ta₂O₅, BaO, TiO₂, etc. Additionally, the semiconductor material constituting the resistance changing layer 523 may include, for example, Si, Ge, IGZO, GaAs, etc. When silicon (Si) is used as the semiconductor material, the metal semiconductor oxide of the resistance changing layer 523 may include, for example, Ta silicate, Ba silicate, Ti silicate, etc. As another example, when germanium (Ge) is used as the semiconductor material, the metal semiconductor oxide of the resistance changing layer 523 may include TaGe. x O y BaGe x O y TiGe x O y And so on. Here, x and y can vary depending on the ratio between the semiconductor material and the transition metal oxide.

[0103] To form a sufficient amount of charge traps in the resistance-changing layer 523, the ratio of semiconductor material to resistance-changing layer 523 can be appropriately selected. For example, although the ratio of semiconductor material can vary depending on the amount of transition metal oxide and semiconductor material used, the ratio of semiconductor material to resistance-changing layer 523 can be from about 20 at.% to about 80 at.%. Alternatively, the ratio of semiconductor material to resistance-changing layer 523 can be, for example, from about 40 at.% to about 60 at.%. In other words, the concentration of semiconductor material in resistance-changing layer 523 can be from about 20 at.% to about 80 at.% and / or from about 40 at.% to about 60 at.%.

[0104] The resistance-changing layer 523 can be formed to have a small thickness in the x-direction, such that the resistance-changing layer 523 has uniform characteristics throughout its entire region. For example, the thickness of the resistance-changing layer 523 in the x-direction can be in the range of about 0.1 nm to about 2.0 nm. Alternatively, the thickness of the resistance-changing layer 523 can be in the range of about 0.3 nm to about 1.5 nm. Alternatively, the thickness of the resistance-changing layer 523 can be in the range of about 0.5 nm to about 1.0 nm. The thickness and composition of the resistance-changing layer 523 can be relatively uniform throughout its entire region. For example, the thickness of the resistance-changing layer 523 can be approximately constant within a deviation range of about 10% throughout its entire region. Furthermore, the metal semiconductor oxide in the resistance-changing layer 523 can have a relatively uniform composition throughout its entire region. For example, the ratio of semiconductor material to the resistance-changing layer 523 can be approximately constant within a deviation range of about 10% throughout its entire region.

[0105] The resistance-changing layer 523 can be formed by preparing a separate metal-semiconductor oxide comprising a semiconductor material and a transition metal oxide, and then depositing the separate metal-semiconductor oxide directly along the surface of the semiconductor layer 522. Alternatively, during the process of depositing the transition metal oxide along the surface of the semiconductor layer 522, the semiconductor material and the transition metal oxide can be mixed on the surface of the semiconductor layer 522, and then the resistance-changing layer 523 can be formed.

[0106] When a single metal semiconductor oxide is directly deposited, the semiconductor material of semiconductor layer 522 and the semiconductor material of resistance-changing layer 523 can be the same as or different from each other. In other words, semiconductor layer 522 can include a first semiconductor material, and the metal semiconductor oxide of resistance-changing layer 523 can include a second semiconductor material that is the same as or different from the first semiconductor material. For example, when semiconductor layer 522 includes Si, Ta silicate, Ba silicate, Ti silicate, etc., can be deposited directly along the surface of semiconductor layer 522, or TaGe can be deposited directly along the surface of semiconductor layer 522. x O y BaGe x O y TiGe x O y The resistance-changing layer 523 is formed by depositing materials such as Si to form the first semiconductor material of the semiconductor layer 522. In the latter case, the second semiconductor material of the metal semiconductor oxide of the resistance-changing layer 523 may include Ge. As another example, when the semiconductor layer 522 includes Ge, TaGe can be deposited directly along the surface of the semiconductor layer 522. x O y BaGe x O y TiGe x O y Alternatively, a resistance variation layer 523 may be formed by directly depositing Ta silicate, Ba silicate, Ti silicate, etc., along the surface of the semiconductor layer 522.

[0107] When the first semiconductor material of semiconductor layer 522 and the second semiconductor material of the metal semiconductor oxide of resistance changing layer 523 are different from each other, a portion of the first semiconductor material can diffuse into resistance changing layer 523, such that the metal semiconductor oxide can include both the first semiconductor material and the second semiconductor material. For example, when the first semiconductor material includes Si and the second semiconductor material includes Ge, and when the first semiconductor material includes Ge and the second semiconductor material includes Si, the metal semiconductor oxide of resistance changing layer 523 can include both Si and Ge.

[0108] When the resistance-changing layer 523 is formed by thinly depositing a transition metal oxide along the surface of the semiconductor layer 522, the second semiconductor material included in the metal semiconductor oxide of the resistance-changing layer 523 can be the same as the first semiconductor material of the semiconductor layer 522. For example, when the semiconductor layer 522 includes Si, and when Ta2O5, BaO, or TiO2 is thinly deposited along the surface of the semiconductor layer 522, a resistance-changing layer 523 including Ta silicate, Ba silicate, or Ti silicate can be formed. Furthermore, when the semiconductor layer 522 includes Ge, and when Ta2O5, BaO, or TiO2 is thinly deposited along the surface of the semiconductor layer 522, a resistance-changing layer 523 including TaGe can be formed. x O y BaGe x O y or TiGe x O y The resistance variation layer 523.

[0109] When the resistance changing layer 523 is formed to have a small thickness as described above, most of the transition metal oxide can be mixed with the semiconductor material in the semiconductor layer 522; therefore, a large portion of the resistance changing layer 523 can include the metal semiconductor oxide. As described above, by forming the resistance changing layer 523 thinly, the thickness and composition of the resistance changing layer 523 can be relatively uniform throughout the entire region of the resistance changing layer 523. However, a portion of the transition metal oxide can remain at the edge of the resistance changing layer 523 away from the interface between the resistance changing layer 523 and the semiconductor layer 522. Similarly, in this case, the thickness of the resistance changing layer 523 can be defined by including both the metal semiconductor oxide and the remaining transition metal oxide.

[0110] An insulating support 524 may be disposed on the inner side of the resistance-changing layer 523. For example, the insulating support 524 may comprise silicon oxide. A memory cell string CS may comprise an insulating support 524 and a resistance-changing layer 523, a semiconductor layer 522, a gate insulating layer 521, the plurality of gates 531, and the plurality of insulators 532 (or particularly configured thereof). Thus, the insulating support 524 may be disposed at the central portion of the memory cell string CS. The semiconductor layer 522 and the resistance-changing layer 523 disposed on the inner surface of the semiconductor layer 522 may contact and be electrically connected to the doped region 510 (i.e., the common source region). The gates 531 and the insulators 532 disposed on the outer surface of the semiconductor layer 522 may not contact the doped region 510.

[0111] Drain 540 may be disposed on pillar 520. Drain 540 may comprise silicon material doped with a second type of impurity. For example, drain 540 may comprise silicon material doped with an n-type impurity. Bit line 550 may be disposed on drain 540. Drain 540 and bit line 550 may be connected to each other via contact plugs. Bit line 550 may comprise a metallic material. For example, bit line 550 may comprise polysilicon. Conductive material may be bit line 550.

[0112] and Figure 4 In contrast, the plurality of gates 531, the plurality of insulators 532, the gate insulating layer 521, the semiconductor layer 522, and the resistance changing layer 523 can be configuration elements of a memory cell string CS. Specifically, the gates 531, gate insulating layer 521, and semiconductor layer 522 can be configuration elements of transistors, and the resistance changing layer 523 can be a resistor. Furthermore, one of the plurality of gates 531, and a portion of the gate insulating layer 521, a portion of the semiconductor layer 522, and a portion of the resistance changing layer 523 adjacent to that one of the plurality of gates 531 in the horizontal direction, can be configuration elements of a memory cell MC. Memory cells MC with this structure can be vertically stacked to form each memory cell string CS.

[0113] As described above, the resistance-changing layer 523 can have a high-resistance state or a low-resistance state, thus allowing "0" and "1" to be written on the memory cell MC. In each memory cell MC, the semiconductor layer 522 of the transistor can be connected in parallel with the resistance-changing layer 523, and the parallel structures can be arranged continuously in the vertical direction to form a memory cell string CS. Furthermore, the common source line 510 and the bit line 550 can be connected to the two ends of the memory cell string CS, respectively. Moreover, programming, reading, and erasing operations can be performed on the plurality of memory cells MC by applying voltages to the common source line 510 and the bit line 550.

[0114] According to this embodiment, instead of forming the memory block using a phase change material, the memory block can be formed using a resistance change layer 523, thereby improving the heat generation and stress (pressure) that may occur when using a phase change material. Furthermore, by forming and operating the memory block as described in detail above, even when repeatedly operating the memory cells included in the memory block, ion movement between adjacent memory cells and current leakage and operational failures caused by ion movement can be limited and / or prevented. Moreover, the memory block according to this embodiment can solve the miniaturization problem between memory cells in next-generation VNAND structures, thereby significantly increasing density. Therefore, memory capacity can be greatly increased. In detail, as described below, the metal semiconductor oxide included in the resistance change layer 523 according to this embodiment can have good uniformity and a good on / off current ratio; therefore, the resistance state can be changed relatively more easily and accurately, and multilayer cells (MLC) can be realized.

[0115] The memory block according to this embodiment can be implemented in the form of a chip and can be used as a neuromorphic computing platform. Furthermore, the memory block according to this disclosure can be implemented in the form of a chip and can be used to form neural networks.

[0116] Figure 7A and Figure 7C This is a programming mode for non-volatile memory devices according to one embodiment. Figure 4 The circuit diagram of the equivalent circuit of the storage block. Figure 7B and Figure 7D This is according to one embodiment of the erase mode of a non-volatile storage device. Figure 4 The circuit diagram of the equivalent circuit of the storage block.

[0117] Figures 7A to 7D Each of the plurality of storage cells 710 and 720 shown may include Figure 5 The diagram shows a gate 531, a gate insulating layer 521, a semiconductor layer 522, and a resistance variation layer 523.

[0118] The plurality of storage cells 710 and 720 of the storage block can be divided into selected storage cells 710 and unselected storage cells 720. (Refer to...) Figure 7A and Figure 7C The programming mode of a non-volatile storage device can represent a mode in which programming operations are performed on the memory cells included in the memory block. Furthermore, the selected memory cell 710 can represent the memory cell on which programming operations will be performed. Figure 7A An example of a selected memory cell 710 in the memory cell string CS being programmed is shown, but the example implementation is not limited to this. Figure 7CAs depicted, in one embodiment, two selected memory cells 710 can be programmed simultaneously in the same memory cell string CS.

[0119] Reference Figure 2 , Figure 4 , Figure 7A and Figure 7C Control logic 250 can control the application of a turn-on voltage Von to the string select line SSL, which is connected to the string of memory cells CS including the selected memory cell 710. Control logic 250 can also apply a turn-on voltage Von to the word lines WL connected to the unselected memory cells 720, and a cut-off voltage Voff to each word line WL connected to each selected memory cell 710. Here, the turn-on voltage Von is a voltage that turns on the transistor, and can also be referred to as the voltage that allows current to flow only through the semiconductor layer of the transistor. The cut-off voltage Voff is a voltage that turns off the transistor, and can also be referred to as the voltage that limits and / or prevents current from flowing through the semiconductor layer of the transistor. The values ​​of the turn-on voltage Von and the cut-off voltage Voff can depend on the material type, thickness, etc., of the gate 531, gate insulating layer 521, semiconductor layer 522, and resistivity variation layer 523 constituting the plurality of memory cells MC. Typically, the absolute value of the turn-on voltage Von can be greater than the absolute value of the cut-off voltage Voff.

[0120] Furthermore, a programming voltage Vprogram can be applied to the bit lines BL connected to the string of memory cells including the selected memory cell 710. The programming voltage Vprogram can be provided from an external source (e.g., memory controller 100) via input / output circuitry 240. The programming voltage Vprogram can be a voltage used to write data onto the memory cell MC, and the value of the programming voltage Vprogram can be changed according to the data.

[0121] Of the multiple bit lines BL, those not connected to the selected memory cell 710 can be grounded or floated. When the bit lines BL not connected to the selected memory cell 710 are grounded or floated, power loss due to current leakage can be limited and / or prevented. Then, the control logic 250 can perform programming operations on the selected memory cell 710.

[0122] In programming mode, when an on-state voltage Von is applied to an unselected memory cell 720, the semiconductor layer 522 of the unselected memory cell 720 can have conductive properties, and when an off-state voltage Voff is applied to a selected memory cell 710, the semiconductor layer 522 of the selected memory cell 710 can have insulating properties. Therefore, a voltage difference caused by the programming voltage Vprogram may appear in the selected memory cell 710. Due to the voltage difference in the selected memory cell 710, electrons can be trapped in charge traps in the resistance-changing layer 523 of the selected memory cell 710, causing the resistance-changing layer 523 to change to a low-resistance state. Furthermore, oxygen vacancies in the resistance-changing layer 523 can move in the direction of the semiconductor layer 522, causing the resistance-changing layer 523 to change to a low-resistance state. The fact that the resistance-changing layer 523 of the selected memory cell 710 can change to a low-resistance state indicates that the value of the resistance included in the selected memory cell 710 can be reduced. The selected memory cell 710 can have ohmic conductivity in the low resistance state of the resistance-varying layer 523.

[0123] Figure 8 This is a schematic diagram illustrating the current movement in the resistance variation layer 523 in a programming mode according to one embodiment. (See also...) Figure 8 The memory block may include a gate 531, an insulator 532, a gate insulating layer 521, a semiconductor layer 522, a resistance-changing layer 523, and an insulating support 524. The gate insulating layer 521, semiconductor layer 522, resistance-changing layer 523, and insulating support 524 may extend in the vertical direction. The gate 531 and insulator 532 may extend in the horizontal direction and may be alternately stacked in the vertical direction. The gate 531, gate insulating layer 521, and semiconductor layer 522 may be included in a transistor, and the resistance-changing layer 523 may correspond to a resistor.

[0124] In programming mode, control logic 250 can perform control operations to apply an on-state voltage Von to the gate 531b of the unselected memory cell 720 and an off-state voltage Voff to the gate 531a of the selected memory cell 710. The semiconductor layer 522b corresponding to the gate 531b of the unselected memory cell 720 can then have conductive properties, and the semiconductor layer 522a corresponding to the gate 531a of the selected memory cell 710 can have insulating properties. When a positive (+) programming voltage Vprogram is applied to the bit line electrically connected to the selected memory cell 710, a voltage difference may occur between the upper and lower portions of the resistance variation layer 523a corresponding to the selected memory cell 710.

[0125] This voltage difference may cause electrons to be trapped in charge traps formed by antisite defects in the metal-semiconductor oxide of the resistance-changing layer 523a corresponding to the selected memory cell 710. Additionally, oxygen vacancies in the resistance-changing layer 523a can move in the direction of the semiconductor layer 522a. Based on these phenomena, such as Figure 8 As shown, conductive filaments can be formed at the interface between the resistance-changing layer 523a and the semiconductor layer 522a. Therefore, due to the change in current conduction, the resistance-changing layer 523a corresponding to the selected memory cell 710 can be changed to a low-resistance state. Here, the selected memory cell 710 can have ohmic conductivity. In other words, the selected memory cell 710 can have bulk conductivity characteristics, such as hopping, space charge-limited current (SCLC), or Purf-Frank. As a result, since the resistance-changing layer 523a of the selected memory cell 710 can have a resistance state that varies according to the programming voltage Vprogram, programming operations can be performed on the selected memory cell 710.

[0126] Conversely, no voltage difference may occur between the upper and lower parts of the resistance variation layer 523b of the unselected memory cell 720. Therefore, electrons may not be trapped in charge traps in the resistance variation layer 523b corresponding to the unselected memory cell 720, and oxygen vacancies may not move.

[0127] Reference Figure 7B and Figure 7D In erase mode, a negative (-) erase voltage Verase can be applied to the bit line electrically connected to the selected memory cell 710. Electrons can then be captured from the charge traps in the metal semiconductor oxide of the resistance-changing layer 523a corresponding to the selected memory cell 710, and oxygen vacancies can be dispersed, thereby changing the resistance-changing layer 523a corresponding to the selected memory cell 710 to a high-resistance state. Figure 7B A non-limiting example is shown, in which one of the storage cells is the selected storage cell 710 that is erased in the storage cell string CS. Figure 7D A non-limiting example is shown, in which two memory cells are selected memory cells 710, which are erased by applying Verase to the selected bit line BL while applying Voff to the word line WL connected to the selected memory cell. However, the example implementation is not limited thereto.

[0128] Figure 9 This is a circuit diagram of a circuit in the read mode of a memory block according to one embodiment. Figure 9 Each of the plurality of storage cells 810 and 820 shown may include Figure 5The diagram shows a gate 531, a gate insulating layer 521, a semiconductor layer 522, and a resistance variation layer 523. The plurality of memory cells 810 and 820 of the memory block can be divided into selected memory cells 810 and unselected memory cells 820. A read mode of a non-volatile memory device can represent a mode in which a read operation is performed on a memory cell included in the memory block, and a selected memory cell 810 can represent the memory cell to which a read operation will be performed.

[0129] In read mode, control logic 250 can apply a turn-on voltage Von to one of the multiple string select lines SSL connected to the string select line SSL of the selected memory cell 810, and apply a turn-on voltage Von to one of the multiple word lines WL connected to the word line WL of the unselected memory cell 820. Here, the turn-on voltage Von can be a voltage with a value that turns on the transistor, and can also be referred to as a voltage that causes current to flow only through the semiconductor layer 522 of the transistor. The cut-off voltage Voff can be a voltage with a value that turns off the transistor, and can also be referred to as a voltage that limits and / or prevents current from flowing through the semiconductor layer 522 of the transistor. The values ​​of the turn-on voltage Von and the cut-off voltage Voff can depend on the material type, thickness, etc., of the gate 531, gate insulating layer 521, semiconductor layer 522, and resistivity variation layer 523 constituting the plurality of memory cells MC. Typically, the absolute value of the turn-on voltage Von can be greater than the absolute value of the cut-off voltage Voff.

[0130] Furthermore, control logic 250 can apply a current-on voltage Vion to the word line WL connected to the selected memory cell 810. The current-on voltage Vion can represent a voltage having a value sufficient to allow current to flow in both the semiconductor layer 522 and the resistance-changing layer 523 of the transistors included in the selected memory cell 810. The absolute value of the current-on voltage Vion can be greater than the absolute value of the cutoff voltage Voff and less than the absolute value of the on-state voltage Von. The value of the current-on voltage Vion can depend on the material type, thickness, etc., of the gate 531, gate insulating layer 521, semiconductor layer 522, and resistance-changing layer 523 constituting the plurality of memory cells. Specifically, the current-on voltage Vion can have a value that allows the resistance distribution of the selected memory cell 810 to have a linear proportion.

[0131] Furthermore, a read voltage Vread can be applied to one of the multiple bit lines BL connected to the selected memory cell 810. The read voltage Vread can be provided externally (e.g., from the memory controller 100) via input and output circuitry 240. The read voltage Vread can be a voltage used to read data written to the selected memory cell 810. Bit lines BL not connected to the selected memory cell 810 can be grounded or floating. A read operation can then be performed on the selected memory cell 810.

[0132] Figure 10 This is a diagram illustrating the current flow in a selected memory cell 810 during read mode, according to one embodiment. (See also...) Figure 10 In read mode, a read voltage Vread can be applied to the bit line BL connected to the selected memory cell 810, and a conduction voltage Von can be applied to the unselected memory cell 820, thus the semiconductor layer 522d of the unselected memory cell 820 can have conductive properties. Therefore, the read current Iread can flow through the semiconductor layer 522d of the unselected memory cell 820. However, the current conduction voltage Vion can be applied to the selected memory cell 810, so the read current Iread can flow through the semiconductor layer 522c and the resistance variation layer 523c of the selected memory cell 810.

[0133] The current-carrying voltage Vion can have a resistance R that allows the semiconductor layer 522c to be... Si The resistance P of the resistance-changing layer 523c RS Values ​​within a similar range. For example, the value of the current-on voltage Vion can be selected such that it corresponds to the resistance R of the semiconductor layer 522c of the selected memory cell 810. Si The resistance is equal to or greater than the minimum resistance of the resistance variation layer 523c corresponding to the selected memory cell 810, or the resistance R of the semiconductor layer 522c of the selected memory cell 810. Si It is equal to or less than the maximum resistance of the resistance variation layer 523c corresponding to the selected memory cell 810.

[0134] As a result, the total resistance of the selected memory cell 810 can be determined as the resistance R of the semiconductor layer 522c. Si and the resistance R of the resistance variation layer 523c RSThe parallel resistance. The read voltage Iread may not flow through the resistance variation layer 523d ​​of the unselected memory cell 820, but only through the semiconductor layer 522d. Therefore, the read current Iread can be determined by the total resistance of the selected memory cell 810. Therefore, the total resistance of the selected memory cell 810 can be calculated by measuring the intensity of the read current Iread.

[0135] Figure 11 This is a schematic cross-sectional view of a structure for testing the operation of a memory cell according to one embodiment. (Refer to...) Figure 11 A SiO2 layer 12 with a thickness of 10 nm can be stacked on a doped p++ Si layer (e.g., a wafer) 11, and a doped n+ Si layer 13 with a thickness of 50 nm can be stacked on the SiO2 layer 12. The SiO2 layer 12 and the n+ Si layer 13 can be formed by deposition via low-pressure chemical vapor deposition (LPCVD) followed by rapid thermal annealing (RTA) at 1000 °C for 30 seconds. The SiO2 layer 12 and the n+ Si layer 13 can then be patterned by etching into a cylindrical shape with a diameter D of 100 μm.

[0136] Subsequently, electrodes 15 and 16 can be formed on the p++Si layer 11 and n+Si layer 13, respectively, using a lift-off process. Pt and Ti, each with a thickness of 20 nm, can be used as electrodes 15 and 16. Next, a transition metal oxide layer 14 can be formed to cover the upper surface of the p++Si layer 11, the side surfaces of the SiO2 layer 12, and the upper surface of the n+Si layer 13. The transition metal oxide layer 14 can be deposited in an O3 atmosphere at a temperature of 150 °C using atomic layer deposition (ALD) to a thickness of 0.5 nm. TiO2 can be used as the transition metal oxide layer 14.

[0137] exist Figure 11 In the structure of the memory cell shown for the experiment, the p++Si layer 11 and n+Si layer 13 can be used as semiconductor layers for the unselected memory cells 720 and 820 that are turned on, the SiO2 layer 12 can be used as semiconductor layers for the selected memory cells 710 and 810 that are turned off, and the transition metal oxide layer 14 can be used as a resistance-changing layer. Therefore, in Figure 11 The structure of the memory cell shown in the experiment illustrates an example in which a resistance variation layer 523 comprising a metal semiconductor oxide is formed by thinly depositing a transition metal oxide along the surface of the semiconductor layer 522.

[0138] Figure 12 It is used to identify by Figure 11The graph shows X-ray photoelectron spectroscopy (XPS) data of a metal-semiconductor oxide formed by a mixture of semiconductor material in semiconductor layer 522 and transition metal oxide in resistance-changing layer 523 of the memory cell structure. (Refer to...) Figure 12 This shows the peak shift due to Ti silicate. Therefore, in Figure 11 In the memory cell shown, it should be understood that Si can diffuse to the transition metal oxide layer 14 formed to cover the upper surface of the p++Si layer 11, the side surface of the SiO2 layer 12, and the upper surface of the n+Si layer 13, thereby forming a metal semiconductor oxide.

[0139] Figure 13 This is a graph showing the experimentally obtained current-voltage behavior of a plurality of memory cells comprising a metal-semiconductor oxide, according to one embodiment. In detail, Figure 13 The experimental results are shown for 64 memory cells, which were manufactured to have... Figure 11 The structure is shown in the diagram. To identify the possibility of multi-level storage during experiments, a limiting current of 100 nA can be applied to the memory cells. By using... Figure 13 The thick solid line in the graph shows the average current-voltage behavior across 64 memory cells. (Example) Figure 13 As shown, resistance changes occur in all memory cells, and multiple resistance states are clearly distinguished.

[0140] Figure 14 Through Figure 13 The graphs identified include those depicting the current-voltage behavior of memory cells containing metal-semiconductor oxides. (Refer to...) Figure 14 The voltage required for the initial setup operation is lower than that required for subsequent setup operations; therefore, an electrical forming process is not required. The voltage applied during the setup operation can be limited to a relatively low value of less than or equal to about 10V. In particular, the voltage applied during the setup operation can be in the range of about 5V to about 8V. Similarly, the voltage during the reset operation can also be limited to a relatively low value of about -6V.

[0141] Therefore, in Figure 7A and Figure 8In the programming mode shown, when a programming voltage Vprogram of less than or equal to about 10V (e.g., about 5V to about 8V) is applied to the bit line BL connected to the selected memory cell 710, electrons can be trapped in charge traps in the resistance change layer 523a corresponding to the selected memory cell 710 among the plurality of resistance change layers 523. Therefore, the resistance of the resistance change layer 523a corresponding to the selected memory cell 710 can be reduced. Conversely, when a programming voltage Vprogram of about -6V is applied to the bit line BL connected to the selected memory cell 710, electrons can be trapped from the charge traps in the resistance change layer 523a corresponding to the selected memory cell 710. Therefore, the resistance of the resistance change layer 523a corresponding to the selected memory cell 710 can be increased.

[0142] Because no forming process is required, there is virtually no possibility of damaging the memory block due to high forming voltage. Furthermore, the setting and reset voltages can be kept relatively low, thus reducing the power consumption of the memory device 200.

[0143] Figure 15 and Figure 16 It is a graph showing the current-voltage behavior of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment. Figure 15 The experimental results for 64 memory cells are shown, where based on Figure 11 The structure of the memory cell shown in the figure uses HfO2 instead of TiO2 as the transition metal oxide layer 14. Figure 16 Experimental results for 64 memory cells using Al₂O₃ are shown. When using HfO₂, a limiting current of 0.1 A can be applied to the memory cells, while when using Al₂O₃, a limiting current of 1 μA can be applied. Figure 15 and Figure 16 As shown, when using HfO2 and Al2O3, sufficient charge traps may not form in Hf silicates and Al silicates, therefore, multiple resistance states may not be clearly delineated.

[0144] Figure 17 This is a comparison table between the characteristics of a memory cell comprising a metal semiconductor oxide according to one embodiment and the characteristics of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment. Figure 17 In the table, yield is the probability that the resistance in the high resistance state (HRS) differs from the resistance in the low resistance state (LRS) by a factor of 1000 or more. In other words, yield is the ratio of memory cells with an on / off current ratio of 1000 or more to all memory cells when a 4V read voltage is applied to the memory cell. (Refer to...) Figure 17When Al2O3 is used as the transition metal oxide layer 14, the percentage of memory cells with an on / off current ratio of 1000 or higher is only about 14.06%. When HfO2 is used, the percentage of memory cells with an on / off current ratio of 1000 or higher is about 90.16%, while when TiO2 is used, the percentage of memory cells with an on / off current ratio of 1000 or higher is the highest, at about 93.88%.

[0145] also, Figure 17 The non-uniformity in the table is obtained by dividing the difference between the maximum resistance Rmax and the minimum resistance Rmin of the memory cells measured with respect to the same resistance state by the average resistance Raver, and can be expressed as 100×(Rmax-Rmin) / (2×Raver). The non-uniformity with respect to 64 memory cells is the highest, approximately 29.2, when Al2O3 is used as the transition metal oxide layer 14, and the non-uniformity with respect to 64 memory cells is the lowest, approximately 8.7, when TiO2 is used as the transition metal oxide layer 14.

[0146] Figure 18 This is a comparison diagram between the resistance distribution of a memory cell comprising a metal semiconductor oxide according to one embodiment and the resistance distribution of a memory cell comprising a metal semiconductor oxide according to a comparative embodiment. When HfO2 is used as the transition metal oxide layer 14, the resistance distribution is obtained by applying limiting currents of 0.1A and 1μA to each of the 64 memory cells. When TiO2 is used as the transition metal oxide layer 14, the resistance distribution is obtained by applying limiting currents of 100nA and 10nA to each of the 64 memory cells. Furthermore, when Al2O3 is used as the transition metal oxide layer 14, the resistance distribution is obtained by applying limiting currents of 1μA and 100nA to each of the 64 memory cells. The read voltage applied to the memory cell is 4V. Figure 18 As shown in the graph, the resistance distribution is minimized when TiO2 is used. Furthermore, the overlap between multiple resistance states is minimized when TiO2 is used. Therefore, when using TiO2, an MLC with at least three different resistance states can be achieved by adjusting the limiting current flowing through the memory cell.

[0147] Figure 19A and Figure 19B These are graphs showing the cumulative probability of the resistance distribution of a memory cell comprising a metal-semiconductor oxide according to one embodiment and the resistance distribution of a memory cell comprising a metal-semiconductor oxide according to a comparative embodiment. Experimental conditions and... Figure 18 The same as described in [the text]. Figure 19A and Figure 19B This means changing the outcome to a cumulative probability. Figure 18 The results obtained. Figure 19A This shows the cumulative probability when TiO2 is used as the transition metal oxide layer 14. Figure 19B The cumulative probabilities are shown when HfO2 is used as the transition metal oxide layer 14. When TiO2 is used, the gradients of the cumulative probabilities for all three resistance states (i.e., LRS1, LRS2, and HRS) are steep, and the overlap between LRS1, LRS2, and HRS is small, thus LRS1, LRS2, and HRS are clearly distinguished. However, when HfO2 is used, there is overlap between the two low-resistance states (i.e., LRS1 and LRS2), therefore, the resistance states are not clearly distinguished.

[0148] As shown in the experimental results above, when TiO2 is used as the transition metal oxide layer 14, that is, when Ti silicate is used as the resistance variation layer 523, high uniformity of the resistance distribution of the resistance variation layer 523 can be obtained. Furthermore, the overlap between the resistance states of the resistance variation layer 523 is low, thus the resistance states can be clearly distinguished. Therefore, the resistance variation layer 523 including Ti silicate is effective for realizing MLC.

[0149] Figures 20A to 20C This is a density of states (DOS) graph showing a comparison between the characteristics of a metal-semiconductor oxide according to one embodiment and the characteristics of a metal-semiconductor oxide according to a comparative embodiment. In detail, Figure 20A This is a diagram of the DOS of SiO2. Figure 20B This is a diagram of the DOS when some Si atoms in the SiO2 site are replaced by Ti atoms. Figure 20C This is a diagram of the DOS when some Si atoms in the SiO2 site are replaced by Hf atoms. Figures 20A to 20C The thick solid line in the figure represents the band gap of SiO2. Additionally, Figure 20B The portion indicated by the thin solid line is the DOS of Ti silicate. Figure 20C The portion indicated by the thin solid line is the DOS of Hf silicate.

[0150] like Figure 20B As shown, in the case of Ti silicates, charge trapping sites formed due to antisite defects may exist within the band gap of SiO2. That is, in the case of Ti silicates, defect states may form directly within the band gap of SiO2, thus creating new trapping sites within the SiO2 band gap. Conversely, as... Figure 20C As shown, in the case of Hf silicates, defect states can form in the valence band or conduction band region of SiO2. Therefore, Hf silicates can prevent the formation of new trapping sites in the band gap of SiO2.

[0151] For this reason, transition metal oxide materials, which can be readily formed into metal semiconductor oxides by mixing with semiconductor materials and can form charge trapping sites in the band gap of the semiconductor oxide due to antisite defects related to the semiconductor material, are suitable for forming the metal semiconductor oxide of the resistance-changing layer 523. Therefore, the transition metal oxide suitable for forming the metal semiconductor oxide of the resistance-changing layer 523 can have a band gap much smaller than that of the semiconductor oxide. For example, the band gap of the transition metal oxide can be less than 4.5 eV. In particular, the band gap of the transition metal oxide can be less than 3.5 eV.

[0152] For example, Figure 21 This is a diagram showing the bandgap distribution of candidate transition metal oxides used to generate the resistance-changing layer 523. (See diagram for example.) Figure 21 As indicated by the circle, when Si is used as the semiconductor material for semiconductor layer 522, transition metal oxides such as Ta2O5, BaO, TiO2, etc., which have small band gaps and are reported to form silicates, can be used. In this case, the metal semiconductor oxide of the resistance-changing layer 523 may include, for example, Ta silicate, Ba silicate, Ti silicate, etc.

[0153] Meanwhile, in oxides with n+Si and a small conduction band offset (CBO) due to their small band gap, resistance changes are typically not observed. According to embodiments of this disclosure, even when the band gap of the transition metal oxide used to form the resistance-changing layer 523 is small, a resistance change can be observed because a large portion of the resistance-changing layer 523 can comprise a metal semiconductor oxide by reducing the thickness of the resistance-changing layer 523. Therefore, when the thickness of the resistance-changing layer 523 is increased, the proportion of transition metal oxide remaining in the resistance-changing layer 523 can increase, and thus, the performance of the resistance-changing layer 523 may deteriorate due to bulk conductivity.

[0154] For example, Figure 22 Is Figure 11 The graph shown illustrates the current-voltage behavior of the memory cell structure as the thickness of the transition metal oxide increases. In detail, Figure 22 Shown in Figure 11 The results of experiments were conducted in the structure of the memory cell shown, where a transition metal oxide layer 14, including TiO2, was deposited to a thickness of 3 nm. (As shown...) Figure 22 As shown, when the thickness of the transition metal oxide layer 14 is increased, bulk conduction inherently included in TiO2 may occur.

[0155] also, Figure 23 It shows the gradual thickness variation according to the transition metal oxide. Figure 11The table shows the changes in the characteristics of the memory cells. (Formed in...) Figure 11 Each memory cell shown has a transition metal oxide layer 14 with only varying thickness, and the current-voltage behavior of the memory cell is measured by applying a limiting current of 100 nA to the memory cell. Figure 23 As shown, when the transition metal oxide layer 14 is deposited to a thickness of 0.5 nm, the ratio of memory cells with an on / off current ratio of 10 or higher can reach 96.8%. Furthermore, as the thickness of the transition metal oxide layer 14 increases and / or decreases, the ratio of memory cells with an on / off current ratio of 10 or higher can decrease. When the transition metal oxide layer 14 is deposited to a thickness of 1.5 nm, resistance changes are rarely observed.

[0156] The deposition limit of the thickness of the transition metal oxide layer 14 can vary depending on the intensity of the limiting current applied to the memory cell or the size or structure of the memory cell. Therefore, the maximum thickness of the resistance variation layer 523 in the actual memory device 200 can be about 2.0 nm. For example, the thickness of the resistance variation layer 523 can be in the range of about 0.1 nm to about 2.0 nm. Alternatively, the thickness of the resistance variation layer 523 can be in the range of about 0.3 nm to about 1.5 nm. Or, the thickness of the resistance variation layer 523 can be in the range of about 0.5 nm to about 1.0 nm.

[0157] When the resistance-changing layer 523 is formed by directly depositing the prepared metal-semiconductor oxide along the surface of the semiconductor layer 522, the first semiconductor material of the semiconductor layer 522 and the second semiconductor material of the metal-semiconductor oxide can be different from each other. In this case, inversion defects may be generated in the metal-semiconductor oxide due to the site reversal between the second semiconductor material and the transition metal. Therefore, the transition metal oxide material, which may form charge-trapping sites due to inversion defects in the band gap of the oxide of the second semiconductor material included in the metal-semiconductor oxide, can be suitable for forming the metal-semiconductor oxide of the resistance-changing layer 523. Moreover, the transition metal oxide suitable for forming the metal-semiconductor oxide of the resistance-changing layer 523 can have a band gap much smaller than that of the oxide of the second semiconductor material.

[0158] When a portion of the first semiconductor material of semiconductor layer 522 diffuses into resistance-changing layer 523, the metal semiconductor oxide may include both the first semiconductor material and the second semiconductor material. In this case, both a transition metal oxide material capable of forming charge trapping sites due to antisite defects in the band gap of the first semiconductor material oxide and a transition metal oxide material capable of forming charge trapping sites due to antisite defects in the band gap of the second semiconductor material oxide can be used. Moreover, the transition metal oxide used to form resistance-changing layer 523 may have a smaller band gap than the first semiconductor material oxide and may also have a smaller band gap than the second semiconductor material oxide.

[0159] Furthermore, when the resistance variation layer 523 is formed by directly depositing the prepared metal semiconductor oxide along the surface of the semiconductor layer 522, the metal semiconductor oxide can be uniformly distributed throughout the entire region of the resistance variation layer 523. Therefore, in this case, a resistance variation layer 523 with a greater thickness than the example described above can be formed.

[0160] Figure 24 This is a schematic diagram of the structure of a memory device according to a comparative embodiment. The memory device according to the comparative embodiment can correspond to resistive random access memory (RRAM) and can have a structure in which memory cells MC0 and MC1 are arranged at each point where multiple bit lines BL00, BL01, BL02, BL10, BL11, and BL12 intersect each other perpendicularly with multiple word lines WL0, WL1, and WL2. Furthermore, Figure 25 yes Figure 24 The diagram shows a schematic cross-sectional view of the structure of a storage cell in a storage device. (Refer to...) Figure 25 The bit line BL and word line WL can be connected to the upper and lower parts of each memory cell MC.

[0161] RRAM can be similar to the memory device 200 according to this disclosure, wherein the RRAM includes memory cells MC containing resistivity-changing material, but may have a different structure and operating principle than the memory device 200 according to this disclosure. In the case of RRAM, according to a comparative embodiment, the resistance change of the memory cell MC may not correspond to the resistance change of the resistivity-changing material. Instead, the resistance change in the RRAM may occur due to ion movement in the electrodes (i.e., bit lines BL and word lines WL). In particular, because the interface direction (x-direction) of the resistivity-changing material is perpendicular to the electric field direction (z-direction), the resistance change may not be concentrated at the interface of the resistivity-changing material.

[0162] Figure 26A and Figure 26BThis is an example conceptual diagram illustrating the principle of resistance change operation in the resistance change layer of a memory cell according to one embodiment. For example... Figure 26A As shown, when multiple charge traps CT are uniformly distributed in the resistance variation layer 523, the resistance variation layer 523 can become a high-resistivity state. The charge traps CT can include charge traps formed due to antisite defects and charge traps formed due to oxygen vacancies. Unlike others, such as... Figure 26B As shown, when the plurality of charge traps CT in the resistance change layer 523 move toward the interface between the resistance change layer 523 and the semiconductor layer 522 to be mainly distributed on the interface between the resistance change layer 523 and the semiconductor layer 522, the resistance change layer 523 can become a low resistance state.

[0163] These resistance changes in the resistance-changing layer 523 can be described as the phenomenon where electrons are trapped in / decaptured from charge traps CT. When the charge traps CT are uniformly distributed in the resistance-changing layer 523, the charge traps CT can be separated from each other by a certain distance, and electrons can be trapped from the charge traps CT, making it difficult for current to flow through the resistance-changing layer 523. Therefore, the resistance-changing layer 523 can become a high-resistance state. In contrast, when the charge traps CT in the resistance-changing layer 523 are mainly distributed at the interface between the resistance-changing layer 523 and the semiconductor layer 522, electrons can fill the interface between the resistance-changing layer 523 and the semiconductor layer 522 (where the charge traps CT are mainly distributed), thus forming conductive filaments. Therefore, the resistance-changing layer 523 can become a low-resistance state.

[0164] Therefore, when the charge traps CT distributed in the resistance-changing layer 523 are moved to the interface between the resistance-changing layer 523 and the semiconductor layer 522 through programming operations, and electrons are trapped in the charge traps CT, the resistance-changing layer 523 can become a low-resistance state. Conversely, when the charge traps CT are uniformly dispersed in the resistance-changing layer 523, the charge traps CT concentrated at the interface between the resistance-changing layer 523 and the semiconductor layer 522 are moved away from the interface by means of an erasure operation and the trapping of electrons from the charge traps CT, and the resistance-changing layer 523 can again become a high-resistance state. For example, in Figure 7A (and / or Figure 7C )and Figure 8In the programming mode shown, when a positive (+) programming voltage Vprogram is applied to the selected memory cell 710 via the bit line BL connected to the selected memory cell 710, the resistance variation layer 523a corresponding to the selected memory cell 710 can have a reduced resistance. Furthermore, when a negative (-) programming voltage is applied to the selected memory cell 710 via the bit line BL, the resistance variation layer 523a corresponding to the selected memory cell 710 can have an increased resistance.

[0165] Therefore, in Figure 7A (and / or Figure 7C )and Figure 8 In the programming mode shown, a positive (+) programming voltage can be applied via the bit line BL connected to the selected memory cell 710 in the memory cell string. Here, charge traps CT can move toward the interface between the semiconductor layer 522 and the resistance change layer 523a corresponding to the selected memory cell 710, and electrons can be trapped in the charge traps CT in the resistance change layer 523a corresponding to the selected memory cell 710. Then, as the density of charge traps CT at the interface between the semiconductor layer 522 and the resistance change layer 523a increases, the resistance of the resistance change layer 523a corresponding to the selected memory cell 710 can decrease.

[0166] Furthermore, a negative (-) programming voltage can be applied to the selected memory cell 710 in the memory cell string via the bit line BL. In this case, the charge trap CT in a portion of the resistance-changing layer 523a corresponding to the selected memory cell 710 can move away from the interface between the semiconductor layer 522 and the resistance-changing layer 523a, allowing electrons to be captured from the charge trap CT, and reducing the density of the charge trap CT at the interface between the semiconductor layer 522 and the resistance-changing layer 523a. Thus, the resistance-changing layer 523a corresponding to the selected memory cell 710 can have increased resistance.

[0167] For reference Figure 14 The positive (+) programming voltage applied during the setup operation can be limited to a relatively low value of less than or equal to about 10V. Specifically, the positive (+) programming voltage can be selected within a range of about 5V and about 8V. Furthermore, the negative (-) programming voltage applied during the reset operation can also be limited to a relatively low value of about -6V.

[0168] Thus, unlike the RRAM according to the comparative embodiment, in the memory device 200 according to an exemplary embodiment, the charge trap CT can be concentrated at the interface between the semiconductor layer 522 and the resistance variation layer 523, and therefore the resistance variation can also be concentrated at the interface between the semiconductor layer 522 and the resistance variation layer 523. Therefore, the uniformity with respect to the plurality of memory cells can be improved. This is likely because the direction (z-direction) of the interface between the semiconductor layer 522 and the resistance variation layer 523 is the same as the direction (z-direction) of the electric field applied to the resistance variation layer 523. In other words, the direction of the current flowing through the resistance variation layer 523 can be the same as the direction in which the resistance variation layer 523 extends.

[0169] In the RRAM according to the comparative embodiment, the direction of the electric field applied to the resistivity-changing material can be perpendicular to the direction of the interface with respect to the resistivity-changing material. Therefore, an electroforming process for activating ion movement may be required after the RRAM is manufactured. The storage device 200 according to the embodiment may not require this electroforming process.

[0170] Furthermore, as described above, an MLC with at least three different resistance states can be achieved by adjusting the limiting current flowing through the resistance-changing layer 523. For example, in Figure 7A (and / or Figure 7C )and Figure 8 In the programming mode shown, the channel resistance of the unselected memory cell 720, or in other words, the resistance of the semiconductor layer 522b of the unselected memory cell 720, can be changed according to the strength of the on-state voltage applied to the gate 531b of the unselected memory cell 720. Therefore, when the programming voltage applied to the bit line BL connected to the selected memory cell 710 is fixed, the current flowing through the resistance variation layer 523a of the selected memory cell 710 can be varied according to the strength of the on-state voltage applied to the gate 531b of the unselected memory cell 720. By adjusting the on-state voltage applied to the gate 531b of the unselected memory cell 720 based on this method, the conditions for the current flowing through the resistance variation layer 523a can be selected, thereby selecting the resistance variation characteristics and resistance state of the resistance variation layer 523a.

[0171] The storage block according to the above embodiments can be implemented in the form of a chip and can be used as a neuromorphic computing platform. For example, Figure 27 This is a schematic diagram of a neuromorphic device 1000 including a storage device according to one embodiment. (See also...) Figure 27 The neuromorphic device 1000 may include processing circuitry 1010 and / or memory 1020. The memory 1020 of the neuromorphic device 1000 may include a memory system 10 according to one embodiment.

[0172] In some example embodiments, processing circuitry 1010 may be configured to control functions for driving neuromorphic device 1000. For example, processing circuitry 1010 may be configured to control neuromorphic device 1000 by executing a program stored in memory 1020 of neuromorphic device 1000. In some example embodiments, processing circuitry may include: hardware such as logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof. For example, processors may include, but are not limited to, central processing unit (CPU), graphics processing unit (GPU), application processor (AP) included in neuromorphic device 1000, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc. In some example embodiments, processing circuitry 1010 may be configured to read / write various data from external device 1030 and / or execute neuromorphic device 1000 by using the read / written data. In some embodiments, external device 1030 may include external memory and / or sensor array with image sensors (e.g., CMOS image sensor circuitry).

[0173] Reference Figures 1-2 The memory controller 100, write / read controller 110, voltage controller 120, data determiner 130, voltage generator 220, control logic 250, and row decoder 230 can also be implemented using processing circuitry. The memory controller 100, including the write / read controller 110, voltage controller 120, and data determiner 130, can be operated based on control signals used to control the operation of the memory device 200 discussed herein, thereby converting the memory controller 100 and its read / write controller 110, voltage controller 120, and data determiner 130 into dedicated processing circuitry.

[0174] In some implementations... Figure 27 Neuromorphic devices in this context can be applied to machine learning systems. Machine learning systems can utilize various artificial neural networks to organize and process models, such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) that optionally include long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0175] Alternatively or additionally, such machine learning systems may include other forms of machine learning models, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models can also be used to provide a variety of services and / or applications, such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which can be performed, executed, or processed by electronic devices.

[0176] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the following claims.

[0177] This application is based on and claims priority to Korean Patent Application No. 10-2020-0089858, filed on July 20, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A non-volatile storage device, comprising: Multiple storage unit strings, Each of the plurality of memory cell strings includes a semiconductor layer, a plurality of gates and a plurality of insulators, a gate insulating layer and a resistance variation layer. The semiconductor layer includes a first semiconductor material and extends in a first direction, the semiconductor layer including a first surface and a second surface opposite to the first surface. The plurality of gates and the plurality of insulators each extend in a second direction perpendicular to the first direction, and the plurality of gates and the plurality of insulators are arranged alternately in the first direction; The gate insulating layer extends in the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer. The resistance variation layer extends in the first direction on the second surface of the semiconductor layer. The resistance-changing layer includes: a metal semiconductor oxide comprising a second semiconductor material and a transition metal oxide; as well as The metal semiconductor oxide has charge trapping sites in the band gap of the oxide of the second semiconductor material.

2. The non-volatile storage device according to claim 1, wherein, The metal semiconductor oxide in the resistance-changing layer has inversion defects caused by site reversal between the second semiconductor material and the transition metal oxide.

3. The non-volatile storage device according to claim 2, wherein, The band gap of the transition metal oxide is smaller than the band gap of the oxide of the second semiconductor material.

4. The non-volatile storage device according to claim 3, wherein, The band gap of the transition metal oxide is less than 4.5 eV.

5. The non-volatile storage device according to claim 4, wherein, The band gap of the transition metal oxide is less than 3.5 eV.

6. The non-volatile storage device according to claim 1, wherein, The first semiconductor material and the second semiconductor material are the same.

7. The non-volatile storage device according to claim 1, wherein... The first semiconductor material and the second semiconductor material are different from each other, and The metal semiconductor oxide of the resistance-changing layer comprises both the first semiconductor material and the second semiconductor material.

8. The non-volatile storage device according to claim 1, wherein The transition metal oxide includes at least one selected from Ta₂O₅, BaO, and TiO₂, and The metal semiconductor oxide includes Ta silicate, Ba silicate, Ti silicate, and TaGe. x O y BaGe x O y and TiGe x O y At least one of them.

9. The non-volatile storage device according to claim 1, wherein, The first semiconductor material of the semiconductor layer includes at least one selected from Si, Ge, indium gallium zinc oxide (IGZO) and GaAs.

10. The non-volatile storage device according to claim 1, wherein, The ratio of the second semiconductor material in the resistance-changing layer is 20 at.% to 80 at.%.

11. The non-volatile storage device according to claim 10, wherein, The proportion of the second semiconductor material in the resistance-changing layer is 40 at.% to 60 at.%.

12. The non-volatile storage device according to claim 10, wherein, The ratio of the second semiconductor material in the resistance-changing layer is approximately constant within a 10% deviation range throughout the entire region of the resistance-changing layer.

13. The non-volatile storage device according to claim 1, wherein, The thickness of the resistance-changing layer in the second direction is 0.1 nm to 2.0 nm.

14. The non-volatile storage device according to claim 13, wherein, The thickness of the resistance-changing layer in the second direction is 0.3 nm to 1.5 nm.

15. The non-volatile storage device according to claim 14, wherein, The thickness of the resistance-changing layer in the second direction is 0.5 nm to 1.0 nm.

16. The non-volatile storage device according to claim 13, wherein, The thickness of the resistance-changing layer is approximately constant within a 10% deviation range over the entire area of ​​the resistance-changing layer extending along the first direction.

17. The non-volatile storage device according to claim 1, wherein... A memory cell is defined by one of the plurality of gates, a portion of the gate insulating layer adjacent to the one gate in the second direction, a portion of the semiconductor layer adjacent to the one gate in the second direction, and a portion of the resistance-changing layer adjacent to the one gate in the second direction. Multiple storage cells are arranged in a vertically stacked structure in each of the storage cell strings.

18. The non-volatile storage device according to claim 17, further comprising: The control logic is configured, in programming mode, to apply an on-state voltage to the gate of an unselected memory cell in the plurality of memory cell strings and to apply a off-state voltage to the gate of a selected memory cell in the plurality of memory cell strings. as well as Bit lines are configured to apply programming voltages to the selected memory cells.

19. The non-volatile storage device according to claim 18, wherein, The resistance-changing layer is configured such that, in response to a positive programming voltage being applied to the selected memory cell through the bit line, the resistance of a portion of the resistance-changing layer corresponding to the selected memory cell decreases because electrons are trapped in charge traps in that portion of the resistance-changing layer. In response to the application of a negative programming voltage to the selected memory cell via the bit line, the resistance of the portion of the resistance-changing layer corresponding to the selected memory cell increases as electrons are captured from the charge traps in the portion of the resistance-changing layer.

20. The non-volatile storage device according to claim 19, wherein, The positive programming voltage is 10V or less.

21. The non-volatile storage device according to claim 20, wherein, The positive programming voltage is in the range of 5V to 8V.

22. The non-volatile storage device according to claim 19, wherein, In response to a decrease in resistance in the portion of the resistance-changing layer, the direction of the current flowing through the portion of the resistance-changing layer is the same as the first direction in which the resistance-changing layer extends.

23. The non-volatile storage device according to claim 19, wherein, The portion of the resistance variation layer has at least three different resistance states.

24. The non-volatile storage device according to claim 23, wherein, The non-volatile storage device is configured to select the resistance state of the portion of the resistance-varying layer based on adjusting the current applied to the portion of the resistance-varying layer.

25. The non-volatile storage device according to claim 18, wherein The resistance-changing layer is configured such that, in response to a positive programming voltage being applied to the selected memory cell via the bit line, oxygen vacancies move toward the interface between the semiconductor layer and the resistance-changing layer in a portion of the resistance-changing layer corresponding to the selected memory cell. In response to applying a negative programming voltage to the selected memory cell via the bit line, the oxygen vacancy moves away from the interface between the semiconductor layer and the resistance-changing layer in the portion of the resistance-changing layer corresponding to the selected memory cell.

26. The non-volatile storage device according to claim 25, wherein The resistance-changing layer is configured such that, in response to the oxygen vacancies moving towards the interface between the semiconductor layer and the resistance-changing layer in the partial region of the resistance-changing layer, thereby increasing the density of the oxygen vacancies at the interface between the semiconductor layer and the resistance-changing layer, the resistance of the partial region of the resistance-changing layer decreases, and... In response to the oxygen vacancies moving away from the interface between the semiconductor layer and the resistance-changing layer in the partial region of the resistance-changing layer, thereby reducing the density of the oxygen vacancies at the interface between the semiconductor layer and the resistance-changing layer, the resistance of the partial region of the resistance-changing layer increases.

27. The non-volatile storage device according to claim 26, wherein, The resistance state of the resistance-changing layer is configured to vary according to the phenomenon in which electrons are trapped in or decaptured from the charge traps defined by the oxygen vacancies.

28. A non-volatile storage device, comprising: substrate; Multiple bit lines above the substrate extend in a first direction and are spaced apart from each other in a second direction that intersects the first direction; Multiple gates and multiple insulators are alternately stacked on the substrate from a third direction perpendicular to the top surface of the substrate; as well as Multiple pillars spaced apart from each other on the substrate Each corresponding post among the plurality of posts is electrically connected to the corresponding bit line among the plurality of bit lines. Each of the plurality of pillars extends upward through a corresponding aperture defined in the alternately stacked plurality of gates and the plurality of insulators in the third direction. Each of the plurality of pillars includes a resistance-varying layer extending upward from the third party, a semiconductor layer surrounding the resistance-varying layer, and a gate insulating layer surrounding the semiconductor layer. The resistance-varying layer comprises a metal semiconductor oxide having a resistance that varies according to the voltage applied thereto, and The resistance variation layer includes charge trapping sites.

29. The non-volatile storage device according to claim 28, wherein, In at least one of the plurality of columns, The gate insulating layer is in direct contact with the first surface of the semiconductor layer. The resistance-changing layer directly contacts the second surface of the semiconductor layer, which is opposite to the first surface of the semiconductor layer, and The gate insulating layer extends between the plurality of gates and the semiconductor layer.

30. The non-volatile storage device according to claim 28, wherein, The thickness of the resistance-changing layer is 0.3 nm to 1.5 nm.

31. The non-volatile storage device according to claim 28, wherein... The metal-semiconductor oxide of the resistance-changing layer includes semiconductor materials and transition metal oxides. The transition metal oxide includes at least one selected from Ta₂O₅, BaO, and TiO₂, and The semiconductor material includes at least one selected from Si, Ge, indium gallium zinc oxide (IGZO), and GaAs.

32. The non-volatile storage device according to claim 31, wherein... In the resistance-changing layer, the ratio of the semiconductor material to the transition metal oxide is 20 at.% to 80 at.%.

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