Adapter plate and preparation method thereof, chip packaging structure and electronic equipment

Abstract

The embodiment of the invention provides an adapter plate and a preparation method thereof, a chip packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for improving the signal transmission efficiency in the adapter plate. The adapter plate comprises a substrate, a conductive structure arranged in the substrate, a first redistribution layer arranged on the substrate and a second redistribution layer arranged on the side, away from the first redistribution layer, of the substrate. The second redistribution layer is coupled to the first redistribution layer through the conductive structure. Wherein the material of the substrate comprises a semiconductor material, the first redistribution layer comprises a first metal wire, the second redistribution layer comprises a second metal wire, and the thickness of the first metal wire and / or the second metal wire is greater than 1 [mu] m.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an adapter board and a preparation method thereof, a chip packaging structure, and an electronic device. Background Art

[0002] With the development of electronic technology, the functions of electronic devices are becoming increasingly diversified and comprehensive. Chips used to realize different functions are integrated into electronic devices, which also increases the demand for chip integration on integrated circuits in electronic devices.

[0003] In 3D or 2.5D packaging, an interposer (INTP) is used to achieve interconnection between chips and between chips and packaging boards.

[0004] However, the signal in INTP is transmitted through multiple layers of metal wiring, and its transmission rate is low, which affects the performance of the adapter board. Summary of the invention

[0005] Embodiments of the present application provide an adapter board and a method for preparing the same, a chip packaging structure, and an electronic device, which are used to improve the signal transmission efficiency in the adapter board.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect of an embodiment of the present application, an adapter board is provided, which is applied to chip packaging. The adapter board includes a substrate, a conductive structure arranged in the substrate, a first redistribution layer arranged on the substrate, and a second redistribution layer arranged on a side of the substrate away from the first redistribution layer. The second redistribution layer is coupled to the first redistribution layer through the conductive structure. The material of the substrate includes a semiconductor material, the first redistribution layer includes a first metal wiring, the second redistribution layer includes a second metal wiring, and the thickness of the first metal wiring and / or the second metal wiring is greater than 1 μm.

[0008] In the adapter board provided by the embodiment of the present application, the first redistribution layer and the second redistribution layer are respectively arranged on two opposite surfaces of the substrate, that is, the first redistribution layer and the second redistribution layer are arranged relative to each other, at this time, the stress of the first redistribution layer on the substrate and the stress of the second redistribution layer on the substrate can partially offset each other, the stress on the substrate is reduced, the warping degree of the substrate can be alleviated, and the reliability of the adapter board is improved. At this time, the adapter board can withstand the additional stress pressure brought by the thicker first metal wiring or the second metal wiring, that is, the first metal wiring or the second metal wiring can have a larger thickness, thereby reducing the resistance of the first redistribution layer or the second redistribution layer, and improving the transmission efficiency of the signal in the adapter board.

[0009] Furthermore, due to the additional stress-bearing capacity brought by the double-sided redistribution layer, the thickness of the substrate can also be made thinner, such as 20μm to 100μm, thereby reducing the thickness of the entire packaging structure and meeting the "thin" requirement for the chip.

[0010] In a possible implementation, the thickness of the substrate is 20 μm to 100 μm. In this way, since the stress on the substrate is relieved, the thickness of the substrate can be reduced.

[0011] In a possible implementation, the first redistribution layer includes multiple layers of first metal wiring, multiple layers of first vias, and multiple layers of first dielectric layers; the multiple layers of first dielectric layers are stacked, and the first metal wiring and the first vias are located in the first dielectric layer; along the direction in which the multiple layers of first dielectric layers are stacked, the first metal wiring and the first vias are alternately arranged; the number of layers of the first metal wiring is greater than 4. In this way, by increasing the number of layers of the first metal wiring, the wiring density of the adapter board can be increased.

[0012] In a possible implementation, the second rewiring layer includes multiple layers of second metal wiring, multiple layers of second vias, and multiple layers of second dielectric layers; the multiple layers of second dielectric layers are stacked, and the second metal wiring and the second vias are located in the second dielectric layer; along the direction in which the multiple layers of second dielectric layers are stacked, the second metal wiring and the second vias are alternately arranged; the number of layers of the first metal wiring and the number of layers of the second metal wiring are the same. In this way, the stress on the substrate can be further relieved.

[0013] In a possible implementation, the conductive structure includes a through silicon via, the through silicon via is coupled to the first metal wiring, and the through silicon via is also coupled to the second metal wiring. In this way, the adapter board can be implemented in multiple ways.

[0014] In a possible implementation, the aspect ratio of the TSV is less than 5: 1. In this way, the aspect ratio of the TSV provided in the substrate can be reduced, thereby reducing the size of the TSV, reducing the size of the blocking area on the substrate, and thus improving the wiring density of the adapter board.

[0015] In a possible implementation, the substrate further includes a deep trench capacitor extending from the surface of the substrate into the substrate; the deep trench capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked in sequence; the first electrode layer and the second electrode layer are both coupled to the first metal wiring. In this way, the adapter board can be implemented in a variety of ways.

[0016] In a possible implementation, the adapter board further includes a metal pattern layer, and the metal pattern layer is located on a side of the first redistribution layer away from the substrate. In this way, the adapter board can be implemented in a variety of ways.

[0017] In a possible implementation, the metal pattern layer includes a first pad, and the first pad is located on a side of the first redistribution layer away from the substrate. In this way, the adapter board can be implemented in a variety of ways.

[0018] In a possible implementation, the first redistribution layer and the second redistribution layer are symmetrical about the center of the substrate, so that the stress on the substrate can be further alleviated.

[0019] The second aspect of the embodiment of the present application provides a method for preparing an adapter board, which is applied to chip packaging, and the method for preparing the adapter board includes: forming a first redistribution layer on one side of the substrate; the material of the substrate includes a semiconductor material; removing part of the substrate to form a substrate; forming a conductive structure in the substrate; forming a second redistribution layer on the side of the substrate away from the first redistribution layer; the second redistribution layer is coupled to the first redistribution layer through the conductive structure; the first redistribution layer includes a first metal wiring, and the second redistribution layer includes a second metal wiring; the thickness of the first metal wiring and / or the second metal wiring is greater than 1μm. At this time, the adapter board can withstand the additional stress pressure brought by the thicker first metal wiring or the second metal wiring, that is, the first metal wiring or the second metal wiring can have a larger thickness, thereby reducing the resistance of the first redistribution layer or the second redistribution layer and improving the transmission efficiency of the signal in the adapter board.

[0020] Furthermore, due to the additional stress-bearing capacity brought by the double-sided redistribution layer, the thickness of the substrate can also be made thinner, such as 20μm to 100μm, thereby reducing the thickness of the entire packaging structure and meeting the "thin" requirement for the chip.

[0021] The method for preparing the adapter board provided in the embodiment of the present application forms a first redistribution layer and a second redistribution layer on two opposite surfaces of the substrate, respectively. At this time, the stress of the first redistribution layer on the substrate and the stress of the second redistribution layer on the substrate can partially offset each other, the stress on the substrate is reduced, the degree of warping of the substrate can be alleviated, and the reliability of the adapter board is improved.

[0022] In addition, since the relative arrangement of the first redistribution layer and the second redistribution layer can alleviate the stress on the substrate, the first redistribution layer and the second redistribution layer can be arranged thicker to achieve a multi-layer stacking of thick metals, and multiple layers can be arranged to increase the wiring density of the adapter board, so that the resistance of the first redistribution layer and the second redistribution layer is lower, thereby increasing the signal transmission rate in the adapter board and improving the performance of the adapter board.

[0023] In a possible implementation, removing part of the substrate to form a substrate includes: forming a through silicon via in the substrate; thinning the substrate away from the surface of the first redistribution layer to form the substrate. In this way, the adapter board can be implemented in multiple ways.

[0024] In a possible implementation, forming the through silicon via includes: forming the through silicon via using a Damascus process, thereby saving processes and reducing costs.

[0025] In a possible implementation, before forming the first redistribution layer on one side of the substrate, the preparation method further includes: forming a deep trench capacitor in the substrate; the deep trench capacitor extends from the surface of the substrate to the inside of the substrate; the deep trench capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked in sequence. In this way, the adapter board can be implemented in multiple ways.

[0026] In a possible implementation, after forming the first redistribution layer on one side of the substrate and before forming the substrate, the preparation method further includes: forming a first pad on the side of the first redistribution layer away from the substrate; after forming the second redistribution layer on the side of the substrate away from the first redistribution layer, the preparation method further includes: forming a second pad on the side of the second redistribution layer away from the substrate. In this way, the adapter board can be implemented in multiple ways.

[0027] In a possible implementation, after forming the first redistribution layer on one side of the base and before forming the substrate, the preparation method further includes: forming a bonding layer on the side of the first redistribution layer away from the base; after forming the second redistribution layer on the side of the substrate away from the first redistribution layer, the preparation method further includes: removing the bonding layer. In this way, the transfer board is formed and the preparation of the transfer board is completed.

[0028] According to a third aspect of the embodiments of the present application, a chip packaging structure includes: a chip; an adapter board of the first aspect, disposed on the chip; and a packaging board, disposed on a side of the adapter board away from the chip.

[0029] The chip packaging structure provided in the third aspect of the embodiment of the present application includes the adapter board of the first aspect, and its beneficial effects are the same as those of the adapter board, which will not be repeated here.

[0030] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising the chip packaging structure according to the third aspect and a printed circuit board, wherein the chip packaging structure is coupled to the printed circuit board.

[0031] The electronic device provided in the fourth aspect of the embodiment of the present application includes the chip packaging structure of the third aspect, and its beneficial effects are the same as the beneficial effects of the chip packaging structure, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0033] Figure 2A A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0034] Figure 2B A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0035] Figure 3A A schematic diagram of the structure of an adapter board provided in an embodiment of the present application;

[0036] Figure 3B A schematic diagram of the structure of another adapter board provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of another adapter board provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a process for preparing a transfer plate provided in an embodiment of the present application;

[0039] Figure 6A-Figure 6O A schematic diagram of a process of preparing a transfer plate provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the structure of another adapter board provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of the structure of another adapter board provided in an embodiment of the present application.

[0042] Reference numerals

[0043] 1-electronic device; 2-display module; 3-middle frame; 4-housing; 5-cover plate; 10-adapter plate; 11-packaging plate; 12-chip; 100'-base; 111-first groove; 112-groove; 100-substrate; 130-conductive structure; 110-through silicon via; 120-deep trench capacitor; 121-first electrode layer; 122-capacitor dielectric layer; 123-second electrode layer; 200-rewiring layer; 210-first rewiring layer; 220-second rewiring layer; 300-dielectric layer; 310-first dielectric layer; 311'-first sub-dielectric film; 311-first sub-dielectric layer; 312'-second sub-dielectric film; 312-second sub-dielectric layer; 320-second dielectric layer; 330-third dielectric layer; 330'-third dielectric film; 331-first contact structure; 332-second contact structure; 301-first via; 302-second via; 303-third via; 304-fourth via; 400-metal wiring; 411-first metal wiring; 421-second metal wiring; 412-first via hole; 422-second via hole; 401-metal layer; 402-via hole; 500-metal pattern layer; 510-first pad; 511-third via hole; 520-second pad; 521-fourth via hole; 101-etching barrier layer; 102-bonding layer; 103-dielectric barrier layer. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0045] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0046] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0047] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0048] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0049] An electronic device is provided in an embodiment of the present application. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product or a financial terminal product. Among them, consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products are such as smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigators, vehicle-mounted DVDs, etc. Financial terminal products are such as ATM machines, self-service terminals, etc. The present application embodiment does not impose any special restrictions on the specific form of the above-mentioned electronic devices. For the convenience of explanation, the following embodiments are all illustrated by taking the electronic device as a mobile phone as an example.

[0050] An example of an electronic device structure is shown in FIG. Figure 1 As shown, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, rear housing) 4 and a cover plate 5.

[0051] The display module 2 has a light-emitting side from which a display image can be seen and a back side arranged opposite to the light-emitting side. The back side of the display module 2 is close to the middle frame 3 , and the cover plate 5 is arranged on the light-emitting side of the display module 2 .

[0052] The display module 2 includes a display panel (DP).

[0053] In a possible embodiment of the present application, the display module 2 is a liquid crystal display module. In this case, the display screen is a liquid crystal display (LCD). Based on this, the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display (away from the side of the LCD for displaying images).

[0054] The backlight module can provide light source to the liquid crystal display screen, so that each subpixel in the liquid crystal display screen can emit light to realize image display.

[0055] The backlight module can provide light (also called backlight) to the liquid crystal display screen, and each sub-pixel in the liquid crystal display screen can control the transmittance of light to realize image display.

[0056] Alternatively, in another possible embodiment of the present application, the display module 2 is an organic light emitting diode display module. In this case, the display screen is an organic light emitting diode (OLED) display screen. Since an electroluminescent layer is provided in each sub-pixel of the OLED display screen, the OLED display screen can be self-luminous after receiving the operating voltage. In this case, the display module 2 having the OLED display screen does not need to be provided with the backlight module.

[0057] The cover plate 5 is located at a side of the display module 2 away from the middle frame 3 . The cover plate 5 may be, for example, a cover glass (CG), and the cover glass may have a certain toughness.

[0058] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. After the housing 4 and the middle frame 3 are covered, the above internal components are located between the housing 4 and the middle frame 3.

[0059] The electronic device 1 also includes a processor (center processing unit, CPU) chip, a dynamic random access memory (dynamic random access memory, DRAM) chip, a radio frequency chip, a radio frequency power amplifier (power amplifier, PA) chip, a system on a chip (system on a chip, SOC), a power management chip (power management integrated circuits, PMIC), a storage chip (such as a high bandwidth memory (high bandwidth memory, HBM)), an audio processor chip, a touch screen control chip, a NAND flash (flash memory), an image sensor chip and other chip packaging structures arranged on the PCB. The PCB is used to carry the above-mentioned chip packaging structure and complete signal interaction with the above-mentioned chip packaging structure.

[0060] like Figure 2A As shown, the chip packaging structure is carried on a PCB. Generally, a chip 12 having a functional circuit is electrically connected to a packaging board 11, and then the packaging board 11 is electrically connected to the PCB.

[0061] The packaging board 11 is a carrier of the chip packaging structure, and serves as a connector between the chip 12 and the PCB, and is used to achieve connection between the chip 12 and the PCB.

[0062] External pins (solder balls or pads) are provided on the first and second surfaces of the package board 11. The external pins on one surface of the package board 11 are connected to the chip 12, and the external pins on the other surface are connected to the PCB.

[0063] Exemplarily, the external pins on the first surface of the package board 11 are connected to the chip 12 , and the external pins on the second surface of the package board 11 are connected to the PCB.

[0064] The chip 12 includes a chip, and can realize electrical connection between the chip and the packaging board 11. The chip 12 can be a bare chip, or a packaged chip. The embodiment of the present application does not limit this, and can be reasonably set according to actual conditions.

[0065] For example, at least one transistor is integrated on the chip 12 , and the transistor here may be, for example, a field effect transistor (FET).

[0066] It is explained here that the field effect transistor may include a planar transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a junction field effect transistor (JFET), and may also include a three-dimensional transistor such as a fin field effect transistor (FinFET), a gate all around field effect transistor (GAAFET), or a forksheet field effect transistor (forksheet FET or FSFET). The embodiments of the present application are not limited to this.

[0067] For example, taking the chip 12 as a bare chip (IC bare chip) as an example, a chip packaging technology is illustrated, the IC bare chip is placed on a packaging board 11, all the pins on the IC are connected to the external pins on the first surface of the packaging board 11 through the flip chip technology, and then the IC is made into a package body, and then connected to the PCB through the external pins on the package body (the external pins on the second surface of the packaging board 11). The IC is connected to the PCB and connected to other devices through the wires on the PCB, thereby realizing the connection between the internal chip and the external circuit.

[0068] With the development of semiconductor technology, the functions of electronic devices are also becoming more and more diversified and comprehensive. Chips used to realize different functions are integrated into electronic devices, and the demand for the integration of chip packaging structures on printed circuit boards in electronic devices is also increasing. While the performance of IC bare chips needs to be improved, the requirements for chip packaging structures are also getting higher and higher. On the one hand, the demand for heterogeneous integration and heterogeneous integration of chips with different processes, different functions or different materials is increasing. On the other hand, it also brings new challenges to the development of planar printed circuit boards, which tends to make the packaging of printed circuit boards develop from planar packaging to vertical stacking packaging, thereby realizing 3D IC packaging technology and 2.5D IC packaging technology. Exemplarily, chips with different functions such as micro-electromechanical system chips, radio frequency communication chips, passive device chips, and processor chips can be vertically stacked and integrated through the above-mentioned packaging technology, thereby maximizing the use of the integration space in the vertical direction to improve the integration of printed circuit boards.

[0069] In 3D or 2.5D packaging, an interposer (INTP) is used to realize the interconnection between chips and chips, and between chip 12 and packaging board 11, such as a through silicon via interposer 2.5D packaging (chip-on-wafer-on-substrate, CoWoS) structure. Chip 12 is connected to PCB through the interposer. As one of the important structures in chip packaging technology, the interposer has significant advantages in design and preparation.

[0070] like Figure 2B As shown, the interconnection between the chip 12 and the packaging board 11 is realized through the adapter board 10. The chip 12 disposed on the adapter board 10 may be one or more.

[0071] For example, a plurality of chips 12 may be arranged side by side on the transfer board 10 .

[0072] Alternatively, for example, a plurality of chips 12 may be stacked and then disposed on the transfer board 10 .

[0073] It is understandable that the above-mentioned multiple chips 12 may all be bare chips, or all be packaged chips, or some may be bare chips and some may be packaged chips.

[0074] In order to realize that multiple chips 12 are arranged on the adapter board 10, it is necessary to increase the number of metal layers of the adapter board 10. At the same time, in order to improve the transmission efficiency of the signal in the adapter board 10 and reduce the voltage drop, it is necessary to increase the metal thickness.

[0075] A transfer board 10 is shown as follows: Figure 3A As shown, the transfer board 10 includes a dielectric layer 300 and a metal wiring 400 located in the dielectric layer 300. The metal wiring 400 includes a plurality of metal layers 401 and a via 402 connecting the metal layers 401.

[0076] Figure 3A The illustrated metal wiring 400 includes four metal layers 401. For example, the thickness of the first metal layer 401a is 2.42 μm, the thickness of the second metal layer 401b is 1.54 μm, the thickness of the third metal layer 401c is 2.59 μm, and the thickness of the fourth metal layer 401d is 1.82 μm.

[0077] However, due to the limitation of the overall structure of the adapter plate 10, such as warping, the thickness of each metal layer 401 is different, for example, only the first metal layer 401a and the third metal layer 401c are thicker.

[0078] Based on this, a switching board 10 is also shown. Figure 3BAs shown, the adapter 10 includes a stacked substrate 100 and a redistribution layer (RDL) 200. The substrate 100 includes a through silicon via 110 and a deep trench capacitor 120. The redistribution layer 200 includes a dielectric layer 300 and a metal wiring 400 located in the dielectric layer 300, and the metal wiring 400 includes a plurality of metal layers 401 and a via 402 connecting the metal layers 401.

[0079] Figure 3B The transfer board shown includes five metal layers 401 , and each metal layer 401 is a thick metal layer.

[0080] because Figure 3B The substrate 100 of the adapter board 10 shown in the figure is relatively thick (greater than 110 μm), resulting in a larger size of the through silicon via 110 (greater than 15 μm), which increases the size of the blocking area on the substrate 100 and reduces the wiring density of the adapter board 10 .

[0081] Figure 3A and Figure 3B In the adapter board 10 shown in the figure, the signal transmission path in the adapter board 10 is long, and the adapter board 10 is subjected to concentrated stress, which is prone to warping, and it is difficult to achieve multi-layer stacking of thick metal layers.

[0082] In addition, since the metal layer is thick, the overall film stress of the adapter plate 10 is increased, increasing the risk of warping. In the process of preparing the adapter plate 10, an annealing process is required to reduce the concentrated stress in the adapter plate 10. The process is complex and uncontrollable, resulting in increased preparation costs.

[0083] Based on this, in order to realize multi-layer stacking of thick metal layers, the present application embodiment provides another adapter plate. Figure 4 As shown, the transfer board 10 includes a substrate 100, a conductive structure 130 disposed in the substrate 100, a first redistribution layer 210 disposed on the substrate 100, and a second redistribution layer 220 disposed on a side of the substrate 100 away from the first redistribution layer 210. The second redistribution layer 220 is coupled to the first redistribution layer 210 through the conductive structure 130.

[0084] In this way, the first redistribution layer 210 and the second redistribution layer 220 are respectively arranged on two opposite surfaces of the substrate 100, so that the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 can at least partially offset each other, the stress on the substrate 100 is reduced, the warping degree of the substrate 100 can be alleviated, and the reliability of the adapter board 10 is improved.

[0085] like Figure 5 As shown, an embodiment of the present application provides a method for preparing an adapter plate, comprising:

[0086] S1, such as Fig. 6A As shown, a substrate 100' is provided.

[0087] The material of the substrate 100 ′ may be, for example, inorganic non-metallic materials such as silicon, glass or ceramics. The material of the substrate 100 ′ may also include semiconductor materials.

[0088] In some embodiments, Figure 6B As shown, step S1 further includes: forming a conductive structure 130 in the substrate 100 ′. For example, the conductive structure 130 includes a through silicon via (TSV) 110 .

[0089] For the convenience of illustration, the embodiment of the present application is illustrated by forming a through silicon via 110 in a substrate 100 ′.

[0090] The method of forming the through silicon via 110 may include, for example, first opening a first groove 111 in the substrate 100 ′ by a photoforming process and an etching process, and then forming the through silicon via 110 in the first groove 111 by a metallization process (eg, chemical plating, electroplating, printing or sputtering).

[0091] The embodiment of the present application does not limit the number and positions of the through silicon vias 110, which can be reasonably set according to actual conditions.

[0092] It is understandable that, since the substrate 100' is relatively thick, after the through silicon via 110 is formed in the substrate 100' in step S1, the substrate 100' needs to be subjected to a back grinding process and a backside via reveal (BVR or BFR) process in subsequent steps to thin the substrate 100' and form the substrate 100.

[0093] It is explained here that in the preparation method of the embodiment of the present application, the process of preparing the silicon through via 110 in steps S11-S12 can be performed in step S1, or after the process of the first redistribution layer 210 is completed. The embodiment of the present application does not limit this, and it can be reasonably set according to the actual situation.

[0094] In other embodiments, Figure 6C As shown, step S1 further includes: forming a deep trench capacitor (DTC) 120 in the substrate 100 ′.

[0095] S11 ′, forming a groove 112 in the substrate 100 ′.

[0096] The groove 112 extends from the surface of the substrate 100 ′ into the substrate 100 ′.

[0097] S12 ′, forming a dielectric barrier layer 103 in the trench 112 .

[0098] The dielectric barrier layer 103 covers the bottom surface of the trench 112 and the sidewalls of the trench 112 , and the dielectric barrier layer 103 also covers the surface of the substrate 100 ′.

[0099] S13 ′, forming a first electrode layer 121 , a capacitor dielectric layer 122 and a second electrode layer 123 in sequence in the trench 112 .

[0100] The first electrode layer 121 , the capacitor dielectric layer 122 and the second electrode layer 123 constitute a deep trench capacitor 120 .

[0101] S14 ′, forming a first contact structure 331 and a second contact structure 332 .

[0102] The first contact structure 331 is coupled to the first electrode layer 121 , and the second contact structure 332 is coupled to the second electrode layer 123 .

[0103] For example, Fig.6D As shown, firstly, a third dielectric film 330' is formed on the surface of the substrate 100' and the deep trench capacitor 120, and then at least two vias 301 are opened on the third dielectric film 330' to form a third dielectric layer 330. The vias 301 expose the first electrode layer 121 and the second electrode layer 123. Afterwards, metal is filled in the vias 301 to form a first contact structure 331 and a second contact structure 332, so that the first contact structure 331 is coupled to the first electrode layer 121, and the second contact structure 332 is coupled to the second electrode layer 123.

[0104] It is explained here that in the preparation process of the adapter plate, only the through silicon via 110 can be formed in the substrate 100'. Alternatively, only the deep trench capacitor 120 can be formed in the substrate 100'. Alternatively, both the through silicon via 110 and the deep trench capacitor 120 can be formed in the substrate 100'. The embodiment of the present application does not limit this, and it can be reasonably set according to the actual situation.

[0105] S2. Form a first redistribution layer 210 on one side of the substrate 100 ′.

[0106] The method for forming the first redistribution layer 210 can be, for example, prepared by a damascene process, that is, a process of first etching out a region on a dielectric layer where a metal interconnection structure is to be formed, and then filling the region with metal material to realize multi-layer metal interconnection.

[0107] Exemplarily, the first redistribution layer 210 includes multiple layers of first dielectric layers, multiple layers of first metal wirings, and multiple layers of first vias.

[0108] The first dielectric layers are stacked, the first metal wiring and the first vias are located in the first dielectric layers, and the first metal wiring and the first vias are alternately arranged along the direction in which the first dielectric layers are stacked.

[0109] For ease of understanding, the following description is made illustratively by assuming that the first redistribution layer 210 includes a layer of first metal wiring 411 .

[0110] In some embodiments, the first redistribution layer 210 is formed using a single damascene process, that is, the first metal wiring and the first via are formed in different process steps.

[0111] Exemplarily, step S2 includes:

[0112] S21, such as Fig. 6E As shown, a first sub-dielectric film 311 ′ is formed on a substrate 100 ′.

[0113] The material of the first sub-dielectric film 311 ′ may include an extreme low-K material (ELK) or a low-K material.

[0114] Exemplarily, the material of the first sub-dielectric film 311' may include undoped silicon glass (USG) material, phosphor silicate glass (PSG) material, fluorinated silica glass (FSG) material, boron phosphor silicate glass (BPSG) material, carbon-containing silicon oxide (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC) or silicon nitride (SiN), etc., and may include silicon oxide (SiO2). It is explained here that the material of the first sub-dielectric film 311' may also be other silicon glass (*SG) materials, which is not limited in the embodiment of the present application, and can be reasonably set according to actual conditions.

[0115] In this way, since the dielectric constant of the above-mentioned material is relatively low, the dielectric constant between the first metal wirings 411 to be formed can be reduced, thereby reducing the parasitic capacitance between the first metal wirings 411 .

[0116] S22, such as Fig. 6E As shown, a second via hole 302 is opened on the first sub-dielectric film 311 ′.

[0117] For example, the second via hole 302 may be opened on the first sub-dielectric film 311 ′ by means of a photoforming process and an etching process.

[0118] like Fig. 6E As shown, the second via hole 302 is opened through the first sub-dielectric film 311 ′. The second via hole 302 is used to fill metal material to form the first metal wiring 411. The first sub-dielectric film 311 ′ in which the second via hole 302 is opened is referred to as the first sub-dielectric layer 311 here.

[0119] In this way, the second via hole 302 penetrates the first sub-dielectric layer 311 , so that the first metal wiring 411 formed subsequently penetrates the first sub-dielectric layer 311 , and the first conductive hole 412 is connected to the substrate 100 ′.

[0120] It is explained here that the embodiment of the present application does not limit the number of second via holes 302 opened on the first sub-dielectric film 311 ′, and can be reasonably set according to actual conditions. It only needs to ensure that at least one of the multiple second via holes 302 opens to expose any one of the through silicon via 110 , the first contact structure 331 or the second contact structure 332 .

[0121] In this way, at least one first metal wiring 411 is coupled to any one of the through silicon via 110 , the first contact structure 331 or the second contact structure 332 .

[0122] S23, such as Fig. 6E As shown, a first metal wiring 411 is formed in the second via hole 302 .

[0123] That is, the first metal wiring 411 is formed in the first sub-dielectric layer 311 , and the first metal wiring 411 penetrates the first sub-dielectric layer 311 .

[0124] S24, such as Fig. 6F As shown, a second sub-dielectric film 312 ′ is formed on a side of the first sub-dielectric layer 311 away from the substrate 100 ′.

[0125] That is to say, Fig. 6F As shown, the second sub-dielectric film 312 ′ is formed on the surface of the first sub-dielectric layer 311 away from the substrate 100 ′.

[0126] The materials of the second sub-dielectric film 312 ′ and the first sub-dielectric layer 311 may be the same or different.

[0127] S25, such as Fig. 6F As shown, a third via hole 303 is opened in the second sub-dielectric film 312'.

[0128] The third via hole 303 is formed through the second sub-dielectric film 312'. The second sub-dielectric film 312' is used to fill the metal material to form the first conductive hole 412. The second sub-dielectric film 312' with the third via hole 303 is referred to as the second sub-dielectric layer 312. At this time, the first sub-dielectric layer 311 and the second sub-dielectric layer 312 form the first dielectric layer 310.

[0129] In this way, the third via hole 303 penetrates the second sub-dielectric layer 312 , so that the first conductive hole 412 formed subsequently penetrates the second sub-dielectric layer 312 .

[0130] It is explained here that the third via hole 303 exposes at least one first metal wiring 411 so that the first conductive via 412 formed subsequently is coupled to the first metal wiring 411 .

[0131] S26, such as Fig. 6F As shown, a first conductive hole 412 is formed in the third via hole 303 .

[0132] That is, a first conductive via 412 is formed in the second sub-dielectric layer 312 , and the first conductive via 412 penetrates the second sub-dielectric layer 312 .

[0133] At this point, a layer of first metal wiring 411 and first via 412 is formed.

[0134] It is explained here that the embodiment of the present application does not limit the order of forming the first metal wiring 411 and the first via 412. The first metal wiring 411 can be formed first and then the first via 412, or the first via 412 can be formed first and then the first metal wiring 411. It can be reasonably set according to the actual situation.

[0135] In some other embodiments, the first redistribution layer 210 is formed by a dual damascene process, that is, the first metal wiring 411 and the first via 412 are formed in the same process step.

[0136] For example, Figure 6G As shown, step S2 includes:

[0137] S21 ′, sequentially forming a second sub-dielectric film 312 ′ and a first sub-dielectric film 311 ′ on the substrate 100 ′.

[0138] The method of forming the second sub-dielectric film 312 ′ and the first sub-dielectric film 311 ′ in step S21 ′ is the same as the method of forming the second sub-dielectric film 312 ′ and the first sub-dielectric film 311 ′ in the above steps.

[0139] S22 ′, opening a fourth via hole 304 on the first sub-dielectric film 311 ′ and the second sub-dielectric film 312 ′.

[0140] like Figure 6G As shown, a fourth via hole 304 is opened on the surface of the first sub-dielectric film 311 ′ away from the substrate 100 ′. The fourth via hole 304 penetrates the first sub-dielectric film 311 ′ and the second sub-dielectric film 312 ′.

[0141] S23 ′, etching the sidewall of the fourth via hole 304 located on the first sub-dielectric film 311 ′ to form a fifth via hole 305 .

[0142] like Figure 6G As shown, only the sidewall of the fourth via hole 304 located at the first sub-dielectric film 311 ′ is etched to form a fifth via hole 305 . The fifth via hole 305 is used to form the first metal wiring 411 later.

[0143] S24 ′, forming a first conductive hole 412 in the fourth via hole 304 , and forming a first metal wiring 411 in the fifth via hole 305 .

[0144] It is explained here that the first via 412 and the first metal wiring 411 can be formed in the same manufacturing process, or the first via 412 can be formed first and then the first metal wiring 411. The first via 412 is coupled to the first metal wiring 411.

[0145] In some other embodiments, the first redistribution layer 210 is formed by a dual damascene process. In step S22', a fifth via hole 305 penetrating the second sub-dielectric film 312' may be firstly formed on the second sub-dielectric film 312', and then a fourth via hole 304 may be formed at the bottom of the fifth via hole 305, and the fourth via hole 304 penetrating the first sub-dielectric film 311'.

[0146] In some other embodiments, the second sub-dielectric film 312' is first formed, and after a via hole to be formed into the first via hole 412 is opened on the second sub-dielectric film 312', the first via hole 412 and the first metal wiring 411 are formed. The first via hole 412 is located in the via hole, and the first metal wiring 411 is located on the second sub-dielectric layer 312. Afterwards, the first sub-dielectric layer 311 covering the second sub-dielectric layer 312 and the first metal wiring 411 is formed.

[0147] In the embodiment of the present application, the first metal wiring 411 and the first via 412 are located in the first dielectric layer 310. The first metal wiring 411 and the first via 412 may be located in the same layer of the first dielectric layer 310. Alternatively, the first metal wiring 411 and the first via 412 may also be located in different layers of the first dielectric layer 310.

[0148] The first metal wiring 411 and the first via 412 may be an integrated structure or may be separately prepared structures. This embodiment of the present application does not limit this, and may be reasonably configured according to actual conditions.

[0149] For example, Figure 6H As shown, before forming the first sub-dielectric film 311 ′ and the second sub-dielectric film 312 ′, the preparation method further includes: forming an etching stop layer 101 .

[0150] The etching stop layer 101 is used to prevent over-etching when etching the surface of the dielectric layer, and can be reasonably set according to actual needs. This embodiment of the present application does not limit this. For ease of understanding, the following figures do not illustrate the etching stop layer 101.

[0151] It is explained here that when it is necessary to prepare multiple layers of first metal wiring 411 and multiple layers of first vias 412, the preparation method is the same as the preparation method of preparing one layer of first metal wiring 411 and one layer of first vias 412, and only step S2 needs to be repeated.

[0152] In the embodiment of the present application, the number of layers of the first metal wiring 411 in the first redistribution layer 210 is not limited.

[0153] Exemplarily, the number of layers of the first metal wiring 411 is greater than or equal to 4. For example, the number of layers of the first metal wiring 411 may be 4, 6 or 7, etc. The following is an illustration of forming 4 layers of the first metal wiring 411 on the substrate 100'.

[0154] S3, such as Fig.6I As shown, a first pad 510 is formed on a side of the first redistribution layer 210 away from the substrate 100 ′.

[0155] The method of forming the first pad 510 is similar to the method of forming the first metal wiring 411 and the first via 412. The specific method can refer to the method of forming the first metal wiring 411 and the first via 412 in step S2, which will not be repeated here.

[0156] For example, Fig.6I As shown, the first pad 510 is coupled to the first redistribution layer 210. For example, the first pad 510 is coupled to a portion of the first metal wiring 411 in the first redistribution layer 210 through a third top via (TV) 511.

[0157] S4, such as Figure 6J As shown, a bonding layer 102 is formed on a side of the first redistribution layer 210 away from the substrate 100 ′.

[0158] That is, the bonding layer 102 is disposed on a side of the first redistribution layer 210 away from the substrate 100 ′. For example, the bonding layer 102 is disposed on a surface of the first redistribution layer 210 away from the substrate 100 ′.

[0159] The bonding layer 102 can be used for fixing. In this way, the structure formed in steps S1 to S3 can be turned over and fixed.

[0160] S5, such as Figure 6K As shown, a portion of the base 100 ′ is removed to form the substrate 100 .

[0161] The substrate 100 ′ is etched away from the surface of the first redistribution layer 210 to thin the substrate 100 ′.

[0162] In some embodiments, a through silicon via 110 is formed in the substrate 100 ′.

[0163] Exemplarily, a wet etching process or a dry etching process is used to thin the surface of the substrate 100 ′ away from the first redistribution layer 210 . Then, a chemical mechanical planarization (CMP) process is used to planarize the surface of the substrate 100 ′ away from the first redistribution layer 210 to form the substrate 100 .

[0164] The thickness of the substrate 100 ranges from 20 μm to 100 μm. For example, the thickness of the substrate 100 is 25 μm, 43 μm, 78 μm, 86 μm, or 95 μm.

[0165] It is explained here that in step S1 , a deep trench capacitor 120 is formed in the substrate 100 ′, and in step S5 , the substrate 100 ′ is thinned to leave at least a portion of the material of the substrate 100 ′ covering the surface of the deep trench capacitor 120 away from the first redistribution layer 210 .

[0166] That is, when the substrate 100 ′ is thinned, the deep trench capacitor 120 is not exposed.

[0167] In some other embodiments, the step S1 does not form the through silicon via 110. Figure 6L As shown, step S5 includes:

[0168] S51 , thinning the surface of the substrate 100 ′ away from the first redistribution layer 210 .

[0169] At this time, the thickness of the substrate 100 ′ after thinning ranges from 20 μm to 100 μm. For example, the thickness of the substrate 100 ′ after thinning ranges from 25 μm, 43 μm, 78 μm, 86 μm, or 95 μm.

[0170] S52 , forming a through silicon via 110 in the base 100 ′ to form the substrate 100 .

[0171] At this time, since the substrate 100 ′ is thin after thinning, the through silicon via 110 can be formed by using a damascene process.

[0172] That is to say, firstly, a first groove 111 is formed on the surface of the substrate 100 ′, wherein the first groove 111 penetrates the substrate 100 ′.

[0173] Then, a through silicon via 110 is formed in the first groove 111. Figure 6L As shown, the through silicon via 110 penetrates through the substrate 100 .

[0174] Finally, the surface of the substrate 100 is planarized by a CMP process.

[0175] That is, at this time, the through silicon via 110 is fabricated by a via last process.

[0176] It is explained here that in step S5 , the through silicon via 110 may be first formed in the substrate 100 ′, and then the surface of the substrate 100 ′ away from the first redistribution layer 210 may be thinned to form the substrate 100 .

[0177] In the embodiment of the present application, forming the through silicon via 110 using the Damascus process can reduce the manufacturing cost.

[0178] In addition, the substrate 100' is thinned first and then the through silicon vias 110 are formed. In this way, the through silicon vias 110 are formed on the thinner substrate 100', and the size of the through silicon vias 110 can be smaller in the direction perpendicular to the thickness direction of the substrate 100, thereby reducing the size of the keep out zone (KOZ) on the substrate 100, and at the same time, the distribution density of the through silicon vias 110 can be increased, and the number of devices set on the substrate 100 can be increased, thereby increasing the wiring density of the adapter board 10.

[0179] S6, such as Figure 6M As shown, a second redistribution layer 220 is formed on a side of the substrate 100 away from the first redistribution layer 210 .

[0180] The method of forming the second redistribution layer 220 is similar to the method of forming the first redistribution layer 210 to achieve multi-layer metal interconnection within the second redistribution layer 220. For details, please refer to the relevant description on forming the first redistribution layer 210 in step S2, which will not be repeated here.

[0181] Exemplarily, the second redistribution layer 220 includes a plurality of second dielectric layers 320 , a plurality of second metal wirings 421 , and a plurality of second vias 422 .

[0182] The second dielectric layers 320 are stacked, and the second metal wirings 421 and the second vias 422 are located in the second dielectric layers 320. Along the stacking direction of the second dielectric layers 320, the second metal wirings 421 and the second vias 422 are alternately arranged.

[0183] Exemplarily, the number of layers of the second metal wiring 421 may be the same as the number of layers of the first metal wiring 411 .

[0184] For example, the number of layers of the second metal wiring 421 and the number of layers of the first metal wiring 411 are both four.

[0185] Alternatively, illustratively, the number of layers of the second metal wiring 421 may be greater than the number of layers of the first metal wiring 411. Alternatively, the number of layers of the second metal wiring 421 may be less than the number of layers of the first metal wiring 411. The present application embodiment does not limit this, and it can be reasonably set according to actual conditions.

[0186] In addition, in the embodiment of the present application, the distribution of the second metal wiring 421 in the second redistribution layer 220 may be the same as or different from the distribution of the first metal wiring 411 in the first redistribution layer 210 .

[0187] Exemplarily, the second redistribution layer 220 and the first redistribution layer 210 are symmetrical about the center of the substrate 100. For example, the second metal wiring 421 in the second redistribution layer 220 and the first metal wiring 411 in the first redistribution layer 210 are symmetrical about the center of the substrate 100.

[0188] In this way, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 offset each other, which can relieve the stress on the substrate 100 and the warping of the substrate 100 and the adapter board 10, thereby improving the reliability of the adapter board 10.

[0189] In addition, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 offset each other, which can relieve the stress on the substrate 100, and thus can realize the provision of multiple metal layers (for example, the first metal wiring 411 or the second metal wiring 421) on the substrate 100, and realize a thicker metal layer (ultra thick top metal, UTM). In other words, the preparation method of the adapter board 10 of the embodiment of the present application can realize the multi-layer stacking of thick metal layers and improve the wiring density of the adapter board 10.

[0190] The second redistribution layer 220 may be coupled to the first redistribution layer 210 through the substrate 100 .

[0191] That is, the second metal wiring 421 may be coupled to the first metal wiring 411 through the substrate 100. For example, the second metal wiring 421 is coupled to the first metal wiring 411 through the through silicon via 110 of the substrate 100.

[0192] S7, such as Figure 6N As shown, a second pad 520 is formed on a side of the second redistribution layer 220 away from the substrate 100 .

[0193] The method of forming the second pad 520 is similar to the method of forming the first pad 510 . For details, please refer to the relevant description of forming the first pad 510 in step S3 , which will not be repeated here.

[0194] For example, Figure 6N As shown, the second pad 520 is coupled to the second redistribution layer 220. For example, the second pad 520 is coupled to a portion of the second metal wiring 421 in the second redistribution layer 220 through the fourth via 521.

[0195] S8, such as Fig.6O As shown, the bonding layer 102 is removed.

[0196] Finally, the bonding layer 102 is removed, and the preparation of the transfer board 10 is completed.

[0197] The above preparation method provided in the embodiments of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0198] In addition, the above steps S1-S8 may remove some of the steps as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to only including the above steps.

[0199] The method for preparing the adapter board provided in the embodiment of the present application forms a first redistribution layer 210 and a second redistribution layer 220 on two opposite surfaces of the substrate 100, respectively. At this time, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 can partially offset each other, and the stress on the substrate 100 is reduced, which can alleviate the warping degree of the substrate 100, thereby improving the reliability of the adapter board 10.

[0200] In addition, since the relative arrangement of the first redistribution layer 210 and the second redistribution layer 220 can relieve the stress on the substrate 100, the adapter board 10 can withstand the additional stress pressure brought by the thicker first metal wiring 411 and the second metal wiring 421. In other words, the first metal wiring 411 and the second metal wiring 421 can have a greater thickness, thereby reducing the resistance of the first redistribution layer 210 and the second redistribution layer 220, improving the transmission efficiency of the signal in the adapter board 10, and improving the performance of the adapter board 10.

[0201] In addition, since the relative arrangement of the first redistribution layer 210 and the second redistribution layer 220 can relieve the stress on the substrate 100, multi-layer first metal wiring 411 and multi-layer second metal wiring 421 can be arranged to achieve multi-layer stacking of thick metal, thereby improving the wiring density of the adapter board 10.

[0202] Furthermore, due to the additional stress bearing capacity brought by the double-sided redistribution layer, the thickness of the substrate 100 can also be made thinner, such as 20 μm to 100 μm, thereby reducing the thickness of the entire packaging structure and meeting the "thin" requirement for the chip.

[0203] The following examples illustrate the adapter plate structure provided in the embodiments of the present application. The adapter plate can be prepared by using the above-mentioned adapter plate preparation method.

[0204] Based on this, Figure 7 As shown, the adapter board 10 mainly includes a substrate 100, a conductive structure 130 disposed in the substrate 100, a first redistribution layer 210 disposed on the substrate 100, and a second redistribution layer 220 disposed on a side of the substrate 100 away from the first redistribution layer 210. The second redistribution layer 220 is coupled to the first redistribution layer 210 through the conductive structure 130.

[0205] like Figure 7 As shown, illustratively, the first redistribution layer 210 includes a first dielectric layer 310 , a first metal wiring 411 , and a first via 412 .

[0206] The material of the first metal wiring 411 may include, for example, copper (Cu).

[0207] Exemplarily, the first metal wiring 411 is multi-layered, and the first via 412 is used to connect the first metal wiring 411 of two adjacent layers.

[0208] That is, the first redistribution layer 210 includes a plurality of first dielectric layers 310 , a plurality of first metal wirings 411 , and a plurality of first vias 412 .

[0209] The first dielectric layers 310 are stacked, and the first metal wirings 411 and the first vias 412 are located in the first dielectric layers 310. Along the direction y in which the first dielectric layers 310 are stacked, the first metal wirings 411 and the first vias 412 are alternately arranged.

[0210] It is explained here that the first vias 412 are connected to at least part of the first metal wirings 411, but it is not limited to that the first vias 412 are connected to all the first metal wirings 411. It can be reasonably set according to the actual situation, and the embodiment of the present application does not limit this.

[0211] In the embodiment of the present application, the first metal wiring 411 and the first via 412 are located in the first dielectric layer 310. The first metal wiring 411 and the first via 412 may be located in the same layer of the first dielectric layer 310. Alternatively, the first metal wiring 411 and the first via 412 may also be located in different layers of the first dielectric layer 310.

[0212] The first metal wiring 411 and the first via 412 may be an integrated structure or may be separately prepared structures. This embodiment of the present application does not limit this, and may be reasonably configured according to actual conditions.

[0213] In some embodiments, the number of layers of the first metal wiring 411 is greater than 4. For example, the first metal wiring 411 has 5 layers, 6 layers, or 7 layers.

[0214] In this way, a greater number of chips 12 can be disposed on the adapter board 10 .

[0215] Exemplarily, along the thickness direction y of the adapter board 10, the size d1 of each layer of the first metal wiring 411 is greater than 1 μm. In other words, the thickness d1 of each layer of the first metal wiring 411 is greater than 1 μm. For example, the thickness d1 of the first metal wiring 411 may be 1.5 μm, 2.3 μm, 4.2 μm, or 5.1 μm.

[0216] It is explained here that the thickness direction y of the adapter board 10 is the direction in which the first metal wirings 411 and the first vias 412 are alternately arranged. The thickness d1 of the first metal wirings 411 is the dimension of the first metal wirings 411 in the thickness direction y of the adapter board 10 .

[0217] In this way, the first metal wiring 411 included in the first redistribution layer 210 of the adapter board 10 is relatively thick, so that the resistance of the first metal wiring 411 is relatively low, the rate of the signal during transmission is accelerated, and the performance of the adapter board 10 is improved. In other words, the adapter board 10 provided in the embodiment of the present application can be provided with multiple thick metal layers (for example, the first metal wiring 411 or the second metal wiring 421) on the substrate 100 to achieve multi-layer stacking of thick metal layers.

[0218] In some embodiments, Figure 7 As shown, the second redistribution layer 220 is disposed on a side of the substrate 100 away from the first redistribution layer 210 .

[0219] That is, the first redistribution layer 210 and the second redistribution layer 220 are respectively disposed on two opposite surfaces of the substrate 100. That is, the first redistribution layer 210 and the second redistribution layer 220 are disposed opposite to each other, and the first redistribution layer 210 and the second redistribution layer 220 are respectively disposed on opposite sides of the substrate 100.

[0220] Continue to refer Figure 7 The second redistribution layer 220 includes a second metal wiring 421 and a second dielectric layer 320 . The second metal wiring 421 is disposed in the second dielectric layer 320 .

[0221] The material of the second metal wiring 421 may include copper (Cu), for example.

[0222] For example, Figure 7 As shown, the second redistribution layer 220 includes a plurality of second dielectric layers 320 , a plurality of second metal wirings 421 , and a plurality of second vias 422 .

[0223] The second dielectric layers 320 are stacked, and the second metal wirings 421 and the second vias 422 are located in the second dielectric layers 320. Along the direction y in which the second dielectric layers 320 are stacked, the second metal wirings 421 and the second vias 422 are alternately arranged.

[0224] Exemplarily, the number of layers of the second metal wiring 421 is greater than 4. For example, the second metal wiring 421 has 5 layers, 6 layers, or 7 layers.

[0225] In this way, a greater number of chips 12 can be disposed on the adapter board 10 .

[0226] The number of layers of the first metal wiring 411 and the number of layers of the second metal wiring 421 may be the same, for example. Alternatively, the number of layers of the first metal wiring 411 and the number of layers of the second metal wiring 421 may be different. This embodiment of the present application does not limit this, and it can be reasonably set according to actual conditions.

[0227] Exemplarily, the thickness of the second metal wiring 421 is greater than 1 μm. For example, the thickness of the second metal wiring 421 may be 1.5 μm, 2.3 μm, 4.2 μm, or 5.1 μm.

[0228] In this way, the second metal wiring 421 included in the second redistribution layer 220 of the adapter board 10 is thicker, so that the resistance of the second metal wiring 421 is lower, the rate of the signal during transmission is accelerated, and the performance of the adapter board 10 is improved.

[0229] In some embodiments, the first redistribution layer 210 and the second redistribution layer 220 are symmetrical with respect to the center of the substrate 100 .

[0230] It can be understood that the distribution of the first metal wiring 411 in the first redistribution layer 210 is the same as the distribution of the second metal wiring 421 in the second redistribution layer 220. For example, the wiring density of the first metal wiring 411 is the same as the wiring density of the second metal wiring 421, the number of layers of the first metal wiring 411 is the same as the number of layers of the second metal wiring 421, and the thickness of the first metal wiring 411 is the same as the thickness of the second metal wiring 421.

[0231] In this way, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 offset each other, which can relieve the stress on the substrate 100, relieve the warping of the substrate 100 and the adapter board 10, and thus improve the reliability of the adapter board 10. In addition, the first redistribution layer 210 and the second redistribution layer 220 are arranged on opposite sides of the substrate 100, which can relieve the stress on the substrate 100, and thus realize the arrangement of multiple thick metal layers (for example, the first metal wiring 411 or the second metal wiring 421) on the substrate 100, realize the multi-layer stacking of thick metal layers, and improve the wiring density of the adapter board 10.

[0232] In some embodiments, Figure 7 As shown, the adapter board 10 may further include a metal pattern layer 500 .

[0233] The metal pattern layer 500 is located on a side of the first redistribution layer 210 away from the substrate 100. Alternatively, the metal pattern layer 500 is located on a side of the second redistribution layer 220 away from the substrate 100.

[0234] Exemplarily, the metal pattern layer 500 includes a first pad 510 .

[0235] That is, the first pad 510 is located on a side of the first redistribution layer 210 away from the substrate 100 .

[0236] For example, the first pad 510 is coupled to the first redistribution layer 210 through the third via 511 .

[0237] The material of the first pad 510 may include, for example, aluminum (Al).

[0238] Or, for example, Figure 7 As shown, the metal pattern layer 500 may further include a second pad 520 .

[0239] The second pad 520 is located on a side of the second redistribution layer 220 away from the substrate 100 .

[0240] For example, the second pad 520 is coupled to the second redistribution layer 220 through the fourth via 521 .

[0241] The material of the second pad 520 may include, for example, aluminum (Al).

[0242] Regarding the substrate 100 , the material of the substrate 100 may include, for example, inorganic non-metallic materials such as silicon, glass, or ceramics. The material of the substrate 100 may also include semiconductor materials.

[0243] The embodiment of the present application does not limit the material of the interconnect transfer layer 123 , and it may be, for example, an inorganic non-metallic material.

[0244] In some embodiments, Figure 7 As shown, the conductive structure 130 of the substrate 100 may include a through silicon via 110 .

[0245] Exemplarily, the material of the substrate 100 may be silicon, for example, and the chip packaging structure packaged with the adapter board 10 may be understood as a through silicon via interposer 2.5D packaging (chip-on-wafer-on-substrate, CoWoS) structure.

[0246] Alternatively, illustratively, the material of the substrate 100 may be glass, for example, and the chip packaging structure packaged with the adapter board 10 may be understood as a through-glass interposer 2.5D packaging (chip on glass-on-substrate, CoGoS) structure.

[0247] Alternatively, illustratively, the substrate 100 may be ceramic, for example, and the chip packaging structure formed by packaging the substrate 10 with the adapter board 10 may be understood as a ceramic through-hole interposer 2.5D packaging (chip on ceramics-on-substrate, CoCoS) structure.

[0248] The through silicon via 110 penetrates the substrate 100 . The through silicon via 110 is coupled to at least a portion of the first metal wiring 411 , and the through silicon via 110 is also coupled to at least a portion of the second metal wiring 421 .

[0249] Alternatively, the conductive structure 130 may also include a copper column or other conductive structures, which are not limited in the embodiments of the present application and can be reasonably configured according to actual conditions.

[0250] In the adapter board 10 provided in the embodiment of the present application, since the first redistribution layer 210 and the second redistribution layer 220 are respectively arranged on opposite sides of the substrate 100, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 can be partially offset, thereby alleviating the stress on the substrate 100 and reducing the thickness of the substrate 100.

[0251] Exemplarily, the thickness d2 of the substrate 100 is 20 μm to 100 μm. For example, the thickness of the substrate 100 is 25 μm, 43 μm, 78 μm, 86 μm, or 95 μm.

[0252] Since the thickness of the substrate 100 is relatively small, the aspect ratio of the through silicon via 110 can be reduced, the size of the through silicon via 110 can be reduced, and the size of the blocking area on the substrate 100 can be reduced. At the same time, the distribution density of the through silicon via 110 can be increased, and the number of devices set on the substrate 100 can be increased, thereby improving the wiring density of the adapter board 10.

[0253] Along a direction x perpendicular to the thickness direction y of the substrate 100 , the size of the through silicon via 110 may be less than 4 μm, for example, the size of the through silicon via 110 is 3.7 μm, 3.2 μm, 2.8 μm, 2.1 μm or 1.5 μm.

[0254] In this way, the aspect ratio of the TSV 110 is less than 5:1.

[0255] In other embodiments, Figure 8 As shown, the substrate 100 further includes a deep trench capacitor 120 .

[0256] Among them, Figure 8 As shown, the deep trench capacitor 120 includes a first electrode layer 121 , a capacitor dielectric layer 122 and a second electrode layer 123 . The capacitor dielectric layer 122 is located between the first electrode layer 121 and the second electrode layer 123 .

[0257] For example, Figure 8 As shown, the transfer board 10 further includes a third dielectric layer 330 and a first contact structure 331 and a second contact structure 332 located in the third dielectric layer 330 .

[0258] The first contact structure 331 is used to realize coupling between the first electrode layer 121 and the metal wiring, and the second contact structure 332 is used to realize coupling between the capacitor dielectric layer 122 and the metal wiring.

[0259] Exemplarily, the first contact structure 331 is used to achieve coupling between the first electrode layer 121 and the first metal wiring 411 , and the second contact structure 332 is used to achieve coupling between the capacitor dielectric layer 122 and the first metal wiring 411 .

[0260] Then, the third dielectric layer 330 is located between the substrate 100 and the first redistribution layer 210 .

[0261] Alternatively, illustratively, the first contact structure 331 is used to achieve coupling between the first electrode layer 121 and the second metal wiring 421 , and the second contact structure 332 is used to achieve coupling between the capacitor dielectric layer 122 and the second metal wiring 421 .

[0262] Then, the third dielectric layer 330 is located between the substrate 100 and the second redistribution layer 220 .

[0263] It is explained here that the substrate may include at least one of the through silicon via 110 or the deep trench capacitor 120. The substrate 100 may include only the through silicon via 110. Alternatively, the substrate 100 may also include only the deep trench capacitor 120. Alternatively, the substrate 100 may also include both the through silicon via 110 and the deep trench capacitor 120. The embodiment of the present application does not limit this, and it can be reasonably set according to the actual situation.

[0264] The substrate 100 provided in the embodiment of the present application may also include other active devices or passive devices.

[0265] The active devices disposed in the substrate 100 may include electronic components such as transistors, electron tubes, and integrated circuits, for example. Alternatively, the passive devices disposed in the substrate 100 may include electronic components such as resistors, capacitors, or inductors, for example.

[0266] The embodiments of the present application do not limit this, and can be reasonably set according to actual conditions.

[0267] The adapter board 10 provided in the embodiment of the present application includes a first redistribution layer 210, a substrate 100 and a second redistribution layer 220 which are stacked in sequence. The first redistribution layer 210 includes a first dielectric layer 310 and a first metal wiring 411 located in the first dielectric layer 310, and the second redistribution layer 220 includes a second dielectric layer 320 and a second metal wiring 421 located in the second dielectric layer 320. The second redistribution layer 220 is coupled to the first redistribution layer 210 through the substrate 100. In the solution provided in the embodiment of the present application, the first redistribution layer 210 and the second redistribution layer 220 are respectively arranged on two opposite surfaces of the substrate 100, that is, the first redistribution layer 210 and the second redistribution layer 220 are arranged opposite to each other. At this time, the stress of the first redistribution layer 210 on the substrate 100 and the stress of the second redistribution layer 220 on the substrate 100 can partially offset each other, the stress on the substrate 100 is reduced, and the warping degree of the substrate 100 can be alleviated, thereby improving the reliability of the adapter board 10.

[0268] In addition, since the relative arrangement of the first redistribution layer 210 and the second redistribution layer 220 can relieve the stress on the substrate 100, the adapter board 10 can withstand the additional stress pressure brought by the thicker first metal wiring 411 and the second metal wiring 421. In other words, the first metal wiring 411 and the second metal wiring 421 can have a greater thickness, thereby reducing the resistance of the first redistribution layer 210 and the second redistribution layer 220, improving the transmission efficiency of the signal in the adapter board 10, and improving the performance of the adapter board 10.

[0269] In addition, since the relative arrangement of the first redistribution layer 210 and the second redistribution layer 220 can relieve the stress on the substrate 100, multi-layer first metal wiring 411 and multi-layer second metal wiring 421 can be arranged to achieve multi-layer stacking of thick metal, thereby improving the wiring density of the adapter board 10.

[0270] Furthermore, due to the additional stress bearing capacity brought by the double-sided redistribution layer, the thickness of the substrate 100 can also be made thinner, such as 20 μm to 100 μm, thereby reducing the thickness of the entire packaging structure and meeting the "thin" requirement for the chip.

[0271] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transfer plate, characterized in that: Applied to chip packaging, including: A substrate, wherein the material of the substrate comprises a semiconductor material; A conductive structure is disposed in the substrate; A first redistribution layer is disposed on the substrate; the first redistribution layer includes a first metal wiring; The second redistribution layer is arranged on the side of the substrate away from the first redistribution layer; the second redistribution layer is coupled to the first redistribution layer through the conductive structure; the second redistribution layer includes a second metal wiring, and the thickness of the first metal wiring and / or the second metal wiring is greater than 1μm.

2. The adapter plate according to claim 1, characterized in that: The thickness of the substrate is 20 μm to 100 μm.

3. The adapter plate according to claim 1 or 2, characterized in that: The first redistribution layer includes multiple layers of the first metal wiring, multiple layers of the first conductive vias and multiple layers of the first dielectric layer; the multiple layers of the first dielectric layer are stacked, and the first metal wiring and the first conductive vias are located in the first dielectric layer; along the direction in which the multiple layers of the first dielectric layer are stacked, the first metal wiring and the first conductive vias are alternately arranged; the number of layers of the first metal wiring is greater than 4.

4. The adapter plate according to claim 3, characterized in that: The second redistribution layer includes multiple layers of the second metal wiring, multiple layers of second conductive vias, and multiple layers of second dielectric layers; the multiple layers of second dielectric layers are stacked, and the second metal wiring and the second conductive vias are located in the second dielectric layer; along the direction in which the multiple layers of second dielectric layers are stacked, the second metal wiring and the second conductive vias are alternately arranged; the number of layers of the first metal wiring is the same as the number of layers of the second metal wiring.

5. The adapter plate according to any one of claims 1 to 4, characterized in that: The conductive structure includes a through silicon via (TSV); the TSV passes through the substrate, is coupled to the first metal wiring, and is also coupled to the second metal wiring.

6. The adapter plate according to claim 5, characterized in that: The aspect ratio of the through silicon via is less than 5:

1.

7. The adapter plate according to any one of claims 1 to 6, characterized in that: The substrate also includes a deep trench capacitor; the deep trench capacitor extends from the surface of the substrate into the substrate; the deep trench capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence; the first electrode layer and the second electrode layer are both coupled to the first metal wiring.

8. The adapter plate according to any one of claims 1 to 7, characterized in that: The adapter board further includes a metal pattern layer, and the metal pattern layer is located on a side of the first redistribution layer away from the substrate.

9. The adapter plate according to claim 8, characterized in that: The metal pattern layer includes a first pad, and the first pad is located on a side of the first redistribution layer away from the substrate.

10. The adapter plate according to any one of claims 1 to 9, characterized in that: The first redistribution layer and the second redistribution layer are symmetrical about the center of the substrate.

11. A method for preparing an adapter plate, characterized in that: The adapter plate is applied to chip packaging, and the preparation method of the adapter plate includes: Forming a first redistribution layer on one side of a substrate; the material of the substrate comprises a semiconductor material; Removing part of the base to form a substrate; a conductive structure is formed in the substrate; A second redistribution layer is formed on a side of the substrate away from the first redistribution layer; the second redistribution layer is coupled to the first redistribution layer through the conductive structure; the first redistribution layer includes a first metal wiring, and the second redistribution layer includes a second metal wiring; the thickness of the first metal wiring and / or the second metal wiring is greater than 1μm.

12. The method for preparing the adapter plate according to claim 11, characterized in that: Removing part of the base to form a substrate, comprising: forming a through silicon via in the substrate; The surface of the base away from the first redistribution layer is thinned to form a substrate.

13. The method for preparing the adapter plate according to claim 12, characterized in that: The step of forming the through silicon via comprises: forming the through silicon via by using a Damascene process.

14. The method for preparing the adapter plate according to any one of claims 11 to 13, characterized in that: Before forming the first redistribution layer on one side of the substrate, the preparation method further comprises: A deep trench capacitor is formed in the substrate; the deep trench capacitor extends from the surface of the substrate into the substrate; the deep trench capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer which are stacked in sequence.

15. The method for preparing the adapter plate according to any one of claims 11 to 14, characterized in that: After forming the first redistribution layer on one side of the base and before forming the substrate, the preparation method further comprises: forming a first pad on a side of the first redistribution layer away from the substrate; After forming a second redistribution layer on a side of the substrate away from the first redistribution layer, the preparation method further comprises: A second pad is formed on a side of the second redistribution layer away from the substrate.

16. The method for preparing the adapter plate according to any one of claims 11 to 15, characterized in that: After forming the first redistribution layer on one side of the base and before forming the substrate, the preparation method further comprises: forming a bonding layer on a side of the first redistribution layer away from the substrate; After forming a second redistribution layer on a side of the substrate away from the first redistribution layer, the preparation method further comprises: The bonding layer is removed.

17. A chip packaging structure, characterized in that: include: chip; The adapter board according to any one of claims 1 to 10, arranged on the chip; The packaging board is arranged on a side of the adapter board away from the chip.

18. An electronic device, characterized in that: The invention comprises the chip packaging structure and a printed circuit board as claimed in claim 17, wherein the chip packaging structure is coupled to the printed circuit board.

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