A DC capture and DC elimination circuit, high-pass filter and chip
By designing DC capture and DC cancellation circuits, using adders, delay modules and multipliers, combined with error processing modules, the problem of inaccurate DC offset capture in the prior art is solved, and more efficient DC cancellation and accuracy are achieved .
Patent Information
- Application Number
- CN202111255798.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-10-27
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2041-10-27
AI Technical Summary
The existing DC elimination filters have a large range of variation when capturing DC offsets, resulting in offsets during the cutoff process, reducing the accuracy of DC elimination.
A DC capture and DC cancellation circuit including a first adder, a second adder, a first delay module and a first multiplier is designed. By adjusting factors α and β, the error processing module is used to reduce the cutoff error and improve the DC. Capture accuracy.
Effectively capture and eliminate DC offset, reduce offsets generated during the cutoff process, improve the accuracy of DC elimination and circuit performance, and reduce DC residue.
Smart Images
Figure CN113972912B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of direct current elimination technology, and in particular to a direct current capture and direct current elimination circuit, a high-pass filter and a chip. Background Art
[0002] In real-time systems, unnecessary problems may occur due to the presence of the signal itself or the DC component generated during analog-to-digital processing. The DC offset of the audio signal may cause abnormal sound. The DC component of the communication signal increases the bit error rate to a certain extent and reduces system performance. It is of great significance to solve the DC offset problem in real-time systems with a simple and efficient DC capture and elimination method.
[0003] Since the frequency of DC offset is close to 0Hz, a high-pass filter is usually used to eliminate DC offset in real-time systems. Common traditional DC elimination filters include Figure 1 shown.
[0004] exist Figure 1 In the conventional DC elimination filter, although it can also eliminate DC offset well, the amount of DC that can be captured has a large variation range, which is not conducive to directly subtracting the DC capture amount from the signal to obtain the output signal. On the other hand, the filter has feedback, and the output y(n) theoretically needs a wider bit width than the sampled input x(n). In hardware implementation, the output y(n) is usually truncated to the same bit width as the input x(n). The truncation process itself will produce an offset, thereby reducing the accuracy of DC elimination. Summary of the invention
[0005] The embodiments of the present disclosure aim to provide a DC capture and DC elimination circuit, a high-pass filter and a chip, which can capture accurate DC offset, reduce the DC offset generated during the truncation process, improve the accuracy of DC elimination, ensure the effect of DC elimination, and improve the performance of the DC capture and DC elimination circuit.
[0006] To solve the above technical problems, the embodiments of the present disclosure provide the following technical solutions: a DC capture and DC elimination circuit, comprising: a first adder and a DC capture and DC elimination sub-circuit, wherein the DC capture and DC elimination sub-circuit comprises a second adder, a first delay module and a first multiplier; wherein:
[0007] The first adder has a first input coupled to the sampled input signal and outputs a DC-eliminated output signal;
[0008] The second adder has a first input coupled to the output of the first adder and an output coupled to the input of the first delay module;
[0009] The first delay module has an input coupled to the output of the second adder, and an output coupled to the second input of the second adder and the first input of the first multiplier respectively;
[0010] The first multiplier has a first input coupled to the output of the first delay module, a second input coupled to the first adjustment factor, and an output DC capture value coupled to the second input of the first adder.
[0011] Optionally, the output signal after DC elimination output by the first adder is as shown in the following formula:
[0012] y(n)=x(n)-DC(n)
[0013] In the above formula, x(n) is the input signal of the current sampling point, DC(n) is the DC capture value of the current sampling point, and y(n) is the output signal value of the current sampling point after DC elimination by the first adder.
[0014] Optionally, the DC capture value DC(n) of the current sampling point is:
[0015] DC(n)=DC(n-1)+α*y(n-1)
[0016] In the above formula, α is the first adjustment factor, DC(n-1) is the DC capture value of the previous sampling point, and y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder.
[0017] Optionally, the relationship between the output signal value after DC elimination output by the first adder and the sampled input signal input by the first adder is:
[0018] y(n)+(α-1)*y(n-1)=x(n)-x(n-1)
[0019] In the above formula, x(n) is the input signal of the current sampling point, x(n) is the input signal of the previous sampling point, y(n) is the output signal value of the current sampling point after DC elimination by the first adder 1, y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder 1, and α is the first adjustment factor.
[0020] Optionally, the formula y(n)+(α-1)*y(n-1)=x(n)-x(n-1) is converted into the frequency domain using the z-transform, and the z-domain transfer function of the correlation between Y(z) and X(z) is obtained as follows:
[0021]
[0022] In the above formula, α is the first adjustment factor.
[0023] Optionally, the DC capture and DC elimination subcircuit further includes an error processing module, an input of which is coupled to the output of the first multiplier, and an output DC capture value of which is coupled to the second input of the first adder.
[0024] Optionally, the error processing module includes the error processing sub-circuit, and the error processing sub-circuit includes: a third adder, a second multiplier, a fourth adder and a second delay module; wherein:
[0025] The third adder has a first input coupled to the output of the first multiplier, and an output coupled to the first input of the second multiplier and the first input of the fourth adder, respectively;
[0026] The second multiplier has a first input coupled to the output of the third adder, a second input coupled to the second adjustment factor, and an output DC capture value coupled to the second input of the fourth adder and the second input of the first adder respectively;
[0027] The fourth adder has a first input coupled to the output of the third adder, a second input coupled to the output of the second multiplier, and an output coupled to the input of the second delay module;
[0028] The second delay module has an input coupled to the output of the fourth adder, and an output coupled to the second input of the third adder.
[0029] Optionally, the DC capture value output by the second multiplier is:
[0030]
[0031] In the above formula, DC′(n) is the DC capture value of the current sampling point output by the second multiplier, DC(n) is the DC capture value of the current sampling point output by the first multiplier, β is the second adjustment factor, and e(n-1) is the truncation error of the previous sampling point output by the fourth adder.
[0032] Optionally, the truncation error e(n) output by the fourth adder is:
[0033]
[0034] In the above formula, β is the second adjustment factor.
[0035] Optionally, a relationship between a DC capture value output by the second multiplier and a DC capture value output by the first multiplier is:
[0036] DC′(n)-(1-β)*DC′(n-1)=β*DC(n)
[0037] In the above formula, DC′(n) is the DC capture value of the current sampling point output by the second multiplier, DC′(n-1) is the DC capture value of the previous sampling point output by the second multiplier, DC(n) is the DC capture value of the current sampling point output by the first multiplier, and β is the second adjustment factor.
[0038] Optionally, the formula DC′(n)-(1-β)*DC′(n-1)=β*DC(n) is converted into the frequency domain using z-transformation, and the z-domain transfer function formula of the correlation between DC′ and DC is obtained as follows:
[0039]
[0040] In the above formula, β is the second adjustment factor.
[0041] Optionally, the DC capture and DC elimination circuit further includes a switch, whose input is coupled to the output of the first adder, and whose output is coupled to the first input of the second adder, and which is used to close or open the DC capture and DC elimination sub-circuit.
[0042] In order to solve the above technical problems, the embodiments of the present disclosure also provide the following technical solutions: a high-pass filter, wherein the high-pass filter comprises the DC capture and DC elimination circuit described in any embodiment of the present disclosure.
[0043] In order to solve the above technical problems, the embodiments of the present disclosure also provide the following technical solutions: a chip, wherein the chip comprises the high-pass filter described in any embodiment of the present disclosure.
[0044] Compared with the prior art, the DC capture and DC elimination circuit, high-pass filter and chip provided by the embodiment of the present disclosure are coupled to the sampling input signal x(n) through the first input of the first adder, coupled to the output of the DC capture value of the first multiplier, and outputting the output signal y(n) after DC elimination through the second input of the second adder coupled to the output of the first adder, coupled to the output of the first delay module, and coupled to the input of the first delay module; the input of the first delay module is coupled to the output of the second adder, and the output is coupled to the second input of the second adder and the first input of the first multiplier respectively; the first input of the first multiplier is coupled to the output of the first delay module, coupled to the first adjustment factor, and the output DC capture value is coupled to the second input of the first adder. In this way, accurate DC offset can be captured, the DC offset generated in the truncation process can be reduced, the accuracy of DC elimination can be improved, the effect of DC elimination can be guaranteed, and the performance of the DC capture and DC elimination circuit can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0046] Figure 1 It is a structural schematic diagram of a traditional DC elimination circuit;
[0047] Figure 2 A schematic diagram of the structure of a DC capture and DC elimination circuit provided in an embodiment of the present disclosure;
[0048] Figure 3 A second structural schematic diagram of a DC capture and DC elimination circuit provided in an embodiment of the present disclosure;
[0049] Figure 4 To use MATLAB to input a 1KHz signal and add a certain DC offset, the simulation result diagram of the input signal x(n) is obtained;
[0050] Figure 5 This is a simulation result diagram of the DC residual after DC elimination of the traditional DC elimination circuit using MATLAB;
[0051] Figure 6 This is a simulation result diagram of the DC residual after DC elimination of the DC capture and DC elimination circuit provided by the present disclosure using MATLAB;
[0052] Figure 7 This is a simulation result diagram of DC capture of a traditional DC elimination circuit using MATLAB;
[0053] Figure 8 The figure is a simulation result diagram of DC capture of the DC capture and DC elimination circuit provided by the present disclosure using MATLAB;
[0054] Fig. 9 This is a superimposed comparison diagram of simulation results of DC capture of a traditional DC elimination circuit and a DC capture and DC elimination circuit provided by the present disclosure using MATLAB;
[0055] Fig.10 A third structural schematic diagram of a DC capture and DC elimination circuit provided in an embodiment of the present disclosure;
[0056] Fig.11 A fourth structural schematic diagram of a DC capture and DC elimination circuit provided in an embodiment of the present disclosure;
[0057] Fig.12 A schematic diagram of the structure of a high-pass filter provided in an embodiment of the present disclosure;
[0058] Fig.13 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0059] In order to facilitate the understanding of the present disclosure, the present disclosure is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on another element, or there can be one or more centered elements therebetween. When an element is described as "connected" to another element, it can be directly connected to another element, or there can be one or more centered elements therebetween. The orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "bottom" and the like used in this specification is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In addition, the terms "first", "second", "third" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0060] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in this specification and in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not used to limit the present disclosure. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.
[0061] In addition, the technical features involved in different embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other.
[0062] In one embodiment, Figure 2 As shown, the embodiment of the present disclosure provides a DC capture and DC elimination circuit, the DC capture and DC elimination circuit 10 includes: a first adder 1 and a DC capture and DC elimination sub-circuit 2, the DC capture and DC elimination sub-circuit 2 includes a second adder 22, a first delay module 21 and a first multiplier 23; wherein:
[0063] The first adder 1 has a first input coupled to the sampled input signal x(n) and outputs a DC-eliminated output signal y(n);
[0064] The second adder 22 has a first input coupled to the output of the first adder 1, and an output coupled to the input of the first delay module 21;
[0065] The first delay module 21 has an input coupled to the output of the second adder 22, and an output coupled to the second input of the second adder 22 and the first input of the first multiplier 23 respectively;
[0066] The first multiplier 23 has a first input coupled to the output of the first delay module 21 , a second input coupled to the first adjustment factor α, and an output DC capture value DC coupled to the second input of the first adder 1 .
[0067] In this embodiment, the first input of the first adder is coupled to the sampled input signal x(n), the second input of the first adder is coupled to the output of the DC capture value of the first multiplier, and the output of the first adder is the output signal y(n) after DC elimination; the first input of the second adder is coupled to the output of the first adder, the second input of the second adder is coupled to the output of the first delay module, and the output of the second adder is coupled to the input of the first delay module; the input of the first delay module is coupled to the output of the second adder, and the output of the first adder is coupled to the second input of the second adder and the first input of the first multiplier respectively; the first input of the first multiplier is coupled to the output of the first delay module, the second input of the first multiplier is coupled to the first adjustment factor, and the output of the DC capture value of the first multiplier is coupled to the second input of the first adder. In this way, accurate DC offset can be captured, the DC offset generated in the truncation process can be reduced, the accuracy of DC elimination can be improved, the effect of DC elimination can be guaranteed, and the performance of the DC capture and DC elimination circuits can be improved.
[0068] In one embodiment, Figure 2 As shown, according to the basic principle of DC elimination, we can get formula (1):
[0069] y(n)=x(n)-DC(n) Formula (1)
[0070] In the above formula (1), x(n) is the input signal of the current sampling point, DC(n) is the DC capture value DC of the current sampling point, and y(n) is the output signal value of the current sampling point after DC elimination by the first adder 1.
[0071] At the same time, the DC capture value DC of the current sampling point can be obtained, as shown in the following formula (2):
[0072] DC(n)=DC(n-1)+α*y(n-1) Formula (2)
[0073] In the above formula (2), α is the first adjustment factor, DC(n-1) is the DC capture value DC of the previous sampling point, and y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder 1.
[0074] In addition, from formula (2), we know that: ΔDC = α*y(n-1)
[0075] The DC has a wide range of variation.
[0076] Combining equation (1) and equation (2), it can be concluded that the relationship between the output signal value after DC elimination output by the first adder 1 and the sampled input signal input by the first adder 1 is:
[0077] y(n)+(α-1)*y(n-1)=x(n)-x(n-1) Formula (3)
[0078] In the above formula (3), x(n) is the input signal of the current sampling point, x(n) is the input signal of the previous sampling point, y(n) is the output signal value of the current sampling point after DC elimination by the first adder 1, y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder 1, and α is the first adjustment factor.
[0079] Then, according to the above formula (3), the time domain of formula (3) is converted into the frequency domain using z-transform, and the z-domain transfer function of the correlation between Y(z) and X(z) can be obtained, as shown in formula (4):
[0080]
[0081] According to the z-domain transfer function (4) of the correlation between Y(z) and X(z), it can be concluded that the amplitude-frequency response of the filter formed by the above DC capture and DC elimination circuit is that when the zero point z=1, H(z)=0, that is, the DC (0Hz) signal is infinitely attenuated to achieve the effect of DC elimination. When the pole is z=1-α, the smaller α is, the closer z is to 1, and the amplitude-frequency response curve is closer to the frequency centered at 0Hz. Therefore, α can be adjusted to achieve the effect of adjusting the filtering. In this way, it is possible to capture accurate DC offset, reduce the DC offset generated during the truncation process, improve the accuracy of DC elimination, ensure the effect of DC elimination, and improve the performance of the DC capture and DC elimination circuit.
[0082] In one embodiment, Figure 3 As shown, the DC capture and DC elimination sub-circuit 2 further includes an error processing module 24 , an input of which is coupled to the output of the first multiplier 23 , and an output DC capture value of which is coupled to the second input of the first adder 1 .
[0083] The error processing module 24 includes the error processing sub-circuit, and the error processing sub-circuit includes: a third adder 243, a second multiplier 242, a fourth adder 244 and a second delay module 245; wherein:
[0084] a third adder 243, a first input of which is coupled to the output of the first multiplier 23, and an output of which is coupled to the first input of the second multiplier 242 and the first input of the fourth adder 244 respectively;
[0085] A second multiplier 242, a first input of which is coupled to the output of the third adder 243, a second input of which is coupled to the second adjustment factor β, and an output DC capture value DC' of which is respectively coupled to the second input of the fourth adder 244 and the second input of the first adder 1;
[0086] a fourth adder 244, a first input of which is coupled to the output of the third adder 243, a second input of which is coupled to the output of the second multiplier 242, and an output of which is coupled to the input of the second delay module 245;
[0087] The second delay module 245 has an input coupled to the output of the fourth adder 244 , and an output coupled to the second input of the third adder 243 .
[0088] like Figure 3 As shown, after the error processing module 24 (error processing subcircuit) is introduced, the DC capture value DC' of the current sampling point can be obtained, as shown in the following formula (5):
[0089]
[0090]
[0091] In the above equations (5) and (6), DC′(n) is the DC capture value of the current sampling point (i.e., the DC capture value output by the second multiplier to the first adder 1), DC(n) is the DC capture value of the current sampling point when the error processing module 24 is not included (i.e., the DC capture value output by the first multiplier to the third adder 243), β is the second adjustment factor, e(n) is the truncation error of the current sampling point output by the fourth adder 244, and e(n-1) is the truncation error of the previous sampling point output by the fourth adder 244.
[0092] Then, according to the above formula (5) and formula (6), it can be concluded that the relationship between the DC capture value output by the second multiplier and the DC capture value output by the first multiplier is:
[0093] DC′(n)-(1-β)*DC′(n-1)=β*DC(n) Formula (7)
[0094] In the above formula (7), DC′(n) is the DC capture value of the current sampling point (i.e., the DC capture value output by the second multiplier to the first adder 1), DC(n) is the DC capture value of the current sampling point when the error processing module 24 is not included (i.e., the DC capture value output by the first multiplier to the third adder 243), and β is the second adjustment factor.
[0095] According to the above formula (7), the time domain of formula (7) is converted into the frequency domain using z-transform, and the z-domain transfer function of the correlation between DC′ and DC can be obtained, as shown in formula (8):
[0096]
[0097] It can be seen from formula (8) that: according to the z-domain transfer function formula (8) of the correlation between DC′ and DC, when β<1, DC′<DC(n), after the error processing subcircuit is introduced, the variation range of DC is smaller, and a more accurate DC capture value can be captured.
[0098] In this embodiment, after the DC capture and DC elimination subcircuit 2 is added with an error processing module 24 (error processing subcircuit), the truncation error is fed back to the truncation loop composed of the error processing subcircuit (i.e., fed back to the third adder 243 in the error processing subcircuit), so that the truncation error of the previous sampling point is included in the truncation processing of the next sampling point, and the modulation reduces the truncation error elimination, which can solve the error caused by the truncation processing; at the same time, the first adjustment factor α and the second adjustment factor β are added to adjust the response and elimination effect of the filter, and the flexible configuration makes the DC variation range smaller, so that the DC offset value with small amplitude and high accuracy can be captured, the accuracy of DC elimination is improved, the effect of DC elimination is guaranteed, and the performance of the DC capture and DC elimination circuit is further improved.
[0099] In one embodiment, Figures 4 to 6 , is a diagram showing the simulation results of DC elimination of the DC capture and DC elimination circuit provided in the present invention using MATLAB.
[0100] like Figure 4 As shown in FIG. 1 , a simulation result diagram of the input signal x(n) is obtained by using MATLAB to input a 1KHz signal and add a certain DC offset.
[0101] like Figure 5 As shown, it is a simulation result diagram of the DC residual after DC elimination of the traditional DC elimination circuit using MATLAB.
[0102] like Figure 6 As shown, it is a simulation result diagram of the DC residual after DC elimination of the DC capture and DC elimination circuit provided by the present disclosure using MATLAB.
[0103] from Figure 5 and Figure 6 The MATLAB simulation results show that when the same input signal x(n) is input, after the traditional DC elimination circuit eliminates the DC, the DC residue is about 500 (such as Figure 5 As shown), after the DC capture and DC elimination circuit provided by the present disclosure eliminates the DC, the DC residual is about 0.6 (as shown Figure 6 shown).
[0104] Therefore, the DC capture and DC elimination circuit provided by the present invention has obvious advantages over the traditional DC elimination circuit. It has a better DC elimination effect. The output signal after DC elimination has almost no DC offset, the output signal almost does not generate gain, and can better restore the input signal without DC offset.
[0105] In one embodiment, Figures 7 to 9 , is a diagram showing the simulation results of DC capture of the DC capture and DC elimination circuit provided in the present invention using MATLAB.
[0106] like Figure 7 As shown, it is the simulation result diagram of DC capture of traditional DC elimination circuit using MATLAB.
[0107] like Figure 8 As shown, it is a simulation result diagram of DC capture of the DC capture and DC elimination circuit provided by the present disclosure using MATLAB.
[0108] like Fig. 9 As shown, it is a superimposed comparison diagram of the simulation results of DC capture of the traditional DC elimination circuit and the DC capture and DC elimination circuit provided by the present disclosure using MATLAB.
[0109] from Figure 7 and Fig. 9 The MATLAB simulation results show that when the same input signal x(n) is input, after the DC capture is performed by the traditional DC elimination circuit, the DC capture value obtained has a large range of swings (such as Figure 7 As shown), after the DC capture and DC elimination circuit provided by the present disclosure performs DC capture, the DC capture value obtained is almost the same as the actual DC offset added (as shown Figure 8 shown).
[0110] Therefore, the DC capture and DC elimination circuit provided by the present invention has obvious advantages over the traditional DC elimination circuit. Its DC capture value is closer to the actual DC offset, and the swing range of the DC offset is small, so that it is possible to obtain an output signal by directly subtracting the DC capture value from the input signal, thereby achieving the purpose of DC elimination, while reducing calculations and lowering power consumption; at the same time, DC capture and DC elimination can reuse the same DC capture and DC elimination sub-circuit 2, saving circuit area.
[0111] In one embodiment, Fig.10 and Fig.11 As shown, the DC capture and DC elimination circuit 10 further includes a switch S1, whose input is coupled to the output of the first adder 1, and whose output is coupled to the first input of the second adder 22, and is used to close or open the DC capture and DC elimination sub-circuit 2.
[0112] Optionally, the switch S1 may be a manual switch, or an electronic switch composed of a transistor, a MOS tube, or an electronic element or circuit with a switching function, which is used to close or open the DC capture and DC elimination sub-circuit 2.
[0113] In this embodiment, after the error processing subcircuit is added to the DC capture and DC elimination subcircuit 2, the truncation error is fed back to the truncation loop composed of the error processing subcircuit, so that the truncation error of the previous sampling point is included in the truncation processing of the next sampling point, and the modulation reduces the elimination of the truncation error, which can solve the error generated by the truncation processing; at the same time, the first adjustment factor α and the second adjustment factor β are added to adjust the response and elimination effect of the filter, and the flexible configuration makes the variation range of DC smaller, so that the DC offset value with small amplitude and high accuracy can be captured, and the DC capture value is closer to the real DC offset. Therefore, in practical applications, after capturing the DC offset value with high accuracy, the switch S1 can be turned on, the DC capture and DC elimination subcircuit 2 can be turned off, and the DC capture value can be directly subtracted from the input signal to obtain the output signal, thereby reducing power consumption. At the same time, when eliminating DC, the configuration of the first adjustment factor α and the second adjustment factor β can be adjusted to minimize the DC residue, thereby achieving the purpose of DC elimination; at the same time, DC capture and DC elimination can reuse the same DC capture and DC elimination subcircuit 2, saving circuit area.
[0114] Based on the same concept, in one embodiment, Fig.12 As shown, the present disclosure provides a high-pass filter 100 , and the high-pass filter 100 includes the DC capture and DC elimination circuit 10 described in any of the above embodiments.
[0115] In the disclosed embodiment, the DC capture and DC elimination circuit 10 is consistent with the DC capture and DC elimination circuit 10 described in any of the above embodiments. The specific structure and function can refer to the DC capture and DC elimination circuit 10 described in any of the above embodiments, which will not be repeated here.
[0116] It should be noted that the above-mentioned filter embodiment and the DC capture and DC elimination circuit embodiment belong to the same concept. The specific implementation process is detailed in the DC capture and DC elimination circuit embodiment, and the technical features in the DC capture and DC elimination circuit embodiment are correspondingly applicable in the filter embodiment, which will not be repeated here.
[0117] Based on the same concept, in one embodiment, Fig.13 As shown, the present disclosure provides a chip, which includes the high-pass filter 100 described in any of the above embodiments.
[0118] In the embodiment of the present disclosure, the high-pass filter 100 is consistent with the high-pass filter 100 described in any of the above embodiments. The specific structure and function can refer to the high-pass filter 100 described in any of the above embodiments, which will not be repeated here.
[0119] It should be noted that the above-mentioned chip embodiment and the high-pass filter and DC capture and DC elimination circuit embodiments belong to the same concept, and their specific implementation process is detailed in the high-pass filter and DC capture and DC elimination circuit embodiments, and the technical features in the high-pass filter and DC capture and DC elimination circuit embodiments are correspondingly applicable in the chip embodiment, which will not be repeated here.
[0120] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0121] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.
[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Under the concept of the present disclosure, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present disclosure as described above, which are not provided in detail for the sake of simplicity. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A DC capture and DC elimination circuit, It is characterized in that The DC capture and DC elimination circuit comprises: a first adder and a DC capture and DC elimination sub-circuit, and the DC capture and DC elimination sub-circuit comprises a second adder, a first delay module and a first multiplier; wherein: The first adder has a first input coupled to the sampled input signal and outputs a DC-eliminated output signal; The second adder has a first input coupled to the output of the first adder and an output coupled to the input of the first delay module; The first delay module has an input coupled to the output of the second adder, and an output coupled to the second input of the second adder and the first input of the first multiplier respectively; The first multiplier has a first input coupled to the output of the first delay module, a second input coupled to the first adjustment factor, and an output DC capture value coupled to the second input of the first adder.
2. The DC capture and DC elimination circuit according to claim 1, It is characterized in that The output signal after DC elimination output by the first adder is as shown in the following formula: y(n)=x(n)-DC(n) In the above formula, x(n) is the input signal of the current sampling point, DC(n) is the DC capture value of the current sampling point, and y(n) is the output signal value of the current sampling point after DC elimination by the first adder.
3. The DC capture and DC elimination circuit according to claim 2, It is characterized in that The DC capture value DC(n) of the current sampling point is: DC(n)=DC(n-1)+α*y(n-1) In the above formula, α is the first adjustment factor, DC(n-1) is the DC capture value of the previous sampling point, and y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder.
4. The DC capture and DC elimination circuit according to claim 3, It is characterized in that The relationship between the output signal value after DC elimination output by the first adder and the sampled input signal input by the first adder is: y(n)+(α-1)*y(n-1)=x(n)-x(n-1) In the above formula, x(n) is the input signal of the current sampling point, x(n) is the input signal of the previous sampling point, y(n) is the output signal value of the current sampling point after DC elimination by the first adder 1, y(n-1) is the output signal value of the previous sampling point after DC elimination by the first adder 1, and α is the first adjustment factor.
5. The DC capture and DC elimination circuit according to claim 4, It is characterized in that The formula y(n)+(α-1)*y(n-1)=x(n)-x(n-1) is converted into the frequency domain using the z-transform, and the z-domain transfer function of the correlation between Y(z) and X(z) is obtained as follows: In the above formula, α is the first adjustment factor.
6. The DC capture and DC elimination circuit according to claim 3, It is characterized in that The DC capture and DC elimination subcircuit further includes an error processing module, an input of which is coupled to the output of the first multiplier, and an output DC capture value of which is coupled to the second input of the first adder.
7. The DC capture and DC elimination circuit according to claim 6, It is characterized in that The error processing module includes an error processing subcircuit, and the error processing subcircuit includes: a third adder, a second multiplier, a fourth adder and a second delay module; wherein: The third adder has a first input coupled to the output of the first multiplier, and an output coupled to the first input of the second multiplier and the first input of the fourth adder, respectively; The second multiplier has a first input coupled to the output of the third adder, a second input coupled to the second adjustment factor, and an output DC capture value coupled to the second input of the fourth adder and the second input of the first adder respectively; The fourth adder has a first input coupled to the output of the third adder, a second input coupled to the output of the second multiplier, and an output coupled to the input of the second delay module; The second delay module has an input coupled to the output of the fourth adder, and an output coupled to the second input of the third adder.
8. The DC capture and DC elimination circuit according to claim 7, It is characterized in that The DC capture value output by the second multiplier is: In the above formula, DC′(n) is the DC capture value of the current sampling point output by the second multiplier, DC(n) is the DC capture value of the current sampling point output by the first multiplier, β is the second adjustment factor, and e(n-1) is the truncation error of the previous sampling point output by the fourth adder.
9. The DC capture and DC elimination circuit according to claim 8, It is characterized in that The truncation error e(n) output by the fourth adder is: In the above formula, β is the second adjustment factor.
10. The DC capture and DC elimination circuit according to claim 9, It is characterized in that The relationship between the DC capture value output by the second multiplier and the DC capture value output by the first multiplier is: DC′(n)-(1-β)*DC′(n-1)=β*DC(n) In the above formula, DC′(n) is the DC capture value of the current sampling point output by the second multiplier, DC′(n-1) is the DC capture value of the previous sampling point output by the second multiplier, DC(n) is the DC capture value of the current sampling point output by the first multiplier, and β is the second adjustment factor.
11. The DC capture and DC elimination circuit according to claim 1, It is characterized in that Convert the formula DC′(n)-(1-β)*DC′(n-1)=β*DC(n) into the frequency domain using the z-transform, and obtain the z-domain transfer function of the correlation between DC′ and DC as follows: In the above formula, β is the second adjustment factor.
12. The DC capture and DC elimination circuit according to claim 1, It is characterized in that The DC capture and DC elimination circuit further includes a switch, an input of which is coupled to the output of the first adder, and an output of which is coupled to the first input of the second adder, and is used to close or open the DC capture and DC elimination sub-circuit.
13. A high pass filter, It is characterized in that The high-pass filter comprises a DC capture and DC elimination circuit as claimed in any one of claims 1 to 12.
14. A chip, It is characterized in that The chip includes the high pass filter as claimed in claim 13.