An interrupt handling method, apparatus, and computer device

Abstract

This disclosure provides an interrupt handling method, apparatus, and computer device applied to a programmable interrupt coprocessor. The interrupt coprocessor includes several subprocessors, each with a built-in coprocessing service routine for a specific type of peripheral. The method includes: the interrupt coprocessor receiving an external interrupt signal; the logic unit of the interrupt coprocessor obtaining the entry address of the coprocessing service routine from a service address register; checking whether the current interrupt type matches through the coprocessing service routine; if it matches, executing the processing procedure for that interrupt type; if it does not match, exiting to a standby state; completing the interrupt handling, and entering a standby state. This solution reduces the frequency of CPU switching between user processes and interrupt handling by decoupling the processing of peripheral interrupts from the CPU and having it handled by an independent interrupt coprocessor, thereby improving the overall performance of the computer system.

Description

Technical Field

[0001] This disclosure belongs to the field of interrupt handling technology, and particularly relates to an interrupt handling method, apparatus and computer equipment. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] Modern computer architectures provide interrupt mechanisms to respond to and handle interrupts triggered by external devices. When an external device sends an interrupt signal, the CPU suspends its currently executing task and executes an interrupt service routine to handle the interrupt. Once completed, it resumes execution of the interrupted task. The task switching caused by interrupts leads to the invalidation of a large amount of cache, therefore, frequent interrupts have a significant impact on computer performance.

[0004] The inventors discovered that, in order to solve the above problems, existing methods employ the following approach:

[0005] (1) In a multi-CPU architecture, the operating system divides the CPU into two groups by setting one group of CPUs to handle interrupts, while the other group of CPUs does not participate in handling interrupts. This avoids the overhead of task switching caused by interrupts and reduces the impact of external interrupts on system performance. However, since the occurrence of peripheral interrupts is random and unpredictable, this method of fixing the purpose of each CPU will obviously affect the unified scheduling of computing resources by the system. There may be a situation where one group of CPUs is very busy, while the other group is idle, resulting in a waste of resources.

[0006] (2) DMA, or Direct Memory Access, can be used to complete the task of batch data exchange between certain types of peripherals and memory, thereby reducing the CPU load; however, DMA is mainly for block devices and cannot reduce the frequency of CPU processing peripheral interrupts. Summary of the Invention

[0007] In order to solve the above problems, this disclosure provides an interrupt handling method, apparatus and computer device. The solution decouples the processing of peripheral interrupts from the CPU and has it handled by an independent interrupt coprocessor, thereby reducing the frequency of CPU switching between user processes and interrupt handling and improving the overall performance of the computer system.

[0008] According to a first aspect of the present disclosure, an interrupt handling method is provided, which is applied to a programmable interrupt coprocessor, the interrupt coprocessor comprising a plurality of such coprocessors, each interrupt coprocessor having a built-in coprocessing service routine for a specific type of peripheral, the method comprising:

[0009] The interrupt coprocessor receives external interrupt signals;

[0010] The logic unit of the interrupt coprocessor obtains the coprocessor service program entry address from the service address register;

[0011] The coprocessor service routine checks whether the current interrupt type matches; if it matches, it executes the processing procedure for that interrupt type; if it does not match, it exits to the standby state.

[0012] The interrupt has been processed and the system is now in standby mode.

[0013] Furthermore, the interrupt handling method requires the following initialization operations to be performed beforehand:

[0014] When the host machine is powered on, the service address register of the interrupt coprocessor is cleared and the instruction cache is cleared;

[0015] During the host operating system startup process, the entry address of the coprocessor service program is stored in the service address register, and the interrupt coprocessor enters a standby state.

[0016] Furthermore, the initialization operation also includes:

[0017] During the host operating system startup process, the interrupt signals of all similar peripherals are configured to be connected to the corresponding interrupt coprocessors.

[0018] Furthermore, the process of executing this interrupt type includes setting the state and filling the buffer.

[0019] According to a second aspect of the present disclosure, an interrupt handling apparatus is provided, including a plurality of interrupt coprocessors, wherein each interrupt coprocessor has a built-in coprocessing service program for a specific type of peripheral.

[0020] The interrupt coprocessor is configured to receive external interrupt signals, obtain the coprocessor service program entry address from the service address register, check whether the current interrupt type matches through the coprocessor service program, execute the processing procedure for that interrupt type if it matches, exit to the standby state if it does not match, and enter the standby state after completing the interrupt processing.

[0021] According to a third aspect of the present disclosure, a computer device is provided, including a main controller and the interrupt handling device described above, wherein external interrupts caused by peripheral devices are all processed by the interrupt handling device.

[0022] Compared with the prior art, the beneficial effects of this disclosure are:

[0023] (1) The method described in this disclosure introduces a dedicated interrupt coprocessor to reduce CPU consumption when switching between user processes and interrupt processing, thereby improving computer performance.

[0024] (2) The interrupt coprocessor of the scheme described in this disclosure is directly oriented towards the peripheral device, which shortens the long path from when the peripheral device issues an interrupt to when the CPU switches tasks to complete the interrupt handling. This helps to reduce the complexity of the computer system and improve its reliability.

[0025] Advantages of this disclosure in additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0026] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure.

[0027] Figure 1 This is a schematic diagram comparing the existing interruption process described in Embodiment 1 of this disclosure with the interruption process of the solution described in this disclosure;

[0028] Figure 2 This is a schematic diagram of the interrupt coprocessor structure described in Embodiment 1 of this disclosure. Detailed Implementation

[0029] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0030] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] Where there is no conflict, the embodiments and features described herein can be combined with each other.

[0033] Example 1:

[0034] The purpose of this embodiment is to provide an interrupt handling method.

[0035] An interrupt handling method is applied to a programmable interrupt coprocessor, wherein the interrupt coprocessor comprises a plurality of coprocessors, and each interrupt coprocessor has a built-in coprocessor service routine for a specific type of peripheral. The method includes:

[0036] The interrupt coprocessor receives external interrupt signals;

[0037] The logic unit of the interrupt coprocessor obtains the coprocessor service program entry address from the service address register;

[0038] The coprocessor service routine checks whether the current interrupt type matches; if it matches, it executes the processing procedure for that interrupt type; if it does not match, it exits to the standby state.

[0039] The interrupt has been processed and the system is now in standby mode.

[0040] Furthermore, the interrupt handling method requires the following initialization operations to be performed beforehand:

[0041] When the host machine is powered on, the service address register of the interrupt coprocessor is cleared and the instruction cache is cleared;

[0042] During the host operating system startup process, the entry address of the coprocessor service program is stored in the service address register, and the interrupt coprocessor enters a standby state.

[0043] Furthermore, the initialization operation also includes:

[0044] During the host operating system startup process, the interrupt signals of all similar peripherals are configured to be connected to the corresponding interrupt coprocessors.

[0045] Furthermore, the process of executing this interrupt type includes setting the state and filling the buffer.

[0046] Furthermore, the interrupt coprocessor includes a logic unit, a service address register, an instruction cache, and a bus interface.

[0047] Furthermore, the logic unit is used to execute interrupt service routines to complete tasks, and its specific implementation adopts a low-power CPU with the same instruction set as the host system CPU.

[0048] or

[0049] Heterogeneous low-power CPU;

[0050] or

[0051] Implemented using FPGA.

[0052] Furthermore, the service address register is used to store the entry address of the coprocessor service program.

[0053] Furthermore, the instruction cache is used to prefetch and cache instructions for the coprocessor service.

[0054] Specifically, for ease of understanding, the following detailed explanation of the solution described in this disclosure is provided in conjunction with the accompanying drawings, covering three aspects: design principles, hardware configuration, and specific workflow.

[0055] First, it should be noted that in this technical field, internal exceptions (such as page faults) and system calls are usually referred to as "internal interrupts," while the methods and apparatus described in this disclosure only handle external interrupts caused by peripheral devices and do not affect the computer system's handling of internal exceptions and system calls.

[0056] (I) Design Principles

[0057] The following combination Figure 1 By comparing with existing interruption processes, the principles and characteristics of the scheme described in this disclosure are explained in detail:

[0058] Figure 1 The left side shows the existing interrupt process:

[0059] Step (1): When a peripheral device reaches a certain state or is triggered by a certain condition, it sends an interrupt signal to the interrupt controller.

[0060] Step (2): The interrupt controller arbitrates all currently pending interrupts and selects one interrupt to report to the CPU based on a predetermined strategy such as priority.

[0061] Step (3): The CPU pauses the currently executing task, saves the state of the current state, and then switches to the corresponding interrupt service routine entry point.

[0062] Step (4): The interrupt service routine begins execution. Based on the content of the peripheral interrupt, the processing logic is executed, including setting the status, filling the data buffer, etc. After the service is completed, the CPU switches back to the original interrupted task to continue execution.

[0063] Figure 1 The right side shows the interruption process in the scheme described in this disclosure:

[0064] Step (1): Initialize the interrupt coprocessor and assign it the corresponding coprocessor service routine.

[0065] Step (2): When the peripheral device reaches a certain state or is triggered by a certain condition, it sends an interrupt signal to the interrupt coprocessor.

[0066] Step (3): The interrupt coprocessor directly calls the corresponding coprocessor service to process the received interrupt, including setting the status, filling the data buffer, etc. The coprocessor executes this process in parallel with the CPU, and no longer triggers the switching of the tasks executed by the CPU.

[0067] As a further limitation, the scheme described in this disclosure sets up a corresponding interrupt coprocessor for each type of peripheral device included in the computer system to handle its interrupts. All coprocessors have identical hardware, except that different coprocessor service routine entry points are specified during initialization to correspond to the respective peripheral device types.

[0068] (II) Hardware Configuration of Interrupt Coprocessor

[0069] like Figure 2 As shown, the interrupt coprocessor in the scheme described in this disclosure consists of four parts: a logic unit, a service address register, an instruction cache, and a bus interface.

[0070] (1) Logic Unit: The logic unit is responsible for executing interrupt service routines to complete tasks and is the core component. There are three types of implementation schemes to choose from. (1) Low-power CPU with the same instruction set as the system CPU; (2) Heterogeneous low-power CPU, such as RISC-V / ARM / MIPS, etc.; (3) FPGA-based implementation.

[0071] (2) Service Address Register: Stores the entry address of the coprocessor service. A coprocessor service is a program that handles interrupts; it is part of the operating system kernel and is loaded into a memory address space when the operating system starts. This service is functionally equivalent to the interrupt service in existing computer systems, and therefore achieves the same effect as traditional interrupt methods. In practice, interrupt services in existing computer systems can be modified and used as coprocessor service programs.

[0072] (3) Instruction cache: Prefetch and cache instructions of the coprocessor service program to improve coprocessor performance.

[0073] (4) Bus interface: The interface between the coprocessor and the outside world. This interface is the only way for the coprocessor to exchange information with the outside world, including interrupt signals, address information and data information.

[0074] (III) Specific Work Process

[0075] Step (1): Initialize the interrupt coprocessor, which includes two stages: the computer power-on stage and the operating system startup stage.

[0076] Specifically, step (1) includes:

[0077] Step (1-1): When the computer system is powered on, the service address register of the interrupt coprocessor is cleared and the instruction cache is emptied. The entire interrupt coprocessor is in a stopped state and does not work.

[0078] Steps (1-2): During the operating system startup process, the entry address of the coprocessor service handler is stored in the service address register, and the coprocessor enters a standby state. That is, from this point onward, once the corresponding external interrupt signal arrives, the logic unit will execute the handler according to the address value stored in the service address register. Furthermore, during operating system startup, the interrupt signals of all peripherals of the same type are configured to be connected to the corresponding interrupt coprocessor; that is, each type of peripheral corresponds to one coprocessor.

[0079] Step (2): The peripheral sends an interrupt signal to the interrupt coprocessor.

[0080] Step (3): When an interrupt is received from a peripheral device, the coprocessor is triggered to call the coprocessor service to execute the following processing procedure.

[0081] Specifically, step (3) includes:

[0082] Step (3-1): The logic unit determines the coprocessor service entry address based on the value of the service address register and begins execution. During execution, the instruction cache assists in prefetching several instructions that are about to be executed, thereby reducing the frequency of fetching instructions from memory.

[0083] Step (3-2): The coprocessor service checks whether the current interrupt type can be handled. If it is not the target type that this service needs to handle, it exits to the B.2.4 standby state.

[0084] Step (3-3): The coprocessor service performs the handling process for this interrupt, including setting the state, filling the buffer, etc.

[0085] Steps (3-4): Complete the interrupt handling, enter the standby state, and wait for the next interrupt signal to wake up.

[0086] The solution described in this disclosure separates the handling of peripheral interrupts from the CPU and assigns it to an independent interrupt coprocessor, thereby reducing the frequency of CPU switching between user processes and interrupt handling and improving the overall performance of the computer system.

[0087] Example 2:

[0088] The purpose of this embodiment is to provide an interrupt handling device.

[0089] An interrupt handling apparatus includes a plurality of interrupt coprocessors, and each interrupt coprocessor has a built-in coprocessing service routine for a specific type of peripheral.

[0090] The interrupt coprocessor is configured to receive external interrupt signals, obtain the coprocessor service program entry address from the service address register, check whether the current interrupt type matches through the coprocessor service program, execute the processing procedure for that interrupt type if it matches, exit to the standby state if it does not match, and enter the standby state after completing the interrupt processing.

[0091] Example 3:

[0092] The purpose of this embodiment is to provide a computer device.

[0093] A computer device includes a main controller and the aforementioned interrupt handling device, wherein external interrupts triggered by peripheral devices are all processed by the interrupt handling device.

[0094] The interrupt handling device includes several interrupt coprocessors, and each interrupt coprocessor has a built-in coprocessing service program for a specific type of peripheral.

[0095] The interrupt coprocessor is configured to receive external interrupt signals, obtain the coprocessor service program entry address from the service address register, check whether the current interrupt type matches through the coprocessor service program, execute the processing procedure for that interrupt type if it matches, exit to the standby state if it does not match, and enter the standby state after completing the interrupt processing.

[0096] In further embodiments, the following is also provided:

[0097] An electronic device includes a memory and a processor, as well as computer instructions stored in the memory and running on the processor. When executed by the processor, the computer instructions perform the method described in Embodiment 1. For brevity, further details are omitted here.

[0098] It should be understood that in this embodiment, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0099] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory may also include non-volatile random access memory. For example, memory may also store information about the device type.

[0100] A computer-readable storage medium for storing computer instructions, which, when executed by a processor, perform the method described in Embodiment 1.

[0101] The method in Embodiment 1 can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in readily available storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, a detailed description is not provided here.

[0102] Those skilled in the art will recognize that the units, i.e., algorithm steps, of the various examples described in connection with this embodiment can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] The interrupt handling method, apparatus, and computer equipment provided in the above embodiments can be implemented and have broad application prospects.

[0104] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An interrupt handling method, characterized in that, It is applied to programmable interrupt coprocessors, which decouple the handling of peripheral interrupts from the CPU and have it handled by an independent interrupt coprocessor; the interrupt coprocessor includes several units, and each interrupt coprocessor has a built-in coprocessor service routine for a specific type of peripheral; the method includes: The interrupt coprocessor receives external interrupt signals; The logic unit of the interrupt coprocessor obtains the coprocessor service program entry address from the service address register; The coprocessor service routine checks whether the current interrupt type matches; if it matches, it executes the processing procedure for that interrupt type; if it does not match, it exits to the standby state. Complete interrupt handling and enter standby mode; The interrupt coprocessor includes a logic unit, a service address register, an instruction cache, and a bus interface; The interruption process in the method includes: Step (1): Initialize the interrupt coprocessor and assign it the corresponding coprocessor service routine; Step (2): When a peripheral device reaches a certain state or is triggered by a certain condition, it sends an interrupt signal to the interrupt coprocessor; Step (3): The interrupt coprocessor directly calls the corresponding coprocessor service to process the received interrupt, including setting the state and filling the data buffer; the coprocessor executes this process in parallel with the CPU and no longer triggers the switching of the tasks executed by the CPU. The interrupt handling method requires the following initialization operations to be performed beforehand: When the host machine is powered on, the service address register of the interrupt coprocessor is cleared and the instruction cache is cleared; During the host operating system startup process, the entry address of the coprocessor service program is stored in the service address register, and the interrupt coprocessor enters the standby state. During the host operating system startup process, the interrupt signals of all similar peripherals are configured to be connected to the corresponding interrupt coprocessors.

2. The interrupt handling method as described in claim 1, characterized in that, The process of executing this interrupt type includes setting the status and filling the buffer.

3. The interrupt handling method as described in claim 1, characterized in that, The logic unit is used to execute interrupt service routines to complete tasks, and its specific implementation uses a low-power CPU with the same instruction set as the host system CPU. or Heterogeneous low-power CPU; or Implemented using FPGA.

4. The interrupt handling method as described in claim 1, characterized in that, The service address register is used to store the entry address of the coprocessor service program.

5. The interrupt handling method as described in claim 1, characterized in that, The instruction cache is used to prefetch and cache instructions for the coprocessor service.

6. An interrupt handling device, characterized in that, This includes several interrupt coprocessors that handle peripheral interrupts independently by separating them from the CPU, and each interrupt coprocessor has a built-in coprocessor service program for a specific type of peripheral. The interrupt coprocessor is configured to receive external interrupt signals, obtain the coprocessor service program entry address from the service address register, check whether the current interrupt type matches through the coprocessor service program, execute the processing procedure for that interrupt type if it matches, exit to the standby state if it does not match, complete the interrupt processing, and enter the standby state. The interrupt coprocessor includes a logic unit, a service address register, an instruction cache, and a bus interface; The interruption process in the method includes: Step (1): Initialize the interrupt coprocessor and assign it the corresponding coprocessor service routine; Step (2): When a peripheral device reaches a certain state or is triggered by a certain condition, it sends an interrupt signal to the interrupt coprocessor; Step (3): The interrupt coprocessor directly calls the corresponding coprocessor service to process the received interrupt, including setting the state and filling the data buffer; the coprocessor executes this process in parallel with the CPU and no longer triggers the switching of the tasks executed by the CPU. The interrupt handling method requires the following initialization operations to be performed beforehand: When the host machine is powered on, the service address register of the interrupt coprocessor is cleared and the instruction cache is cleared; During the host operating system startup process, the entry address of the coprocessor service program is stored in the service address register, and the interrupt coprocessor enters the standby state. During the host operating system startup process, the interrupt signals of all similar peripherals are configured to be connected to the corresponding interrupt coprocessors.

7. A computer device, characterized in that, It includes a main controller and an interrupt handling device as described in claim 6, wherein external interrupts caused by peripheral devices are all handled by the interrupt handling device.

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