Method for manufacturing array substrate and display panel

Abstract

The application discloses a manufacturing method of an array substrate and a display panel. In the manufacturing process of the array substrate, a test key is arranged. When a first metal layer is subjected to first patterning to form a first sub-metal member of a transistor and a second sub-metal member of the test key, a second edge of the second sub-metal member exceeds a first edge of a second sub-semiconductor member. When the first sub-semiconductor member is subjected to re-doping, the test area of the second sub-semiconductor member of the test key is not subjected to re-doping. Then, after the first metal layer is subjected to second patterning, the first edge of the second sub-semiconductor member exceeds the second edge of the second sub-metal member. The exposed part of the second sub-semiconductor member and the first sub-semiconductor member are subjected to light doping. The part of the first edge of the second sub-semiconductor member of the test key only has light doping elements, interference of re-doping elements is avoided, and the concentration of the light doping elements can be well monitored and tested.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and in particular to a manufacturing method of an array substrate and a display panel. BACKGROUND

[0002] Various types of display panels such as liquid crystal display panels and organic light emitting display panels have been widely used in people's life, for example, display screens of mobile phones, computers and the like. The display panel needs to be made of an array substrate, and a test key needs to be made during the manufacturing process of the array substrate to monitor characteristics and yield rates and the like in each process. During the manufacturing process of a thin film transistor, a semiconductor layer will be subjected to heavy doping and light doping, and the doping concentration of the light doping of the semiconductor layer needs to be strictly controlled.

[0003] However, in the current manufacturing process of the array substrate, heavy doping and light doping exist in the test key, the elements of the heavy doping interfere with the monitoring of the concentration of the light doping elements, and it is difficult to monitor the concentration of the light doping elements. SUMMARY

[0004] Embodiments of the present application provide a manufacturing method of an array substrate and a display panel, which can solve the problem that, in the current manufacturing process of the display panel or the array substrate, the elements of the heavy doping of the semiconductor layer interfere with the monitoring of the concentration of the light doping elements, and it is difficult to monitor the concentration of the light doping elements.

[0005] Embodiments of the present application provide a manufacturing method of an array substrate, comprising the following steps:

[0006] Step S100: providing a substrate;

[0007] Step S200: forming a semiconductor layer on the substrate, patterning the semiconductor layer to form a first sub-semiconductor part of a transistor and a second sub-semiconductor part of a test key, the second sub-semiconductor part comprising a first edge;

[0008] Step S300: forming a first insulating layer on the semiconductor layer;

[0009] Step S400: forming a first metal layer on the first insulating layer, performing a first patterning process on the first metal layer to form a first sub-metal part of the transistor and a second sub-metal part of the test key, wherein the second sub-metal part comprises a second edge, the first edge of the second sub-semiconductor part corresponds to the second edge of the second sub-metal part, the second edge exceeds the first edge, and the first sub-semiconductor part is subjected to heavy doping treatment;

[0010] Step S500: performing a second patterning process on the first metal layer to reduce the width of the first and second sub-metal pieces, wherein the first edge exceeds the second edge, and performing a light doping process on the first and second sub-semiconductor pieces;

[0011] Step S600: forming a second insulating layer on the first metal layer;

[0012] Step S700: forming a second metal layer on the second insulating layer, and performing a patterning process on the second metal layer to form the source and drain of the transistor.

[0013] Optionally, in some embodiments of the present application, in the step S400, the length by which the second edge exceeds the first edge is 1-4 microns.

[0014] Optionally, in some embodiments of the present application, in the step S500, the length by which the first edge exceeds the second edge is 1-4 microns.

[0015] Optionally, in some embodiments of the present application, in the step S700, the patterning process on the second metal layer also forms a first connection trace, a second connection trace, a first test terminal and a second test terminal, two ends of the first connection trace are connected to one end of the first edge of the second sub-semiconductor piece and the first test terminal respectively, and two ends of the second connection trace are connected to the other end of the first edge of the second sub-semiconductor piece and the second test terminal respectively.

[0016] Optionally, in some embodiments of the present application, in the steps S400 and S500, the patterning process on the first metal layer also forms a first test terminal and a second test terminal.

[0017] In the step S700, the patterning process on the second metal layer also forms a first connection trace and a second connection trace, two ends of the first connection trace are connected to one end of the first edge of the second sub-semiconductor piece and the first test terminal respectively, and two ends of the second connection trace are connected to the other end of the first edge of the second sub-semiconductor piece and the second test terminal respectively.

[0018] Optionally, in some embodiments of the present application, the shape of the second sub-semiconductor piece includes at least one of a strip shape, an L shape, a U shape, and a V shape.

[0019] Optionally, in some embodiments of the present application, the material of the semiconductor layer includes at least one of amorphous silicon and polycrystalline silicon.

[0020] Optionally, in some embodiments of the present application, the heavily doped and lightly doped element is a pentavalent element or a trivalent element.

[0021] Optionally, in some embodiments of the present application, the material of the semiconductor layer comprises polysilicon, and the heavily doped and lightly doped element is phosphorus.

[0022] Correspondingly, the present application also provides a display panel, which comprises an array substrate manufactured by the manufacturing method of the array substrate.

[0023] In the manufacturing process of the display panel or the array substrate, in the embodiment of the present application, a test key is arranged, a first metal layer is subjected to a first patterning process to form a first sub-metal piece of a transistor and a second sub-metal piece of the test key, the second edge of the second sub-metal piece exceeds the first edge of the second sub-semiconductor piece, the test area of the second sub-semiconductor piece of the test key is not heavily doped when the first sub-semiconductor piece is heavily doped, and then the first metal layer is subjected to a second patterning process, the first edge of the second sub-semiconductor piece exceeds the second edge of the second sub-metal piece, the exposed part of the second sub-semiconductor piece and the first sub-semiconductor piece are lightly doped, the part of the first edge of the second sub-semiconductor piece of the test key is only lightly doped with the element, the interference of the heavily doped element is avoided, and the concentration of the lightly doped element can be well monitored and tested. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0025] Figure 1 is a manufacturing step schematic diagram of a manufacturing method of an array substrate provided by an embodiment of the present application;

[0026] Figure 2 is a schematic diagram after forming a first metal layer in the manufacturing method of the array substrate provided by an embodiment of the present application;

[0027] Figure 3 is a top view schematic diagram after heavily doping a semiconductor layer in the manufacturing method of the array substrate provided by an embodiment of the present application;

[0028] Figure 4 is a sectional view schematic diagram after heavily doping a semiconductor layer in the manufacturing method of the array substrate provided by an embodiment of the present application;

[0029] Figure 5is a top view of a semiconductor layer after light doping in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0030] Figure 6 is a sectional view of a semiconductor layer after light doping in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0031] Figure 7 is a sectional view of a manufacturing method of an array substrate provided by an embodiment of the present application after forming a patterned second metal layer;

[0032] Figure 8 is a schematic diagram of a test key on an array substrate provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0034] The embodiment of the present application provides a manufacturing method of an array substrate, comprising the following steps: step S100: providing a substrate; step S200: forming a semiconductor layer on the substrate, patterning the semiconductor layer to form a first sub-semiconductor part of a transistor and a second sub-semiconductor part of a test key, the second sub-semiconductor part comprising a first edge; step S300: forming a first insulating layer on the semiconductor layer; step S400: forming a first metal layer on the first insulating layer, performing first patterning treatment on the first metal layer to form a first sub-metal part of the transistor and a second sub-metal part of the test key, wherein the second sub-metal part comprises a second edge, the first edge of the second sub-semiconductor part corresponds to the second edge of the second sub-metal part, the second edge exceeds the first edge, and the first sub-semiconductor part is subjected to heavy doping treatment; step S500: performing second patterning treatment on the first metal layer to reduce the width of the first sub-metal part and the second sub-metal part, wherein the first edge exceeds the second edge, and the first sub-semiconductor part and the second sub-semiconductor part are subjected to light doping treatment; step S600: forming a second insulating layer on the first metal layer; and step S700: forming a second metal layer on the second insulating layer, and performing patterning treatment on the second metal layer to form a source electrode and a drain electrode of the transistor.

[0035] The embodiment of the present application provides a manufacturing method of an array substrate and a display panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments.

[0036] Embodiment one,

[0037] Please refer to Figure 1 、 Figure 2 、 Figure 3 , Figure 1 The manufacturing steps of the manufacturing method of the array substrate provided by the embodiment of the present application are shown in the following figure; Figure 2 is a schematic diagram of the manufacturing method of the array substrate provided by the embodiment of the present application after forming the first metal layer; Figure 3 is a top view schematic diagram of the manufacturing method of the array substrate provided by the embodiment of the present application after heavy doping of the semiconductor layer; Figure 4 is a sectional view schematic diagram of the manufacturing method of the array substrate provided by the embodiment of the present application after heavy doping of the semiconductor layer, that is, a schematic diagram of the A-B dotted line section in Figure 3 ; Figure 5 is a top view schematic diagram of the manufacturing method of the array substrate provided by the embodiment of the present application after light doping of the semiconductor layer; Figure 6 is a sectional view schematic diagram of the manufacturing method of the array substrate provided by the embodiment of the present application after light doping of the semiconductor layer, that is, a schematic diagram of the A-B dotted line section in Figure 5 ; Figure 7is a sectional view after forming a patterned second metal layer in a manufacturing method of an array substrate provided by an embodiment of the present application; Figure 8 is a schematic view of a test key on an array substrate provided by an embodiment of the present application.

[0038] An embodiment of the present application provides a manufacturing method of an array substrate, as shown in the figure, Figure 1 The manufacturing method of the array substrate includes manufacturing steps: step S100, step S200, step S300, step S400, step S500, step S600, and step S700.

[0039] Step S100: providing a substrate.

[0040] Specifically, as shown in the figure, Figure 2 a substrate 11 is provided, which can be a glass substrate, a plastic substrate, etc., and is not limited herein.

[0041] Step S200: forming a semiconductor layer on the substrate, patterning the semiconductor layer to form a first sub-semiconductor part of a transistor and a second sub-semiconductor part of a test key, the second sub-semiconductor part including a first edge.

[0042] Specifically, as shown in the figure, Figure 2 a semiconductor layer 12 is formed on the substrate 11, and the semiconductor layer 12 is patterned to form a first sub-semiconductor part 121 of a transistor 10 and a second sub-semiconductor part 122 of a test key 20, the second sub-semiconductor part 122 including a first edge 101.

[0043] Step S300: forming a first insulating layer on the semiconductor layer.

[0044] Specifically, as shown in the figure, Figure 2 a first insulating layer 13 is formed on the semiconductor layer 12, which can be a gate insulating layer, and the first insulating layer 13 can also be patterned, as long as the first insulating layer 13 is present on the first sub-semiconductor part 121 and the second sub-semiconductor part 122.

[0045] Step S400: forming a first metal layer on the first insulating layer, and performing a first patterning process on the first metal layer to form a first sub-metal part of a transistor and a second sub-metal part of a test key, wherein the second sub-metal part includes a second edge, the first edge of the second sub-semiconductor part corresponds to the second edge of the second sub-metal part, the second edge exceeds the first edge, and the first sub-semiconductor part is subjected to a heavy doping process.

[0046] Specifically, as shown in the figure, Figure 2 , Figure 3 , Figure 4As shown in FIG. 1, the first metal layer 14 is formed on the first insulating layer 13, and the first metal layer 14 is subjected to the first patterning process to form the first sub-metal member 141 of the transistor 10 and the second sub-metal member 142 of the test key 20. The second sub-metal member 142 includes the second edge 102 corresponding to the first edge 101 of the second sub-semiconductor member 122, and the second edge 102 exceeds the first edge 101. The first sub-semiconductor member 121 is subjected to the heavy doping process.

[0047] Specifically, at this time, in the transistor 10, the first sub-metal member 141 exposes the heavy doped region 1211 of the first sub-semiconductor member 121, and the first sub-semiconductor member 121 is subjected to the heavy doping process to form the heavy doped region 1211.

[0048] Specifically, at this time, in the test key 20, the second edge 102 of the second sub-metal member 142 exceeds the first edge 101 of the second sub-semiconductor member 122, that is, the second sub-metal member 142 covers the first edge 101 of the second sub-semiconductor member 122, and thus the first edge 101 of the second sub-semiconductor member 122 is not subjected to the heavy doping.

[0049] Specifically, the first metal layer 14 is subjected to the first patterning process, that is, the first metal layer 14 is subjected to the first etching process.

[0050] Step S500: The first metal layer is subjected to the second patterning process to reduce the width of the first sub-metal member and the second sub-metal member, the first edge exceeds the second edge, and the first sub-semiconductor member and the second sub-semiconductor member are subjected to the light doping process.

[0051] Specifically, as shown in FIG. 1, the first metal layer 14 is subjected to the second patterning process to reduce the width of the first sub-metal member 141 and the second sub-metal member 142, the first edge 101 exceeds the second edge 102, and the first sub-semiconductor member 121 and the second sub-semiconductor member 122 are subjected to the light doping process. Figure 5 Figure 6 Specifically, the first metal layer 14 is subjected to the second patterning process, that is, the first metal layer 14 is subjected to the second etching process.

[0052] Specifically, the first metal layer 14 is subjected to the second patterning process to reduce the width of the first sub-metal member 141, the first sub-metal member 141 forms a preset width, the first sub-metal member 141 is the gate of the transistor 10, and the width of the first sub-metal member 141 is reduced to form a preset gate width.

[0053] Specifically, the first metal layer 14 is subjected to the second patterning process to reduce the width of the first sub-metal member 141, the first sub-metal member 141 forms a preset width, the first sub-metal member 141 is the gate of the transistor 10, and the width of the first sub-metal member 141 is reduced to form a preset gate width.

[0054] ​Specifically, the first metal layer 14 is subjected to a second patterning process, so that the width of the second sub-metal piece 142 is reduced, and the second sub-metal piece 142 forms a preset width, and the second sub-metal piece 142 is formed by light doping to form a shield.

[0055] Specifically, when the first sub-semiconductor piece 121 and the second sub-semiconductor piece 122 are subjected to light doping treatment, the first sub-semiconductor piece 121 forms a first light doping region 1212, and the second sub-semiconductor piece 122 forms a second light doping region 1221. At this time, the second sub-semiconductor piece 122 of the test key 20 only has the second light doping region 1221, and does not have a heavy doping region.

[0056] Step S600: Forming a second insulating layer on the first metal layer.

[0057] Specifically, as shown in Figure 7 , the second insulating layer 15 is an interlayer dielectric layer (ILD), which is not limited here.

[0058] Step S700: Forming a second metal layer on the second insulating layer, and the second metal layer is subjected to a patterning process to form the source and drain of the transistor.

[0059] Specifically, the second metal layer 16 is formed on the second insulating layer 15, and the second metal layer 16 is subjected to a patterning process to form the source 161 and the drain 162 of the transistor 10.

[0060] Specifically, the source 161 and the drain 162 are respectively connected to the heavy doping region 1211 of the first sub-semiconductor piece 121 through different vias.

[0061] In some embodiments, in step S400, the length by which the second edge exceeds the first edge is 1-4 microns.

[0062] Specifically, as shown in Figure 4 , after the first patterning process of the first metal layer 14, the length d1 by which the second edge 102 exceeds the first edge 101 is 1-4 microns, and the length d1 by which the second edge 102 exceeds the first edge 101 is appropriate, so that after the second patterning process of the first metal layer 14, the part of the first edge 101 of the second sub-semiconductor piece 122 can be exposed.

[0063] Specifically, preferably, the length d1 by which the second edge 102 exceeds the first edge 101 is 2-3 microns, and the length d1 by which the second edge 102 exceeds the first edge 101 is greater than or equal to 2 microns, so that after the first patterning process of the first metal layer 14, the second edge 102 exceeds the first edge 101.

[0064] In some embodiments, the length by which the first edge exceeds the second edge is 1-4 microns in step S500.

[0065] Specifically, the length d2 by which the first edge 101 exceeds the second edge after the second patterning of the first metal layer 14 is 1-4 microns, which can provide a lightly doped portion of the first edge 101 of the second sub-semiconductor component 122.

[0066] Specifically, preferably, the length d2 by which the first edge 101 exceeds the second edge after the second patterning of the first metal layer 14 is 2-3 microns, and the length d1 by which the first edge 101 exceeds the second edge 102 is greater than or equal to 2 microns, so that the first edge 101 exceeds the second edge 102 after the second patterning of the first metal layer 14, and has an exposed portion.

[0067] In some embodiments, the first connection trace, the second connection trace, the first test terminal and the second test terminal are formed in step S700 when the second metal layer is patterned, and the two ends of the first connection trace are respectively connected to one end of the first edge of the second sub-semiconductor component and the first test terminal, and the two ends of the second connection trace are respectively connected to the other end of the first edge of the second sub-semiconductor component and the second test terminal.

[0068] Specifically, as shown in Figure 7 , Figure 8 In step S700, the first connection trace 163, the second connection trace 164, the first test terminal 165 and the second test terminal 166 are formed when the second metal layer 16 is patterned, the two ends of the first connection trace 163 are respectively connected to one end of the first edge 101 of the second sub-semiconductor component 122 and the first test terminal 165, and the two ends of the second connection trace 164 are respectively connected to the other end of the first edge 101 of the second sub-semiconductor component 122 and the second test terminal 166.

[0069] Specifically, the first connection trace 163 and the second connection trace 164 are respectively connected to the two ends of the first edge 101 of the second sub-semiconductor component 122 through different vias, for monitoring and testing the concentration of the lightly doped elements of the second lightly doped region 1221 between the two ends.

[0070] Specifically, the first test terminal 165 and the second test terminal 166 are connected by the external testing device, and the concentration of the light doping element of the second light doping region 1221 between the two terminals can be tested. The concentration of the light doping element of the second light doping region 1221 of the second sub-semiconductor piece 122 can represent the concentration of the light doping element of the first light doping region 1212 of the first sub-semiconductor piece 121, because the first sub-semiconductor piece 121 and the second sub-semiconductor piece 122 are simultaneously light doped by the same process.

[0071] In the embodiment of the present application, during the manufacturing process of the display panel or the array substrate, the test key 20 is provided, the first metal layer 14 is subjected to the first patterning process to form the first sub-metal piece 141 of the transistor 10 and the second sub-metal piece 142 of the test key 20, the second edge 102 of the second sub-metal piece 142 exceeds the first edge 101 of the second sub-semiconductor piece 122, and the second sub-semiconductor piece 122 of the test key 20 is not subjected to the heavy doping when the first sub-semiconductor piece 121 is subjected to the heavy doping. Then, after the second patterning process of the first metal layer 14, the first edge 101 of the second sub-semiconductor piece 122 exceeds the second edge 102 of the second sub-metal piece 142, and the first sub-semiconductor piece 121 exposed by the second sub-semiconductor piece 122 is subjected to the light doping. The part of the first edge 101 of the second sub-semiconductor piece 122 of the test key only has the light doping element, avoids the interference of the heavy doping element, and can well monitor and test the concentration of the light doping element.

[0072] Embodiment two,

[0073] The embodiment of the present application is the same as or similar to the above-mentioned embodiments, and the difference lies in that the metal layers of the first test terminal and the second test terminal are arranged differently.

[0074] In some embodiments, the first test terminal 165 and the second test terminal 166 are also formed when the first metal layer 14 is subjected to the patterning process in steps S400 and S500. In step S700, the first connection wire 163 and the second connection wire 164 are also formed when the second metal layer 16 is subjected to the patterning process, and the two ends of the first connection wire 163 are connected to one end of the first edge 101 of the second sub-semiconductor piece 122 and the first test terminal 165, respectively, and the two ends of the second connection wire 164 are connected to the other end of the first edge 101 of the second sub-semiconductor piece 122 and the second test terminal 166, respectively.

[0075] Specifically, the first test terminal 165 and the second test terminal 166 are formed by the first metal layer 14, the first connection wire 163 and the second connection wire 164 are formed by the second metal layer 16, and the related parts are connected by the via, which will not be described here.

[0076] Embodiment three,

[0077] The embodiment of the present application is the same as or similar to the above-mentioned embodiment, and the difference is that the structure and features of the above-mentioned embodiment are described in further detail.

[0078] In some embodiments, the shape of the second sub-semiconductor piece 122 includes at least one of a strip shape, an L shape, a U shape, and a V shape. Figure 8 The shape of the second sub-semiconductor piece 122 is exemplified as a strip shape in some embodiments.

[0079] In some embodiments, the material of the semiconductor layer 12 includes at least one of amorphous silicon or polycrystalline silicon.

[0080] In some embodiments, the heavily doped and lightly doped elements are pentavalent elements or trivalent elements.

[0081] In some embodiments, the material of the semiconductor layer includes polycrystalline silicon, and the heavily doped and lightly doped elements are phosphorus elements.

[0082] Embodiment four,

[0083] The embodiment of the present application also provides a display panel, which includes an array substrate, and the array substrate is manufactured by the manufacturing method of the array substrate of any one of the above.

[0084] It should be noted that the above-mentioned array substrate and display panel include a display area and a non-display area, and the test key can be arranged in the non-display area.

[0085] The manufacturing method of the array substrate and the display panel provided by the embodiment of the present application are described in detail above, and specific examples are applied in this paper to explain the principles and implementation modes of the present application. The above embodiment is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above-mentioned content of the description should not be understood as the limitation of the present application.

Claims

1. A method for manufacturing an array substrate, characterized in that, Includes the following steps: Step S100: Provide a substrate; Step S200: A semiconductor layer is formed on the substrate, and the semiconductor layer is patterned to simultaneously form a first sub-semiconductor device of a transistor and a second sub-semiconductor device of a test bond, the second sub-semiconductor device including a first edge; Step S300: Form a first insulating layer on the semiconductor layer; Step S400: A first metal layer is formed on the first insulating layer, and the first metal layer is patterned for the first time to form a first sub-metal component of the transistor and a second sub-metal component of the test bond, wherein the second sub-metal component includes a second edge, the first edge of the second sub-semiconductor component corresponds to the second edge of the second sub-metal component, the second edge extends beyond the first edge, and the first sub-semiconductor component is heavily doped. Step S500: Perform a second patterning process on the first metal layer to reduce the width of the first sub-metal element and the second sub-metal element, wherein the first edge extends beyond the second edge, and perform a light doping process on the first sub-semiconductor element and the second sub-semiconductor element; Step S600: Form a second insulating layer on the first metal layer; Step S700: A second metal layer is formed on the second insulating layer, and the second metal layer is patterned to form the source and drain of the transistor; In the array substrate prepared by the method of manufacturing the array substrate, the first sub-semiconductor includes a first lightly doped region and a heavily doped region, the second sub-semiconductor includes a second lightly doped region, and the second sub-semiconductor has no heavily doped region. In step S700, when the second metal layer is patterned, a first connection trace, a second connection trace, a first test terminal, and a second test terminal are also formed. The two ends of the first connection trace are respectively connected to one end of the first edge of the second sub-semiconductor and the first test terminal. The two ends of the second connection trace are respectively connected to the other end of the first edge of the second sub-semiconductor and the second test terminal.

2. The method for manufacturing an array substrate as described in claim 1, characterized in that, In step S400, the second edge extends from the first edge by a length of 1 micrometer to 4 micrometers.

3. The method for manufacturing an array substrate as described in claim 2, characterized in that, In step S500, the length by which the first edge extends beyond the second edge is 1 micrometer to 4 micrometers.

4. The method for manufacturing an array substrate as described in claim 1, characterized in that, In steps S400 and S500, a first test terminal and a second test terminal are also formed when the first metal layer is patterned. In step S700, when the second metal layer is patterned, a first connection trace and a second connection trace are also formed. The two ends of the first connection trace are respectively connected to one end of the first edge of the second sub-semiconductor and the first test terminal. The two ends of the second connection trace are respectively connected to the other end of the first edge of the second sub-semiconductor and the second test terminal.

5. The method for manufacturing an array substrate as described in claim 1, characterized in that, The shape of the second sub-semiconductor includes at least one of the following: bar shape, L-shape, U-shape, and V-shape.

6. The method for manufacturing an array substrate as described in claim 1, characterized in that, The semiconductor layer is made of at least one of amorphous silicon or polycrystalline silicon.

7. The method for manufacturing an array substrate as described in claim 6, characterized in that, The heavily doped and lightly doped elements are pentavalent or trivalent elements.

8. The method for manufacturing an array substrate as described in claim 7, characterized in that, The semiconductor layer is made of polycrystalline silicon, and the heavily doped and lightly doped elements are phosphorus.

9. A display panel, characterized in that, It includes an array substrate, which is manufactured using the method for manufacturing an array substrate as described in any one of claims 1 to 8.

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