Slave device and method for configuring its MIPI line sequence

Abstract

The embodiment of the present invention provides a slave device and a method for configuring the line sequence of MIPI thereof, the method comprising: step a, writing the first line sequence of the MIPI of the preset slave device into the first register; step b, setting the second register to the first value, and enabling all MIPI lines of the slave device and the pull-up resistors corresponding to all MIPI lines respectively based on the first value; step c, receiving the initialization instruction sent by the host device; step d, if the initialization instruction includes the second line sequence of the MIPI of the host device, writing the second line sequence into the first register, setting the second register to the second value, and configuring the line sequence of the MIPI of the slave device based on the second value and the second line sequence. The technical solution of the embodiment of the present invention does not need to set a dedicated pad for configuring the line sequence of the MIPI of the slave device, thereby saving pad resources on the slave IC.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a slave device and a method for configuring the line sequence of its MIPI. Background Art

[0002] Mobile Industry Processor Interface (MIPI) is an open standard and specification developed by the MIPI Alliance for mobile application processors. It is used to standardize the internal interfaces of mobile devices (also known as slave devices) into standard internal interfaces, including camera interface (Camera Serial Interface, CSI), display interface (Display Serial Interface, DSI), and radio frequency interface (Digital Radio Frequency, DigRF). The external device (also known as the host device) that communicates with the standard internal interface of the slave device includes a processor, which controls the communication with the slave device.

[0003] The standard internal interface of the mobile device has a physical layer module (for example, a D-PHY module or a C-PHY module); the physical layer module has multiple channels (Lane), including a data channel and a clock channel, and the data channel includes two operating modes: high-speed (HS) mode and low-power (LP) mode.

[0004] The line sequence of the MIPI of the host device may be different from that of the MIPI of the slave device. The existing solution is to set a dedicated pad on the integrated circuit (IC) of the slave to configure the MIPI line sequence. For example, for a 4-line MIPI application, 4 pads are generally occupied. However, setting a dedicated pad occupies more pad resources on the slave IC. Summary of the invention

[0005] The technical problem solved by the present invention is that setting a dedicated pad occupies more pad resources on the slave IC.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for configuring the line sequence of the MIPI of a slave device, comprising: step a, writing the first line sequence of the MIPI of a preset slave device into a first register; step b, setting the second register to a first value, and enabling all MIPI lines of the slave device and the pull-up resistors corresponding to all MIPI lines based on the first value; step c, receiving an initialization instruction sent by a host device; step d, if the initialization instruction includes the second line sequence of the MIPI of the host device, writing the second line sequence into the first register, setting the second register to a second value, and configuring the line sequence of the MIPI of the slave device based on the second value and the second line sequence.

[0007] Optionally, the method further includes: step e, if the initialization instruction does not include the line sequence information of the MIPI of the host device, setting the second register to a second value; and configuring the line sequence of the MIPI of the slave device based on the second value and the first line sequence.

[0008] Optionally, the MIPI line sequence includes the number of MIPI lines and their arrangement order.

[0009] Optionally, the first value is one of 0 or 1, and the second value is the other of 0 or 1.

[0010] Optionally, the method includes: based on the second value and the line sequence of the MIPI that needs to be configured by the slave device, keeping the pull-up resistors corresponding to the non-enabled MIPI lines enabled and disabling the pull-up resistors corresponding to the enabled MIPI lines.

[0011] Optionally, step c includes receiving an initialization instruction sent by the host device via an LP (Low Power) mode, where the initialization instruction includes a second line sequence.

[0012] Optionally, step a includes: configuring the LP output logic unit in the slave device as AND logic based on the first value; step c includes: the LP receiving unit in the slave device receives and outputs the initialization instruction on one MIPI line, and outputs a high level on the remaining MIPI lines; step d includes: one input end of the LP output logic unit receives the initialization instruction output by the LP receiving unit, the remaining input ends receive the high level output by the LP receiving unit, and the data of each input end is calculated by AND logic to output the initialization instruction, and the data processing unit in the slave device receives the initialization instruction output by the LP output logic unit to obtain a second line sequence, and writes it into the first register.

[0013] Optionally, the method includes: releasing the configuration of the AND logic of the LP output logic unit based on the second value, so that the enabled MIPI line directly outputs the data sent by the host device through the LP mode to the data processing unit.

[0014] Optionally, step c includes: an HS enabling control unit in the slave device detects an HS enabling sequence sent by the host device, and an HS receiving unit in the slave device receives an initialization instruction sent by the host device in HS (High Speed) mode.

[0015] Optionally, it includes: when the HS enable control unit detects the HS enable sequence, disabling the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located to receive the initialization instruction.

[0016] Optionally, it includes: after receiving the initialization instruction, enabling the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located.

[0017] Optionally, step c includes: the HS receiving unit in the slave device receives and outputs the initialization instruction to the data processing unit in the slave device; wherein the initialization instruction includes a data packet in HS format; step e includes: the data processing unit processes the initialization instruction according to the first line sequence to obtain the processed initialization instruction.

[0018] An embodiment of the present invention also provides a slave device, comprising: a first register, which is suitable for storing the line sequence of MIPI, and writing the received MIPI line sequence as the MIPI line sequence of the slave device into the first register; a second register, which is suitable for storing the instruction sent by the data processing unit, and configuring the second register to be a first value or a second value based on the instruction; a plurality of receiving units, which are respectively arranged on each MIPI line of the slave device, and are suitable for receiving and outputting the initialization instruction sent by the host device, and enabling each MIPI line based on the first value; a plurality of pull-up resistors, which respectively correspond to each MIPI line, and are suitable for enabling the plurality of pull-up resistors based on the first value; a data processing unit, which is suitable for receiving the initialization instruction sent by the receiving unit; wherein, if the initialization instruction includes the line sequence of the MIPI of the host device, the line sequence of the MIPI of the host device is written into the first register.

[0019] Optionally, the pull-up resistor is adapted to keep the pull-up resistor corresponding to the non-enabled MIPI line enabled and disable the pull-up resistor corresponding to the enabled MIPI line based on the second value and the MIPI line sequence of the slave device.

[0020] Optionally, the receiving unit is an LP receiving unit, which is suitable for receiving and outputting an initialization instruction sent by the host device through the LP mode on a MIPI line and outputting a high level on the remaining MIPI lines, wherein the initialization instruction includes the line sequence of the MIPI of the host device; the slave device also includes an LP output logic unit, which is suitable for being configured as AND logic based on a first value, one input end of which receives the initialization instruction output by the LP receiving unit, and the remaining input ends receive the high level output by the LP receiving unit, and performs AND logic calculation on the data of each input end to output the initialization instruction; the data processing unit is suitable for receiving the initialization instruction output by the LP output logic unit.

[0021] Optionally, the LP output logic unit is adapted to release the configuration of its AND logic based on the second value, so that the enabled MIPI lane outputs the data sent by the host device through the LP mode directly to the data processing unit.

[0022] Optionally, the receiving unit is a HS receiving unit, which is suitable for receiving an initialization instruction sent by the host device through the HS mode.

[0023] Optionally, it also includes: an HS enable control unit, which is suitable for detecting the HS enable sequence in the initialization instruction and sending a release instruction for enabling to the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located, and sending a restore instruction for enabling to the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located after the initialization instruction is sent; wherein the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located is suitable for receiving a release instruction to disengage and receiving a restore instruction to restore.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention does not need to set a dedicated pad for configuring the line sequence of the slave device MIPI, thereby saving pad resources on the slave IC. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a slave device in an embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a communication system including a slave device and a host device in an embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of another slave device in an embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of another slave device in an embodiment of the present invention;

[0029] Figure 5 It is a schematic diagram of a method for configuring a MIPI line sequence of a slave device in an embodiment of the present invention;

[0030] Figure 6 It is a schematic diagram of another method for configuring the MIPI line sequence of a slave device in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In an embodiment of the present invention, the slave device may communicate with the host device via one or more MIPI lines, and the communication mode may be LP mode or HS mode.

[0032] The slave device may be a mobile device including a standard internal interface MIPI (eg, CSI, DSI, DigRF); the host device may be a device including a processor to control communication with the slave device.

[0033] In the drawings of the present invention, the same reference numerals represent the same components or steps, which have the same or similar functions, positional relationships, and connection relationships.

[0034] In order to make the above-mentioned purposes, features and beneficial effects of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 is a schematic diagram of a slave device 100 according to an embodiment of the present invention; Figure 2 is a schematic diagram of a communication system including a slave device 100 and a host device 200 according to an embodiment of the present invention.

[0036] The slave device 100 can communicate with the host device 200 through one or more MIPI lines D0, D1, ..., DN, and the communication mode can be LP mode or HS mode.

[0037] The slave device 100 includes a first register 110 , a second register 120 , a plurality of receiving units 130 , a plurality of pull-up resistors 140 , and a data processing unit 150 .

[0038] The first register 110 , which may also be referred to as a line sequence register, may receive a line sequence of the MIPI and write the received line sequence of the MIPI into the first register 110 as the line sequence of the MIPI of the slave device 100 .

[0039] The MIPI line sequence (ie, the first line sequence) of the slave device may be preconfigured before the slave device communicates with the host device. The MIPI line sequence may include the number of MIPI lines and their arrangement order.

[0040] In a specific implementation, after obtaining the initialization instruction sent by the host device 200, the data processing unit 150 can send an instruction to the first register 110. After receiving the instruction, the first register 110 can obtain the line sequence of MIPI, for example, obtain the line sequence of MIPI stored in a memory (such as a one-time programmable memory, One Time Programmable, OTP), and then write the received MIPI line sequence as the MIPI line sequence of the slave device 100.

[0041] Based on the line sequence of MIPI configured by the first register 110, the data processing unit 150 can determine the disabled MIPI lines and the enabled MIPI lines; the data processing unit 150 can directly or through the first register 110 keep the pull-up resistor 140 corresponding to the disabled MIPI line enabled to avoid leakage and other faults caused by the pad of the MIPI line that is not connected to the host device 200 in the slave device 100 being suspended, and disable the pull-up resistor 140 corresponding to the enabled MIPI line, so that the slave device 100 and the host device 200 can communicate based on the enabled MIPI line.

[0042] The second register 120 , which may also be referred to as a flag register, may store one or more bits of data.

[0043] The second register 120 can receive an instruction sent by the data processing unit 150, and configure the second register 120 (for example, its flag bit) to a first value or a second value based on the instruction, wherein the first value can be one of 0 or 1, and the second value can be the other of 0 or 1.

[0044] For example, before the slave device 100 communicates with the host device 200 , the data processing unit 150 may send an instruction to the second register 120 , and after receiving the instruction, the second register 120 sets the second register 120 to the first value.

[0045] For another example, after obtaining the initialization instruction sent by the host device 200, the data processing unit 150 may send an instruction to the second register 120, and after receiving the instruction, the second register 120 sets the second register 120 to the second value.

[0046] When the value of the second register 120 is set to the first value, since the slave device 100 does not know which MIPI lines the host device 200 will send initialization instructions from, the data processing unit 150 can enable all MIPI lines of the slave device 100 (for example, enable each receiving unit 130 on all MIPI lines) directly or through the second register 120 to ensure that the slave device 100 can receive the initialization instructions of the host device 200, and can also enable the pull-up resistors 140 corresponding to all MIPI lines directly or through the second register 120 to avoid leakage and other faults caused by the pads of the MIPI lines in the slave device 100 that are not connected to the host device being suspended.

[0047] When the value of the second register 120 is set to the second value, the data processing unit 150 can configure the line sequence of the MIPI of the slave device 100; and the non-enabled MIPI lines and the enabled MIPI lines can be determined based on the line sequence of the MIPI currently configured by the first register 110. The data processing unit 150 can directly or through the second register 120 keep the pull-up resistor 140 corresponding to the non-enabled MIPI line enabled to avoid leakage and other faults caused by the pad of the MIPI line that is not connected to the host device 200 in the slave device 100 being suspended, and disenable the pull-up resistor 140 corresponding to the enabled MIPI line so that the slave device 100 and the host device 200 can communicate based on the enabled MIPI line.

[0048] The plurality of receiving units 130 are respectively arranged on each MIPI line of the slave device 100 , and can receive and output the initialization instruction sent by the host device 200 .

[0049] When the host device 200 sends the initialization instruction in the LP mode, the receiving unit 130 may include an LP receiving unit (such as Figure 3 When the host device 200 sends an initialization instruction in HS mode, the receiving unit 130 may include a HS receiving unit (such as Figure 4 132).

[0050] The multiple receiving units 130 can enable all MIPI lines based on the first value. The multiple receiving units 130 can also enable corresponding MIPI lines based on the second value, and the corresponding MIPI lines can be enabled MIPI lines determined according to the line sequence of the MIPI currently configured by the first register 110.

[0051] In a specific implementation, the data processing unit 150 may enable one or more receiving units 130 directly or through the second register 120 , thereby enabling the corresponding MIPI lines.

[0052] The plurality of pull-up resistors 140 may correspond to respective MIPI lines.

[0053] The pull-up resistors 140 respectively corresponding to all MIPI lanes may be enabled based on the first value.

[0054] In a specific implementation, when the second register 120 is set to the first value, the data processing unit 150 can enable the pull-up resistors 140 corresponding to all MIPI lines respectively directly or through the second register 120 .

[0055] The pull-up resistor 140 corresponding to the relevant MIPI line may also be enabled and disabled based on the second value.

[0056] In a specific implementation, when the second register 120 is set to the second value, the data processing unit 150 determines the disabled MIPI lines and the enabled MIPI lines based on the line sequence of the MIPI currently configured by the first register 110, wherein the data processing unit 150 can directly or through the second register 120 keep the pull-up resistor 140 corresponding to the disabled MIPI line enabled to avoid the pad of the MIPI line in the slave device 100 that is not connected to the host device 200 being suspended and causing leakage, and disenable the pull-up resistor 140 corresponding to the enabled MIPI line so that the slave device 100 and the host device 200 can communicate based on the enabled MIPI line.

[0057] In an embodiment of the present invention, enabling the pull-up resistor 140 includes connecting the pad 160 of the slave device 100 to a high level.

[0058] The data processing unit 150 may receive the initialization instruction sent by the receiving unit 130 ; if the initialization instruction includes the line sequence of the MIPI of the host device 200 , the line sequence of the MIPI of the host device 200 is written into the first register 110 .

[0059] The data processing unit 150 may send an instruction to the first register 110 , and the first register 110 may receive and obtain the line sequence of the MIPI based on the instruction, and then write the received line sequence of the MIPI as the line sequence of the MIPI of the slave device 100 therein.

[0060] The data processing unit 150 may also send an instruction to the second register 120 , and the second register 120 may receive and configure the second register 120 (eg, a flag bit thereof) to the first value or the second value based on the instruction.

[0061] Figure 3It is a schematic diagram of another slave device 300 in an embodiment of the present invention, wherein the slave device 300 can communicate with the host device 200 through one or more MIPI lines D0, D1, ..., DN, and the communication mode is LP mode.

[0062] Figure 3 Different from Figure 1 In other words, the receiving unit 130 includes an LP receiving unit 131 and further includes an LP output logic unit 170 .

[0063] The LP receiving unit 131 can receive and output an initialization instruction sent by the host device 200 in LP mode on one MIPI line and output a high level on the remaining MIPI lines; wherein the initialization instruction includes or does not include the line sequence information of the MIPI of the host device 200 .

[0064] The LP output logic unit 170 can be configured as AND logic based on the first value, one input end of which receives the initialization instruction output by the LP receiving unit 131, and the other input ends receive the high level output by the LP receiving unit 131, and performs AND logic calculation on the data of each input end to output the initialization instruction.

[0065] The data processing unit 150 may receive the initialization instruction output by the LP output logic unit 170 .

[0066] If the received initialization instruction includes the second line order of the MIPI of the host device 200, the second line order is written into the first register 110, the second register 120 is set to a second value, and the line order of the MIPI of the slave device 100 is configured based on the second value and the second line order.

[0067] If the received initialization instruction does not include the line sequence information of the MIPI of the host device 200 , the second register 120 is set to a second value; and the line sequence of the MIPI of the slave device 100 is configured based on the second value and the first line sequence.

[0068] The LP output logic unit 170 may also release its AND logic configuration based on the second value, so that data subsequently sent by the host device 200 in the LP mode may be directly output to the data processing unit 150 through the LP output logic unit 170 .

[0069] Figure 4 It is a schematic diagram of another slave device 400 in an embodiment of the present invention, wherein the slave device 400 can communicate with the host device 200 through one or more MIPI lines D0, D1, ..., DN, and the communication mode is HS mode.

[0070] Figure 4 Different from Figure 1In other words, the receiving unit 130 includes a HS receiving unit 132 and further includes a HS enabling control unit 180 .

[0071] The HS receiving unit 132 may receive an initialization instruction sent by the host device 200 through the HS mode.

[0072] The HS enable control unit 180 can detect the HS enable sequence in the initialization instruction to determine the line sequence used by the host device 200; then send an enable release instruction to the pull-up resistor 140 corresponding to the MIPI line where the HS enable sequence is located so that the slave device 400 and the host device 200 can communicate based on the MIPI line where the HS enable sequence is located, and the data processing unit 150 can therefore receive the initialization instruction sent by the host device 200 through the HS receiving unit 132.

[0073] After receiving the initialization instruction, the subsequent communication between the slave device 400 and the host device 200 may be based on the LP mode instead of the HS mode, that is, the data sent by the host device 200 through the LP mode is output to the data processing unit 150 via the LP receiving unit and directly through the LP output logic unit. Therefore, after the initialization instruction is sent, an enable recovery instruction can be sent to the pull-up resistor 140 corresponding to the MIPI line where the HS enable sequence is located.

[0074] exist Figure 4 In the illustrated embodiment, since the initialization instruction does not include the line sequence information of the MIPI of the host device 200, the second register 120 can be set to a second value, and the line sequence of the MIPI of the slave device 100 can be configured based on the second value and the first line sequence, so that the enabled MIPI line outputs the data subsequently sent by the host device 200 through the LP mode directly to the data processing unit 150 through the LP receiving unit 131.

[0075] Figure 5 is a flow chart of a method 500 for configuring a MIPI line sequence of a slave device in an embodiment of the present invention; Figure 6 It is a flowchart of another method 600 for configuring the MIPI line sequence of a slave device according to an embodiment of the present invention.

[0076] Both methods 500 and 600 include the following steps:

[0077] Step a, writing the first line sequence of the MIPI of the preset slave device into the first register;

[0078] Step b, setting the second register to a first value, and enabling all MIPI lines of the slave device and the pull-up resistors corresponding to all MIPI lines respectively based on the first value;

[0079] Step c: receiving an initialization instruction sent by the host device.

[0080] In the execution of step a, the slave device has a preset MIPI line sequence (ie, a first line sequence); the slave device may include a first register, which may store the MIPI line sequence of the slave device. The MIPI line sequence may include the number of MIPI lines and their arrangement order.

[0081] During the execution of step b, the second register is set to a first value; the slave device may include a second register which may store one or more bits of data.

[0082] Specifically, the value of the second register can be set to a first value or a second value, wherein the first value is one of 0 or 1, and the second value is the other of 0 or 1.

[0083] When the value of the second register is set to the first value, since the slave device does not know which MIPI lines the host device will send the initialization instruction from, all MIPI lines of the slave device can be enabled to ensure that the slave device can receive the initialization instruction of the host device, and the pull-up resistors corresponding to all MIPI lines can be enabled to avoid leakage and other faults caused by the pad of the MIPI line that is not connected to the host device in the slave device being left floating.

[0084] When the value of the second register is set to the second value, the line sequence of the MIPI of the slave device can be configured; and the non-enabled MIPI lines and enabled MIPI lines can be determined based on the line sequence of the MIPI configured by the slave device (which is the line sequence currently configured by the first register), and the pull-up resistors corresponding to the non-enabled MIPI lines are kept enabled to avoid leakage and other faults caused by the pads of the MIPI lines in the slave device that are not connected to the host device being left hanging, and the pull-up resistors corresponding to the enabled MIPI lines are disabled so that the slave device and the host device can communicate based on the enabled MIPI lines.

[0085] During the execution of step c, an initialization instruction sent by the host device is received.

[0086] Specifically, the host device may send the initialization instruction in LP mode or HS mode.

[0087] Before the host device communicates with the slave device, it can be manually determined in advance through the hardware information of the host device and the slave device whether the MIPI line sequence of the host device and the slave device is consistent. When it is manually determined that the MIPI line sequence of the host device and the slave device is inconsistent, the initialization instruction must include the MIPI line sequence of the host device, and it is necessary to manually select the host device to send the initialization instruction to the slave device through the LP mode. When it is manually determined that the MIPI line sequence of the host device and the slave device is consistent, the initialization instruction does not need to include the MIPI line sequence of the host device, and the host device is manually selected to send the initialization instruction to the slave device through the HS mode or the LP mode.

[0088] In some embodiments, the slave device may execute step d based on the determination result, such as Figure 5 shown.

[0089] Specifically, if the judgment result is that the initialization instruction includes the second line sequence of the MIPI of the host device, the second line sequence is written to the first register, the second register is set to the second value, and the line sequence of the MIPI of the slave device is configured based on the second value and the second line sequence.

[0090] For example, when the second register is set to the second value, the disabled MIPI lines and the enabled MIPI lines are determined according to the second line sequence, the pull-up resistors corresponding to the disabled MIPI lines are kept enabled, and the pull-up resistors corresponding to the enabled MIPI lines are disabled.

[0091] In a specific implementation, if the judgment result is that the initialization instruction includes the second line sequence, the host device may send the initialization instruction through the LP mode, and may include specific execution of the following steps.

[0092] During the execution of step a, the LP output logic unit in the slave device may be configured as an AND logic based on the first value.

[0093] During the execution of step c, the LP receiving unit in the slave device may receive and output the initialization instruction sent by the host device through the LP mode on one MIPI line, and output a high level on the remaining MIPI lines.

[0094] In the execution of step d, the value of the second register is set to the second value, and the disabled MIPI line and the enabled MIPI line can be determined based on the second line sequence currently configured by the first register, and the pull-up resistor corresponding to the disabled MIPI line is kept enabled. Optionally, the pull-up resistor corresponding to the enabled MIPI line is disabled.

[0095] During the execution of step d, the value of the second register is set to the second value, one input end of the LP output logic unit can receive the initialization instruction output by the LP receiving unit, and the remaining input ends can receive the high level output by the LP receiving unit, and the data of each input end is subjected to logical calculation to output the initialization instruction, and the data processing unit in the slave device receives the initialization instruction output by the LP output logic unit to obtain the second line sequence, and writes it into the first register.

[0096] After step d is executed, the AND logic configuration of the LP output logic unit can be released based on the second value, so that data subsequently sent by the host device through the LP mode can be directly output to the data processing unit through the LP output logic unit.

[0097] In other embodiments, the slave device may execute step e based on the determination result, such as Figure 6 shown.

[0098] Specifically, if the judgment result is that the initialization instruction does not include the second line sequence of the MIPI of the host device, the second register is set to a second value; and the line sequence of the MIPI of the slave device is configured based on the second value and the first line sequence.

[0099] For example, when the second register is set to the second value, the disabled MIPI lines and the enabled MIPI lines are determined according to the first line sequence, the pull-up resistors corresponding to the disabled MIPI lines are kept enabled, and the pull-up resistors corresponding to the enabled MIPI lines are disabled.

[0100] In a specific implementation, if the judgment result is that the initialization instruction does not include the second line sequence, the host device may send the initialization instruction in LP mode, and may include specific execution of the following steps.

[0101] During the execution of step a, the LP output logic unit in the slave device may be configured as an AND logic based on the first value.

[0102] During the execution of step c, the LP receiving unit in the slave device may receive and output the initialization instruction sent by the host device through the LP mode on one MIPI line, and output a high level on the remaining MIPI lines.

[0103] In the execution of step e, the value of the second register is set to the second value, and the non-enabled MIPI line and the enabled MIPI line can be determined based on the first line sequence currently configured by the first register, and the pull-up resistor corresponding to the non-enabled MIPI line is kept enabled to avoid leakage and other faults caused by the pad of the MIPI line that is not connected to the host in the slave device being suspended. Optionally, the pull-up resistor corresponding to the enabled MIPI line is disabled so that the slave device and the host device can communicate based on the enabled MIPI line.

[0104] During the execution of step e, the value of the second register is set to the second value, one input end of the LP output logic unit can receive the initialization instruction output by the LP receiving unit, and the remaining input ends can receive the high level output by the LP receiving unit, and the data of each input end is subjected to logical calculation to output the initialization instruction, and the data processing unit in the slave device receives the initialization instruction output by the LP output logic unit.

[0105] After step e is executed, the AND logic configuration of the LP output logic unit can be released based on the second value, so that data subsequently sent by the host device through the LP mode can be directly output to the data processing unit through the LP output logic unit.

[0106] In a specific implementation, if the judgment result is that the initialization instruction does not include the second line sequence, the host device may also send the initialization instruction in HS mode, and may include the specific execution of the following steps.

[0107] During the execution of step c, the host device may first send an HS enable sequence, and the HS enable control unit in the slave device may detect the HS enable sequence so as to disable the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located to receive the initialization instruction; the HS enable control unit may also control whether the HS receiving unit receives the initialization instruction based on the detected HS enable sequence; the HS receiving unit in the slave device may receive and output the initialization instruction sent by the host device through the HS mode.

[0108] For example, the HS receiving unit receives and outputs an initialization instruction to a data processing unit in the slave device, wherein the initialization instruction includes a data packet in the HS format.

[0109] During the execution of step e, the data processing unit may process the initialization instruction to obtain a processed initialization instruction.

[0110] In the execution of step e, since the subsequent communication between the host device and the slave device after receiving the initialization instruction may be based on the LP mode instead of the HS mode, the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located may be enabled.

[0111] In the execution of step e, the disabled MIPI lines and the enabled MIPI lines can be determined according to the line sequence currently configured by the first register (ie, the first line sequence), and the pull-up resistors corresponding to the enabled MIPI lines can be disabled.

[0112] During the execution of step e, the pull-up resistor corresponding to the non-enabled MIPI line can be kept enabled to avoid leakage and other faults caused by the pad of the MIPI line that is not connected to the host in the slave device being suspended.

[0113] After step e is executed, data subsequently sent by the host device in the LP mode can be output to the data processing unit via the LP receiving unit and directly through the LP output logic unit.

[0114] The various methods for configuring the MIPI line sequence of the slave device in the embodiments of the present invention can be based on the above combination Figures 1 to 4 Therefore, the execution of each step in the method and the relationship between them can also refer to the above description about the slave device, which will not be repeated here.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for configuring the line sequence of MIPI of a slave device, characterized in that: include: Step a, writing the first line sequence of the MIPI of the preset slave device into the first register; Step b, setting the second register to a first value, and enabling all MIPI lines of the slave device and the pull-up resistors corresponding to all the MIPI lines respectively based on the first value; Step c, receiving an initialization instruction sent by the host device; Step d: if the initialization instruction includes the second line sequence of the MIPI of the host device, write the second line sequence into the first register, set the second register to a second value, and configure the line sequence of the MIPI of the slave device based on the second value and the second line sequence.

2. The method according to claim 1, characterized in that The method further includes: step e, if the initialization instruction does not include the MIPI line sequence information of the host device, setting the second register to a second value; and configuring the MIPI line sequence of the slave device based on the second value and the first line sequence.

3. The method according to claim 1 or 2, characterized in that: The MIPI line sequence includes the number of MIPI lines and their arrangement order.

4. The method according to claim 1 or 2, characterized in that: The first value is one of 0 or 1, and the second value is the other of 0 or 1.

5. The method according to claim 1 or 2, characterized in that: include: Based on the second value and the line sequence of the MIPI that the slave device needs to configure, the pull-up resistors corresponding to the non-enabled MIPI lines are kept enabled and the pull-up resistors corresponding to the enabled MIPI lines are disabled.

6. The method according to claim 1, characterized in that Step c includes receiving the initialization instruction sent by the host device through the low power consumption LP mode, and the initialization instruction includes the second line sequence.

7. The method according to claim 6, characterized in that Step a includes: configuring the LP output logic unit in the slave device to be AND logic based on the first value; Step c comprises: the LP receiving unit in the slave device receives and outputs the initialization instruction on one MIPI line, and outputs a high level on the remaining MIPI lines; Step d includes: one input end of the LP output logic unit receives the initialization instruction output by the LP receiving unit, the other input ends receive the high level output by the LP receiving unit, and the data of each input end is subjected to a logic calculation to output the initialization instruction; the data processing unit in the slave device receives the initialization instruction output by the LP output logic unit to obtain the second line sequence, and writes it into the first register.

8. The method according to claim 7, characterized in that include: The AND logic configuration of the LP output logic unit is released based on the second value, so that the enabled MIPI line directly outputs the data sent by the host device through the LP mode to the data processing unit.

9. The method according to claim 2, characterized in that: Step c includes: the high-speed HS enabling control unit in the slave device detects the HS enabling sequence sent by the host device, and the HS receiving unit in the slave device receives the initialization instruction sent by the host device through the HS mode.

10. The method according to claim 9, characterized in that include: When the HS enable control unit detects the HS enable sequence, the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located is disabled to receive the initialization instruction.

11. The method according to claim 10, characterized in that include: After receiving the initialization instruction, the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located is enabled.

12. The method according to claim 2, characterized in that: Step c comprises: the high-speed HS receiving unit in the slave device receives and outputs the initialization instruction to the data processing unit in the slave device; wherein the initialization instruction comprises a data packet in HS format; Step e includes: the data processing unit processes the initialization instruction according to the first line sequence to obtain a processed initialization instruction.

13. A slave device, characterized in that: include: A first register, which is adapted to receive a line sequence of MIPI, and write the received line sequence of MIPI into the first register as the line sequence of MIPI of the slave device; A second register, which is adapted to receive an instruction sent by a data processing unit, and configure the second register to a first value or a second value based on the instruction; the first value is 0, and the second value is 1; or the first value is 1, and the second value is 0; A plurality of receiving units, which are respectively arranged on each MIPI line of the slave device and are adapted to receive and output an initialization instruction sent by the host device, and enable each MIPI line based on the first value; a plurality of pull-up resistors, which correspond to the MIPI lines respectively and are adapted to be enabled based on the first value; A data processing unit is adapted to receive the initialization instruction sent by the receiving unit; wherein, if the initialization instruction includes the line sequence of the MIPI of the host device, the line sequence of the MIPI of the host device is written into the first register.

14. The slave device according to claim 13, characterized in that: The pull-up resistor is adapted to keep the pull-up resistor corresponding to the non-enabled MIPI line enabled and disable the pull-up resistor corresponding to the enabled MIPI line based on the second value and the MIPI line sequence of the slave device.

15. The slave device according to claim 13, characterized in that: The receiving unit is a low power consumption LP receiving unit, which is adapted to receive and output the initialization instruction sent by the host device in LP mode on one MIPI line and output a high level on the remaining MIPI lines, wherein the initialization instruction includes the line sequence of the MIPI of the host device; The slave device further comprises an LP output logic unit, which is adapted to be configured as an AND logic based on the first value, wherein one input terminal receives the initialization instruction output by the LP receiving unit, and the remaining input terminals receive the high level output by the LP receiving unit, and performs an AND logic calculation on the data of each input terminal to output the initialization instruction; The data processing unit is adapted to receive the initialization instruction output by the LP output logic unit.

16. The slave device according to claim 15, characterized in that: The LP output logic unit is adapted to release its AND logic configuration based on the second value, so that the enabled MIPI line directly outputs the data sent by the host device through the LP mode to the data processing unit.

17. The slave device according to claim 13, characterized in that: The receiving unit is a high-speed HS receiving unit, which is suitable for receiving the initialization instruction sent by the host device through the HS mode.

18. The slave device according to claim 17, characterized in that: Also includes: An HS enable control unit, which is adapted to detect the HS enable sequence in the initialization instruction and send a release instruction for enabling to the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located, and send a restore instruction for enabling to the pull-up resistor corresponding to the MIPI line where the HS enable sequence is located after the initialization instruction is sent; The pull-up resistor corresponding to the MIPI line where the HS enable sequence is located is suitable for receiving the release instruction to release the enablement and receiving the restore instruction to restore the enablement.

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