Memory card device ensuring information security and chip control method used therein

Abstract

The embodiment of the present invention relates to a memory card device for ensuring information security and a chip control method used therein. The memory card device includes a non-volatile memory device; a security chip and a non-volatile memory controller. The non-volatile memory controller is connected to a host by signal. The non-volatile memory controller responds to a single instruction of a single instruction cycle issued by the host and interacts with the security chip to complete encryption-related procedures.

Description

Technical Field

[0001] The present invention relates to the technical field of memory cards, and in particular to a memory card device for ensuring information security and a chip control method used in the memory card device. Background Art

[0002] With the popularization of information technology, many important data that need to be kept confidential (various accounts and passwords) are stored together with general data in the user's information device, such as common personal computers, laptops or popular smart phones, and portable devices will exchange data or conduct financial transactions with other information devices through various data transmission channels (such as USB interfaces or the Internet, etc.). Therefore, if the important data that needs to be kept confidential is not properly stored, such data is very likely to be stolen and cause significant losses. However, few information devices in the hands of users today have such functions. Only a few newly launched information devices may have built-in data security modules to complete the function of data security storage, and most existing information processing devices cannot obtain data encryption functions through simple installation.

[0003] In order to effectively improve this defect, existing old organic species can easily add data security storage functions, such as Figure 1 The memory card 11 with information security function is invented. It is mainly composed of a common memory card (such as a microSD card in a secure digital memory card (SD)) plus a secure chip (Secure Element) 119 that has passed CCEAL5+ certification, and is used to provide functions such as cryptographic services, key management, and data storage. Figure 1As can be seen in FIG. 1 , when the application 100 in the host 10 has a need to perform a data encryption program, the application 100 can issue an encryption instruction, and the file system 101 can respond to the encryption instruction issued by the application 100 to issue a default special combination 102 to the flash memory controller 110 in the memory card 11. The default special combination 102 can be composed of multiple and continuous read and write commands. For example, the default special combination 102 can be a continuous read command (Read command) twice and a write command (Write command) once. The default special combination 102 will trigger the flash memory controller 110 to establish a vendor command tunnel (Vendor commands Tunnel, referred to as VC Tunnel) 103 with the file system 101. When the vendor command pipeline 103 is established, a write command sent by the file system 101 through the vendor command pipeline 103 will be identified as a vendor command by the flash memory controller 110. Therefore, when the vendor command is defined as a data encryption-related action in advance, the flash memory controller 110 can be used to complete the encryption action corresponding to the encryption instruction. For example, the content of the vendor command is: to enable the flash memory controller 110 to transmit a piece of data related to the write command to the security chip 119 for encryption, and then transmit it back to the application through the vendor command pipeline 103 or store it in the flash memory 111 after encryption.

[0004] However, it can be seen from the above description that the common method is to use the default special combination 102 of multiple consecutive read and write commands to further define the vendor command (Vendor command), and then "establish a vendor command pipeline" to perform subsequent encryption instructions, and the flash memory controller 110 and the security chip 119 communicate using the traditional ISO-7816 smart card communication protocol. However, the default special combination 102 is too complicated and wastes instruction cycles, and the maximum operating frequency of ISO-7816 can only reach 1.25MHz, and the configuration of the three pins (IO / CLK / RST0) can only perform half-duplex signal transmission. The data processing speed is too slow and cannot meet the current requirements. Summary of the invention

[0005] In order to improve the deficiencies of the above-mentioned common methods, the inventors propose the following technical concepts and implementation methods.

[0006] On the one hand, an embodiment of the present invention provides a memory card device for ensuring information security, which is used to complete a signal connection with a host, and includes: a non-volatile memory device for storing data; a security chip; and a non-volatile memory controller, which is signal-connected to the host, the non-volatile memory device and the security chip, and the non-volatile memory controller interacts with the security chip in response to a security chip control instruction issued by the host, wherein the security chip control instruction includes a single instruction of a single instruction cycle, and the single instruction of the single instruction cycle includes a first special address corresponding to the security chip, and the non-volatile memory controller also interacts with the non-volatile memory device but not with the security chip in response to a non-security chip control instruction issued by the host, and the non-security chip control instruction includes a regular address unrelated to the security chip, and the regular address is different from the first special address.

[0007] In one embodiment of the present invention, the security chip control instruction includes a file system in the host executing a write command to the non-volatile memory controller to the first special address, and the first special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the first special address, the write command to the first special address will set the encryption mode of the security chip.

[0008] In one embodiment of the present invention, the security chip has multiple encryption modes, and the write command of the first special address is used to set the security chip to a first encryption mode, and the write command of the second special address is used to set the security chip to a second encryption mode.

[0009] In one embodiment of the present invention, the security chip control instruction includes a write command from a file system in the host to the non-volatile memory controller to write a first specific data to a third special address, and the third special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the third special address, it will rewrite a set of parameters of the security chip, and the content of the first specific data is the parameter value to be rewritten.

[0010] In one embodiment of the present invention, the security chip control instruction includes a write command from a file system in the host to the non-volatile memory controller to a fourth special address, where the fourth special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the fourth special address, the write command to the fourth special address will be used to read specific information of the security chip from the security chip.

[0011] In one embodiment of the present invention, the specific information of the security chip is a firmware version. The security chip transmits the firmware version back to the non-volatile memory controller, and the firmware writes the firmware version into the reserved area or temporarily stores it in the non-volatile memory controller, and the file system reads the firmware version back from the reserved area or the non-volatile memory controller.

[0012] In one embodiment of the present invention, the security chip control instruction includes a write command for a file system in the host to write a second specific data to a fifth special address of the non-volatile memory controller, and the fifth special address is located in a reserved area of ​​the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the fifth special address, it drives the security chip to encrypt the second specific data and transmit the encrypted data back to the non-volatile memory controller, and the firmware writes the encrypted data to the reserved area or temporarily stores it in the non-volatile memory controller, and the file system reads the encrypted data back from the reserved area or the non-volatile memory controller.

[0013] In one embodiment of the present invention, the single instruction of the single instruction cycle is a data access command to a specific address.

[0014] In one embodiment of the present invention, the special address is in the form of a default multi-digit number.

[0015] In one embodiment of the present invention, the special address is a dynamic address selected from a plurality of multi-digit numbers that conform to a specific formula.

[0016] In a second aspect, an embodiment of the present invention provides a chip control method, which is applied between a host and a memory card device, wherein the memory card device includes a non-volatile memory device, a security chip and a non-volatile memory controller, and the chip control method includes the following steps: the host sends a security chip control instruction to the non-volatile memory controller, and the security chip control instruction includes a single instruction of a single instruction cycle; the non-volatile memory controller interacts with the security chip in response to the single instruction of the single instruction cycle, and the single instruction of the single instruction cycle includes a first special address corresponding to the security chip; and the non-volatile memory controller interacts with the non-volatile memory device but not with the security chip in response to a non-security chip control instruction sent by the host, and the non-security chip control instruction includes a regular address unrelated to the security chip, and the regular address is different from the first special address.

[0017] In one embodiment of the present invention, the security chip control instruction includes a write command from a file system in the host to the non-volatile memory controller to a first special address, and the first special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the first special address, the write command of the first special address will set the encryption mode of the security chip.

[0018] In one embodiment of the present invention, the security chip has multiple encryption modes, the write command of the first special address is used to set the security chip to a first encryption mode, and the write command of the second special address is used to set the security chip to a second encryption mode.

[0019] In one embodiment of the present invention, the security chip control instruction includes a write command from a file system in the host to the non-volatile memory controller to write a first specific data to a third special address, and the third special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the third special address, it will rewrite a set of parameters of the security chip, and the content of the first specific data is the parameter value to be rewritten.

[0020] In one embodiment of the present invention, the security chip control instruction includes a file system in the host to issue a write command to the non-volatile memory controller to a fourth special address, and the fourth special address is located in a reserved area range in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the fourth special address, the write command of the fourth special address will be used to read specific information of the security chip from the security chip.

[0021] In one embodiment of the present invention, the specific information of the security chip is the firmware version. The security chip transmits the firmware version of the security chip back to the non-volatile memory controller, and the firmware writes the firmware version of the security chip into the reserved area, and the file system reads the firmware version of the security chip back from the reserved area.

[0022] In one embodiment of the present invention, the security chip control instruction includes a write command from a file system in the host to the non-volatile memory controller to write a second specific data to a fifth special address, and the fifth special address is located in a reserved area in the non-volatile memory device. When a firmware in the non-volatile memory controller recognizes the fifth special address, it drives the security chip to encrypt the second specific data and transmit the encrypted data back to the non-volatile memory controller, and the firmware writes the encrypted data to the reserved area, and the file system reads the encrypted data back from the reserved area.

[0023] In one embodiment of the present invention, the single instruction of the single instruction cycle is a data access command to a specific address.

[0024] In one embodiment of the present invention, the special address is in the form of a default multi-digit number.

[0025] In one embodiment of the present invention, the special address is a dynamic address selected from a plurality of multi-digit numbers that conform to a specific formula. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0027] Figure 1 The figure is a functional block diagram of a conventional memory card with information security function.

[0028] Figure 2 A functional block diagram of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0029] Figure 3a -c is a functional block diagram and a process sequence diagram of a first embodiment of an encryption-related program for a memory card device for ensuring information security provided by an embodiment of the present invention.

[0030] Figure 4a -c is a functional block diagram and a process sequence diagram of a second embodiment of an encryption-related program of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0031] Figure 5a -c is a functional block diagram and a process sequence diagram of a third embodiment of an encryption-related program of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0032] Figure 6a -c is a functional block diagram and a process sequence diagram of a fourth embodiment of an encryption-related program of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0033] Figure 7 A schematic diagram of another process sequence of encryption-related procedures of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0034] Figure 8A schematic diagram of another process sequence of encryption-related procedures of a memory card device for ensuring information security provided by an embodiment of the present invention.

[0035] Description of main component symbols:

[0036] 11 is a memory card; 119 is a security chip; 10 is a host; 100 is an application; 101 is a file system; 110 is a flash memory controller; 102 is a default special combination; 103 is a vendor command pipeline; 111 is a flash memory; 21 is a memory card device; 20 is a host; 210 is a non-volatile memory device; 211 is a security chip; 212 is a non-volatile memory controller; 2120 is a firmware; 201 is an application; 202 is a file system; 2100 is a reserved area; 2101 is a regular data storage area. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] See also Figure 2 , which is a functional block diagram of a memory card device for ensuring information security provided by an embodiment of the present invention. The memory card device 21 completes a signal connection with a host 20 (for example, a wired signal connection method of a metal pin or a wireless signal connection method of a Bluetooth or wireless network). The memory card device 21 mainly includes a non-volatile memory device 210, a security chip 211 and a non-volatile memory controller 212, wherein the non-volatile memory device 210 is used to store data, and the security chip 211 can be a security chip that has passed CC EAL5+ certification (for example, a security chip produced by Infineon), which is used to provide functions such as cryptographic services, key management, and data storage. As for the non-volatile memory controller 212, the signal is connected to the host 20, the non-volatile memory device 210 and the security chip 211. In the embodiment of the present invention, the non-volatile memory controller 212 can also interact with the security chip 211 in response to a security chip control instruction, and the security chip control instruction can be a single instruction of a single instruction cycle. In this embodiment, a firmware 2120 is disposed in the non-volatile memory controller 212 to respond to the single instruction of the single instruction cycle to trigger the security chip 211 to perform encryption-related procedures.

[0039] Specifically, when the application 201 in the host 20 needs to perform various programs that interact with the security chip 211, the application 201 first instructs the file system 202 to perform a write command (Write Command) of a special address to the non-volatile memory controller 212. This command is one of the above-mentioned security chip control instructions, that is, a single instruction of a single instruction cycle. The above-mentioned special address can be in the form of a default multi-digit number, and the special address points to, for example, Figure 2 . The non-volatile memory controller 212 is a reserved area 2100 in the non-volatile memory device 210 shown in FIG. The firmware 2120 in the non-volatile memory controller 212 is configured to have an address decoding function that can identify the special address. Therefore, when the write command (Write Command) of the special address is decoded by the firmware 2120 and the special address is identified, the firmware 2120 can interact with the security chip 211, for example, triggering the security chip 211 to perform encryption-related procedures. In addition, the non-volatile memory controller 212 also responds to a non-security chip control instruction issued by the file system (file system) 202 of the host 20 to interact with the non-volatile memory device 210 but not with the security chip 211, and the non-security chip control instruction includes a regular address that is not related to the security chip, and the regular address is different from the first special address. In other words, the file system 202 can perform another instruction write command (Write Command) of the normal address (i.e., other addresses that do not belong to the special address) to the non-volatile memory controller 212, and the normal address and the first special address do not overlap each other, so the above-mentioned normal address refers to Figure 2 When a regular data storage area 2101 (i.e., another data storage area that does not overlap with the reserved area 2100) in the non-volatile memory device 210 shown in FIG. 2 is used, the non-volatile memory controller 212 directly interacts with the non-volatile memory device 210, but does not interact with the security chip 211. For example, data can be directly read and written to the regular data storage area 2101 in the non-volatile memory device 210. The following further describes various embodiments of interacting with the security chip 211.

[0040] Please see first Figure 3a, which is a functional block diagram of a first embodiment of a program for interacting with the security chip 211 provided by an embodiment of the present invention, wherein the file system 202 mainly performs a write command (Write Command) of a first special address as indicated by arrow C1 to the non-volatile memory controller 212. This command is a single instruction of a single instruction cycle without writing data, and the first special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the first special address, it will issue a command as indicated by arrow C2 to set the encryption mode of the security chip 211. For example, the security chip 211 can have multiple encryption modes, and the write command of the first special address is used to set the security chip 211 to the first encryption mode (e.g., AES-256-CBC). Similarly, if a write command (Write Command) of a second special address without writing data is issued, the security chip 211 can be set to the second encryption mode (e.g., AES-256-CTR).

[0041] See next Figure 3b , which corresponds to Figure 3a , which clearly shows the details and sequence of command transmission and execution of the first embodiment of the related program for interacting with the security chip 211. First, the host 20 sends a write command to the non-volatile memory controller 212. The non-volatile memory controller 212 responds to the write command and sets the encryption mode for the security chip 211. After the setting is successful, the security chip 211 will send a setting completion signal shown by the dotted line in the figure to the non-volatile memory controller 212, and the non-volatile memory controller 212 can respond to the setting completion signal and write a code representing the result of the successful encryption mode setting in the non-volatile memory device 210, and reply a write completion signal to the host 20.

[0042] Of course, you can also Figure 3c The method shown omits the step of "writing the result record of successful encryption mode setting in the non-volatile memory device 210", and instead allows the security chip 211 to send the setting completion signal directly to the host 20 after the setting is successful, thereby avoiding excessive use of the non-volatile memory device 210 and shortening its life.

[0043] See also Figure 4a, which is a functional block diagram of the second embodiment of the program for interacting with the security chip 211 provided by the embodiment of the present invention, mainly the file system 202 performs a write command (WriteCommand) on the non-volatile memory controller 212 as shown by the arrow D1, writing a first specific data to the third special address, and this command is a single instruction of a single instruction cycle, and the third special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the third special address, it will issue a command as shown by the arrow D2, which will be used to rewrite a set of parameters of the security chip 211, and the content of the first specific data is the parameter value to be rewritten. For example, the security chip 211 has a set of parameters, such as an initialization vector value IV, and this D2 command can be used to set the IV value used in AES-256-CBC. The purpose of rewriting the parameters in the security chip 211 can be achieved through such a write command.

[0044] See next Figure 4b , which corresponds to Figure 4a The process timing diagram clearly shows the details and sequence of the command transmission and execution of the second embodiment of the related program interacting with the security chip 211. First, the host 20 sends a write command with specific data to the non-volatile memory controller 212. The non-volatile memory controller 212 responds to the write command and the specific data and rewrites the parameters of the security chip 211. After the rewrite is successful, the security chip 211 will send a rewrite completion signal shown by the dotted line in the figure to the non-volatile memory controller 212, and the non-volatile memory controller 212 responds to the rewrite completion signal and writes a code representing the result of the successful parameter rewrite in the non-volatile memory device 210, and replies to the host 20 with a write completion signal. Of course, it can also be as follows Figure 4c As shown, the step of "writing a code representing the result of successful parameter rewriting in the non-volatile memory device 210" is omitted, and instead, after the parameter rewriting is successful, the rewriting completion signal sent by the security chip 211 is directly sent to the host 20, thereby avoiding excessive use of the non-volatile memory device 210 and shortening its life.

[0045] See also Figure 5a, which is a functional block diagram of a third embodiment of a program for interacting with the security chip 211 provided by an embodiment of the present invention, wherein the file system 202 performs a write command (WriteCommand) to the non-volatile memory controller 212 as shown by arrow E1, with no data being written to the fourth special address, and this command is also a single instruction of a single instruction cycle, and the fourth special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the fourth special address, it is used to read specific information (such as the firmware version) of the security chip 211 from the security chip 211, and the purpose of obtaining specific information in the security chip 211 can be achieved through such a write command. For example, the security chip 211 transmits the firmware version of the security chip 211 back to the non-volatile memory controller 212 (as shown by arrow E2), and the firmware 2120 writes the firmware version of the security chip 211 into the reserved area 2100 (as shown by arrow E3), and the file system 202 can read the firmware version of the security chip 211 back from the reserved area 2100 (as shown by arrow E4). The purpose of reading back the firmware version of the security chip 211 can be achieved through such a write command.

[0046] See next Figure 5b , which corresponds to Figure 5a The process timing diagram of FIG. 2 clearly shows the details and sequence of the command transmission and execution of the third embodiment of the related program for interacting with the security chip 211. First, the host 20 issues a write command to the non-volatile memory controller 212. The non-volatile memory controller 212 responds to the write command and reads specific information (such as the firmware version) from the security chip 211. After the read is successful, the security chip 211 will send a read completion signal shown by the dotted line in the figure to the non-volatile memory controller 212. The non-volatile memory controller 212 responds to the read completion signal and writes the read specific information (such as the firmware version) in the non-volatile memory device 210, and replies to the host 20 with a write completion signal. The host 20 responds to the write completion signal and issues a read result command to the non-volatile memory controller 212. The non-volatile memory controller 212 reads the specific information (such as the firmware version) from the non-volatile memory device 210 and transmits the specific information (such as the firmware version) to the host 20.

[0047] Of course, you can also Figure 5cIn the method shown, the step of “writing the read specific information (e.g., firmware version) in the non-volatile memory device 210” is not performed. Instead, the read specific information (e.g., firmware version) is temporarily stored in the memory of the non-volatile memory controller 212, and a write completion signal is replied to the host 20. Then, the file system 202 issues a read result (firmware version) command, the content of which is a read command of a special address. The special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the special address, the data (e.g., firmware version) temporarily stored in the memory of the non-volatile memory controller 212 can be transmitted back to the host 20, so as to avoid excessive use of the non-volatile memory device 210 and shortening its life.

[0048] See also Figure 6a , which is a functional block diagram of a fourth embodiment of a program for interacting with the security chip 211 provided by an embodiment of the present invention, wherein the file system 202 mainly performs a write command (WriteCommand) to write a second specific data to the fifth specific address as shown by the arrow F1 to the non-volatile memory controller 212, and this command is also a single instruction of a single instruction cycle, and the fifth specific address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the fifth special address, it will drive the security chip 211 to encrypt the second specific data. For example, the security chip 211 encrypts the second specific data and transmits the encrypted data back to the non-volatile memory controller 212 (as shown by arrow F2), and the firmware 2120 writes the encrypted data into the reserved area 2100 (as shown by arrow F3), and the file system 202 reads the encrypted data back from the reserved area 2100 (as shown by arrow F4). Such write commands can achieve the purpose of encrypting specific data and reading back the encrypted data.

[0049] See next Figure 6b , which corresponds to Figure 6aThe process timing diagram of FIG. 2 clearly shows the details and sequence of the command transmission and execution of the fourth embodiment of the related program for interacting with the security chip 211. First, the host 20 sends a write command with the data to be encrypted to the non-volatile memory controller 212. The non-volatile memory controller 212 responds to the write command and sends the data to be encrypted to the security chip 211 for data encryption. After the encryption is successful, the security chip 211 will send the encryption completion signal shown by the dotted line in the figure to the non-volatile memory controller 212, and the non-volatile memory controller 212 responds to the encryption completion signal and writes the encrypted data in the non-volatile memory device 210, and replies to the host 20 with a write completion signal. In response to the write completion signal, the host 20 sends a read encryption result command to the non-volatile memory controller 212. The non-volatile memory controller 212 reads the encrypted data from the non-volatile memory device 210 and transmits the encrypted data to the host 20.

[0050] Of course, you can also Figure 6c In the flowchart shown, the step of "non-volatile memory controller 212 writing encrypted data into the non-volatile memory device 210" is not performed. Instead, the encrypted data is temporarily stored in the memory of the non-volatile memory controller 212, and a write completion signal is replied to the host 20. Then, the file system 202 issues a read result (encrypted data) command, the content of which is a read command of a special address. The special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the special address, the encrypted data temporarily stored in the memory of the non-volatile memory controller 212 can be returned to the host 20, so as to avoid excessive use of the non-volatile memory device 210 and shortening its life.

[0051] In addition, if Figure 7As shown in the process timing diagram, the single instruction of the single instruction cycle used in this case, in addition to the above-mentioned specific data write command of the special address, of course, can also use the data read command of the special address as shown in the figure. First, the host 20 sends a data read command with a special address to the non-volatile memory controller 212. The firmware 2120 of the non-volatile memory controller 212 can identify the special address, and then respond to the trigger of the data read command to read specific information (such as the firmware version) from the security chip 211. After the read is successful, the security chip 211 will send a signal of the completion of the specific information reading shown by the dotted line in the figure to the non-volatile memory controller 212, and the non-volatile memory controller 212 will respond to the read completion signal and write the read specific information (such as the firmware version) in the non-volatile memory device 210, and reply to the host 20 with a data read command completion signal. Of course, the single instruction of the single instruction cycle can also be other similar data access commands, which will not be repeated here.

[0052] See also Figure 8 The process timing diagram is as follows: Figure 5c Similar to the procedures for interacting with the security chip 211, first, the host 20 sends a write command with a special dynamic address to the non-volatile memory controller 212. The special dynamic address can be dynamically selected from a plurality of multi-digit numbers that conform to a specific formula, mainly to allow the firmware 2120 to quickly identify and have uniqueness. In response to the triggering of the write command of the special dynamic address that conforms to the specific formula, the non-volatile memory controller 212 can read specific information (such as the firmware version) from the security chip 211. After the read is successful, the security chip 211 will send a read completion signal shown by the dotted line in the figure to the non-volatile memory controller 212. The read specific information (such as the firmware version) is temporarily stored in the memory of the non-volatile memory controller 212, and the host 20 is replied with a write completion signal. Then, the file system 202 sends a read result (firmware version) command, whose content is a read command of a special address. The special address is located in the range of the reserved area 2100. When the firmware 2120 in the non-volatile memory controller 212 recognizes the special address, it can return the data (such as the firmware version) temporarily stored in the memory of the non-volatile memory controller 212 to the host 20, so as to avoid excessive use of the non-volatile memory device 210 and shorten the life span.

[0053] The non-volatile memory 210 of the present invention may be a flash memory or other similar memory, and the non-volatile memory controller 212 may be a flash memory controller. The firmware 2120 in the non-volatile memory controller 212 and the security chip 211 may communicate via a full-duplex communication bus such as the SPI Protocol. Full-duplex communication means that the data flow is bidirectional, and data can be received while transmitting data. Therefore, it has a faster transmission speed than the traditional ISO-7816 smart card communication protocol.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory card device for ensuring information security, used to complete signal connection with a host, characterized in that: Include: A non-volatile memory device for storing data, comprising a regular address and a reserved area range, wherein the regular address and the reserved area range are different and do not overlap with each other; A security chip; as well as A non-volatile memory controller is signal-connected to the host, the non-volatile memory device and the security chip. The non-volatile memory controller interacts with the security chip in response to a security chip control instruction issued by the host, wherein the security chip control instruction includes a single instruction of a single instruction cycle, and the single instruction of the single instruction cycle includes a first special address corresponding to the security chip, and the first special address is located in the reserved area of ​​the non-volatile memory device. The non-volatile memory controller also interacts with the non-volatile memory device but does not interact with the security chip in response to a non-security chip control instruction issued by the host, and the non-security chip control instruction includes the regular address unrelated to the security chip, and the regular address is different from the first special address and does not overlap with each other. When the security chip control instruction includes a write command for a first special address to be executed by a file system in the host to the non-volatile memory controller, and a firmware in the non-volatile memory controller recognizes the first special address, the write command for the first special address will set the security chip to a first encryption mode, and when the security chip control instruction includes a write command corresponding to a second special address belonging to the reserved area, and the firmware in the non-volatile memory controller recognizes the second special address, the write command for the second special address will set the security chip to a second encryption mode; or when the security chip control instruction includes a write command for a third special address to be executed by a file system in the host to the non-volatile memory controller to write a first specific data to a third special address belonging to the reserved area, when the firmware in the non-volatile memory controller recognizes the third special address, a set of parameters of the security chip will be rewritten, and the content of the first specific data is the parameter value to be rewritten.

2. A memory card device for ensuring information security, used to complete signal connection with a host, characterized in that: Include: A non-volatile memory device for storing data, comprising a regular address and a reserved area range, wherein the regular address and the reserved area range are different and do not overlap with each other; A security chip; as well as A non-volatile memory controller is signal-connected to the host, the non-volatile memory device and the security chip. The non-volatile memory controller interacts with the security chip in response to a security chip control instruction issued by the host, wherein the security chip control instruction includes a single instruction of a single instruction cycle, and the single instruction of the single instruction cycle includes a first special address corresponding to the security chip, and the first special address is located in the reserved area of ​​the non-volatile memory device. The non-volatile memory controller also interacts with the non-volatile memory device but does not interact with the security chip in response to a non-security chip control instruction issued by the host, and the non-security chip control instruction includes a regular address unrelated to the security chip, and the regular address is different from the first special address and does not overlap with each other. When the security chip control instruction includes a command for a file system in the host to write a fourth special address to the non-volatile memory controller, the fourth special address is located in the reserved area of ​​the non-volatile memory device, and a firmware in the non-volatile memory controller identifies the fourth special address, the write command of the fourth special address will be used to read the specific information of the security chip from the security chip; or when the security chip control instruction includes a command for the file system in the host to write a second specific data to a fifth special address to the non-volatile memory controller, the fifth special address is located in the reserved area of ​​the non-volatile memory device, and the firmware in the non-volatile memory controller identifies the fifth special address, the security chip will be driven to encrypt the second specific data and then transmit the encrypted data back to the non-volatile memory controller, and the firmware will then write the encrypted data to the reserved area or temporarily store it in the non-volatile memory controller, and the file system will then read the encrypted data back from the reserved area or the non-volatile memory controller.

3. The memory card device according to claim 2, characterized in that: The specific information of the security chip is the firmware version. The security chip transmits the firmware version back to the non-volatile memory controller, and the firmware writes the firmware version into the reserved area or temporarily stores it in the non-volatile memory controller, and the file system reads the firmware version back from the reserved area or the non-volatile memory controller.

4. The memory card device according to claim 2, wherein: The single instruction of the single instruction cycle is a data access command to a special address. The special address is in the form of a default multi-bit number. The special address is a dynamic address selected from a plurality of multi-bit numbers that meet a specific formula.

5. A chip control method, applied between a host and a memory card device, characterized in that: The memory card device includes a non-volatile memory device, a security chip and a non-volatile memory controller. The non-volatile memory device includes a regular address and a reserved area range. The regular address and the reserved area range are different and do not overlap. The chip control method includes the following steps: The host sends a security chip control instruction to the non-volatile memory controller, wherein the security chip control instruction includes a single instruction of a single instruction cycle; The non-volatile memory controller interacts with the security chip in response to a single instruction of the single instruction cycle, wherein the single instruction of the single instruction cycle includes a first special address corresponding to the security chip, and the first special address is located in the reserved area of ​​the non-volatile memory device; as well as The non-volatile memory controller interacts with the non-volatile memory device but does not interact with the security chip in response to a non-security chip control instruction issued by the host. The non-security chip control instruction includes the regular address that is unrelated to the security chip. The regular address is different from the first special address and does not overlap with each other. When the security chip control instruction includes a file system in the host that performs a write command on the non-volatile memory controller to the first special address, and a firmware in the non-volatile memory controller recognizes the first special address, the write command of the first special address will set the security chip to a first encryption mode, and when the security chip control instruction includes a file system in the host that performs a write command on the first special address to the non-volatile memory controller, and a firmware in the non-volatile memory controller recognizes the first special address, the write command of the first special address will set the security chip to a first encryption mode. The chip control instruction includes a write command corresponding to a second special address belonging to the reserved area, and when the firmware in the non-volatile memory controller recognizes the second special address, the write command of the second special address will set the security chip to a second encryption mode; or when the security chip control instruction includes a write command of a file system in the host to write a first specific data to a third special address belonging to the reserved area of ​​the non-volatile memory controller, when the firmware in the non-volatile memory controller recognizes the third special address, a set of parameters of the security chip will be rewritten, and the content of the first specific data is the parameter value to be rewritten.

6. A chip control method, applied between a host and a memory card device, characterized in that: The memory card device includes a non-volatile memory device, a security chip and a non-volatile memory controller. The non-volatile memory device includes a regular address and a reserved area range. The regular address and the reserved area range are different and do not overlap. The chip control method includes the following steps: The host sends a security chip control instruction to the non-volatile memory controller, wherein the security chip control instruction includes a single instruction of a single instruction cycle; The non-volatile memory controller interacts with the security chip in response to a single instruction of the single instruction cycle, wherein the single instruction of the single instruction cycle includes a first special address corresponding to the security chip, and the first special address is located in the reserved area of ​​the non-volatile memory device; as well as The non-volatile memory controller interacts with the non-volatile memory device but does not interact with the security chip in response to a non-security chip control instruction issued by the host, the non-security chip control instruction includes a regular address that is unrelated to the security chip, the regular address is different from the first special address and does not overlap with each other, when the security chip control instruction includes a file system in the host to issue a write command to the non-volatile memory controller to a fourth special address, the fourth special address is located in the reserved area of ​​the non-volatile memory device, and a firmware in the non-volatile memory controller recognizes the fourth special address, the write command of the fourth special address will be used to write from the security chip or when the security chip control instruction includes a write command for the file system in the host to write a second specific data to a fifth specific address of the non-volatile memory controller, the fifth specific address is located in the reserved area of ​​the non-volatile memory device, and when the firmware in the non-volatile memory controller recognizes the fifth special address, the security chip is driven to encrypt the second specific data and transmit the encrypted data back to the non-volatile memory controller, and the firmware writes the encrypted data to the reserved area or temporarily stores it in the non-volatile memory controller, and the file system reads the encrypted data back from the reserved area or the non-volatile memory controller.

7. The chip control method according to claim 6, characterized in that: The specific information of the security chip is the firmware version. The security chip transmits the firmware version of the security chip back to the non-volatile memory controller, and the firmware writes the firmware version of the security chip into the reserved area, and the file system reads the firmware version of the security chip back from the reserved area.

8. The chip control method according to claim 6, characterized in that: The single instruction of the single instruction cycle is a data access command to a special address. The special address is in the form of a default multi-bit number. The special address is a dynamic address selected from a plurality of multi-bit numbers that meet a specific formula.

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