Semiconductor device and reading method of NAND type flash memory

Abstract

The present invention provides a semiconductor device and a readout method of a NAND type flash memory, which can perform high-speed readout or high-reliability readout. The readout method of the NAND type flash memory of the present invention comprises: a precharging step, precharging a sensing node through a voltage supply node; a discharging step, discharging the sensing node to the voltage supply node in order to perform a prescribed action; a recharging step, recharging the sensing node through the voltage supply node after the prescribed action; and a readout step, discharging the NAND string and sensing the storage unit.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a NAND flash memory and a readout method of the NAND flash memory, and more particularly to a recovery method of a sensing node of a page buffer / sensing circuit. Background Art

[0002] NAND flash memories are equipped with a continuous read function (burst read function) for continuously reading multiple pages in response to external commands. The page buffer / sensing circuit includes, for example, two latches, and during the continuous read operation, while one latch holds the data read from the array, the data held in the other latch can be output (for example, Japanese Patent No. 5323170, Japanese Patent No. 5667143, U.S. Patent Application US2014 / 0104947A1, etc.).

[0003] In the read operation of NAND flash memory, in order to more accurately receive the charge from the sensing node, the latch of the page buffer needs to be reset, and the reset is performed before the precharge period of the bit line. In particular, in the continuous read operation, the reset of the latch must be performed before the data of the latch is transferred to another latch and then the precharge of the bit line of the next page is read. If the continuous read operation is to be accelerated, it may not be possible to ensure sufficient time for resetting the latch.

[0004] To avoid the above situation, it is possible to consider resetting the latch after the pre-charging of the bit line and before the discharge of the NAND string. Although the reset of the latch electrically connects the node of the latch to the ground (Ground, GND) level, if the discharge path of the node of the latch is set to the voltage supply node, there is no need to set a reset transistor. However, in the above case, there are sensing nodes on the discharge path, so the sensing nodes are also discharged to the GND level at the same time. Therefore, the sensing node must be restored to the original voltage again after the latch is reset. If the recovery of the sensing node takes a long time, the read time will be longer, and the voltage of the sensing node will be used for sensing the memory cell after the discharge of the NAND string, so it is necessary to restore the original voltage more accurately.

[0005] In the shielded read of the bit line, an even bit line or an odd bit line is selected, and the selected bit line is precharged to make the unselected bit line GND level, and the time for discharging the potential of the unselected bit line to the GND level is longer than the time for precharging the selected bit line to the clamping voltage. This is because, when the selected bit line is precharged to the clamping voltage, the potential of the unselected bit line temporarily rises due to the capacitive coupling between the selected bit line and the unselected bit line, and then discharges to the GND level, and the RC time constant is large. In order to avoid read disturbance, the discharge of the NAND string of the selected bit line waits for the discharge of the unselected bit line to end. However, during the period of waiting for the discharge of the unselected bit line to end, the precharged clamping voltage of the selected bit line gradually increases, and the voltage of the selected bit line deviates from the clamping voltage. The deviation of the clamping voltage will affect the sensing accuracy of the memory cell, so this situation should be avoided as much as possible.

[0006] Therefore, it is conceivable to cut off the selected bit line from the voltage supply node after the selected bit line is precharged to the clamp voltage so that the voltage of the selected bit line does not deviate from the clamp voltage during a period when the discharge of the unselected bit lines is completed.

[0007] As a method of shutting off the selected bit line from the voltage supply node, the transistor BLPRE connected between the selected bit line and the voltage supply node can be turned off. When the transistor BLPRE is turned off, the sensing node SNS becomes a floating state. The layout of the page buffer / sensing circuit is complex, and the sensing node SNS may be affected by unexpected noise. Therefore, it is not preferred to make the sensing node SNS a floating state. Assuming that the charge of the sensing node is discharged to the voltage supply node and the sensing node is fixed to the GND level, the sensing node must be restored to the original voltage again after the discharge of the unselected bit line is completed. If the recovery time of the sensing node takes a long time, the read time will become longer, which will affect the voltage of the sensing node for sensing the storage cell after the NAND string is discharged, so it is necessary to restore the original voltage more accurately. Summary of the invention

[0008] The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a semiconductor device capable of high-speed reading and high-reliability reading.

[0009] The reading method of the NAND type flash memory of the present invention includes: a first step of precharging the sensing node by the voltage from the voltage supply node; a second step of discharging the voltage of the sensing node to the voltage supply node in order to perform a prescribed action; a third step of recharging the sensing node by the voltage from the voltage supply node after the prescribed action; and a fourth step of discharging the NAND string after the third step and sensing the storage unit.

[0010] In one embodiment of the present invention, the prescribed action is a reset of a latch circuit of a page buffer / sensing circuit. In one embodiment of the present invention, the prescribed action includes an action of causing a selected bit line to be in a floating state during a period in which a discharge of an unselected bit line is terminated. In one embodiment of the present invention, the driving capability of the voltage supply node in the third step is equal to or larger than the driving capability of the voltage supply node in the first step. In one embodiment of the present invention, the driving capability of the voltage supply node in the third step changes in stages. In one embodiment of the present invention, the readout method further includes a fifth step of electrically connecting the selected bit line to the sensing node after recharging the sensing node.

[0011] The semiconductor device of the present invention includes: a NAND type memory cell array; a readout unit that reads data from a selected page of the memory cell array; and an output unit that outputs the data read out by the readout unit to the outside, and the readout unit includes a page buffer / sensing circuit connected to the memory cell array by a bit line. After precharging the sensing node with a voltage from a voltage supply node, the readout unit discharges the voltage of the sensing node to the voltage supply node before discharging the NAND string in order to perform a prescribed action, and after the prescribed action, the sensing node is recharged with the voltage from the voltage supply node.

[0012] In one embodiment of the present invention, the prescribed action is a reset of a latch circuit of a page buffer / sensing circuit. In one embodiment of the present invention, the prescribed action includes an action of making a selected bit line float during a period until the discharge of an unselected bit line ends. In one embodiment of the present invention, the readout unit includes a bit line selection circuit connected to the page buffer / sensing circuit, the bit line selection circuit includes an even selection transistor for selecting an even bit line and an odd selection transistor for selecting an odd bit line, and the prescribed action makes the even selection transistor or the odd selection transistor non-conductive, so that the selected even bit line or odd bit line becomes a floating state. In one embodiment of the present invention, the readout unit includes a drive circuit for driving a voltage supply node, and the drive circuit recharges the sensing node with a drive capability equal to or higher than that when the bit line is precharged. In one embodiment of the present invention, the drive circuit supplies a supply voltage or a reference potential to the voltage supply node in response to a switching control signal, and the drive circuit changes the drive capability of the supply voltage of the voltage supply node in response to a plurality of drive signals. In one embodiment of the present invention, a page buffer / sensing circuit includes: a voltage supply node, a sensing node, a latch circuit, a first selection transistor connected between the voltage supply node and the sensing node, a second selection transistor connected between the sensing node and a bit line, and a third selection transistor connected between the sensing node and the latch circuit, and a readout unit turns on the first selection transistor and the third selection transistor, turns off the second selection transistor, and electrically connects the latch circuit to a reference potential of the voltage supply node to reset the latch circuit. In one embodiment of the present invention, a page buffer / sensing circuit includes: a voltage supply node, a sensing node, a latch circuit, a first selection transistor connected between the voltage supply node and the sensing node, a second selection transistor connected between the sensing node and a bit line, and a third selection transistor connected between the sensing node and the latch circuit, and a readout unit turns on the first selection transistor, turns off the second selection transistor and the third selection transistor, and electrically connects the sensing node to a reference potential of the voltage supply node to make the selected bit line floating. In one embodiment of the present invention, the page buffer / sensing circuit also includes other latch circuits that receive the data held in the latch circuit, and when the read-out unit performs continuous reading, the latch circuit maintains the data read from the next selected page of the memory cell array while outputting the data of the other latch circuits.

[0013] According to the present invention, the sensing node is restored after the bit line is precharged, so that a high-speed read and a highly reliable read operation can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention;

[0015] Figure 2 is a diagram showing an example of the structure of a NAND string of a flash memory according to an embodiment of the present invention;

[0016] Figure 3 is a diagram showing the structure of a bit line selection circuit of a flash memory according to an embodiment of the present invention;

[0017] Figure 4 (A) Figure 4 (B) is a diagram showing the structure of a page buffer / sensing circuit of a flash memory according to an embodiment of the present invention;

[0018] Figure 5 is a diagram showing the structure of a driving circuit of a voltage supply source according to an embodiment of the present invention;

[0019] Figure 6 is a flowchart showing a read operation according to the first embodiment of the present invention;

[0020] Figure 7 is a timing diagram of a readout action based on the first embodiment of the present invention;

[0021] Figure 8 is a flowchart showing a readout operation according to a second embodiment of the present invention;

[0022] Fig. 9 This is a timing chart of the readout operation according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0023] The semiconductor storage device of the present invention is, for example, a NAND flash memory or a microprocessor, a microcontroller, a logic, an application specific integrated circuit (ASIC), a processor for processing images or sounds, a processor for processing signals such as wireless signals, etc. embedded in such a flash memory. In the following description, a NAND flash memory is exemplified. In one embodiment of the present invention, in order to achieve interchangeability with a NOR flash memory, the NAND flash memory is equipped with a serial peripheral interface (SPI) and has the function of reading multiple pages synchronously and continuously with an external clock signal.

[0024] Figure 11 is a diagram showing the structure of a NAND type flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment includes the following components: a memory cell array 110, in which a plurality of memory cells are arranged in a matrix; an input / output circuit 120, which is connected to an external input / output terminal and responds to an external clock signal ExCLK and outputs read data to the outside, or inputs data from the outside; an error detection and correction (ECC) circuit 130, which performs symbol generation of data to be programmed or error detection and correction of read data; an address register 140, which receives address data via the input / output circuit 120; a controller 150, which controls each unit based on command data received via the input / output circuit 120 or a control signal applied to a terminal; a word line 130, which performs a control operation on the data to be programmed or a control operation on the data to be read; and a control circuit 150. The page buffer / sensing circuit 170 holds the data read out from the page selected by the word line selection circuit 160, or holds the data to be programmed to the selected page; the column selection circuit 180 receives the column address information Ay from the address register 140, decodes the column address information Ay, and selects the column within the page buffer / sensing circuit 170 based on the decoding result; and the internal voltage generation circuit 190 generates various voltages required for reading, programming and erasing data (programming voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

[0025] The memory cell array 110 has, for example, m memory blocks BLK(0), BLK(1), ..., BLK(m-1) arranged along the column direction. Figure 2 As shown, a memory block includes a plurality of NAND strings, and a NAND string NU includes a plurality of memory cells MCi (for example, i=0, 1, ..., 31) connected in series, a bit line side selection transistor TD, and a source line side selection transistor TS. The drain of the bit line side selection transistor TD is connected to one bit line GBL among the bit lines GBL0 to GBLn, and the source of the source line side selection transistor TS is connected to a common source line SL. The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the bit line side selection transistor TD and the source line side selection transistor TS are respectively connected to the selection gate line SGD and the selection gate line SGS. The word line selection circuit 160 drives the bit line side selection transistor TD and the source line side selection transistor TS via the selection gate line SGD and the selection gate line SGS based on the row address information Ax to select a block or a word.

[0026] NAND strings can be formed two-dimensionally on the substrate surface or three-dimensionally in the vertical direction from the substrate surface. In addition, the storage cell can be a single-level cell (SLC) type that stores one bit (binary data) or a multi-level cell (MLC) type that stores multiple bits.

[0027] exist Figure 3 2 shows the structure of the bit line selection circuit. Figure 3 The example shows a page buffer / sensing circuit 170 shared by an even bit line GBLe and an odd bit line GBLo, and a bit line selection circuit 200 connected thereto.

[0028] The bit line selection circuit 200 includes: a transistor BLSe for selecting an even bit line GBLe, a transistor BLSo for selecting an odd bit line GBLo, a transistor YBLe for connecting a virtual power supply VIRPWR to the even bit line GBLe, and a transistor YBLo for connecting a virtual power supply VIRPWR to the odd bit line GBLo. A NAND string is connected between the even bit line GBLe and the source line SL, and a NAND string is connected between the odd bit line GBLo and the source line SL. For example, in a read operation, a shielded read is performed, and when the even bit line GBLe is selected, the odd bit line GBLo is not selected, and when the odd bit line GBLo is selected, the even bit line GBLe is not selected. The unselected bit lines are connected to the GND level via the virtual power supply VIRPWR.

[0029] exist Figure 4 (A) shows the structure of the page buffer / sensing circuit 170. Figure 4 (A) represents a page buffer / sensing circuit. For convenience, the signal applied to the gate of the transistor represents the transistor. The page buffer / sensing circuit 170 includes two latches L1 and L2, and a transfer gate (transistor CACHE) is connected between the latch L1 and the latch L2. By turning on the transfer gate, bidirectional data transfer from the latch L1 to the latch L2 or from the latch L2 to the latch L1 can be performed.

[0030] The latch L1 includes a pair of cross-coupled inverters, a node SLR1 of the latch L1 is connected to the common source / drain (S / D) of the transistor BLCD1 and the transistor DTG, and a node SLS1 is connected to the determination circuit 210. The determination circuit 210 determines, for example, whether the program verification (Program Verify) or the erase verification is qualified. When the node SLR1 is selectively charged to Vdd from the voltage supply node V2 or the node SLR1 is selectively discharged to GND during the program verification, the transistor DTG is turned on. Furthermore, the latch L1 can short-circuit the node SLR1 and the node SLS1 through the transistor EQ.

[0031] The nodes SLR1 and SLS1 of the latch L1 are connected to the nodes SLS2 and SLR2 of the latch L2 via the transistor CACHE, respectively. The node SLR2 of the latch L2 is connected to the sensing node SNS via the transistor BLCD2, and the node SLS2 is connected to the transistor RESET2. When the latch L2 is reset, the transistor RESET2 is turned on. In addition, the nodes SLS2 and SLR2 are connected to the differential sense amplifier SA via the data line DL and the data line / DL, and the output of the differential sense amplifier SA is connected to the input-output circuit 120.

[0032] A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the sensing node SNS, and the gate of the transistor VG is connected to the S / D of the transistor DTG. The voltage supply node V1 is connected to the sensing node SNS via the transistor BLPRE. The voltage supply node V1 supplies the internal supply voltage Vdd when precharging the bit line, and supplies the GND potential when resetting the latch L1 or making the selected bit line float. The transistor BLCN and the transistor BLCLAMP are connected in series between the sensing node SNS and the node BLS of the bit line selection circuit 200.

[0033] exist Figure 4(B) shows the circuit structure of an inverter constituting the latch L1. The inverter includes four transistors connected in series, namely, a P-type transistor PT1, a P-type transistor PT2, an N-type transistor NT1, and an N-type transistor NT2. The latch enable signal / LAT1 and the latch enable signal LAT1 are respectively input to the gates of the transistor PT1 and the transistor NT2, and the voltage of the node SLS1 / SLR1 is input to the common gate of the transistor PT2 and the transistor NT1. When the latch enable signal LAT1 is at an H level, the inverter can operate. When the latch enable signal LAT1 is at an L level, the transistor PT2 and the transistor NT1 become a three-state state separated from the internal supply voltage Vdd and GND, so that the inverter can be reset. The reset of the latch L1 is performed using a current path passing through the sensing node SNS, so it is reset when the sensing node SNS is free, that is, when it does not cause adverse effects on the sensing node SNS.

[0034] exist Figure 5 , a driving circuit for driving the voltage supply node V1 is shown in FIG. The driving circuit 300 includes: a plurality of P-channel metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) transistors P1, P2, P3, P4 connected in parallel between the Vdd node and the output node V1, and an N-channel metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) transistor N1 connected between the output node V1 and GND. The driving capabilities (drain currents) of transistors P1, P2, P3, and P4 may be equal, or may be set to P1<P2<P3<P4. In the latter case, the driving capabilities are set to, for example, P2=2×P1, P3=4×P1, and P4=8×P1. The driving capabilities may be changed according to the gate width of the transistor, or the ratio of the gate width to the gate length.

[0035] The gates of transistors P1, P2, P3, and P4 are connected to the outputs of inverter IV1 and NAND1, NAND2, and NAND3. The output of inverter IV3 is applied to one of the inputs of NAND1, NAND2, and NAND3 in a common manner, and the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> are applied to the other inputs of NAND1, NAND2, and NAND3, respectively. Inverters IV2, IV3, and IV4 are connected in series to the gate of NMOS transistor N1, and a switching control signal Y1_V1 is input to inverter IV4.

[0036] The controller 150 outputs the drive signal DRV<0>, the drive signal DRV<1>, the drive signal DRV<2> and the switching control signal Y1_V1 to the drive circuit 300 during the read operation. When the switching control signal Y1_V1 is at the H level, the internal supply voltage Vdd is generated at the output node V1, and when the switching control signal Y1_V1 is at the L level, the GND level is generated at the output node V1. In addition, when the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> are all at the H level, all transistors P1, transistor P2, transistor P3, and transistor P4 are turned on, and the driving capability is the maximum. When the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> are all at the L level, only the transistor P1 is turned on, and the driving capability is the minimum.

[0037] The word line selection circuit 160 and the column selection circuit 180 (see Figure 1 ) selects the data read start position in the page according to the row address information Ax and the column address information Ay, or automatically reads data from the beginning of the page without using the row address and the column address. Furthermore, the word line selection circuit 160 and the column selection circuit 180 may include a row address counter and a column address counter that increment the row address and the column address in response to the clock signal.

[0038] In the read operation of the flash memory, a certain positive voltage is applied to the bit line, a certain voltage (e.g., 0V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5V) is applied to the unselected word line, a positive voltage (e.g., 4.5V) is applied to the selected gate line SGD and the selected gate line SGS, the bit line side selection transistor TD and the source line side selection transistor TS are turned on, and 0V is applied to the common source line. In the programming operation, a high voltage programming voltage Vpgm (15V to 20V) is applied to the selected word line, an intermediate potential (e.g., 10V) is applied to the unselected word line, the bit line side selection transistor TD is turned on, the source line side selection transistor TS is turned off, and a potential corresponding to the data "0" or "1" is supplied to the bit line. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (e.g., 20V) is applied to the P well, and the data is erased in units of blocks by extracting electrons from the floating gate to the substrate.

[0039] Next, the read operation according to the first embodiment of the present invention will be described. Figure 6The flowchart shows the sequence of the read operation of the first embodiment. The read operation of the present embodiment includes: a step of precharging the bit line (S100), a step of resetting the latch L1 after the precharging (S110), a step of restoring the sense node SNS after resetting the latch L1 (S120), a step of discharging the memory cell of the NAND string (S130), and a step of sensing the sense node SNS (S140).

[0040] In the pre-charging of the bit line, first, the controller 150 converts the voltage supply node V1 to the supply voltage Vdd through the driving circuit 300 via the switching control signal Y1_V1. At this time, the controller 150 can change the driving capability of the driving circuit 300 from the minimum to the maximum through the driving signal DRV<0>, the driving signal DRV<1>, and the driving signal DRV<2>. The transistor BLPRE is turned on, the sensing node SNS is charged to the Vdd level, the transistor BLCLAMP and the transistor BLCN are turned on, and the node BLS is charged to VCLMP1. It is in the relationship of Vdd≧VCLMP1. The transistors BLCD1, BLCD2, and REG are turned off, the transistor BLSe is turned on (here, it is set to select the even bit line GBLe), and the node BLS is electrically connected to the even bit line GBLe. The bit line side selection transistor TD of the NAND string connected to the even bit line GBLe is turned on, the source line side selection transistor TS is turned off, and the pass voltage is applied to the selected page and the unselected page. Thus, the clamp voltage VCLMP1 is precharged to the even bit line GBLe. On the other hand, the unselected odd bit line GBLo is electrically connected to the GND of the virtual power supply VIRPWR via the transistor YBLo.

[0041] When the precharging of the bit line is completed, the latch L1 is reset. Figure 7 A timing diagram showing the reset of latch L1 and the recovery of the sensing node. During the reset period, transistor BLPRE, transistor BLCN, and transistor BLCLAMP are in the on state. At time t1, transistor BLSe is made non-conductive (L level), and even bit line GBLe is electrically separated from page buffer / sensing circuit 170. Then, at time t2, controller 150 switches voltage supply node V1 to GND through driver circuit 300 via switching control signal Y1_V1. As a result, sensing node SNS drops from supply voltage Vdd to GND level, and node TOBL and node BLS drop from clamp voltage VCLMP1 to GND level.

[0042] Next, at time t3, the latch enable signal LAT1 for resetting the latch L1 is switched from the H level to the L level, and the latch L1 is placed in a resettable state. Next, at time t4, the transistor EQ is turned on for a certain period of time, and the nodes SLR1 and SLS1 are short-circuited at the same potential, and then at time t5, the transistor BLCD1 is turned on for a certain period of time. As a result, the charge of the node SLR1 is discharged to the GND of the voltage supply node V1 via the sensing node SNS, and the resetting of the latch L1 is completed.

[0043] After the latch L1 is reset, the sensing node SNS and the like are restored. That is, the sensing node SNS, the node TOBL, and the node BLS are recharged so that the voltages of these nodes return to the pre-charged state before the latch L1 is reset. At time t6, the controller 150 switches the voltage supply node V1 from GND to the supply voltage Vdd through the driving circuit 300 via the switching control signal Y1_V1, thereby recharging the sensing node SNS to Vdd, and recharging the node TOBL and the node BLS to the clamping voltage VCLMP1. At this time, the controller 150 converts the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> to the H level, thereby turning on the transistors P1 to P4, and charging the sensing node SNS with the maximum driving capability, thereby shortening the recovery time of the sensing node SNS. Alternatively, the controller 150 causes the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> to be converted to the H level in stages between time t6 and time t7 (for example, one or more selected transistors among transistor P1, transistor P2, transistor P3, and transistor P4 are turned on in stages to gradually increase the driving capability), and finally turns on transistors P1 to transistor P4 to charge the sensing node SNS with the maximum driving capability, thereby suppressing the coupling received by the gate voltage of transistor BLCLAMP from the sensing node SNS, and at the same time achieving a shortening of the recovery time of the sensing node SNS.

[0044] After the recovery of the sensing node SNS, at time t7, the transistor BLSe is turned on (H level), the even bit line GBLe is electrically connected to the page buffer / sensing circuit 170, and the voltage error generated between the node TOBL and the node BLS (recharged to the clamping voltage VCLMP1 by recovery) and the even bit line GBLe (charged to the clamping voltage VCLMP1 by precharging the bit line) is corrected. Thereafter, the discharge and sensing of the NAND string are performed in the same manner as before (illustration omitted). That is, during the discharge of the NAND string, the transistor BLSe is made non-conductive, the source line side selection transistor TS of the NAND string is turned on, and the NAND string is electrically connected to the source line SL. Furthermore, a gate voltage for generating the clamping voltage VCLMP2 at the node TOBL is applied to the transistor BLCLAMP. VCLMP1>VCLMP2. Thereafter, by turning on the transistor BLSe for a certain period of time, the potential corresponding to the data "0" and data "1" of the selected storage cell is displayed at the sensing node SNS. If the selected memory cell holds data "0", the potential of the bit line is not discharged to the source line SL, so the potential of the sensing node SNS hardly changes. On the other hand, if the selected memory cell holds data "1", the potential of the bit line is discharged to the source line SL, and the potential of the sensing node SNS decreases. In this way, the sensing node SNS senses the charge corresponding to the data "0" and data "1" of the selected memory cell. Thereafter, the charge sensed by the sensing node SNS is transmitted to the node SLR1 of the latch L1 via the transistor BLCD1.

[0045] The readout method of this embodiment is particularly suitable for continuous readout of multiple pages. When the controller 150 receives a command for continuous readout of a page via the input-output circuit 120, the continuous readout of multiple pages starts from the start address. The continuous readout ends when the command for the end of continuous readout is input, or when the readout is performed to a predetermined end address. In the continuous readout of a page, during the period when data is output from the latch L2, the data read from the selected page of the memory cell array is transmitted to the latch L1. The data transmission from the latch L1 to the latch L2 is not performed in units of 1 page, but is divided into 1 / 2 pages (the first cache or the second cache). During the period when the data of one of the caches of the latch L2 is transmitted to the input-output circuit 120, the data of the other cache is processed by the ECC circuit 130. The data transmitted to the input-output circuit 120 is output to the outside from the external input-output terminal in synchronization with the external clock signal ExCLK (for example, the rising edge and the falling edge). The reading of data from the memory cell array and the data transmission from latch L1 to latch L2 are performed based on the internal clock signal, the data transmission between latch L2 and the input-output circuit 120 and the data output from the input-output circuit 120 are performed based on the external clock signal ExCLK, and the data transmission between latch L2 and the ECC circuit 130 and the operation of the ECC circuit are performed based on other internal clock signals or a clock signal obtained by dividing the external clock signal ExCLK.

[0046] When reading the selected page of the memory cell array, the sensing node SNS reads the potential of the selected bit line, and then the charge of the sensing node SNS is transmitted to the node SLR1 of the latch L1 via the transistor BLCD1. For the latch L1, if the transmitted charge is above the threshold, it is judged as data "1", and if it is less than the threshold, it is judged as data "0", and the data is maintained. The latch L1 resets the potential of the node SLR1 to the GND level so as to accurately reflect the charge transmitted from the sensing node SNS. When resetting the latch L1, the controller 150 converts the voltage supply node V1 to GND through the driving circuit 300 via the switching control signal Y1_V1, turns on the transistors BLCD1 and BLPRE, and electrically connects the node SLR1 to the voltage supply node V1.

[0047] In the conventional continuous reading of flash memory, the reset of latch L1 is performed before the precharge of the bit line when reading the next page. However, the reset of latch L1 must be performed after the data of latch L1 is transferred to latch L2. When the data output is accelerated, it may not be possible to fully ensure the time for resetting latch L1. In this embodiment, the reset of latch L1 is performed between the precharge period of the bit line and the discharge period of the NAND string, so the time for resetting latch L1 can be guaranteed, and then, the array reading can be started immediately after the data of latch L1 is transferred to latch L2.

[0048] Next, a second embodiment of the present invention will be described. Figure 8 The flowchart of the sequence of the read operation of the second embodiment includes: a step of precharging the bit line (S200), a step of floating the selected bit line after precharging (S210), a step of restoring the sensing node SNS (S220), a step of discharging the storage cell of the NAND string (S230), and a step of sensing the sensing node SNS (S240).

[0049] exist Fig. 9 , a timing diagram of the readout action of the second embodiment is shown. In the precharging of the bit line, as described in the first embodiment, at time t1, the charging of the sensing node SNS, the node TOBL, and the node BLS is started by the voltage Vdd supplied from the voltage supply node V1. In addition, the transistor BLSe is turned on (H level), and the charging of the selected bit line GBLe is started (here, it is assumed that the even bit line is selected). For the unselected bit line GBLo, the transistor BLSo is non-conductive (L level) and isolated from the node BLS, and the transistor YBLo is turned on and electrically connected to the virtual power supply VIRPWR (GND level).

[0050] When the voltage of the selected bit line GBLe rises, the voltage of the unselected bit line GBLo also rises due to the capacitive coupling between the bit lines. After the voltage of the selected bit line GBLe rises to a certain level, the voltage of the unselected bit line GBLo is saturated, and then slowly drops to the GND level. This is because the RC time constant of the bit line is large. The speed at which the voltage of the selected bit line GBLe rises can be appropriately adjusted according to the supply capacity of the driving circuit 300.

[0051] At time t2, when the selected bit line GBLe reaches the precharge voltage VCLMP1, the controller 150 makes the transistor BLSe non-conductive (L level), isolates the selected bit line GBLe from the node BLS, and puts the selected bit line GBLe into a floating state. As in the past, when the transistor BLSe is kept conductive at time t2, the gate voltage of the transistor BLCLAMP that actually generates the clamp voltage VCLMP1 has an offset voltage, so the voltage of the selected bit line GBLe rises above the precharge voltage VCLMP1 as shown by the dotted line.

[0052] At time t3, the controller 150 switches the voltage supply node V1 to GND via the switching control signal Y1_V1 through the driving circuit 300. At this time, the transistors BLPRE, BLCLAMP, and BLCN are in the conducting state, the transistors REG, BLCD1, and BLCD2 are in the non-conducting state, and the sensing node SNS, the node TOBL, and the node BLS are electrically connected to the voltage supply node V1 and fixed to the GND level. The sensing node SNS, the node TOBL, and the node BLS are not in a floating state, so they do not change due to unexpected noise.

[0053] While the selected bit line GBLe is in the floating state, the unselected bit line GBLo is discharged to the GND level. In other words, while waiting for the unselected bit line GBLo to be in the GND level, the selected bit line GBLe is in the floating state.

[0054] At time t4, the controller 150 switches the voltage supply node V1 from GND to the supply voltage Vdd through the drive circuit 300 via the switching control signal Y1_V1. As a result, the sensing node SNS is recharged to Vdd, and the nodes TOBL and BLS are recharged to the voltage VCLMP1. At this time, the controller 150 converts the drive signal DRV<0>, the drive signal DRV<1>, and the drive signal DRV<2> to the H level, so that the driving capacity of the drive circuit 300 is maximized, thereby shortening the recharging time. However, the driving capacity does not necessarily need to be the maximum, and can be determined based on the time allowed for the recovery of the sensing node.

[0055] At time t5, the controller 150 turns on the transistor BLSe (H level), electrically connects the selected bit line GBLe to the page buffer / sensing circuit 170, and corrects the voltage error generated between the node TOBL and the node BLS (recharged to the clamp voltage VCLMP1 by recovery) and the selected bit line GBLe (charged to the clamp voltage VCLMP1 by precharging the bit line). Thereafter, the memory cells of the NAND string are discharged, and the sensing node SNS is sensed, similarly to the first embodiment.

[0056] Thus, according to this embodiment, the sensing node is restored (recharged) after the bit line is precharged, so during the precharge period of the bit line, the selected bit line is made to float, and the sensing node SNS, the node TOBL, and the node BLS are fixed to the GND level, which can prevent the selected bit line from rising to an unexpected voltage during the period of waiting for the unselected bit line to become the GND level. As a result, the reliability of the read operation can be improved.

[0057] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A method for reading a NAND flash memory, characterized in that: include: In a first step, the sensing node is precharged by a voltage from a voltage supply node; The second step is to discharge the voltage of the sensing node to the voltage supply node in order to perform a prescribed action; A third step, after the prescribed action, recharging the sensing node with the voltage from the voltage supply node; as well as The fourth step is to discharge the NAND string after the third step and sense the storage unit. The predetermined action includes resetting a latch circuit of the page buffer / sensing circuit, or making the selected bit line float during a period when the discharge of the unselected bit line is completed.

2. The reading method according to claim 1, wherein: The driving capability of the voltage supply node in the third step is equal to or greater than the driving capability of the voltage supply node in the first step.

3. The reading method according to claim 1, wherein: The driving capability of the voltage supply node in the third step changes in stages.

4. The reading method according to claim 1, wherein: The readout method further includes a fifth step of electrically connecting a selection bit line to the sensing node after recharging the sensing node.

5. A semiconductor device, characterized in that: include: A memory cell array of NAND type; a readout unit, which reads out data from a selected page of the memory cell array; as well as an output unit, outputting the data read out by the read unit to the outside, The readout unit includes a page buffer / sensing circuit connected to the memory cell array via a bit line, After the readout component pre-charges the sensing node with the voltage from the voltage supply node, before the discharge of the non-AND string, in order to perform a specified action, the sensing node is discharged to the voltage supply node, and after the specified action, the sensing node is recharged with the voltage from the voltage supply node.

6. The semiconductor device according to claim 5, wherein: The specified actions include resetting the latch circuit of the page buffer / sensing circuit Or, an operation of placing a selected bit line in a floating state during a period in which discharge of an unselected bit line is completed.

7. The semiconductor device according to claim 5, wherein: The readout unit includes a bit line selection circuit connected to the page buffer / sensing circuit, the bit line selection circuit includes an even selection transistor for selecting an even bit line and an odd selection transistor for selecting an odd bit line. The predetermined operation renders the even selection transistor or the odd selection transistor non-conductive, thereby placing the selected even bit line or odd bit line in a floating state.

8. The semiconductor device according to claim 5, wherein: The sensing unit includes a driving circuit that drives the voltage supply node, the driving circuit recharging the sensing node with a driving capability equal to or higher than that of precharging a bit line.

9. The semiconductor device according to claim 8, wherein: The driving circuit supplies a supply voltage or a reference potential to the voltage supply node in response to a switching control signal, and the driving circuit changes a driving capability of the supply voltage of the voltage supply node in response to a plurality of driving signals.

10. The semiconductor device according to claim 6, wherein The page buffer / sensing circuit includes: a voltage supply node, a sensing node, a latch circuit, a first selection transistor connected between the voltage supply node and the sensing node, a second selection transistor connected between the sensing node and a bit line, and a third selection transistor connected between the sensing node and the latch circuit, and The readout unit turns on the first selection transistor and the third selection transistor, turns off the second selection transistor, and electrically connects the latch circuit to a reference potential of the voltage supply node to reset the latch circuit.

11. The semiconductor device according to claim 6, wherein: The page buffer / sensing circuit includes: a voltage supply node, a sensing node, a latch circuit, a first selection transistor connected between the voltage supply node and the sensing node, a second selection transistor connected between the sensing node and a bit line, and a third selection transistor connected between the sensing node and the latch circuit, and The readout unit turns on the first selection transistor, turns off the second selection transistor and the third selection transistor, electrically connects the sensing node to the reference potential of the voltage supply node, and makes the selected bit line float.

12. The semiconductor device according to claim 10, wherein: The page buffer / sensing circuit also includes other latch circuits that receive the data held in the latch circuits. The reading unit causes the latch circuit to hold data read from a next selected page of the memory cell array while the data of the other latch circuit is output when performing continuous reading.

Images