Capacitor structure and manufacturing method thereof, and memory

Abstract

The present invention relates to a capacitor structure and a manufacturing method thereof, and a memory. The method comprises: providing a substrate; forming a first columnar conductive structure on the substrate; forming a second conductive structure on the substrate, wherein the second conductive structure surrounds the first conductive structure and is spaced apart from the first conductive structure, and the first conductive structure and the second conductive structure together constitute a lower electrode; forming a capacitor dielectric layer, wherein the capacitor dielectric layer covers the surface of the substrate and the lower electrode; and forming an upper electrode covering the surface of the capacitor dielectric layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory devices, and in particular to a capacitor structure and a preparation method thereof, and a memory. Background Art

[0002] Dynamic random access memory (DRAM) includes capacitors for storing charge and transistors for accessing the capacitors. DRAM stores data in the form of charge on the capacitors, so the capacitors need to be regularly recharged every few milliseconds. The larger the capacitance of the capacitor, the longer the data stored in the DRAM can be maintained.

[0003] In order to make more chips on a wafer, one method is to shrink the size, and the other is to change the memory structure. Currently, DRAM is mainly a 6F2 structure; when the size is shrunk to a certain extent, the 4F2 structure will usher in a new era. In the 4F2 structure, the capacitor structure has also undergone corresponding changes. Currently, it is mainly stacked capacitors, and as the size becomes smaller and smaller, the columnar 3D capacitor structure is about to become the main trend; however, when forming a columnar 3D capacitor structure, due to the small thickness of the electrode, it is easy to bend or collapse when squeezed. Summary of the invention

[0004] Based on this, it is necessary to provide a capacitor structure and its preparation method, and a memory to address the problem that electrodes of 3D capacitor structures in the prior art are prone to collapse or bending due to compression during the manufacturing process.

[0005] In order to achieve the above object, the present invention provides a method for manufacturing a capacitor structure, comprising:

[0006] providing a substrate;

[0007] forming a first columnar conductive structure on the substrate;

[0008] forming a second conductive structure on the substrate, wherein the second conductive structure surrounds the first conductive structure and is spaced apart from the first conductive structure, and the first conductive structure and the second conductive structure together constitute a lower electrode;

[0009] forming a capacitor dielectric layer, wherein the capacitor dielectric layer covers surfaces of the substrate and the lower electrode;

[0010] An upper electrode is formed to cover the surface of the capacitor dielectric layer.

[0011] In one embodiment, forming a second conductive structure on the substrate includes:

[0012] forming a sacrificial material layer, wherein the sacrificial material layer covers the side surface of the first conductive structure;

[0013] forming a second conductive material layer covering the side surface of the sacrificial material layer;

[0014] The sacrificial material layer on the side surface of the first conductive structure is removed, and the remaining second conductive material layer serves as the second conductive structure.

[0015] In one embodiment, the sacrificial material layer on the side surface of the first conductive structure is removed by wet etching process. The first conductive structure is formed by polysilicon material.

[0016] In one embodiment, the second conductive structure and the upper electrode are made of one or more materials selected from titanium, titanium nitride or tungsten.

[0017] In one embodiment, the first columnar conductive structure formed on the substrate includes:

[0018] forming a first conductive material layer on the surface of the substrate;

[0019] forming a hard mask layer on the first conductive material layer, wherein the hard mask layer has a first graphic target pattern defining the first conductive structure;

[0020] The first conductive material layer is etched using the hard mask layer as a mask to form a plurality of columnar first conductive structures.

[0021] In one of the embodiments, before forming the first conductive structure, the method further includes forming a capacitor contact material layer covering the surface of the substrate;

[0022] After forming the first conductive structure, the sacrificial material layer and the second conductive structure on the capacitor contact material layer, the capacitor contact material layer is etched until the substrate is exposed, and the retained capacitor contact material layer forms a capacitor contact pad, and the capacitor contact pad corresponds to the first conductive structure in position and quantity.

[0023] In one embodiment, the capacitor dielectric layer is made of a dielectric material with a dielectric constant greater than 7.

[0024] Based on the same inventive concept, an embodiment of the present invention further provides a capacitor structure, including:

[0025] substrate;

[0026] A lower electrode, comprising a first conductive structure and a second conductive structure located on the surface of the substrate, wherein the first conductive structure is columnar, and the second conductive structure surrounds the first conductive structure and is spaced apart from the first conductive structure;

[0027] a capacitor dielectric layer, located on the surfaces of the substrate and the lower electrode; and

[0028] The upper electrode is located on the surface of the capacitor dielectric layer.

[0029] In one embodiment, the first conductive structure is cylindrical, and the bottom diameter of the first conductive structure is 30 nm to 50 nm.

[0030] In one embodiment, the capacitor structure further includes a capacitor contact pad, wherein the capacitor contact pad is located between the substrate and the lower electrode, and the lower electrode is electrically connected to the capacitor contact pad.

[0031] In one embodiment, the capacitor dielectric layer is also located on the side surface of the capacitor contact pad and in the area between adjacent capacitor contact pads.

[0032] In one of the embodiments, the height of the top of the lower electrode relative to the substrate is 500 nm to 800 nm.

[0033] In one embodiment, the capacitor dielectric layer is made of a dielectric material with a dielectric constant greater than 7.

[0034] Based on the same inventive concept, an embodiment of the present invention further provides a memory, wherein the memory adopts the capacitor structure as described in any of the above embodiments.

[0035] In summary, the embodiments of the present invention provide a capacitor structure and a manufacturing method thereof, and a memory. Among them, the manufacturing method of the capacitor structure includes: providing a substrate; forming a columnar first conductive structure on the substrate; forming a second conductive structure on the substrate, wherein the second conductive structure surrounds the first conductive structure and is spaced apart from the first conductive structure, and the first conductive structure and the second conductive structure together constitute a lower electrode; forming a capacitor dielectric layer, the capacitor dielectric layer covers the surface of the substrate and the lower electrode; forming an upper electrode covering the surface of the capacitor dielectric layer. In this embodiment, by first forming a columnar first conductive structure, then forming a second conductive structure surrounding the first conductive structure, and finally forming a capacitor dielectric layer covering the surface of the substrate and the lower electrode, and an upper electrode covering the surface of the capacitor dielectric layer in sequence; because the columnar first conductive structure is relatively straight and large in size, and has a strong bearing capacity, the subsequent process will not cause it to collapse or bend, and it can also prevent the upper / lower electrodes formed subsequently from collapsing or bending due to extrusion; in addition, the upper electrode, the lower electrode and the capacitor dielectric layer together constitute a 3D columnar capacitor, which can effectively increase the relative area between the upper electrode and the lower electrode, thereby increasing the capacitance of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A flowchart of a method for preparing a capacitor structure provided by an embodiment of the present invention;

[0038] Figure 2-14 A schematic structural diagram of a capacitor structure that is gradually formed according to an embodiment of the present invention.

[0039] Explanation of the accompanying drawings: substrate-100, lower electrode-200, first conductive structure-210, first conductive material layer-210a, second conductive structure-220, second conductive material layer-220a, capacitor dielectric layer-300, lower electrode 400, capacitor contact material layer-500a, capacitor contact pad-500, hard mask layer-600, first organic mask material layer-610, first hard mask material layer-620, first photoresist layer-630, second hard mask material layer-640, sacrificial material layer-700. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] Embodiments of the invention are described herein with reference to cross-sectional illustrations which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, and such variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes as a result, for example, of manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0044] See also Figure 1 , an embodiment of the present invention provides a method for manufacturing a capacitor structure, comprising:

[0045] Step S110, providing a substrate 100;

[0046] Step S120, forming a columnar first conductive structure 210 on the substrate 100;

[0047] Step S130, forming a second conductive structure 220 on the substrate 100, wherein the second conductive structure 220 surrounds the first conductive structure 210 and is spaced apart from the first conductive structure 210, and the first conductive structure 210 and the second conductive structure 220 together constitute a lower electrode 200;

[0048] Step S140, forming a capacitor dielectric layer 300, wherein the capacitor dielectric layer 300 covers the surfaces of the substrate 100 and the lower electrode 200;

[0049] Step S150 , forming an upper electrode 400 covering the surface of the capacitor dielectric layer 300 .

[0050] It can be understood that when a columnar capacitor structure is currently manufactured, a stacked structure is first formed, the stacked structure includes two upper and lower support layers and a filling layer located between the two support layers, and a capacitor hole is formed in the stacked structure; then, a lower electrode is formed on the surface of the capacitor hole by a deposition process; then, the filling layer is removed, and a dielectric material layer covering the surface of the lower electrode is formed; finally, the gap between the node material layers is filled to form an upper electrode. However, after removing the filling layer, the lower electrode is prone to bending or collapse in subsequent processes due to its small thickness. To solve this problem, in this embodiment, a first columnar conductive structure 210 is first formed, and then a second conductive structure 220 surrounding the first conductive structure 210 is formed, and finally a capacitor dielectric layer 300 covering the surface of the substrate 100 and the lower electrode 200, and an upper electrode 400 covering the surface of the capacitor dielectric layer 300 are formed in sequence; since the first columnar conductive structure 210 is relatively straight and large in size and has a strong bearing capacity, subsequent processes will not cause it to collapse or bend, and at the same time, it can also prevent the subsequently formed upper electrode 400 / lower electrode 200 from collapsing or bending due to squeezing; in addition, the upper electrode 400, the lower electrode 200 and the capacitor dielectric layer 300 together constitute a 3D columnar capacitor, which can effectively increase the relative area between the upper electrode 400 and the lower electrode 200, thereby increasing the capacitance of the capacitor structure.

[0051] In this embodiment, the substrate 100 includes a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-covered insulating substrate, but is not limited thereto. Those skilled in the art can select the type of the semiconductor substrate 100 according to the semiconductor device to be formed on the substrate 100 as required, so the type of the semiconductor substrate 100 should not limit the protection scope of the present invention. In this embodiment, the substrate 100 is a P-type crystalline silicon substrate.

[0052] The substrate 100 includes a base and a shallow trench structure formed in the base, wherein a plurality of active areas arranged in parallel and staggered are defined by the shallow trench structure, and the shallow trench structure is filled with insulating material to form a shallow trench isolation structure. The substrate 100 also includes a word line structure and a bit line structure, wherein the word line structure is a buried word line structure, and the extension direction of the buried word line structure intersects with the extension direction of the bit line structure.

[0053] See also Figure 2 In order to reduce the contact resistance between the capacitor structure and the substrate 100, before forming the first conductive structure 210, the step of forming a capacitor contact material layer 500a covering the surface of the substrate 100 is also included;

[0054] In this embodiment, a deposition process is used to deposit a conductive material, such as any one or any combination of titanium nitride, titanium, tungsten silicide, and tungsten nitride, on the surface of the substrate to form a capacitor contact material layer 500a on the surface of the substrate 100. The deposition process may include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), and plasma enhanced ALD (PEALD). After the first conductive structure, the sacrificial material layer, and the second conductive structure are formed on the capacitor contact material layer, the capacitor contact material layer 500a is etched until the substrate 100 is exposed, and the retained capacitor contact material layer 500a forms a capacitor contact pad, and the capacitor contact pad corresponds to the first conductive structure in position and quantity.

[0055] In one embodiment, the specific steps of forming the columnar first conductive structure 210 on the substrate 100 include:

[0056] Forming a first conductive material layer 210a on the surface of the substrate 100;

[0057] forming a hard mask layer 600 on the first conductive material layer 210a, wherein the hard mask layer 600 has a first graphic target pattern defining the first conductive structure 210;

[0058] The first conductive material layer 210 a is etched using the hard mask layer 600 as a mask to form a plurality of columnar first conductive structures 210 .

[0059] See also Figure 3-Figure 8 In order to ensure the accuracy of etching in this embodiment, one photolithography process and two dry etching processes are used in the etching process. The specific steps are as follows:

[0060] Step 1: First, a first conductive material layer 210a, a first organic mask material layer 610 and a first hard mask material layer 620 are sequentially formed on the substrate 100 on which the capacitor contact material layer 500a is formed by a deposition process, and a layer of photoresist is coated on the surface of the first hard mask material layer to form a photoresist layer 630. The material of the first hard mask material layer 620 can be nitride, oxide, such as silicon oxynitride, silicon carbon oxide, etc., and the first organic mask material layer 610 can be an anti-reflective material, an organic carbon material, etc. Secondly, the photoresist layer 630 is exposed, cleaned, etc. to form a first graphical target pattern defining the first conductive structure 210. Again, the first organic mask material layer and the first hard mask material layer are etched with the photoresist layer 630 mask until the first conductive material layer 210a is exposed, and the first graphic target pattern of the first conductive structure 210 is transferred to the first organic mask material layer 610 and the first hard mask material layer 620 to form a through hole penetrating the first organic mask material layer 610 and the first hard mask material layer 620, and then the remaining photoresist is removed. Figure 3 and Figure 4 .

[0061] Step 2: Form a second hard mask material layer 640 by a deposition process. The second hard mask material layer 640 fills the through hole penetrating the first organic mask material layer 610 and the first hard mask material layer 620 and covers the surface of the first hard mask material layer 620. Then, remove the second hard mask material layer 640 covering the surface of the first hard mask material layer 620 by an etching process or a chemical mechanical polishing process. Finally, remove the first organic mask material layer 610 and the first hard mask material layer 620 by an organic solvent, and retain the second hard mask material layer 640 as the hard mask layer 600. The hard mask layer 600 has a first graphical target pattern defining the first conductive structure 210, see Figure 5-Figure 7 .

[0062] Step three, using the hard mask layer 600 as a mask, etching the first conductive material layer 210a to form the first conductive structure 210, see Figure 8 .

[0063] In addition, in some other embodiments, a hard mask material layer and an anti-reflective material layer can be formed on the first conductive material, and then a photoresist layer can be formed on the surface of the anti-reflective material layer. A first graphical target pattern of the first conductive structure 210 can be defined in the photoresist layer through a photolithography composition process, and the hard mask material layer and the anti-reflective material layer can be etched using the patterned photoresist layer as a mask until the first conductive material layer 210a is exposed; finally, the photoresist layer and the anti-reflective material layer can be removed, and the retained hard mask material layer can be used as the hard mask layer 600, and the first conductive material layer 210a can be etched using this as a mask to form the first conductive structure 210.

[0064] In one of the embodiments, the first conductive structure 210 is cylindrical, and the bottom diameter of the first conductive structure 210 is 30nm to 50nm. It can be understood that when the first conductive structure 210 is set to a cylindrical shape, it is beneficial to increase the number of capacitor structures in the capacitor structure. In some other embodiments, the cross-section of the first conductive structure 210 can also be rectangular, positive, triangular or irregular. In this embodiment, when forming the through hole, a vertically crossed strip mask structure is generally used as a hard mask to etch the organic mask material layer and the hard mask material layer, but due to the limitation of the etching process, the cross-section of the through hole formed during the pattern transfer process is usually circular. In addition, the size of the bottom diameter of the first conductive structure 210 is controlled within the range of 30nm to 50nm, which can prevent the first conductive structure 210 from bending or collapsing due to being too thin, and can also maximize the capacitance of the capacitor structure.

[0065] In one embodiment, polysilicon material is used to form the first conductive structure 210. It is understood that any conductive metal material or semiconductor conductive material can be used when manufacturing the capacitor electrode. In this embodiment, since the first conductive material layer 210a to be formed has a large thickness, and the deposition speed of polysilicon material is much greater than the deposition speed of other commonly used conductive material layers, the first conductive structure 210 is formed using polysilicon material in this embodiment to shorten the manufacturing cycle.

[0066] In one embodiment, forming the second conductive structure 220 on the substrate 100 includes:

[0067] forming a sacrificial material layer 700 , wherein the sacrificial material layer 700 covers the side surface of the first conductive structure 210 ;

[0068] forming a second conductive material layer 220a covering the side surface of the sacrificial material layer 700;

[0069] The sacrificial material layer 700 on the side surface of the first conductive structure 210 is removed, and the remaining second conductive material layer 220 a serves as the second conductive structure 220 .

[0070] In this embodiment, the steps of forming the second conductive structure 220 specifically include:

[0071] 1) Forming a sacrificial material layer 700 by a deposition process, wherein the sacrificial material layer 700 covers the surface of the substrate 100 and the first conductive structure 210, see Fig. 9 In the implementation process, the sacrificial material layer 700 may be formed using insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the sacrificial material layer 700 is specifically made of silicon oxide material.

[0072] 2) Depositing any one of titanium nitride, titanium, tungsten silicide, and tungsten nitride or any combination thereof by a deposition process to form a second conductive material layer 220a covering the surface of the sacrificial material layer 700, see Fig.10 In this embodiment, titanium nitride is specifically used to form the second conductive material layer 220a to increase the conductivity of the second conductive material layer 220a.

[0073] 3) Etching the second conductive material layer 220a and the sacrificial material layer 700 by a dry etching process to remove the second conductive material layer 220a and the sacrificial material layer 700 located on the top of the first conductive structure 210 and the surface of the capacitor contact material layer 500a, and retaining the second conductive material layer 220a and the sacrificial material layer 700 located on the side surface of the first conductive structure 210.

[0074] 4) Using the first conductive structure 210, the remaining second conductive material layer 220a and the sacrificial material layer 700 as masks, the capacitor base material layer is etched until the substrate 100 is exposed, and the remaining capacitor contact material layer 500a forms a capacitor contact pad 500, and the capacitor contact pad 500 is used to reduce the contact resistance between the capacitor structure and the substrate 100, see Fig.11 .

[0075] 5) Remove the sacrificial material layer 700, see Fig.12 .

[0076] In this embodiment, the cross-sectional shape of the second conductive structure is annular, surrounding the first conductive structure 210, and the distance between the second conductive structure 210 is not less than twice the sum of the thickness of the sacrificial material layer 700 and the second conductive material layer 220a, so as to prevent the air gap from being generated due to the large depth-to-width ratio of the gap between the sacrificial material layers used to form the second conductive material layer 220a after the sacrificial material layer is formed, thereby affecting the conductivity of the second conductive material layer 220a. Based on this, in this embodiment, the second conductive material layer 220a is formed by atomic layer deposition technology. It can be understood that atomic layer deposition technology is a method of coating a material on the surface of a substrate layer by layer in the form of a single atomic film. Compared with ordinary chemical deposition, the second conductive material layer 220a formed by atomic layer deposition technology has a very uniform film thickness and consistency on its surface.

[0077] In one embodiment, the second conductive structure 220 and the lower electrode 200 are made of one or more materials selected from titanium, titanium nitride or tungsten. In view of the good stability and conductivity of titanium nitride, in this embodiment, the second conductive structure 220 and the upper electrode 400 are both made of titanium nitride; and, using the same material to make the second conductive structure 220 and the upper electrode 400 is also beneficial to material management, simplifies process design, and reduces production costs.

[0078] In one embodiment, the sacrificial material layer 700 located on the side surface of the first conductive structure 210 is removed by a wet etching process.

[0079] In this embodiment, hydrofluoric acid HF is used to remove the sacrificial material layer 700. Since the sacrificial material layer 700 in this embodiment has a higher selective etching ratio relative to the lower electrode 200, the capacitor contact material layer 500a and the substrate 100, the etching of the lower electrode 200, the capacitor contact material layer 500a and the substrate 100 during the process of removing the sacrificial material layer 700 using hydrofluoric acid HF can be ignored.

[0080] See also Fig.13 After forming the lower electrode 200 , a dielectric material is deposited using a deposition process to form a capacitor dielectric layer 300 , and the capacitor dielectric layer 300 covers the first conductive structure 210 , the second conductive structure 220 , the capacitor contact pad 500 and the surface of the substrate 100 .

[0081] In one embodiment, the capacitor dielectric layer 300 is made of a dielectric material with a dielectric constant greater than 7. It can be understood that when the relative area between the upper electrode 400 and the lower electrode 200 is determined, the capacitance can be increased by increasing the dielectric coefficient of the capacitor dielectric layer 300 between the upper electrode 400 and the lower electrode 200. Therefore, in this embodiment, the capacitor dielectric layer 300 is made of a dielectric material with a dielectric constant greater than 7. Commonly used high-K dielectric materials include Ta2O5, TiO2, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or metal oxides of other components.

[0082] See also Fig.14 After forming the capacitor dielectric layer 300, a titanium nitride material is deposited using a deposition process to form an upper electrode 400 covering the surface of the capacitor dielectric layer 300. The lower electrode 200 (including the first conductive structure 210 and the second conductive structure 220) and the upper electrode 400 together constitute the capacitor structure.

[0083] Based on the same inventive concept, the embodiment of the present invention also provides a capacitor structure formed by the above-mentioned manufacturing method. Please continue to refer to Fig.14 The capacitor structure includes a substrate 100 , a lower electrode 200 , a capacitor dielectric layer 300 and an upper electrode 400 .

[0084] The lower electrode 200 includes a first conductive structure 210 and a second conductive structure 220 located on the surface of the substrate 100 , wherein the first conductive structure 210 is columnar, and the second conductive structure 220 surrounds the first conductive structure 210 and is spaced apart from the first conductive structure 210 .

[0085] The capacitor dielectric layer 300 is located on the surfaces of the substrate 100 and the lower electrode 200 .

[0086] The upper electrode 400 is located on the surface of the capacitor dielectric layer 300 .

[0087] In this embodiment, since the columnar first conductive structure 210 is relatively straight and large in size and has a strong bearing capacity, the subsequent process will not cause it to collapse or bend, and it can also prevent the subsequently formed upper / lower electrodes 200 from collapsing or bending due to squeezing; in addition, the upper electrode 400, the lower electrode 200 and the capacitor dielectric layer 300 together constitute a 3D columnar capacitor, which can effectively increase the relative area between the upper electrode 400 and the lower electrode 200, thereby increasing the capacitance of the capacitor structure.

[0088] In one embodiment, the first conductive structure 210 is cylindrical, and the bottom diameter of the first conductive structure 210 is 30 nm to 50 nm.

[0089] It can be understood that when the first conductive structure 210 is cylindrical, it is beneficial to increase the number of capacitor structures in the capacitor structure. In some other embodiments, the cross-section of the first conductive structure 210 can also be rectangular, positive, triangular or irregular. In this embodiment, when forming the through hole, a vertically crossed strip mask structure is generally used as a hard mask to etch the organic mask material layer and the hard mask material layer, but due to the limitations of the etching process, the cross-section of the through hole formed during the pattern transfer process is usually circular. In addition, the size of the bottom diameter of the first conductive structure 210 is controlled within the range of 30nm to 50nm, which can prevent the first conductive structure 210 from bending or collapsing due to being too thin, and can also maximize the capacitance of the capacitor structure.

[0090] In one embodiment, the thickness of the second conductive structure 220 is in the range of 2 nm to 8 nm.

[0091] In one embodiment, the capacitor structure further includes a capacitor contact pad 500, the capacitor contact pad 500 is located between the substrate 100 and the lower electrode 200, and the lower electrode 200 is electrically connected to the capacitor contact pad 500. In this embodiment, the capacitor contact pad 500 can reduce the contact resistance between the capacitor structure and the substrate 100.

[0092] In one embodiment, the height of the top of the lower electrode 200 relative to the substrate 100 is 500nm to 800nm. It can be understood that by increasing the height of the electrode, the relative area between the upper electrode 400 and the lower electrode 200 can also be increased, thereby increasing the capacitance of the capacitor structure. In addition, the height of the top of the lower electrode 200 relative to the substrate 100 is controlled within the range of 500nm to 800nm, reducing the size of the memory while keeping the capacitor structure as large as possible.

[0093] In one embodiment, the capacitor dielectric layer 300 is also located on the side surface of the capacitor contact pad 500 and the area between adjacent capacitor contact pads, and is used to insulate the upper electrode 400 from the capacitor contact pad 500 and the substrate 100, thereby preventing contact leakage between the upper electrode 400 and the capacitor contact pad and / or between the upper electrode 400 and the substrate 100.

[0094] In one embodiment, the capacitor dielectric layer 300 is made of a dielectric material with a dielectric constant greater than 7. In this embodiment, the capacitor dielectric layer 300 is made of a dielectric material with a dielectric constant greater than 7 to increase the capacitance by increasing the dielectric constant of the capacitor dielectric layer 300 between the upper electrode 400 and the lower electrode 200. Commonly used high-K dielectric materials include Ta2O5, TiO2, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or metal oxides of other components.

[0095] In one embodiment, the thickness of the capacitor dielectric layer 300 is in the range of 2 nm to 12 nm.

[0096] Based on the same inventive concept, an embodiment of the present invention further provides a memory, wherein the memory adopts the capacitor structure as described in any of the above embodiments. The memory further comprises: a transistor (not shown) and a capacitor contact structure (not shown) connected to the transistor at one end are formed on the surface of the substrate 100, and the bottom of the lower electrode 200 is connected to the other end of the capacitor contact structure.

[0097] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0098] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a capacitor structure, characterized in that: include: providing a substrate; forming a first columnar conductive structure on the substrate; forming a second conductive structure on the substrate, wherein the second conductive structure has a ring-shaped cross-section, surrounds the first conductive structure, and is spaced apart from the first conductive structure, and the first conductive structure and the second conductive structure together constitute a lower electrode; forming a capacitor contact pad, wherein the capacitor contact pad is located between the substrate and the lower electrode, the lower electrode is electrically connected to the capacitor contact pad, the first conductive structure and the second conductive structure belonging to the same lower electrode are both landed on the top surface of the corresponding capacitor contact pad, and the width of the contact pad is the same as the width of the second conductive structure; forming a capacitor dielectric layer, wherein the capacitor dielectric layer covers surfaces of the substrate and the lower electrode; An upper electrode is formed to cover the surface of the capacitor dielectric layer.

2. The method for manufacturing a capacitor structure according to claim 1, wherein: The forming of a second conductive structure on the substrate comprises: forming a sacrificial material layer, wherein the sacrificial material layer covers the side surface of the first conductive structure; forming a second conductive material layer covering the side surface of the sacrificial material layer; The sacrificial material layer on the side surface of the first conductive structure is removed, and the remaining second conductive material layer serves as the second conductive structure.

3. The method for manufacturing a capacitor structure according to claim 2, wherein: The sacrificial material layer on the side surface of the first conductive structure is removed by a wet etching process.

4. The method for manufacturing a capacitor structure according to claim 1, wherein: The first conductive structure is formed by using polysilicon material.

5. The method for manufacturing a capacitor structure according to any one of claims 1 to 4, characterized in that: The second conductive structure and the upper electrode are made of one or more materials selected from the group consisting of titanium, titanium nitride and tungsten.

6. The method for manufacturing a capacitor structure according to claim 1, wherein: The first conductive structure formed in a column shape on the substrate includes: forming a first conductive material layer on the surface of the substrate; forming a hard mask layer on the first conductive material layer, wherein the hard mask layer has a first graphic target pattern defining the first conductive structure; The first conductive material layer is etched using the hard mask layer as a mask to form a plurality of columnar first conductive structures.

7. The method for manufacturing a capacitor structure according to claim 2, wherein: Before forming the first conductive structure, the method further includes forming a capacitor contact material layer covering the surface of the substrate; After forming the first conductive structure, the sacrificial material layer and the second conductive structure on the capacitor contact material layer, the capacitor contact material layer is etched until the substrate is exposed, and the retained capacitor contact material layer forms the capacitor contact pad, and the capacitor contact pad corresponds to the first conductive structure in position and quantity.

8. The method for manufacturing a capacitor structure according to claim 1, wherein: The capacitor dielectric layer is made of a dielectric material with a dielectric constant greater than 7.

9. A capacitor structure, characterized in that: include: substrate; A lower electrode, comprising a first conductive structure and a second conductive structure located on the surface of the substrate, wherein the first conductive structure is columnar, and the cross-sectional shape of the second conductive structure is ring-shaped, surrounding the first conductive structure and spaced from the first conductive structure; A capacitor dielectric layer, located on the surface of the substrate and the lower electrode; as well as An upper electrode, located on the surface of the capacitor dielectric layer; A capacitor contact pad, wherein the capacitor contact pad is located between the substrate and the lower electrode, the lower electrode is electrically connected to the capacitor contact pad, the first conductive structure and the second conductive structure belonging to the same lower electrode both land on the top surface of the corresponding capacitor contact pad, and the width of the contact pad is the same as the width of the second conductive structure.

10. The capacitor structure according to claim 9, wherein: The first conductive structure is cylindrical, and the bottom diameter of the first conductive structure is 30 nm to 50 nm.

11. The capacitor structure according to claim 9, wherein: The capacitor dielectric layer is also located on the side surfaces of the capacitor contact pads and in the area between adjacent capacitor contact pads.

12. The capacitor structure according to claim 9, wherein: The height of the top of the lower electrode relative to the substrate is 500nm-800nm.

13. The capacitor structure according to claim 9, wherein: The capacitor dielectric layer is made of a dielectric material with a dielectric constant greater than 7.

14. A memory, characterized in that: A capacitor structure as described in any one of claims 9 to 13 is adopted.

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