Semiconductor module and method of manufacturing the same

Abstract

A semiconductor module and a manufacturing method thereof are disclosed. The semiconductor module includes a substrate, a shielding structure, and a piezoelectric layer. The substrate includes a front side and at least one semiconductor element formed on the front side. The shielding structure is formed on the at least one semiconductor element. The piezoelectric layer is formed on the shielding structure.

Description

Technical Field

[0001] This invention relates to a semiconductor module and a method for manufacturing the same, and more particularly to a semiconductor module having a piezoelectric layer and a method for manufacturing the same. Background Technology

[0002] Existing stacked semiconductor apparatuses typically utilize bonding techniques to connect individual semiconductor components by stacking them together. Common bonding techniques include wire bonding, flip chip bonding, and through-silicon via (TSV).

[0003] Wire bonding is a technique that uses metal wires to connect semiconductor components, such as chips, to leadframes or external circuits. Depending on the shape of the bonding joint, it can be divided into wedge bonding and ball bonding. Flip chip technology involves flipping the chip face up and directly connecting it to the substrate using solder balls or bumps. Through-silicon vias (TSVs) use holes that penetrate the chip and fill those holes with conductive material to create electrical interconnects between vertically stacked semiconductor components.

[0004] Taking the front-end module (FEM), a common technology in the prior art, as an example, surface acoustic wave (SAW) filters and integrated circuit substrates are fabricated separately in different manufacturing processes. Then, bonding technologies such as wire bonding, flip-chip bonding, and through-silicon via (TSV) are used to electrically connect the SAW filters and the integrated circuit substrate, forming a stacked semiconductor device. However, existing bonding technologies face many serious challenges, such as the alignment accuracy when bonding the SAW filters and the integrated circuit substrate, the stability of wire bonding quality, the difficulty in controlling individual semiconductor components, such as the SAW filters, due to the additional bonding process, and the increased manufacturing cost and reduced integration and performance of the overall semiconductor device due to the additional bonding process.

[0005] Therefore, developing a technology to improve the integration of semiconductor modules is a goal that companies in this field are constantly striving for. Summary of the Invention

[0006] This invention relates to a semiconductor module and a method for manufacturing the same, which can improve the integration, controllability and performance of the semiconductor module and reduce additional bonding processes, thereby improving the aforementioned existing problems.

[0007] One aspect of the present invention provides a semiconductor module. The semiconductor module includes a substrate, a shielding structure, and a piezoelectric layer. The substrate includes a front side and at least one semiconductor element formed on the front side. The shielding structure is formed on the at least one semiconductor element. The piezoelectric layer is formed on the shielding structure.

[0008] Another aspect of the present invention provides a method for manufacturing a semiconductor module. The method includes the following steps: providing a substrate, the substrate including a front side and at least one semiconductor element formed on the front side; forming a shielding structure on the at least one semiconductor element; and forming a piezoelectric layer on the shielding structure.

[0009] According to the above embodiments, in the semiconductor module provided by the present invention, a shielding structure is first formed on the front-end module, and a piezoelectric layer is directly formed on the shielding structure using, for example, deposition or bonding techniques. Then, subsequent processes are performed to form one or more surface acoustic wave (SAW) filters. Compared to existing technologies that pre-form filters through manufacturing processes and then use additional bonding processes to install the fabricated filters onto the front-end module of the semiconductor module, the semiconductor module provided by the present invention avoids alignment accuracy problems and unstable wire bonding quality issues caused by additional bonding processes. Furthermore, since no additional bonding processes are required, the SAW filters in the semiconductor module provided by the present invention can be well controlled, and the integration and performance of the semiconductor module can be improved, while manufacturing costs are reduced.

[0010] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a semiconductor module according to an embodiment of the present invention;

[0012] Figure 2A This is a top view schematic diagram of a conductive structure according to an embodiment of the present invention;

[0013] Figure 2B This is a top view schematic diagram of a conductive structure according to an embodiment of the present invention;

[0014] Figure 3 This is a schematic diagram of a semiconductor module according to another embodiment of the present invention;

[0015] Figures 4A-4E This is a schematic diagram of a semiconductor module manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0017] This invention relates to a semiconductor module and a method for manufacturing the same. The semiconductor module includes a substrate, a shielding structure, and a piezoelectric layer. The substrate includes a front side and at least one semiconductor element formed on the front side. The shielding structure is formed on the at least one semiconductor element. The piezoelectric layer is formed on the shielding structure. With these configurations, the semiconductor module can be manufactured without additional bonding processes, thereby improving the integration, controllability, and performance of the semiconductor module.

[0018] It should be noted that this invention does not show all possible embodiments, and other embodiments not presented in this invention may also be applied. Furthermore, the dimensions in the drawings are not drawn to scale with actual products. Therefore, the description and illustrations are for illustrative purposes only and are not intended to limit the scope of protection of this invention. Additionally, the descriptions in the embodiments, such as detailed structures, manufacturing processes, and material applications, are for illustrative purposes only and are not intended to limit the scope of protection of this invention. The details of the steps and structures of the embodiments can be varied and modified according to the needs of the actual application and manufacturing process without departing from the spirit and scope of this invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0019] Furthermore, throughout this document, all directional terms, such as "upper surface," "lower surface," "front," and "rear," are used only to explain the relative positions or orientations of the components of the device in a specific orientation (e.g., the orientation shown in the accompanying drawings). Therefore, if the device shown in one of the accompanying drawings is flipped, the directional indication will change accordingly, but should not affect the relative positions or orientations of the components.

[0020] Furthermore, the use of terms such as "first" and "second" in this document is for descriptive purposes only and should not be construed as indicating or implying their relative importance or manufacturing / assembly sequence, nor should it be construed as implying the number of technical features described.

[0021] Figure 1 This is a schematic diagram of a semiconductor module 10 according to an embodiment of the present invention. The semiconductor module 10 includes a substrate 100, a shielding structure 107, and a piezoelectric layer 109. The substrate 100 includes at least one semiconductor element 103 formed on the front side of the substrate 100. The shielding structure 107 is formed on the semiconductor element 103. The piezoelectric layer 109 is formed on the shielding structure 107.

[0022] In one embodiment, the substrate 100 may include a carrier 101, a first circuit layer 102, and a plurality of semiconductor elements 103. The carrier 101 is provided on a plane formed by the intersection of a first direction D1 and a second direction D2. The upper surface 101U of the carrier 101 is perpendicular to a third direction D3, and the first direction D1, the second direction D2, and the third direction D3 are all mutually perpendicular. The semiconductor elements 103 are formed on the upper surface 101U of the carrier 101, and the first circuit layer 102 is disposed between the semiconductor elements 103 and the upper surface 101U of the carrier 101 to provide electrical connection between the semiconductor elements 103 and the carrier 101.

[0023] In one embodiment, the front side of the substrate 100 can be understood as the side of the substrate 100 that includes the integrated circuit, with the front side relative to the rear side where the integrated circuit is not disposed; in other words, the front side of the substrate 100 can be understood as being in the same direction as the upper surface 101U of the carrier 101 in the third direction D3. In one embodiment, the carrier 101 can be a handling wafer or a silicon-containing substrate.

[0024] In one embodiment, the first circuit layer 102 may include an interlayer dielectric (ILD) 102a. In one embodiment, wiring techniques may be used to form metallic interconnects 102b in the interlayer dielectric 102a to fabricate the first circuit layer 102. In one embodiment, the first circuit layer 102 may include a redistribution layer (RDL).

[0025] Semiconductor element 103 can be a radio frequency (RF) front-end component used in the field of wireless communications. For example, in one embodiment, semiconductor element 103 can be a functional substrate with embedded inductors, wires, and couplers. In another embodiment, semiconductor element 103 can be a front end module (FEM) that can be integrated with controllers, power amplifiers, and other semiconductor switches on the same integrated circuit (IC) substrate.

[0026] A shielding structure 107 may be formed above the semiconductor element 103. More specifically, the shielding structure 107 is formed above the semiconductor element 103 along a third direction D3, such that the shielding structure 107 and the carrier 101 are respectively disposed on opposite sides of the semiconductor element 103. The semiconductor module 10 may further include a second circuit layer 104 and a metal layer 105 disposed between the shielding structure 107 and the semiconductor element 103. The metal layer 105 may be a metal pad with a nanometer-level thickness. In one embodiment, the thickness of the metal layer 105 may be between 0.5 micrometers (μm) and 1 millimeter (mm).

[0027] The second wiring layer 104 may be disposed between the metal layer 105 and the semiconductor element 103 to provide an electrical connection between the metal layer 105 and the semiconductor element 103. In one embodiment, the structure of the second wiring layer 104 is similar to that of the first wiring layer 102, and may include an interlayer dielectric material 104a and metal interconnects 104b. In another embodiment, the second wiring layer 104 may include a redistribution layer.

[0028] In one embodiment, the material forming the shielding structure 107 may include a dielectric material or a magnetic material. For example, the magnetic material may include ferrite, soft magnetic metallic materials, etc.; the soft magnetic metallic material may include iron (Fe), cobalt (Co), nickel (Ni), or alloys thereof. In another embodiment, the material forming the shielding structure 107 may include silicon nitride (SIN), a low dielectric constant material, hafnium oxide (HfO), etc. x Materials used include silicon dioxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium tantalate (LiTaO3), lithium niobate (LiNbO3), and iron(II,III) oxide (Fe3O4), etc. This invention does not limit the types of materials used in the shielding structure 107.

[0029] In this embodiment, the shielding structure 107 may include a first shielding layer 107a and a second shielding layer 107b. The first shielding layer 107a has a first density and is stacked on top of the semiconductor element 103 in a third direction D3. The second shielding layer 107b has a second density and is stacked on top of the first shielding layer 107a. The first density of the first shielding layer 107a is greater than the second density of the second shielding layer 107b. However, in another embodiment, the first density of the first shielding layer 107a may be less than the second density of the second shielding layer 107b.

[0030] Specifically, the first shielding layer 107a and the second shielding layer 107b can be formed into a sheet-like shielding structure 107 using lamination technology. Lamination technology can improve the strength and stability of the shielding structure 107. The greater the difference between the first density of the first shielding layer 107a and the second density of the second shielding layer 107b, the better the performance of the semiconductor module 10. For example, the first density of the first shielding layer 107a is close to 0, while the second density of the second shielding layer 107b is close to the density of tungsten (19.35 g / cm³). 3 )), or vice versa.

[0031] For example, the first shielding layer 107a may include a high dielectric constant material (high-k material), and the second shielding layer 107b may include a low dielectric constant material, or vice versa. The high dielectric constant material and the low dielectric constant material can be materials existing in the technical field described in this invention. Low dielectric constant materials can be, for example, silicon nitride, silicon dioxide, fluorinated silicate glass (FSG), ultra-low-k material (ULK), or nitrogen-doped carbide (NDC). High dielectric constant materials can be, for example, aluminum oxide (HfO2) or aluminum oxide (AlO2). x Zirconia (ZrO2), rhodium oxide (La2O3), or other suitable materials.

[0032] It is worth noting that the shielding structure 107 is not merely a two-layer structure. In one embodiment, the shielding structure 107 may include a third shielding layer (not shown) stacked on top of the second shielding layer 107b in the third direction D3. The material constituting the third shielding layer may be the same as or different from the material constituting the first shielding layer 107a and / or the second shielding layer 107b. The third density of the third shielding layer differs from the second density of the adjacent second shielding layer 107b; however, the third density of the third shielding layer may be the same as or different from the first density of the first shielding layer 107a.

[0033] In one embodiment, the semiconductor module 10 may further include a first buffer layer 106 disposed between the metal layer 105 and the shielding structure 107. Alternatively, the first buffer layer 106 may be formed between the shielding structure 107 and the semiconductor element 103. In one embodiment, the first buffer layer 106 may include oxides, oxynitrides, or carbonitrides, but is not limited thereto. For example, the first buffer layer 106 may include silicon oxynitride (SiON) or silicon carbonitride (SiCN). In one embodiment, the first buffer layer 106 may improve the heat dissipation performance of the semiconductor module 10. In one embodiment, the first buffer layer 106 may improve the interface compatibility between different layer elements, such as improving the interface compatibility between the metal layer 105 and the shielding structure 107, so that the metal layer 105 and the shielding structure 107 are stably connected.

[0034] A piezoelectric layer 109 may be formed on the shielding structure 107. More specifically, on the third direction D3, the piezoelectric layer 109 may be formed on the shielding structure 107, and the piezoelectric layer 109 and the semiconductor element 103 may be respectively disposed on opposite sides of the shielding structure 107. The piezoelectric layer 109 may be made of a piezoelectric material. The piezoelectric material may include a piezoelectric single crystal, a piezoelectric polycrystalline, a piezoelectric polymer, or a piezoelectric composite material. More specifically, the piezoelectric material may include any suitable piezoelectric material such as aluminum nitride (AlN), quartz, lithium tantalate (LiTaO3), lithium niobate (LiNbO3), ceramics, lead zirconate titanate (PZT), PVDF (polyvinylidene fluoride) and its copolymers, polyvinyl chloride (PVC), or a composite material composed of ceramics and polymers.

[0035] In this embodiment, the piezoelectric layer 109 is formed directly on the shielding structure 107 without the need for an additional bonding process to connect the piezoelectric layer 109 to the shielding structure 107. In other words, the piezoelectric layer 109 can be integrated into the semiconductor module 10 without requiring additional soldering steps or additional bumps or through-holes for connection. Therefore, the reliability of the semiconductor module 10 is not reduced due to poor alignment accuracy or unstable wire bonding quality, and the controllability of the piezoelectric layer 109 is improved. That is, the problems of difficulty in controlling the bonding process used to connect components in the prior art, as well as the insufficient consistency, integration, and performance of the semiconductor module 10 in the prior art, can be improved through the technical solution provided by the present invention.

[0036] like Figure 1As shown, the semiconductor module 10 may further include a conductive structure 110 embedded in the piezoelectric layer 109. The conductive structure 110 may extend through the third direction D3. Piezoelectric layer 109 The upper and lower surfaces. In this embodiment, the conductive structure 110 includes a plurality of interdigitated electrodes 210 / 211 extending in the third direction D3, and the plurality of interdigitated electrodes 210 / 211 are spaced apart in the piezoelectric layer 109 along the second direction D2.

[0037] For example, please refer to Figure 2A , Figure 2A It is a drawing Figure 1 A top view of the conductive structure 110. In this embodiment, the conductive structure 110 includes at least one pair of interdigitated electrodes 210 / 211 disposed in the piezoelectric layer 109. The interdigitated electrodes 210 include multiple interconnected conductive fingers 110F1, and the interdigitated electrodes 211 include multiple interconnected conductive fingers 110F2. They are dispersedly disposed on a plane formed by the intersection of a first direction D1 and a second direction D2, with the conductive fingers 110F1 of the interdigitated electrodes 210 and the conductive fingers 110F2 of the interdigitated electrodes 211 spaced apart from each other. The configuration of the interdigitated electrodes 210 / 211 in the conductive structure 110 can form a metal-insulator-metal capacitor (MOM CAP) element.

[0038] In one embodiment, a pair of interdigital electrodes 210 / 211 in the conductive structure 110 can be configured as an interdigital transducer (IDT). Alternatively, the conductive structure 110 can be described as including an interdigital transducer. In this case, the conductive structure 110 and the piezoelectric layer 109 can function as a filter, such as a surface acoustic wave filter. When the conductive structure 110 and the piezoelectric layer 109 function as a filter, the pair of interdigital electrodes 210 / 211 in the conductive structure 110 can be a signal input electrode and a signal output electrode, respectively.

[0039] In another embodiment, the interdigitated transducer can include various configurations to form various types of filters, such as transverse filters, multistrip coupler filters, interdigitated interdigital transducers, and double-mode filters. In addition, the semiconductor module 10 may also include a resonant circuit to reduce the insertion loss of the filter.

[0040] However, it is worth noting that the configuration of the conductive structure 110 is not limited to this. Although in this embodiment, the interdigitated electrodes 210 / 211 extend along the third direction D3 through the piezoelectric layer 109, in another embodiment, the conductive structure 110 is only disposed on the upper surface of the piezoelectric layer 109. Furthermore, although... Figure 2A Only one pair of interdigitated electrodes 210 / 211 is shown in the diagram, and the shown interdigitated electrode 210 includes only three conductive fingers 110F1, and the interdigitated electrode 211 includes only four conductive fingers 110F2. However, the conductive structure 110 may include multiple pairs of interdigitated electrodes 210 / 211 (e.g., Figure 2B The conductive structure 110 has three pairs of interdigitated electrodes 210 / 211. The number of conductive fingers 110F1 and 110F2 in each pair of interdigitated electrodes 210 / 211 is not limited thereto. In other embodiments, the number of conductive fingers 110F1 and 110F2 in the interdigitated electrodes 210 / 211 can be increased or decreased according to the design requirements of the semiconductor module 10. In one embodiment, the semiconductor module 10 may further include a second buffer layer 108 disposed on the shielding structure 107. Figure 1 As shown, on the third direction D3, the first buffer layer 106 and the second buffer layer 108 are respectively disposed on opposite sides of the shielding structure 107. In other words, the second buffer layer 108 is formed between the shielding structure 107 and the piezoelectric layer 109. In one embodiment, the second buffer layer 108 may include oxides, oxynitrides, or carbonitrides, but is not limited thereto. For example, the second buffer layer 108 may include silicon oxynitride (SiON) or silicon carbonitride (SiCN). In one embodiment, the second buffer layer 108 and the first buffer layer 106 may include the same material or be made of the same material.

[0041] In one embodiment, the second buffer layer 108 can absorb electromagnetic waves in the semiconductor module 10. In another embodiment, the second buffer layer 108 can improve the interface compatibility between different layer elements, such as improving the interface compatibility between the shielding structure 107 and the piezoelectric layer 109, so as to make the shielding structure 107 and the piezoelectric layer 109 stably connected.

[0042] The semiconductor module 10 may further include a first protective layer 111 disposed on the piezoelectric layer 109. In one embodiment, the first protective layer 111 is disposed on the upper surface of the piezoelectric layer 109, the second buffer layer 108 is disposed on the lower surface of the piezoelectric layer 109, and the conductive structure 110 penetrates the first protective layer 111, the piezoelectric layer 109 and the second buffer layer 108 along the third direction D3, and the lower end point of the conductive structure 110 in the third direction D3 is disposed in the second buffer layer 108.

[0043] The semiconductor module 10 may further include a second protective layer 112 disposed on the first protective layer 111. In one embodiment, the second protective layer 112 is disposed on the upper surface of the first protective layer 111, and also on the side surfaces of the first protective layer 111, the piezoelectric layer 109, and the second buffer layer 108. In another embodiment, the second protective layer 112 is disposed on a portion of the upper surface and a portion of the side surfaces of the shielding structure 107.

[0044] In one embodiment, the first protective layer 111 and the second protective layer 112 may comprise the same or different materials. In one embodiment, the first protective layer 111 and the second protective layer 112 may comprise a dielectric material. In one embodiment, the first protective layer 111 and the second protective layer 112 may comprise materials compatible with existing complementary metal-oxide-semiconductor (CMOS) fabrication processes, such as nitride, oxide, or ceramic materials. In one embodiment, the first protective layer 111 and the second protective layer 112 may comprise silicon nitride (SiN).

[0045] In one embodiment, the first protective layer 111 and the second protective layer 112 can improve the stiffness of the semiconductor module 10.

[0046] The semiconductor module 10 may also include an oxide structure 113 disposed on the second protective layer 112.

[0047] The semiconductor module 10 may also include a contact structure 114. In one embodiment, the contact structure 114 is disposed on the upper surface of the metal layer 105 to provide electrical connection between the metal layer 105 and other circuitry or devices (not shown).

[0048] In one embodiment, when the conductive structure 110 and the piezoelectric layer 109 serve as a surface acoustic wave (SAW) filter, the shielding structure 107 can enhance the signal; the first protective layer 111 and the second protective layer 112 can improve the performance of the SAW filter; the metal layer 105 can be used for heat dissipation and to prevent heat generated by the SAW filter from being transferred between the metal layer 105 and the carrier 101, for example, to the semiconductor element 103. The first protective layer 111 can improve the stiffness of the SAW filter and can improve the efficiency of the SAW filter, for example, the efficiency of the SAW filter at high frequencies. The second protective layer 112 can electrically isolate the two SAW filters from each other, or the second protective layer 112 can electrically isolate the two SAW filters from the contact structure 114. In one embodiment, the semiconductor module 10 may also include a temperature detection circuit (not shown) and / or a temperature compensation circuit (not shown) to prevent the stability of the SAW filter from being reduced by temperature.

[0049] Figure 3 This is a schematic diagram of a semiconductor module 30 according to another embodiment of the present invention. The structure of the semiconductor module 30 is generally similar to that of the semiconductor module 10. The difference lies in... Figure 3 The semiconductor element 303 shown may include a gallium nitride (GaN) device and a radio frequency silicon-on-insulator (RF-SOI) device, and the shielding structure 307 used in the semiconductor module 30 is different from the shielding structure 107 used in the semiconductor module 10.

[0050] In this embodiment, the semiconductor module 30 includes a substrate 300, a shielding structure 307, and a piezoelectric layer 309. The substrate 300 includes a carrier 301, a first circuit layer 302, and a plurality of semiconductor elements 303. The shielding structure 307 is formed on the semiconductor elements 303. The piezoelectric layer 309 is formed on the shielding structure 307.

[0051] In detail, the first circuit layer 302 is formed on the upper surface 301U of the carrier 301, and includes an interlayer dielectric material 302a and a metal interconnect 302b. The semiconductor device 303 includes two radio frequency insulated-cell (RFI) silicon-on-insulator (SiI) devices 303a and one gallium nitride (GaN) device 303b. The SiI devices 303a are disposed above the first circuit layer 302; the GaN device 303b is disposed above the SiI devices 303a; and a dielectric buffer layer 315 is also included between the SiI devices 303a and the GaN device 303b.

[0052] The semiconductor module 30 may further include a second wiring layer 304 and a metal layer 305 disposed between the shielding structure 307 and the semiconductor element 303. The metal layer 305 may be a metal pad with a nanometer-level thickness. In one embodiment, the thickness of the metal layer 305 may be between 0.5 micrometers (μm) and 1 millimeter (mm). The second wiring layer 304 may be disposed between the metal layer 305 and the semiconductor element 303 to provide electrical connection between the metal layer 305 and the semiconductor element 303. In one embodiment, the structure of the second wiring layer 304 is similar to that of the first wiring layer 302, and may include an interlayer dielectric material 304a and metal interconnects 304b. In another embodiment, the second wiring layer 304 may include a redistribution layer.

[0053] This invention does not limit the types of materials used in the shielding structure 307. In one embodiment, the material forming the shielding structure 307 may include dielectric materials or magnetic materials. For example, magnetic materials may include ferrite, soft magnetic metallic materials, silicon nitride, low dielectric constant materials, hafnium oxide, silicon dioxide, aluminum nitride, aluminum oxide, zinc oxide, lead zirconate titanate, lithium tantalate, lithium niobate, or iron(II,III) oxide, etc.

[0054] In this embodiment, the shielding structure 307 can be a single-layered structure with a gradient density. More specifically, the shielding structure 307 has a density that gradually increases or decreases along the stacking direction of the carrier 301, the first circuit layer 302, the semiconductor element 303, the shielding structure 307, and the piezoelectric layer 309. In one embodiment, the density of the shielding structure 307 decreases along the aforementioned stacking direction as the distance from the piezoelectric layer 309 increases; in another embodiment, the density of the shielding structure 307 decreases along the aforementioned stacking direction as the distance from the piezoelectric layer 309 decreases.

[0055] In one embodiment, the semiconductor module 30 may further include a first buffer layer 306 disposed between the metal layer 305 and the shielding structure 307. Alternatively, the first buffer layer 306 may be formed between the shielding structure 307 and the semiconductor element 303. The first buffer layer 306 may include oxides, oxynitrides, or carbonitrides (but is not limited to these), which can improve the heat dissipation performance of the semiconductor module 30 and improve the interface compatibility between the metal layer 305 and the shielding structure 307, thereby ensuring a stable connection between the metal layer 305 and the shielding structure 307.

[0056] A piezoelectric layer 309 can be formed on the shielding structure 307, allowing the piezoelectric layer 309 and the semiconductor element 303 to be disposed on opposite sides of the shielding structure 307. The piezoelectric layer 309 can be made of a piezoelectric material. In this embodiment, the piezoelectric layer 309 is formed directly on the shielding structure 307 without requiring additional bonding processes to complete the connection between the piezoelectric layer 309 and the shielding structure 307. Therefore, the reliability of the semiconductor module 30 is not reduced due to poor alignment accuracy or unstable wire bonding quality, and the controllability of the piezoelectric layer 309 is improved.

[0057] The semiconductor module 30 may further include a conductive structure 310 embedded in the piezoelectric layer 309. In this embodiment, the structure of the conductive structure 310 is similar to... Figure 1 and Figures 2A-2B The illustrated conductive structures 110 are identical, each including at least one pair of interdigitated electrodes 210 / 211 disposed in the piezoelectric layer 309. The interdigitated electrodes 210 / 211 in the conductive structure 310 can be configured as an interdigitated transducer.

[0058] The semiconductor module 30 may further include a second buffer layer 308, a first protective layer 311, a second protective layer 312, and an oxide structure 313. The second buffer layer 308 is disposed between the shielding structure 307 and the piezoelectric layer 309, such that the first buffer layer 306 and the second buffer layer 308 are respectively disposed on opposite sides of the shielding structure 307. The first protective layer 311 is disposed on the piezoelectric layer 309. The second protective layer 312 is disposed on the first protective layer 311 and covers the side surfaces of the shielding structure 307, the first protective layer 311, the piezoelectric layer 309, and the second buffer layer 308. The oxide structure 313 is disposed on the second protective layer 312.

[0059] The second buffer layer 308 may include oxides, oxynitrides, or carbonitrides (but is not limited to these), which can absorb electromagnetic waves in the semiconductor module 30 and improve the interface compatibility between the shielding structure 307 and the piezoelectric layer 309, so as to make the shielding structure 307 and the piezoelectric layer 309 stably connected. The first protective layer 311 and the second protective layer 312 can improve the rigidity of the semiconductor module 30.

[0060] The semiconductor module 30 may also include a contact structure 314 disposed on the upper surface of the metal layer 305 to provide electrical connection between the metal layer 305 and other circuits or devices (not shown).

[0061] Figures 4A-4E This is a schematic diagram of a method for manufacturing a semiconductor module 10 according to an embodiment of the present invention. Figures 4A-4E Cross-sectional views of exemplary structures in various manufacturing processes of the semiconductor module 10 are shown respectively. The method includes the following steps:

[0062] Please refer to Figure 4A A substrate 100 is provided, comprising a carrier 101, a first wiring layer 102, and at least one semiconductor element 103. The semiconductor element 103 is formed on an upper surface 101U of the carrier 101, and the first wiring layer 102 is formed between the semiconductor element 103 and the upper surface 101U of the carrier 101 to provide electrical connection between the semiconductor element 103 and the carrier 101. The first wiring layer 102 may include an interlayer dielectric material 102a and metal interconnects 102b. In one embodiment, the step of providing the substrate 100 includes depositing the interlayer dielectric material 102a and the metal interconnects 102b on the upper surface of the carrier 101 according to a wiring pattern to form the first wiring layer 102.

[0063] Next, a second circuit layer 104 is formed on the upper surface of the semiconductor element 103. In one embodiment, the structure of the second circuit layer 104 is similar to that of the first circuit layer 102, and may include an interlayer dielectric material 104a and metal interconnects 104b. In one embodiment, the interlayer dielectric material 104a and metal interconnects 104b may be deposited on the upper surface of the carrier 101 according to a wiring pattern to form the second circuit layer 104. Next, a metal layer 105 is formed on the second circuit layer 104, such that the second circuit layer 104 is disposed between the metal layer 105 and the semiconductor element 103. In one embodiment, the metal layer 105 may be deposited on the second circuit layer 104.

[0064] A first buffer layer 106 is formed on the upper surface of the metal layer 105, and then a shielding structure 107 is formed on the upper surface of the first buffer layer 106. In one embodiment, the first buffer layer 106 may be deposited on the upper surface of the metal layer 105, and the shielding structure 107 may be deposited on the upper surface of the first buffer layer 106.

[0065] In one embodiment, the step of forming the shielding structure 107 may include forming a first shielding layer 107a and a second shielding layer 107b. More specifically, the step of forming the shielding structure 107 may include: forming a first shielding layer 107a, the first shielding layer 107a having a first density and stacked on the semiconductor device 103; and forming a second shielding layer 107b, the second shielding layer 107b having a second density and stacked on the first shielding layer 107a. In one embodiment, the first shielding layer 107a and the second shielding layer 107b may be formed sequentially on the first buffer layer 106, for example, by a deposition technique. In another embodiment, the shielding structure 107 including the first shielding layer 107a and the second shielding layer 107b may be formed in a separate manufacturing process, and then the shielding structure 107 including the first shielding layer 107a and the second shielding layer 107b may be connected to the first buffer layer 106 by a bonding technique.

[0066] Please refer to Figure 4B After the shielding structure 107 is formed, a second buffer layer 108 is formed on the upper surface of the shielding structure 107, a piezoelectric layer 109 is formed on the upper surface of the second buffer layer 108, and then a first protective layer 111 is formed on the upper surface of the piezoelectric layer 109. In one embodiment, the second buffer layer 108, the piezoelectric layer 109, and the first protective layer 111 may be formed using deposition technology or bonding technology.

[0067] Please refer to Figure 4CNext, a conductive structure 110 is formed through the piezoelectric layer 109. In one embodiment, a portion of the second buffer layer 108, the piezoelectric layer 109, and the first protective layer 111 may be removed to form a first opening 501, which exposes the second buffer layer 108; a conductive material is then deposited in the first opening 501 to form the conductive structure 110. In one embodiment, the removal may be performed using an etching technique.

[0068] Please refer to Figure 4D A portion of the shielding structure 107, the second buffer layer 108, the piezoelectric layer 109, and the first protective layer 111 are removed to form a second opening 502. The second opening 502 exposes the sidewalls of the second buffer layer 108, the piezoelectric layer 109, and the first protective layer 111, and also exposes the shielding structure 107. In one embodiment, the second opening 502 exposes a portion of the sidewalls of the shielding structure 107. In one embodiment, the removal can be performed using an etching technique.

[0069] Please refer to Figure 4E ,exist Figure 4D After the initial processing stage, a second protective layer 112 can be formed on the side surface of the second opening 502, the bottom surface of the second opening 502, and the upper surface of the first protective layer 111, and the second protective layer 112 covers the conductive structure 110. Next, the second protective layer 112, the shielding structure 107, and the first buffer layer 106 on the bottom surface of the second opening 502 are removed to expose the metal layer 105. In one embodiment, removal can be performed using an etching technique.

[0070] exist Figure 4E After the processing stage, oxide structure 113 and contact structure 114 can be formed to form such as Figure 1 The semiconductor module 10 shown.

[0071] According to the above embodiments, in the semiconductor module provided by the present invention, a shielding structure is first formed on the front-end module, and a piezoelectric layer is directly formed on the shielding structure using, for example, deposition or bonding techniques. Then, subsequent processes are performed to form one or more surface acoustic wave (SAW) filters. Compared to existing technologies that pre-form the filters through manufacturing processes and then use additional bonding processes to install the fabricated filters onto the front-end module of the semiconductor module, the present invention avoids alignment accuracy problems and unstable wire bonding quality issues caused by additional bonding processes. Furthermore, since no additional bonding processes are required, the SAW filters in the semiconductor module provided by the present invention can be well controlled, and the integration and performance of the semiconductor module can be improved, while manufacturing costs are reduced.

[0072] In summary, although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A semiconductor module, characterized in that, include: A substrate having a front side, the substrate including at least one semiconductor element formed on the front side; A shielding structure is formed on the at least one semiconductor element; A piezoelectric layer is formed on the shielding structure; A second buffer layer is formed between the shielding structure and the piezoelectric layer; A first protective layer is formed on the upper surface of the piezoelectric layer; The second protective layer is disposed on the upper and side surfaces of the first protective layer, the side surface of the piezoelectric layer, the side surface of the second buffer layer, a portion of the upper surface of the shielding structure, and a portion of the side surface of the shielding structure. as well as A conductive structure extends through the first protective layer, the piezoelectric layer, and the second buffer layer, with the lower end of the conductive structure disposed in the second buffer layer.

2. The semiconductor module as described in claim 1, characterized in that, The shielding structure includes: A first shielding layer having a first density and stacked on the at least one semiconductor element; and The second shielding layer has a second density and is stacked on the first shielding layer.

3. The semiconductor module as described in claim 2, characterized in that, The first density is greater than the second density.

4. The semiconductor module as described in claim 2, characterized in that, The first density is less than the second density.

5. The semiconductor module as described in claim 1, characterized in that, The shielding structure has a gradient density.

6. The semiconductor module as described in claim 5, characterized in that, The gradient density decreases with increasing distance from the piezoelectric layer.

7. The semiconductor module as described in claim 5, characterized in that, The gradient density decreases as the distance from the piezoelectric layer decreases.

8. The semiconductor module as described in claim 1, characterized in that, It also includes a first buffer layer formed between the shielding structure and the at least one semiconductor element.

9. The semiconductor module as claimed in claim 1, characterized in that, The conductive structure includes an interdigital transducer.

10. The semiconductor module as claimed in claim 1, characterized in that, The at least one semiconductor device includes a gallium nitride (GaN) device and a radio frequency silicon-on-insulator (RF-SOI) device.

11. The semiconductor module as claimed in claim 1, characterized in that, The at least one semiconductor element includes a temperature detection circuit.

12. The semiconductor module as claimed in claim 1, characterized in that, The at least one semiconductor element includes a front-end module (FEM).

13. A method for manufacturing a semiconductor module, comprising: A substrate is provided having a front side, and the substrate includes at least one semiconductor element formed on the front side; A shielding structure is formed on the at least one semiconductor element; A second buffer layer is formed on this shielding structure; A piezoelectric layer is formed on the second buffer layer; a first protective layer is formed on the upper surface of the piezoelectric layer. A conductive structure is formed penetrating the first protective layer, the piezoelectric layer, and the second buffer layer, with the lower end of the conductive structure disposed in the second buffer layer; and A second protective layer is formed on the first protective layer. The second protective layer is disposed on the upper and side surfaces of the first protective layer, the side surface of the piezoelectric layer, the side surface of the second buffer layer, a portion of the upper surface of the shielding structure, and a portion of the side surface of the shielding structure.

14. The method as described in claim 13, characterized in that, Also includes: Prior to the step of forming the shielding structure, a first buffer layer is formed on the at least one semiconductor element.

15. The method as described in claim 13, characterized in that, The shielding structure is deposited on the at least one semiconductor element.

16. The method as described in claim 13, characterized in that, The piezoelectric layer is bonded to the second buffer layer, or the piezoelectric layer is deposited on the second buffer layer.

17. The method as described in claim 13, characterized in that, The steps for forming this shielding structure include: A first shielding layer is formed, the first shielding layer having a first density and stacked on the at least one semiconductor element; and A second shielding layer is formed, which has a second density and is stacked on the first shielding layer.

18. The method as described in claim 13, characterized in that, The step of forming the shielding structure includes forming the shielding structure with a gradient density.

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