Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method for operating the semiconductor memory device are provided herein. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks respectively connected to a plurality of source selection lines. The peripheral circuit performs a programming operation on the memory block. The control logic is configured to control the peripheral circuit to increase the voltage of a common source line connected to the memory block, increase the voltage of at least one source selection line among the plurality of source selection lines to a first voltage level, and set the voltage of a bit line connected to the memory block and increase the voltage of at least one source selection line from the first voltage level to a second voltage level.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Art

[0002] Semiconductor memory devices can have a two-dimensional (2D) structure in which strings are arranged horizontally on a semiconductor substrate. Alternatively, memory devices can have a three-dimensional (3D) structure in which strings are stacked vertically on a semiconductor substrate. As memory devices with a 2D structure reach their physical scaling limitations (i.e., limitations on integration), semiconductor manufacturers are producing 3D memory devices that include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0003] One embodiment of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include a memory block, a peripheral circuit, and control logic. The memory block may include multiple sub-blocks, each of which is connected to a plurality of source select lines. The peripheral circuit may be configured to perform a data programming operation on the memory block. The control logic may be configured to control the peripheral circuit to increase the voltage of a common source line connected to the memory block, increase the voltage of at least one source select line among the plurality of source select lines to a first voltage level, set the voltage of a bit line connected to the memory block, and increase the voltage of the at least one source select line from the first voltage level to a second voltage level.

[0004] One embodiment of the present disclosure may provide a method for operating a semiconductor memory device. Based on the method for operating a semiconductor memory device, a memory block having multiple sub-blocks may be programmed. The multiple sub-blocks may be respectively connected to multiple source select lines. The voltage of a common source line connected to the memory block may be increased, the voltage of at least one source select line among the multiple source select lines may be increased to a first voltage level, and the voltage of a bit line connected to the memory block may be set simultaneously with the voltage of the at least one source select line being increased from the first voltage level to a second voltage level.

[0005] One embodiment of the present disclosure may provide a method for operating a semiconductor memory device. Based on the method for operating a semiconductor memory device, a memory block having multiple sub-blocks may be programmed. The multiple sub-blocks may be respectively connected to multiple source select lines. The voltage of a common source line connected to the memory block may be increased, the voltage of at least one source select line among the multiple source select lines may be increased to a first voltage level, the voltage of a bit line connected to the memory block may be set, and the voltage of the at least one source select line may be increased from the first voltage level to a second voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0007] Figure 2 It shows Figure 1 FIG. 1 is a diagram of one embodiment of a memory cell array.

[0008] Figure 3 It shows Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0009] Figure 4 It shows Figure 2 1 is a circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0010] Figure 5 is a diagram showing an example of sub-blocks forming a memory block.

[0011] Figure 6A It is shown in detail Figure 5 The circuit diagram of the first sub-block among the sub-blocks shown.

[0012] Figure 6B is a circuit diagram showing some cell strings included in the first sub-block and the second sub-block.

[0013] Figure 7 is a circuit diagram illustrating a page buffer PB1 included in the semiconductor memory device 100 according to one embodiment of the present disclosure.

[0014] Figure 8 is a diagram illustrating a program operation of a semiconductor memory device according to one embodiment of the present disclosure.

[0015] Figure 9 is a timing diagram illustrating in detail a program operation of a semiconductor memory device according to one embodiment of the present disclosure.

[0016] Figure 10is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0017] Figure 11 It shows Figure 10 A flow chart of one embodiment of a method of operating a semiconductor memory device.

[0018] Figure 12 It is an explanation Figure 11 A timing diagram of an implementation method of FIG.

[0019] Figure 13 It shows Figure 10 A flow chart of one embodiment of a method of operating a semiconductor memory device.

[0020] Figure 14 It is an explanation Figure 13 A timing diagram of an implementation method of FIG.

[0021] Figure 15 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0022] Figure 16 It shows Figure 15 A flow chart of an embodiment of a method of operating a semiconductor memory device.

[0023] Figure 17 It is an explanation Figure 16 A timing diagram of an implementation method of FIG.

[0024] Figure 18 It shows Figure 15 A flow chart of an embodiment of a method of operating a semiconductor memory device.

[0025] Figure 19 It is an explanation Figure 18 A timing diagram of an implementation method of FIG.

[0026] Figure 20 is a diagram showing an example of sub-blocks forming a memory block.

[0027] Figure 21 is a circuit diagram illustrating a portion of a cell string included in each of the first to fourth subblocks.

[0028] Figure 22 It shows that Figure 1 1 is a block diagram of an embodiment of a memory system 1000 of a semiconductor memory device 100.

[0029] Figure 23 It shows Figure 22 A block diagram of an application example of a memory system.

[0030] Figure 24 is shown with reference Figure 23 A block diagram of a computing system depicting a memory system. DETAILED DESCRIPTION

[0031] The specific structural description or functional description in the embodiments of the present disclosure introduced in this specification or this application is exemplified to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0032] In the following description of the embodiments, when a parameter is referred to as being "predetermined," it may be intended that the value of the parameter is predetermined before the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the execution of the process or algorithm.

[0033] It should be understood that although the terms "first," "second," "third," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present disclosure.

[0034] Furthermore, it should be understood that when an element is referred to as being “connected” or “coupled” to another element, the element can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0035] Various embodiments of the present disclosure are directed to a semiconductor memory device capable of reducing a peak current and a method of operating the semiconductor memory device.

[0036] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0037] Reference Figure 1 , the semiconductor memory device 100 may include a memory cell array 110 , an address decoder 120 , a read / write circuit 130 , a control logic 140 , and a voltage generator 150 .

[0038] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may be coupled to the address decoder 120 via word lines WL. The memory blocks BLK1 to BLKz may be coupled to the read / write circuit 130 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells and may be implemented as nonvolatile memory cells having a vertical channel structure. The memory cell array 110 may be implemented as a memory cell array having a two-dimensional (2D) structure. In one embodiment, the memory cell array 110 may be implemented as a memory cell array having a three-dimensional (3D) structure. Each memory cell included in the memory cell array may store at least one bit of data. In one embodiment, each memory cell included in the memory cell array 110 may be a single-level cell (SLC) storing 1 bit of data. In one embodiment, each memory cell included in the memory cell array 110 may be a multi-level cell (MLC) storing 2 bits of data. In one embodiment, each memory cell included in the memory cell array 110 may be a triple-level cell (TLC) storing 3-bit data. In one embodiment, each memory cell included in the memory cell array 110 may be a quad-level cell (QLC) storing 4-bit data. In various embodiments, the memory cell array 110 may include a plurality of memory cells each storing 5 or more bits of data.

[0039] The address decoder 120, the read / write circuit 130, the control logic 140, and the voltage generator 150 may operate as peripheral circuits to drive the memory cell array 110. The address decoder 120 may be coupled to the memory cell array 110 through word lines WL. The address decoder 120 may operate based on the control logic 140. The address decoder 120 may receive an address through an input / output buffer (not shown) provided in the semiconductor memory device 100.

[0040] The address decoder 120 can decode the block address among the received addresses. The address decoder 120 can select at least one memory block based on the decoded block address. When performing a read voltage application operation during a read operation, the address decoder 120 can apply the read voltage Vread generated by the voltage generator 150 to the selected word line of the selected memory block and can apply the pass voltage Vpass to the remaining unselected word lines. During a program verification operation, the address decoder 120 can apply the verification voltage generated by the voltage generator 150 to the selected word line of the selected memory block and can apply the pass voltage Vpass to the remaining unselected word lines.

[0041] The address decoder 120 may decode the column address among the received addresses and may transmit the decoded column address to the read / write circuit 130 .

[0042] The read operation and programming operation of the semiconductor memory device 100 can be performed page by page. The address received at the request of the read operation and programming operation may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line based on the block address and the row address. The column address can be decoded by the address decoder 120 and then provided to the read / write circuit 130.

[0043] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0044] The read / write circuit 130 may include a plurality of page buffers PB1 to PBm. The read / write circuit 130 may operate as a "read circuit" during a read operation of the memory cell array 110 and as a "write circuit" during a write operation. The plurality of page buffers PB1 to PBm may be coupled to the memory cell array 110 via bit lines BL1 to BLm. During a read operation or a program verification operation, in order to sense the threshold voltage of a memory cell, the page buffers PB1 to PBm may continuously provide a sensing current to the bit line coupled to the memory cell while each of the page buffers PB1 to PBm is sensing a change in a flowing current based on the programming state of the corresponding memory cell through a sensing node and latching it as sense data. The read / write circuit 130 may operate based on a page buffer control signal output from the control logic 140.

[0045] During a read operation, the read / write circuit 130 may sense data stored in a memory cell and may temporarily store the read data. The read / write circuit 130 may then output the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read / write circuit 130 may include a column selection circuit, etc., and a page buffer (or page register).

[0046] The control logic 140 may be coupled to the address decoder 120, the read / write circuit 130, and the voltage generator 150. The control logic 140 may receive a command CMD and a control signal CTRL via an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 may control the overall operation of the semiconductor memory device 100 based on the control signal CTRL. The control logic 140 may output a control signal that controls the precharge potential level at the sensing nodes of the plurality of page buffers PB1 to PBm. The control logic 140 may control the read / write circuit 130 to perform a read operation on the memory cell array 110.

[0047] The voltage generator 150 may generate a read voltage Vread and a pass voltage Vpass required for a read operation based on a control signal output from the control logic 140. The voltage generator 150 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of voltages having various voltage levels, and may generate the plurality of voltages by selectively enabling the plurality of pumping capacitors based on the control logic 140.

[0048] The address decoder 120, the read / write circuit 130, and the voltage generator 150 may function as peripheral circuits for performing read, write, and erase operations on the memory cell array 110. The peripheral circuits may perform read, write, and erase operations on the memory cell array 110 based on the control logic 140.

[0049] Figure 2 It shows Figure 1 Schematic diagram of an embodiment of a memory cell array.

[0050] Reference Figure 2 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional (3D) structure. Each memory block may include a plurality of memory cells stacked on a substrate. These memory cells may be arranged along a positive X (+X) direction, a positive Y (+Y) direction, and a positive Z (+Z) direction. Figure 3 and Figure 4 Describe the structure of each memory block in detail.

[0051] Figure 3 It shows Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0052] Reference Figure 3, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (ie, a positive (+) X direction). Figure 3 , two cell strings are arranged in the column direction (ie, the positive (+) Y direction). However, this illustration is made for convenience of description, and it should be understood that three or more cell strings may be arranged in the column direction.

[0053] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0054] The select transistors SST and DST and the memory cells MC1 to MCn may each have a similar structure. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a column providing a channel layer may be provided for each cell string. In one embodiment, a column providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided for each cell string.

[0055] The source select transistor SST of each cell string may be connected between the common source line CSL and the memory cells MC1 to MCp.

[0056] In one embodiment, source selection transistors of cell strings arranged in the same row may be coupled to one source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows may be coupled to different source selection lines. Figure 3 , source selection transistors of cell strings CS11 to CS1m in a first row may be coupled to a first source selection line SSL1 , and source selection transistors of cell strings CS21 to CS2m in a second row may be coupled to a second source selection line SSL2 .

[0057] In one embodiment, source select transistors of cell strings CS11 to CS1m and CS21 to CS2m may be commonly coupled to a single source select line.

[0058] The first to nth memory cells MC1 to MCn in each cell string may be coupled between a source select transistor SST and a drain select transistor DST.

[0059] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MC1 and p+1th to nth memory cells MCp+1. The first to pth memory cells MCp can be arranged sequentially in the negative Z (-Z) direction and can be connected in series between the source select transistor SST and the tubular transistor PT. The p+1th to nth memory cells MCp+1 can be arranged sequentially in the positive Z (+Z) direction and can be connected in series between the tubular transistor PT and the drain select transistor DST. The first to pth memory cells MC1 and p+1th to nth memory cells MCp+1 can be connected to each other via the tubular transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string can be connected to the first to nth word lines WL1 to WLn, respectively.

[0060] A gate of the tube transistor PT of each cell string may be coupled to a pipeline PL.

[0061] The drain select transistor DST of each cell string can be connected between the corresponding bit line and the memory cells MCp+1 to MCn. Cell strings arranged in different rows can be connected to different drain select lines extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0062] Cell strings arranged in different columns can be connected to different bit lines extending in the column direction. Figure 3 , the cell strings CS11 and CS21 in the first column may be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column may be coupled to the m-th bit line BLm.

[0063] Memory cells connected to the same word line in cell strings arranged in the same row can constitute a single page. For example, among cell strings CS11 to CS1m in the first row, memory cells connected to the first word line WL1 can constitute a single page. Among cell strings CS21 to CS2m in the second row, memory cells connected to the first word line WL1 can constitute another single page. Cell strings arranged in a single row can be selected by selecting one of drain select lines DSL1 and DSL2. A single page can be selected from the selected cell string by selecting one of word lines WL1 to WLn.

[0064] In one embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be respectively connected to even bit lines, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be respectively connected to odd bit lines.

[0065] In one embodiment, one or more of the first to nth memory cells MC1 to MCn may be used as dummy memory cells. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKa may be improved, but the size of the memory block BLKa may increase. When fewer memory cells are provided, the size of the memory block BLKa may be reduced, but the operational reliability of the memory block BLKa may deteriorate.

[0066] In order to effectively control one or more dummy memory cells, each dummy memory cell may have a desired threshold voltage. Before or after performing an erase operation on the memory block BLKa, a programming operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after the programming operation has been performed, the threshold voltage of the dummy memory cell may control the voltage applied to the dummy word line connected to the corresponding dummy memory cell, and thus, the dummy memory cell may have a desired threshold voltage.

[0067] Figure 4 It shows Figure 2 1 is a circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0068] Reference Figure 4 , the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' may extend along a positive Z (+Z) direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0069] The source select transistor SST of each cell string can be connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row can be connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row can be connected to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row can be connected to a second source select line SSL2. In one embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly connected to a single source select line.

[0070] First to nth memory cells MC1 to MCn in each cell string may be connected in series between source select transistors SST and drain select transistors DST. Gates of first to nth memory cells MC1 to MCn may be coupled to first to nth word lines WL1 to WLn, respectively.

[0071] The drain select transistor DST of each cell string can be connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in different rows can be connected to different drain select lines extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0072] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 4 The memory block BLKb is connected to Figure 3 The memory block BLKa has a similar equivalent circuit.

[0073] In one embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in a row direction may be connected to even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in a row direction may be connected to odd bit lines, respectively.

[0074] In one embodiment, one or more of the first to nth memory cells MC1 to MCn may be used as dummy memory cells. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKb may be improved, but the size of the memory block BLKb may increase. When fewer memory cells are provided, the size of the memory block BLKb may be reduced, but the operational reliability of the memory block BLKb may deteriorate.

[0075] In order to effectively control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Before or after performing an erase operation on the memory block BLKb, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after the programming operation has been performed, the threshold voltage of the dummy memory cell can control the voltage applied to the dummy word line connected to the corresponding dummy memory cell, and thus, the dummy memory cell can have the desired threshold voltage.

[0076] Figure 5 is a diagram showing an example of sub-blocks forming a memory block.

[0077] Reference Figure 5 , showing Figure 3 or Figure 4 The memory block BLKa or BLKb shown includes sub-blocks SUB BLOCK 1 and SUB BLOCK 2. In one example, referring to Figure 5 Combined with Figure 3 , the sub-blocks included in the memory block BLKa can be defined as cell strings that share a drain selection line or a source selection line. Figure 3 , cell strings CS11 to CS1m sharing the first drain select line DSL1 and the first source select line SSL1 may form a first sub-block SUB BLOCK 1. Meanwhile, cell strings CS21 to CS2m sharing the second drain select line DSL2 and the second source select line SSL2 may form a second sub-block SUB BLOCK2.

[0078] In one example, Figure 4, cell strings CS11' to CS1m' sharing the first drain selection line DSL1 and the first source selection line SSL1 may form a first sub-block SUB BLOCK 1. At the same time, cell strings CS21' to CS2m' sharing the second drain selection line DSL2 and the second source selection line SSL2 may form a second sub-block SUB BLOCK 2. The memory block may include two sub-blocks SUB BLOCK 1 and SUB BLOCK 2 arranged in the +Y direction. Each of the sub-blocks SUB BLOCK 1 and SUB BLOCK 2 may include cell strings arranged in a row direction (i.e., +X direction). At the same time, each of the sub-blocks SUB BLOCK 1 and SUB BLOCK 2 may include pages arranged in a string direction (i.e., +Z direction). This will be described below with reference to Figure 6A and Figure 6B Describes the detailed configuration of each sub-block.

[0079] Figure 6A It is shown in detail Figure 5 1. A circuit diagram of a first sub-block among the sub-blocks shown in FIG. Since the second sub-block can be configured in the same manner as the first sub-block, a detailed circuit diagram of the second sub-block is omitted here.

[0080] Reference Figure 6A The first sub-block SUB BLOCK 1 may include cell strings CS11 to CS1m that share a first drain select line DSL1 and a first source select line SSL1. That is, the cell strings CS11 to CS1m included in the first sub-block SUB BLOCK 1 may be commonly coupled to the first drain select line DSL1 and the first source select line SSL1. The cell strings CS11 to CS1m may be arranged in the +X direction in the first sub-block SUB BLOCK 1. The cell strings CS11 to CS1m may be coupled to corresponding bit lines BL1 to BLm, respectively.

[0081] Meanwhile, the first sub-block SUB BLOCK 1 may include pages PAGE11 to PAGE1n arranged in the +Z direction. Each of the pages PAGE11 to PAGE1n may be a group of memory cells coupled to a corresponding one of the word lines WL1 to WLn.

[0082] Although Figure 6A Although not shown in FIG, the second sub-block SUB BLOCK 2 may also include cell strings CS21 to CS2m arranged in the +X direction. Meanwhile, the second sub-block SUB BLOCK 2 may include pages PAGE21 to PAGE2n arranged in the +Z direction.

[0083] Figure 6B is a circuit diagram showing some cell strings included in the first sub-block and the second sub-block.

[0084] Reference Figure 6B , shows a cell string CS11 included in a first sub-block SUB BLOCK 1 and a cell string CS21 included in a second sub-block SUBBLOCK 2 . Figure 6B is shown in the +Y direction Figure 5 Therefore, in Figure 6B , the cell strings CS12 to CS1m included in the first sub-block SUB BLOCK 1 and the cell strings CS22 to CS2m included in the second sub-block SUB BLOCK 2 are not shown.

[0085] The cell string CS11 in the first sub-block SUB BLOCK 1 may include memory cells MC11 to MC1n coupled between the first drain select transistor DST1 and the first source select transistor SST1. The cell string CS21 in the second sub-block SUB BLOCK 2 may include memory cells MC21 to MC2n coupled between the second drain select transistor DST2 and the second source select transistor SST2.

[0086] The cell strings CS11 included in the first sub-block SUB BLOCK 1 and the cell strings CS21 included in the second sub-block SUB BLOCK 2 may be commonly coupled to the bit line BL1. At the same time, the page buffer PB1 may be commonly coupled to the bit line BL1. That is, the cell strings CS11 included in the first sub-block SUB BLOCK 1 and the cell strings CS21 included in the second sub-block SUB BLOCK 2 may share the page buffer PB1.

[0087] Figure 7 is a circuit diagram illustrating a page buffer PB1 included in the semiconductor memory device 100 according to one embodiment of the present disclosure. Figure 7 The page buffer shown can be Figure 1 One of the page buffers PB1 to PBm included in the read / write circuit 130. Since a plurality of page buffers PB1 to PBm included in the read / write circuit 130 may be configured in a similar manner, one page buffer is described by way of example.

[0088] The page buffer may be operated based on signals output from the control logic 140. Signals PB_SENSE, SA_PRECH_N, SA_SENSE, SA_CSOC, SA_DISCH, and PRECHSO_N, which will be described below, may be included in the control signal CTRPB output from the control logic 140. The page buffer PB1 will be described in detail below.

[0089] Reference Figure 7The page buffer PB1 can be coupled to the memory cells via the bit line BL1 and can perform a bit line precharge operation in which the bit line BL1 is charged with charge supplied from the power supply voltage source VCORE via the first to fifth NMOS transistors N1 to N5 and the first to third PMOS transistors P1 to P3. Furthermore, the page buffer PB1 can discharge the charged bit line BL1 to the ground voltage via the first, fourth, and fifth NMOS transistors N1, N4, and N5.

[0090] A first NMOS transistor N1 may be coupled between a bit line BL1 and a common node CSO. A first PMOS transistor P1 may be coupled between a power supply voltage source VCORE and a sense amplifier (AMP) node SAN. A second NMOS transistor N2 may be coupled between the common node CSO and a sense AMP node SAN. A second PMOS transistor P2 may be coupled between the sense AMP node SAN and a sense node SO. A third NMOS transistor N3 may be coupled between the sense node SO and the common node CSO. A third PMOS transistor P3 may be coupled between the power supply voltage source VCORE and the sense node SO. A fourth NMOS transistor N4 and a fifth NMOS transistor N5 may be coupled in series between the common node CSO and a ground voltage source.

[0091] The first NMOS transistor N1 can be controlled based on the page buffer sense signal PB_SENSE, the second NMOS transistor N2 can be controlled based on the current sense signal SA_CSOC, and the third NMOS transistor N3 can be controlled based on the sense amp sense signal SA_SENSE. Furthermore, the fourth NMOS transistor N4 can be controlled based on the sense amp discharge signal SA_DISCH, and the fifth NMOS transistor N5 and the first PMOS transistor P1 can be controlled based on the voltage of the node QS of the sense latch circuit LATS. The second PMOS transistor P2 can be controlled based on the sense amp precharge signal SA_PRECH_N, and the third PMOS transistor P3 can be controlled based on the sense node precharge signal PRECHSO_N. That is, the page buffer sense signal PB_SENSE can be applied to the gate of the first NMOS transistor N1, the current sense signal SA_CSOC can be applied to the gate of the second NMOS transistor N2, and the sense amp sense signal SA_SENSE can be applied to the gate of the third NMOS transistor N3. In addition, the sense AMP discharge signal SA_DISCH may be applied to the gate of the fourth NMOS transistor N4, and the voltage of the node QS of the sense latch circuit LATS may be applied to the gates of the fifth NMOS transistor N5 and the first PMOS transistor P1. The sense AMP precharge signal SA_PRECH_N may be applied to the gate of the second PMOS transistor P2, and the sense node precharge signal PRECHSO_N may be applied to the gate of the third PMOS transistor P3.

[0092] The sensing latch circuit LATS may include a latch composed of two inverters (not shown) connected to the node QS, and a reset transistor (not shown) and a set transistor (not shown) for controlling the voltage of the node QS. Since the structure of the sensing latch circuit LATS is well known, Figure 7 The detailed configuration will be omitted.

[0093] Figure 8 is a diagram illustrating a program operation of a semiconductor memory device according to one embodiment of the present disclosure.

[0094] Reference Figure 8 The programming operation of the semiconductor memory device may include multiple programming loops, each of which may include a precharge phase, a programming phase, and a verification phase.

[0095] In the precharge phase, an operation of setting a bit line voltage of a sub-block as a program target in a memory block may be performed, and a string precharge operation of sub-blocks other than the program target in the memory block may be performed.

[0096] The operation of setting the bit line voltage of the sub-block as the programming target may include setting the bit line voltage to a program enable voltage or a program inhibit voltage to program data into the page indicating the programming target in the corresponding sub-block. When a program pulse is applied to the selected word line in a subsequent programming phase, the threshold voltage of the memory cell connected to the bit line set to the program enable voltage may shift. Meanwhile, in the subsequent programming phase, the threshold voltage of the memory cell connected to the bit line set to the program inhibit voltage may not shift.

[0097] In one embodiment, the program enable voltage may be a ground voltage. Figure 7 In the structure of the page buffer PB1 shown, the ground voltage can be transmitted to the bit line BL1 through the fifth NMOS transistor N5, the fourth NMOS transistor N4, and the first NMOS transistor N1.

[0098] In one embodiment, the program inhibit voltage may be a power supply voltage VCORE. In this case, in a case such as Figure 7 In the structure of the page buffer PB1 shown, the power supply voltage VCORE can be transmitted to the bit line BL1 through the first PMOS transistor P1, the second NMOS transistor N2, and the first NMOS transistor N1. In one embodiment, the power supply voltage VCORE can be transmitted to the bit line BL1 through the first PMOS transistor P1, the second PMOS transistor P2, the third NMOS transistor N3, and the first NMOS transistor N1.

[0099] In both cases (one case of transmitting a program enable voltage to the bit line and the other case of transmitting a program inhibit voltage to the bit line), the first NMOS transistor N1 can be turned on and, therefore, a corresponding voltage can be transmitted to the bit line. That is, the operation of setting the bit line voltage can be performed by increasing the page buffer sense signal PB_SENSE applied to the page buffers PB1 to PBm from a cut-off voltage to a cut-on voltage.

[0100] The string precharge operation for sub-blocks other than the program target may include an operation of transferring a voltage applied from a common source line to strings included in unselected sub-blocks. Figure 3 and Figure 4 As shown, since different sub-blocks are commonly coupled to a selected word line, memory cells included in unselected sub-blocks may also be affected by a program pulse applied to a word line during a program operation on a selected sub-block.

[0101] For example, in Figures 5 to 6BIn the illustrated memory block structure, consider the case of programming page PAGE11 having memory cells MC11 included in cell string CS11. In this case, the first sub-block SUB BLOCK 1 may correspond to the sub-block selected as the programming target, and the second sub-block SUB BLOCK 2 may correspond to the unselected sub-block. When programming page PAGE11, a programming pulse may be applied to the first word line WL1. The cell string CS21 included in the unselected sub-block may also be connected to the first word line WL1. Therefore, when a programming pulse is applied to the first word line WL1 when the channel voltage of memory cell MC21 is low, the threshold voltage of memory cell MC21 may shift. Therefore, when a sub-block having cell strings CS11 to CS1m is selected as the programming target, the problem of unexpected shifting of the threshold voltage of the memory cells included in the unselected sub-block can be prevented by sufficiently increasing the channel voltage of the cell strings included in the unselected sub-block (e.g., cell strings CS21 to CS2m). This operation may be referred to as a "string precharge operation."

[0102] According to the semiconductor memory device 100 , according to one embodiment of the present disclosure, an operation of setting a bit line voltage to program a page included in a selected subblock and a string precharge operation on unselected subblocks may be performed in a precharge phase included in each cycle.

[0103] During the programming phase, the threshold voltages of the memory cells included in the selected page can be selectively shifted by applying a programming pulse to the selected word line and a program pass voltage to the unselected word lines. In this case, the threshold voltages of the memory cells included in the selected page can be shifted or maintained based on the corresponding bit line voltages set during the precharge phase. That is, when a programming pulse is applied to the selected word line, the threshold voltages of the memory cells connected to the bit line designated to apply the program enable voltage during the precharge phase can be shifted. Furthermore, even if a programming pulse is applied to the selected word line, the threshold voltages of the memory cells connected to the bit line designated to apply the program inhibit voltage during the precharge phase may not be shifted.

[0104] In the verification phase, it is possible to check whether the memory cells included in the selected page have been programmed to the target programming state by verifying the voltage. When the threshold voltages of a predetermined proportion or more of the memory cells included in the selected page have reached the target level, the programming operation can be completed. In this case, subsequent loops may not be performed and the programming operation may be terminated. When the proportion of memory cells whose threshold voltages have reached the target level among the memory cells included in the selected page is less than a predetermined proportion, the programming operation may not be terminated and subsequent loops may be performed.

[0105] Figure 91 is a timing diagram showing in detail a programming operation of a semiconductor memory device according to one embodiment of the present disclosure. Figure 9 , the verification phase of the (N-1)th programming loop, and the precharge phase and programming phase of the Nth programming loop are shown. Figure 9 , shows a case where the first sub-block among the first sub-block and the second sub-block included in the memory block is selected as a programming target. Specifically, Figure 9 2 shows a case where a memory cell coupled to the i-th word line WLi among the memory cells included in the first sub-block is selected as a program target memory cell.

[0106] exist Figure 9 , the voltage applied to the selected i-th word line, the voltage applied to the (i-5)th word line WL(i-5) through the (i-1)th word line WL(i-1) arranged adjacent to the selected i-th word line WLi among the unselected word lines, and the voltage applied to the remaining unselected word lines (other word lines) are shown. Furthermore, the voltage applied to the first drain select line DSL1 coupled to the selected first sub-block SUB BLOCK 1 and the voltage applied to the unselected second drain select line DSL2 are shown. Furthermore, the voltage applied to the first source select line SSL1 coupled to the selected first sub-block SUB BLOCK 1 and the voltage applied to the unselected second source select line SSL2 are shown. Also shown are the voltage of the common source line CSL and the voltage of the page buffer sense signal PB_SENSE.

[0107] At time t1 of the verification phase, the verification voltage V VRF is applied to the selected word line WLi, and the verification pass voltage V VRPASS , applied to unselected word lines. Simultaneously, a turn-on voltage may be applied to drain select lines DSL1 and DSL2 and source select lines SSL1 and SSL2. At a subsequent time t2, a turn-off voltage may be applied to unselected drain select line DSL2 and unselected source select line SSL2. During at least a portion of the interval between time t2 and time t3, page buffer sense signal PB_SENSE may be enabled to a turn-on voltage, thereby enabling sensing of the threshold voltage of a selected memory cell. At a subsequent time t3, the verify operation may terminate. Consequently, a turn-off voltage may be applied to the word lines, drain select lines, and source select lines.

[0108] At time t4 of the precharge phase, the voltage of the common source line may be increased. At this time, the voltage applied to the common source line may be a voltage for precharging the strings included in the unselected sub-blocks. At subsequent time t5, a string precharge operation may be performed by increasing the voltage of the selected first source selection line SSL1 and the unselected second source selection line SSL2 to a voltage level Va. Figure 9 In the embodiment shown, not only the strings included in the unselected sub-blocks can be precharged, but also the strings included in the selected sub-blocks can be precharged. At time t5, a turn-on voltage can be applied to the selected word line WLi and its adjacent word lines WL(i-5) to WL(i-1), so that the string precharge operation can be performed smoothly. At subsequent time t6, a turn-off voltage can be applied to the selected word line WLi and its adjacent word lines WL(i-5) to WL(i-1).

[0109] Meanwhile, at time t5 of the precharge phase, the operation of setting the bit line voltage can be performed simultaneously with the string precharge operation. Therefore, as described above, the program enable voltage or the program inhibit voltage can be applied to the bit lines BL1 to BLm by increasing the page buffer sense signal PB_SENSE to the turn-on voltage.

[0110] At time t7, the string precharge operation and the bit line voltage setting operation may be terminated. Therefore, the voltage applied to the source selection line may be reduced to a cut-off voltage, and the voltage of the page buffer sense signal PB_SENSE may also be reduced to a cut-off voltage.

[0111] At time t8 of the programming phase, the voltage of the word line can be increased to the programming pass voltage V PGMPASS In addition, a voltage of the first drain select line DSL1 coupled to the first sub-block SUB BLOCK 1 as the selected sub-block may increase to a turn-on voltage, and a voltage of the second drain select line DSL2 coupled to the unselected second sub-block SUB BLOCK 2 may be maintained at a turn-off voltage.

[0112] At time t9, the voltage of the selected i-th word line WLi among the word lines may increase to the programming voltage V PGM The voltage of the remaining word lines (ie, unselected word lines) can be maintained at the programming pass voltage V PGMPASS The programming voltage V is applied to the selected i-th word line WLi. PGM This may be maintained until time t10. At time t10, the programming phase may terminate.

[0113] Reference Figure 9, a string precharge operation can be performed by increasing the voltage of the selected first source select line SSL1 and the unselected second source select line SSL2 to voltage level Va and applying the increased voltage at time t5, and a bit line voltage setting operation can be performed by increasing the page buffer sense signal PB_SENSE to a turn-on voltage. That is, at time t5, the string precharge operation and the bit line voltage setting operation can be performed simultaneously. Here, the current required for the string precharge operation and the current required for the bit line voltage setting operation may be consumed simultaneously. Therefore, problems may arise when the current consumed by the semiconductor memory device 100 increases sharply.

[0114] According to other embodiments of the present disclosure, the semiconductor memory device can be controlled so that the string precharge operation and the bit line voltage setting operation are started at different time points. In this case, the current consumed by the semiconductor memory device 100 can be dispersed over time, thereby solving the above-mentioned problem.

[0115] Figure 10 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure. Figure 10 Based on a method of operating a semiconductor memory device according to an embodiment of the present disclosure, in step S110, the voltage of a common source line connected to a memory block selected as a target of a programming operation may be increased, in step S130, the voltage of a source selection line connected to the memory block as a target of the programming operation may be increased to a first voltage level, and in step S150, the voltage of a bit line connected to the memory block as a target of the programming operation may be set while increasing the voltage of the source selection line from the first voltage level to the second voltage level. Figure 10 The method shown in Figure 8 and Figure 9 The precharge phase is performed as shown.

[0116] That is, in a state where the voltage of the common source line is increased in step S110, the voltage of the source selection line may be first increased to a first voltage level in step S130. In the subsequent step S150, a bit line voltage setting operation may be performed while the voltage of the source selection line is increased from the first voltage level to the second voltage level. Therefore, the current consumed by the string precharge operation in steps S130 and S150 may be dispersed. Figures 11 to 14 describe Figure 10 Detailed implementation of a method for operating a semiconductor memory device.

[0117] Figure 11 It shows Figure 10 A flowchart of one embodiment of a method of operating a semiconductor memory device in FIG. Figure 12 It is an explanation Figure 11 Hereinafter, reference will be made to Figure 11 and Figure 12 Provide a description.

[0118] Reference Figure 11 Based on the method for operating a semiconductor memory device according to one embodiment of the present disclosure, in step S110, the voltage of the common source line connected to the memory block selected as the target of the programming operation can be increased. Thereafter, in step S131, the voltage of the source select lines connected to the sub-block selected as the programming target and the unselected sub-blocks among the source select lines connected to the multiple sub-blocks included in the selected memory block can be increased to a first voltage level. That is, in step S131, the voltage of all the source select lines connected to the memory block can be increased to the first voltage level. Thereafter, in step S151, the voltage of the bit line connected to the selected memory block can be set while the voltage of the source select lines connected to the selected sub-block and the unselected sub-blocks is increased from the first voltage level to the second voltage level.

[0119] That is, while the voltage of the common source line is increased in step S110, the voltages of all source select lines connected to the memory block may be increased to a first voltage level in step S131. In subsequent step S151, a bit line voltage setting operation may be performed while the voltages of all source select lines are increased from the first voltage level to a second voltage level. Therefore, the current consumed by the string precharge operation in steps S131 and S151 may be dispersed.

[0120] Reference Figure 12 , shows the verification phase in the (N-1)th programming loop and the precharge phase and programming phase in the Nth programming loop. Figure 12 , shows a case where the first sub-block among the first sub-block and the second sub-block included in the memory block is selected as a programming target. Specifically, Figure 12 2 shows a case where a memory cell coupled to the i-th word line WLi among the memory cells included in the first sub-block is selected as a program target memory cell.

[0121] At time t11 of the verification phase, the verification voltage V VRF is applied to the selected word line WLi, and the verification pass voltage V VRPASS is applied to the unselected word lines. At the same time, a turn-on voltage may be applied to the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2. In one example, the turn-on voltage applied to the source select lines SSL1 and SSL2 may have a second voltage level V2. The second voltage level V2 may be substantially the same as Figure 9The voltage level Va shown is the same as that shown in FIG. At a subsequent time t12, a cutoff voltage may be applied to the unselected drain select line DSL2 and the unselected source select line SSL2. During at least a portion of the interval between time t12 and time t13, the page buffer sense signal PB_SENSE may be enabled to a turn-on voltage, and thus, the threshold voltage of the selected memory cell may be sensed. At a subsequent time t13, the verify operation may be terminated. Thus, a cutoff voltage may be applied to the word lines, drain select lines, and source select lines.

[0122] At time t14 of the precharge phase, the voltage of the common source line may be increased. This may correspond to Figure 10 and Figure 11 The voltage applied to the common source line may be a voltage for precharging the strings included in the unselected sub-blocks. At a subsequent time t15, the voltages of the selected first source selection line SSL1 and the unselected second source selection line SSL2 may be increased to a first voltage level V1. This may correspond to Figure 10 Step S130 or Figure 11 Here, the first voltage level V1 may be a voltage for slightly turning on the source selection transistor coupled to the common source line CSL.

[0123] At a subsequent time t16, the voltage of the selected first source selection line SSL1 and the unselected second source selection line SSL2 may be increased from the first voltage level V1 to the second voltage level V2. Simultaneously, at time t16, a turn-on voltage may be applied to the selected word line WLi and the adjacent word lines WL(i-5) to WL(i-1) so that the string precharge operation may be performed smoothly. At a subsequent time t17, a turn-off voltage may be applied to the selected word line WLi and the adjacent word lines WL(i-5) to WL(i-1). Figure 12 In the illustrated embodiment, the turn-on voltage is shown as being applied to the selected word line WLi and its adjacent word lines WL(i-5) to WL(i-1) at time t16 to allow the string precharge operation to proceed smoothly. However, according to one embodiment, the turn-on voltage may be applied to the word lines at time t15 when the voltage of the source select line is increased to the first voltage level.

[0124] Meanwhile, at time t16 of the precharge phase, a bit line voltage setting operation may be performed. Thus, as described above, a program enable voltage or a program inhibit voltage may be applied to the bit lines BL1 to BLm by increasing the page buffer sense signal PB_SENSE to a turn-on voltage.

[0125] At time t16, the operation of setting the bit line voltage by increasing the voltage of the selected first source selection line SSL1 and the unselected second source selection line SSL2 from the first voltage level V1 to the second voltage level V2 and by increasing the page buffer sense signal PB_SENSE to the turn-on voltage may correspond to Figure 10 Step S150 or Figure 11 Step S151.

[0126] At time t18, the string precharge operation and the bit line voltage setting operation may be terminated. Therefore, the voltage applied to the source selection line may be reduced to a cut-off voltage, and the voltage of the page buffer sense signal PB_SENSE may also be reduced to a cut-off voltage.

[0127] At time t19 of the programming phase, the voltage of the word line can be increased to the programming pass voltage V PGMPASS In addition, a voltage of the first drain select line DSL1 coupled to the first sub-block SUB BLOCK 1 as the selected sub-block may increase to a turn-on voltage, and a voltage of the second drain select line DSL2 coupled to the unselected second sub-block SUB BLOCK 2 may be maintained at a turn-off voltage.

[0128] At time t20, the voltage of the selected i-th word line WLi among the word lines may increase to the program voltage V PGM The voltage of the remaining word lines (ie, unselected word lines) can be maintained at the programming pass voltage V PGMPASS The programming voltage V is applied to the selected i-th word line WLi. PGM This may be maintained until time t21. At time t21, the programming phase may terminate.

[0129] according to Figure 11 and Figure 12 The illustrated embodiment can disperse the time during which current is consumed by increasing the voltage of the source select line through a two-step process during the string precharge operation. Therefore, the peak current used by the semiconductor memory device 100 can be reduced.

[0130] Figure 13 It shows Figure 10 A flowchart of one embodiment of a method of operating a semiconductor memory device in FIG. Figure 14 It is an explanation Figure 13 Hereinafter, reference will be made to Figure 13 and Figure 14 Provide a description.

[0131] Reference Figure 13, based on the method of operating a semiconductor memory device, according to one embodiment of the present disclosure, in step S110, the voltage of the common source line connected to the memory block selected as the target of the programming operation can be increased. Thereafter, in step S133, the voltage of the source selection line connected to the unselected sub-block (which is the sub-block not selected as the target of the programming operation (programming target)) among the source selection lines connected to the multiple sub-blocks included in the selected memory block can be increased to a first voltage level. That is, in step S133, the voltage of the source selection line connected to the unselected sub-block other than the target of the programming operation among all the source selection lines connected to the memory block can be increased to a first voltage level. Thereafter, in step S153, the voltage of the bit line connected to the selected memory block can be set while increasing the voltage of the source selection line connected to the unselected sub-block from the first voltage level to the second voltage level. Here, from Figure 13 Starting from the verification phase prior to the precharge phase performed in the steps shown in , the voltage applied to the source selection line coupled to the selected sub-block may be maintained at the second voltage level.

[0132] That is, while the voltage of the common source line is increased in step S110, the voltage of the source select lines connected to the unselected sub-blocks among the source select lines connected to the memory block can be first increased to a first voltage level in step S133. In the subsequent step S153, the bit line voltage setting operation can be performed while the voltage of the source select lines connected to the unselected sub-blocks is increased from the first voltage level to the second voltage level. Therefore, the current consumed by the string precharge operation in steps S133 and S153 can be dispersed.

[0133] Reference Figure 14 , shows the verification phase in the (N-1)th programming loop and the precharge phase and programming phase in the Nth programming loop. Figure 14 , shows a case where the first sub-block among the first sub-block and the second sub-block included in the memory block is selected as a programming target. Specifically, Figure 14 A case is shown in which a memory cell coupled to an i-th word line WLi among memory cells included in a first sub-block is selected as a program target memory cell.

[0134] At time t22 of the verification phase, the verification voltage V VRF is applied to the selected word line WLi, and the verification pass voltage V VRPASS is applied to the unselected word lines. At the same time, a turn-on voltage may be applied to the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2. In one example, the turn-on voltage applied to the source select lines SSL1 and SSL2 may have a second voltage level V2. The second voltage level V2 may be substantially the same as Figure 9The voltage level Va shown is the same. At a subsequent time t23, a cutoff voltage may be applied to the unselected drain select line DSL2 and the unselected source select line SSL2. During at least a portion of the interval between time t23 and time t24, the page buffer sense signal PB_SENSE may be enabled to a turn-on voltage, and thus, the threshold voltage of the selected memory cell may be sensed. At a subsequent time t24, the verification operation may be terminated. Therefore, a cutoff voltage may be applied to some word lines and drain select lines. Figure 14 In the illustrated embodiment, the voltage of the first source select line SSL1 coupled to the selected first sub-block SUB BLOCK 1 may be maintained at the second voltage level V2.

[0135] At time t25 of the precharge phase, the voltage of the common source line may be increased. This may correspond to Figure 10 and Figure 13 The voltage applied to the common source line may be a voltage for precharging the strings included in the unselected sub-blocks. In addition, at time t25, the voltage applied to the selected word line may be a voltage from the verification voltage V VRF Increase to the verification pass voltage V VRPASS . Verify by voltage V VRPASS May be a voltage for turning on a memory cell regardless of its threshold voltage.

[0136] At a subsequent time t26, the voltage of the unselected second source selection line SSL2 may be increased to the first voltage level V1. This may correspond to Figure 10 Step S130 or Figure 13 Here, the first voltage level V1 may be a voltage for slightly turning on the source selection transistor coupled to the common source line CSL. Meanwhile, at time t26, the voltage of the selected first source selection line SSL1 may maintain the second voltage level V2 from the previous verification stage.

[0137] At a subsequent time t27, the voltage of the unselected second source select line SSL2 may increase from the first voltage level V1 to the second voltage level V2. The voltage of the first source select line SSL1 may be maintained at the second voltage level V2.

[0138] Meanwhile, at time t27 of the precharge phase, a bit line voltage setting operation may be performed. Thus, as described above, a program enable voltage or a program inhibit voltage may be applied to the bit lines BL1 to BLm by increasing the page buffer sense signal PB_SENSE to a turn-on voltage.

[0139] At time t27, the operation of setting the bit line voltage by increasing the voltage of the unselected second source selection line SSL2 from the first voltage level V1 to the second voltage level V2 and by increasing the page buffer sense signal PB_SENSE to the turn-on voltage may correspond to Figure 10 Step S150 or Figure 13 Meanwhile, at time t28, a turn-off voltage may be applied to the selected word line WLi and the word lines WL(i-5) to WL(i-1) adjacent thereto.

[0140] At time t29, the string precharge operation and the bit line voltage setting operation may be terminated. Therefore, the voltage applied to the source selection line may be reduced to a cut-off voltage, and the voltage of the page buffer sense signal PB_SENSE may also be reduced to a cut-off voltage.

[0141] At time t30 of the programming phase, the voltage of the word line can be increased to the programming pass voltage V PGMPASS In addition, a voltage of the first drain select line DSL1 coupled to the first sub-block SUB BLOCK 1 as the selected sub-block may increase to a turn-on voltage, and a voltage of the second drain select line DSL2 coupled to the unselected second sub-block SUB BLOCK 2 may be maintained at a turn-off voltage.

[0142] At time t31, the voltage of the selected i-th word line WLi among the word lines may increase to the program voltage V PGM The voltage of the remaining word lines (ie, unselected word lines) can be maintained at the programming pass voltage V PGMPASS The programming voltage V is applied to the selected i-th word line WLi. PGM This may be maintained until time t32. At time t32, the programming phase may terminate.

[0143] according to Figure 13 and Figure 14 The illustrated embodiment can disperse the time during which current is consumed by increasing the voltage of the source select lines coupled to the unselected sub-blocks in a two-step process during the string precharge operation.

[0144] Figure 15 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure. Figure 15, based on the method of operating a semiconductor memory device, according to one embodiment of the present disclosure, in step S210, the voltage of a common source line connected to a memory block selected as a target of a programming operation may be increased, in step S230, the voltage of a source selection line connected to the memory block as a target of the programming operation may be increased to a first voltage level, in step S250, the voltage of a bit line connected to the memory block as a target of the programming operation is set, and in step S270, the voltage of the source selection line may be increased from the first voltage level to a second voltage level. Figure 15 The method shown in Figure 8 and Figure 9 The precharge phase is performed as shown.

[0145] That is, in a state where the voltage of the common source line is increased in step S210, the voltage of the source selection line may be first increased to a first voltage level in step S230. In a subsequent step S250, an operation of setting the bit line voltage may be performed, and in a subsequent step S270, the voltage of the source selection line may be increased from the first voltage level to a second voltage level. Therefore, the current consumed by the string precharge operation in steps S230 and S270 may be dispersed. In addition, the current consumed by the bit line voltage setting operation may also be separated from the current consumed by the above-mentioned string precharge operation. Figures 16 to 19 describe Figure 15 Detailed implementation of a method for operating a semiconductor memory device.

[0146] Figure 16 It shows Figure 15 A flowchart of one embodiment of a method of operating a semiconductor memory device in FIG. Figure 17 It is an explanation Figure 16 Hereinafter, reference will be made to Figure 16 and Figure 17 Provide a description.

[0147] Reference Figure 16Based on a method for operating a semiconductor memory device, according to one embodiment of the present disclosure, in step S210, the voltage of a common source line connected to a memory block selected as a target for a programming operation may be increased. Thereafter, in step S231, the voltage of a source select line connected to a sub-block selected as a programming target and unselected sub-blocks among the source select lines connected to a plurality of sub-blocks included in the selected memory block may be increased to a first voltage level. That is, in step S231, the voltage of all source select lines connected to the memory block may be increased to a first voltage level. Thereafter, in step S250, the voltage of a bit line connected to the selected memory block may be set. Thereafter, in step S271, the voltage of the source select line connected to the selected sub-block and the unselected sub-block may be increased from the first voltage level to a second voltage level.

[0148] That is, while the voltage of the common source line is increased in step S210, the voltages of all source select lines connected to the memory block can first be increased to a first voltage level in step S231. In a subsequent step S250, an operation of setting the bit line voltage can be performed, and in a subsequent step S271, the voltages of all source select lines can be increased from the first voltage level to a second voltage level. Therefore, in steps S231, S250, and S271, the current consumed by the string precharge operation and the bit line voltage setting operation can be dispersed.

[0149] Reference Figure 17 , showing the verification phase in the (N-1)th programming loop, the precharge phase in the Nth programming loop, and the programming phase in the Nth programming loop. Figure 17 , shows a case where the first sub-block among the first sub-block and the second sub-block included in the memory block is selected as a programming target. Specifically, Figure 17 A case is shown in which a memory cell coupled to an i-th word line WLi among memory cells included in a first sub-block is selected as a program target memory cell.

[0150] At time t33 of the verification phase, the verification voltage V VRF is applied to the selected word line WLi, and the verification pass voltage V VRPASS is applied to the unselected word lines. At the same time, a turn-on voltage may be applied to the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2. In one example, the turn-on voltage applied to the source select lines SSL1 and SSL2 may have a second voltage level V2. The second voltage level V2 may be substantially the same as Figure 9The voltage level Va shown is the same as that shown in FIG. At a subsequent time t34, a cutoff voltage may be applied to the unselected drain select line DSL2 and the unselected source select line SSL2. During at least a portion of the interval between time t34 and time t35, the page buffer sense signal PB_SENSE may be enabled to a turn-on voltage, and thus, the threshold voltage of the selected memory cell may be sensed. At a subsequent time t35, the verify operation may be terminated. Thus, a cutoff voltage may be applied to the word lines, drain select lines, and source select lines.

[0151] At time t36 of the precharge phase, the voltage of the common source line may be increased. This may correspond to Figure 15 and Figure 16 The voltage applied to the common source line may be a voltage for precharging the strings included in the unselected sub-blocks. At a subsequent time t37, the voltages of the selected first source selection line SSL1 and the unselected second source selection line SSL2 may be increased to a first voltage level V1. This may correspond to Figure 15 Step S230 or Figure 16 Here, the first voltage level V1 may be a voltage for slightly turning on the source selection transistor coupled to the common source line CSL.

[0152] Thereafter, at time t38 of the precharge phase, an operation of setting the bit line voltage may be performed. Thus, as described above, a program enable voltage or a program inhibit voltage may be applied to the bit lines BL1 to BLm by increasing the page buffer sense signal PB_SENSE to a turn-on voltage. This may correspond to Figure 15 and Figure 16 Step S250.

[0153] At a subsequent time t39, the voltages of the selected first source selection line SSL1 and the unselected second source selection line SSL2 may be increased from the first voltage level V1 to the second voltage level V2. This may correspond to Figure 15 Step S270 or Figure 16 Step S271.

[0154] At the same time, at time t39, a turn-on voltage may be applied to the selected word line WLi and the adjacent word lines WL(i-5) to WL(i-1) so that the string precharge operation can be smoothly performed. At a subsequent time t40, a turn-off voltage may be applied to the selected word line WLi and the adjacent word lines WL(i-5) to WL(i-1). Figure 17In the illustrated embodiment, the turn-on voltage is shown as being applied to the selected word line WLi and its adjacent word lines WL(i-5) to WL(i-1) at time t39 to allow the string precharge operation to proceed smoothly. However, according to one embodiment, the turn-on voltage may be applied to the word lines at time t37 when the voltage of the source select line is increased to the first voltage level.

[0155] At time t41, the string precharge operation and the bit line voltage setting operation may be terminated. Therefore, the voltage applied to the source selection line may be reduced to a cut-off voltage, and the voltage of the page buffer sense signal PB_SENSE may also be reduced to a cut-off voltage.

[0156] At time t42 of the programming phase, the voltage of the word line may be increased to the programming pass voltage V PGMPASS Furthermore, a voltage of the first drain select line DSL1 coupled to the first sub-block SUB BLOCK 1 as the selected sub-block may be increased to a turn-on voltage, and a voltage of the second drain select line DSL2 coupled to the unselected second sub-block SUB BLOCK 2 may be maintained at a turn-off voltage.

[0157] At time t43, the voltage of the selected i-th word line WLi among the word lines may be increased to a program voltage V PGM The voltage of the remaining word lines (ie, unselected word lines) can be maintained at the programming pass voltage V PGMPASS The programming voltage V is applied to the selected i-th word line WLi. PGM This can be maintained until time t44. At time t44, the programming phase ends.

[0158] according to Figure 16 and Figure 17 The illustrated embodiment can disperse the time during which current is consumed by increasing the voltage of the source select line during a string precharge operation in a two-step process. In this case, after increasing the voltage of the source select line to a first voltage level V1, a bit line voltage setting operation can be initiated, after which the voltage of the source select line can be increased to a second voltage level V2. Therefore, the peak current consumed by the semiconductor memory device 100 can be reduced during the string precharge operation and the bit line voltage setting operation.

[0159] Figure 18 It shows Figure 15 A flowchart of one embodiment of a method of operating a semiconductor memory device in FIG. Figure 19 It is an explanation Figure 18 Hereinafter, reference will be made to Figure 18 and Figure 19 Provide a description.

[0160] Reference Figure 18, based on the method of operating a semiconductor memory device, according to one embodiment of the present disclosure, in step S210, the voltage of the common source line connected to the memory block selected as the target of the programming operation can be increased. Thereafter, in step S233, the voltage of the source selection line connected to the unselected sub-block (which is the sub-block not selected as the target of the programming operation (programming target)) among the source selection lines connected to the multiple sub-blocks included in the selected memory block can be increased to a first voltage level. That is, in step S233, the voltage of the source selection line connected to the unselected sub-block other than the target of the programming operation among all the source selection lines connected to the memory block can be increased to a first voltage level. Thereafter, in step S250, the voltage of the bit line connected to the selected memory block is set. Thereafter, in step S273, the voltage of the source selection line connected to the unselected sub-block can be increased from the first voltage level to the second voltage level. Here, from Figure 18 Starting from the verification phase preceding the precharge phase performed in the steps shown, the voltage applied to the source selection line coupled to the selected sub-block may be maintained at the second voltage level.

[0161] That is, while the voltage of the common source line is increasing in step S210, the voltage of the source select lines connected to the unselected sub-blocks among the source select lines connected to the memory block can first be increased to a first voltage level in step S233. In a subsequent step S250, an operation of setting the bit line voltage can be performed, and in a subsequent step S273, the voltage of the source select lines connected to the unselected sub-blocks can be increased from the first voltage level to a second voltage level. Therefore, the current consumed by the string precharge operation and the bit line voltage setting operation is dispersed in steps S233, S250, and S273.

[0162] Reference Figure 19 , shows the verification phase in the (N-1)th programming loop and the precharge phase and programming phase in the Nth programming loop. Figure 19 , shows a case where the first sub-block among the first sub-block and the second sub-block included in the memory block is selected as a programming target. Specifically, Figure 19 2 shows a case where a memory cell coupled to the i-th word line WLi among the memory cells included in the first sub-block is selected as a program target memory cell.

[0163] At time t45 of the verification phase, the verification voltage V VRF is applied to the selected word line WLi, and the verification pass voltage V VRPASSis applied to the unselected word lines. At the same time, a turn-on voltage may be applied to the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2. In one example, the turn-on voltage applied to the source select lines SSL1 and SSL2 may have a second voltage level V2. The second voltage level V2 may be substantially the same as Figure 9 The voltage level Va shown is the same. At a subsequent time t46, a cutoff voltage may be applied to the unselected drain select line DSL2 and the unselected source select line SSL2. During at least a portion of the interval between time t46 and time t47, the page buffer sense signal PB_SENSE may be enabled to a turn-on voltage, and thus, the threshold voltage of the selected memory cell may be sensed. At a subsequent time t47, the verification operation may be terminated. Therefore, a cutoff voltage may be applied to some word lines and drain select lines. Figure 19 In the illustrated embodiment, the voltage of the first source select line SSL1 coupled to the selected first sub-block SUB BLOCK 1 may be maintained at the second voltage level V2.

[0164] At time t48 of the precharge phase, the voltage of the common source line may be increased. This may correspond to Figure 15 and Figure 18 The voltage applied to the common source line may be a voltage for precharging the strings included in the unselected sub-blocks. In addition, at time t48, the voltage applied to the selected word line may be increased from the verification voltage V VRF Increase to the verification pass voltage V VRPASS . Verify by voltage V VRPASS May be a voltage for turning on a memory cell regardless of its threshold voltage.

[0165] At a subsequent time t49, the voltage of the unselected second source selection line SSL2 may be increased to the first voltage level V1. This may correspond to Figure 15 Step S230 or Figure 18 Here, the first voltage level V1 may be a voltage for slightly turning on the source selection transistor coupled to the common source line CSL. Meanwhile, at time t49, the voltage of the selected first source selection line SSL1 may be maintained at the second voltage level V2 from the previous verification stage.

[0166] Thereafter, at time t50 of the precharge phase, an operation of setting the bit line voltage may be performed. Thus, as described above, a program enable voltage or a program inhibit voltage may be applied to the bit lines BL1 to BLm by increasing the page buffer sense signal PB_SENSE to a turn-on voltage. This may correspond to Figure 15 and Figure 18 Step S250.

[0167] Thereafter, at time t51 of the precharge phase, the voltage of the unselected second source selection line SSL2 may be increased from the first voltage level V1 to the second voltage level V2. This may correspond to Figure 15 Step S270 or Figure 18 At this time, the voltage of the first source selection line SSL1 may be maintained at the second voltage level V2. Meanwhile, at time t52, a cutoff voltage may be applied to the selected word line WLi and the adjacent word lines WL(i-5) to WL(i-1).

[0168] At time t53, the string precharge operation and the bit line voltage setting operation may be terminated. Therefore, the voltage applied to the source selection line may be reduced to a cut-off voltage, and the voltage of the page buffer sense signal PB_SENSE may also be reduced to a cut-off voltage.

[0169] At time t54 of the programming phase, the voltage of the word line may be increased to the programming pass voltage V PGMPASS Furthermore, a voltage of the first drain select line DSL1 coupled to the first sub-block SUB BLOCK 1 as the selected sub-block may be increased to a turn-on voltage, and a voltage of the second drain select line DSL2 coupled to the unselected second sub-block SUB BLOCK 2 may be maintained at a turn-off voltage.

[0170] At time t55, the voltage of the selected i-th word line WLi among the word lines may be increased to the programming voltage V PGM The voltage of the remaining word lines (ie, unselected word lines) can be maintained at the programming pass voltage V PGMPASS The programming voltage V is applied to the selected i-th word line WLi. PGM This may be maintained until time t56. At time t56, the programming phase may terminate.

[0171] according to Figure 18 and Figure 19 The illustrated embodiment can disperse the time during which current is consumed by increasing the voltage of the source select lines connected to unselected sub-blocks during a string precharge operation in a two-step process. In this case, after increasing the voltage of the unselected source select lines to a first voltage level V1, a bitline voltage setting operation can be initiated, after which the voltage of the unselected source select lines can be increased to a second voltage level V2. Therefore, the peak current consumed by semiconductor memory device 100 can be reduced during the string precharge operation and the bitline voltage setting operation.

[0172] Figure 20 is a diagram showing an example of sub-blocks forming a memory block. Figure 21 is a circuit diagram showing some cell strings included in the first to fourth sub-blocks.

[0173] Reference Figure 20 , the memory block may include four sub-blocks SUB BLOCK 1 to SUB BLOCK 4. Figure 4 As described above, the sub-blocks included in the memory block can be defined as cell strings that share a drain selection line or a source selection line. Figure 5 The memory block includes two sub-blocks, but the memory block can also be configured to include four sub-blocks, such as Figure 20 shown.

[0174] Reference Figure 21 , showing a cell string CS11 included in the first sub-block SUB BLOCK 1 , a cell string CS21 included in the second sub-block SUBBLOCK 2 , a cell string CS31 included in the third sub-block SUB BLOCK 3 , and a cell string CS41 included in the fourth sub-block SUBBLOCK 4 . Figure 21 Can be shown in the +X direction Figure 20 Circuit diagram of the memory block.

[0175] The cell string CS11 in the first sub-block SUB BLOCK 1 may include memory cells MC11 to MC1n coupled between a first drain select transistor DST1 and a first source select transistor SST1. The cell string CS21 in the second sub-block SUB BLOCK 2 may include memory cells MC21 to MC2n coupled between a second drain select transistor DST2 and a second source select transistor SST2. The cell string CS31 in the third sub-block SUB BLOCK 3 may include memory cells MC31 to MC3n coupled between a third drain select transistor DST3 and a third source select transistor SST3. The cell string CS41 in the fourth sub-block SUBBLOCK 4 may include memory cells MC41 to MC4n coupled between a fourth drain select transistor DST4 and a fourth source select transistor SST4.

[0176] Reference Figures 9 to 19 , the operation method according to the present disclosure has been described as being performed on a memory block having two sub-blocks. However, the operation method according to the present disclosure can also be applied to a memory block having four sub-blocks, such as Figure 20 and Figure 21 In this case, when one sub-block (e.g., the first sub-block) is selected as a programming target, the source selection line (e.g., SSL1) connected to the corresponding sub-block may be the selected source selection line. Meanwhile, the source selection lines (e.g., SSL2 to SSL4) respectively connected to the remaining three sub-blocks (e.g., the second to fourth sub-blocks) may be the unselected source selection lines.

[0177] Figure 22 It shows that Figure 1 1 is a block diagram of an embodiment of a memory system 1000 of a semiconductor memory device 100.

[0178] Reference Figure 22 , the memory system 1000 may include a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference Figure 1 A semiconductor memory device is described.

[0179] The memory controller 1100 may be coupled to the host Host and the semiconductor memory device 100. The memory controller 1100 may access the semiconductor memory device 100 based on a request from the host Host. For example, the memory controller 1100 may control read operations, write operations, erase operations, and background operations of the semiconductor memory device 100. The memory controller 1100 may provide an interface between the semiconductor memory device 100 and the host Host. The memory controller 1100 may execute firmware for controlling the semiconductor memory device 100.

[0180] The memory controller 1100 may include a random access memory (RAM) 1110, a processor 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 may be used as at least one of a working memory for the processor 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processor 1120 may control the overall operation of the memory controller 1100. In addition, the memory controller 1100 may temporarily store programming data provided from the host Host during a write operation.

[0181] The host interface 1130 may include a protocol for performing data exchange between the host Host and the memory controller 1100. In one embodiment, the memory controller 1100 may communicate with the host Host through at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

[0182] The memory interface 1140 may interface with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0183] The error correction block 1150 may use an error correction code (ECC) to detect and correct errors in data received from the semiconductor memory device 100. The processor 1120 may adjust a read voltage based on a result of error detection by the error correction block 1150 and may control the semiconductor memory device 100 to perform a reread. In one example embodiment, the error correction block may be provided as an element of the memory controller 1100.

[0184] The memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device. In one embodiment, the memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), or a Universal Flash Storage (UFS).

[0185] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). The SSD may include a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of a host connected to the memory system 1000 can be significantly improved.

[0186] In one embodiment, the memory system 1000 may be configured as one of various components of an electronic device, such as a computer, an ultra-portable PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various electronic devices forming a home network, one of various electronic devices forming a computer network, one of various electronic devices forming a telematics network, a radio frequency identification (RFID) device, or one of various components forming a computing system.

[0187] In one exemplary embodiment, the semiconductor memory device 100 or the memory system 1000 may be mounted in various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 may be packaged and mounted in the following types: package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP), or wafer-level processing stacked package (WSP).

[0188] Figure 23 It shows Figure 22 A block diagram of an application example of a memory system.

[0189] Reference Figure 23 , the memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include a plurality of semiconductor memory chips. The semiconductor memory chips are divided into a plurality of groups.

[0190] exist Figure 23 , it is shown that a plurality of groups communicate with the memory controller 2200 through the first channel CH1 to the kth channel CHk. Each semiconductor memory chip can communicate with the reference Figure 1 The described semiconductor memory device 100 is configured and operates in the same manner.

[0191] Each group can communicate with the memory controller 2200 through a common channel. The memory controller 2200 can communicate with the reference Figure 22 The described memory controller 1100 has the same configuration and may control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

[0192] Figure 24 is shown with reference Figure 23 A block diagram of a computing system depicting a memory system.

[0193] The computing system 3000 may include a central processing unit (CPU) 3100 , a RAM 3200 , a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system 2000 .

[0194] The memory system 2000 may be electrically coupled to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 may be stored in the memory system 2000.

[0195] exist Figure 24 , the semiconductor memory device 2100 is shown as being coupled to the system bus 3500 through the memory controller 2200. However, the semiconductor memory device 2100 may be directly coupled to the system bus 3500. Here, the function of the memory controller 2200 may be performed by the CPU 3100 and the RAM 3200.

[0196] exist Figure 24 In the figure, reference is shown Figure 23 However, the memory system 2000 may be configured by referring to Figure 22 In one exemplary embodiment, the computing system 3000 may include a memory system 1000 described in the embodiment of the present invention. Figure 22 The memory system 1000 described and referenced Figure 23 Both memory systems 2000 are described.

[0197] In addition, the embodiments disclosed in this specification and the accompanying drawings are intended to help those skilled in the art to more clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. Therefore, those skilled in the art will be able to easily understand that various modifications can be made based on the technical scope of the present disclosure.

[0198] The present disclosure may provide a semiconductor memory device capable of reducing a peak current and a method of operating the semiconductor memory device.

[0199] CROSS-REFERENCE TO RELATED APPLICATIONS

[0200] This application claims the benefit of Korean Patent Application No. 10-2020-0101439 filed on August 12, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a memory block having a plurality of sub-blocks respectively coupled to a plurality of source selection lines; a peripheral circuit configured to perform a data programming operation on the memory block; as well as control logic configured to control the peripheral circuit to: increasing a voltage of a common source line coupled to the memory block, increasing a voltage of at least one source selection line among the plurality of source selection lines to a first voltage level, and A voltage of a bit line coupled to the memory block is set, and a voltage of the at least one source select line is increased from the first voltage level to a second voltage level.

2. The semiconductor memory device according to claim 1, wherein The control logic is configured to control the peripheral circuit to increase the voltage of a first source selection line among the multiple source selection lines connected to a sub-block selected as a programming target and the voltage of a second source selection line among the multiple source selection lines connected to at least one sub-block other than the programming target to the first voltage level.

3. The semiconductor memory device according to claim 2, wherein: The control logic is configured to control the peripheral circuit to increase a voltage of the first source select line and a voltage of the second source select line from the first voltage level to the second voltage level.

4. The semiconductor memory device according to claim 1, wherein: The second voltage level is a voltage that enables a transistor coupled to the at least one source select line to be turned on.

5. The semiconductor memory device according to claim 1, wherein: The control logic is configured to control the peripheral circuit to increase the voltage of a second source selection line connected to at least one sub-block not selected as the programming target among the multiple source selection lines to the first voltage level while the voltage of the first source selection line connected to the sub-block selected as the programming target is maintained at the second voltage level.

6. The semiconductor memory device according to claim 5, wherein: The control logic is configured to control the peripheral circuit to increase the voltage of the second source select line from the first voltage level to the second voltage level in a state in which the voltage of the first source select line is maintained at the second voltage level.

7. The semiconductor memory device according to claim 1, wherein: The control logic is configured to control the peripheral circuit to: After increasing the voltage of the at least one source selection line to the first voltage level, setting the voltage of the bit line, and After the voltage of the bit line has started to be set, the voltage of the at least one source select line is increased from the first voltage level to the second voltage level.

8. A method of operating a semiconductor memory device, the method for programming a memory block having a plurality of sub-blocks respectively connected to a plurality of source selection lines, the method comprising the steps of: increasing a voltage of a common source line coupled to the memory block; increasing a voltage of at least one source select line among the plurality of source select lines to a first voltage level; as well as A voltage of a bit line coupled to the memory block is set while the voltage of the at least one source select line is increased from the first voltage level to a second voltage level.

9. The method according to claim 8, wherein: The step of increasing the voltage of the at least one source selection line among the plurality of source selection lines to the first voltage level comprises the following steps: A voltage of a first source selection line coupled to a sub-block selected as a program target among the plurality of sub-blocks and a voltage of a second source selection line coupled to at least one sub-block other than the program target are increased to the first voltage level.

10. The method according to claim 9, wherein: The step of setting the voltage of the bit line coupled to the memory block while increasing the voltage of the at least one source selection line from the first voltage level to the second voltage level comprises the following steps: The voltage of the first source select line and the second source select line is increased from the first voltage level to the second voltage level.

11. The method according to claim 8, wherein: The step of setting the voltage of the bit line coupled to the memory block while increasing the voltage of the at least one source selection line from the first voltage level to the second voltage level comprises the following steps: A voltage to be applied to each of a plurality of bit lines coupled to the memory block is set to one of a program enable voltage and a program inhibit voltage to program memory cells included in a page of one of the plurality of sub-blocks.

12. The method according to claim 8, wherein: The step of increasing the voltage of the at least one source selection line among the plurality of source selection lines to the first voltage level comprises the following steps: maintaining a voltage of a first source selection line coupled to a sub-block selected as a programming target among the plurality of source selection lines at the second voltage level; and A voltage of a second source selection line coupled to at least one sub-block not selected as a program target is increased to the first voltage level.

13. The method according to claim 12, wherein: The step of setting the voltage of the bit line coupled to the memory block while increasing the voltage of the at least one source selection line from the first voltage level to the second voltage level comprises the following steps: maintaining the voltage of the first source select line at the second voltage level; and The voltage of the second source select line is increased from the first voltage level to the second voltage level.

14. A method of operating a semiconductor memory device, the method for programming a memory block having a plurality of sub-blocks respectively connected to a plurality of source selection lines, the method comprising the steps of: increasing a voltage of a common source line coupled to the memory block; increasing a voltage of at least one source select line among the plurality of source select lines to a first voltage level; setting a voltage of a bit line coupled to the memory block; as well as The voltage of the at least one source select line is increased from the first voltage level to a second voltage level.

15. The method according to claim 14, wherein: The step of increasing the voltage of the at least one source selection line among the plurality of source selection lines to the first voltage level comprises the following steps: A voltage of a first source selection line coupled to a sub-block selected as a program target among the plurality of sub-blocks and a voltage of a second source selection line coupled to at least one sub-block other than the program target are increased to the first voltage level.

16. The method according to claim 15, wherein: The step of increasing the voltage of the at least one source select line from the first voltage level to the second voltage level comprises the following steps: A voltage of the first source select line and a voltage of the second source select line are increased from the first voltage level to the second voltage level.

17. The method according to claim 14, wherein: The step of setting the voltage of the bit line coupled to the memory block comprises the following steps: A voltage to be applied to each of a plurality of bit lines coupled to the memory block is set to one of a program enable voltage and a program inhibit voltage to program memory cells included in a page included in one of the plurality of sub-blocks.

18. The method according to claim 14, wherein: The step of increasing the voltage of the at least one source selection line among the plurality of source selection lines to the first voltage level comprises the following steps: maintaining a voltage of a first source selection line coupled to a sub-block selected as a programming target among the plurality of source selection lines at the second voltage level; and A voltage of a second source selection line coupled to at least one sub-block not selected as a program target is increased to the first voltage level.

19. The method according to claim 18, wherein: The step of increasing the voltage of the at least one source select line from the first voltage level to the second voltage level comprises the following steps: maintaining the voltage of the first source select line at the second voltage level; and The voltage of the second source select line is increased from the first voltage level to the second voltage level.

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