Encoding of microelectronic device test data and related methods, apparatuses, and systems

Abstract

Encoding test data for microelectronic devices and related methods, apparatuses, and systems are disclosed. A memory device can include a plurality of column planes and at least one circuit. The at least one circuit can be configured to receive test result data for a column address of each column plane of the plurality of column planes of the memory device. The at least one circuit can also be configured to convert the test result data to a first result in response to only one bit of a plurality of bits of the plurality of column planes failing a test for the column address. Further, the at least one circuit can be configured to convert the test result data to a second result in response to only one column plane failing the test for the column address and more than one bit of the one column plane being defective.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application Serial No. 16 / 996,120, entitled “Encoding test data of microelectronic devices, and related methods, apparatus, and systems,” filed on August 18, 2020. Technical Field

[0003] The embodiments of this disclosure generally relate to microelectronic devices. More specifically, the embodiments relate to encoding test data for microelectronic devices, and to related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically housed in computers or other electronic systems as internal semiconductor integrated circuits. There are many different types of memory, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), dual data rate memory (DDR), low power dual data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Memory devices typically contain a number of memory cells capable of holding charges representing data bits. These memory cells are usually arranged in a memory array. Data can be written to or retrieved from memory cells by selectively activating the memory cells via associated word line drivers. Summary of the Invention

[0006] Various embodiments of this disclosure may include an apparatus. The apparatus may include: a memory array comprising a plurality of column planes; and at least one circuit coupled to the memory array. The at least one circuit may be configured to receive test result data for a column address of each of the plurality of column planes of the memory array. The at least one circuit may also be configured to convert the test result data into a first result in response to only one bit of a plurality of bits of the plurality of column planes failing the test for the column address, wherein the first result identifies the one bit and the column plane containing the one bit. Furthermore, the at least one circuit may be configured to convert the test result data into a second result in response to only one column plane failing the test for the column address and more than one bit of the one column plane being defective, wherein the second result identifies the one column plane.

[0007] According to another embodiment of this disclosure, a method for testing a memory device may include testing column addresses of a plurality of column planes of a memory array. The method may further include testing column addresses of a plurality of column planes of the memory array. The method may further include generating a first signal in response to only one bit of the plurality of column planes failing the test for the column address, wherein the first signal identifies the one bit and the column plane containing the one bit among the plurality of column planes. Furthermore, the method may include generating a second signal in response to only one column plane of the plurality of column planes failing the test for the column address and more than one bit of the one column plane failing the test for the column address, wherein the second signal identifies the one column plane.

[0008] According to another embodiment of this disclosure, the apparatus may include a memory array comprising a plurality of column planes. The apparatus may also include at least one circuit coupled to the memory array. The at least one circuit may be configured to test column addresses of the plurality of column planes of the memory array, wherein the plurality of column planes comprises a first set of column planes and a second set of column planes, and the first set of column planes and the second set of column planes together comprise a plurality of bits. The at least one circuit may also be configured to generate a first signal in response to each of the plurality of bits having a non-defective state for the column address. Further, the at least one circuit may be configured to generate a second signal in response to only one of the plurality of bits having a defective state for the column address, wherein the second signal identifies the address of the one bit. Additionally, the at least one circuit may be configured to generate a third signal in response to two or more of the plurality of bits having a defective state for the column address.

[0009] Further embodiments of this disclosure include a system. The system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The system may also include at least one memory device operatively coupled to the at least one processor device and include a circuit system. The circuit system may be configured to write data to each of N column planes of the at least one memory device and to read data from each of the N column planes. The circuit system may also be configured to compare the written data with the read data to generate N-bit test data. The circuit system may be configured to convert the N-bit test data into a first M-bit result in response to a defective single bit among a plurality of bits in the N column planes, wherein the first M-bit result identifies the single bit and the column plane among the N column planes containing the single bit. Furthermore, the circuit system can be configured to convert the N-bit test data into different second M-bit results in response to only one of the N column planes being defective and two or more bits of the one column plane being defective, wherein the different second M-bit results identify the one column plane. Attached Figure Description

[0010] Figure 1 This is a block diagram of an example memory device according to at least one embodiment of the present disclosure.

[0011] Figure 2 An example memory device comprising a portion of a memory array is depicted.

[0012] Figure 3 Several elements of the example memory array are depicted.

[0013] Figure 4A An example memory device comprising multiple elements coupled to a bus is depicted according to various embodiments of the present disclosure.

[0014] Figure 4B An example memory device comprising a plurality of elements coupled to an encoder is depicted according to various embodiments of the present disclosure.

[0015] Figure 5 This is another illustration of multiple elements of an example memory array according to various embodiments of the present disclosure.

[0016] Figure 6 This is a flowchart of an example method for testing a memory device according to various embodiments of the present disclosure.

[0017] Figure 7This is a flowchart of another example method for testing a memory device according to various embodiments of the present disclosure.

[0018] Figure 8 This is a simplified block diagram of a memory system according to various embodiments of the present disclosure.

[0019] Figure 9 This is a simplified block diagram of an electronic system according to various embodiments of the present disclosure. Detailed Implementation

[0020] Semiconductor memory devices typically comprise an array of memory cells. Memory cells in the array are selected for reading and writing by means of row and column address signals input to the memory device. The row and column address signals are processed by an address decoding circuitry system to select the row and column lines in the array to access one or more desired memory cells.

[0021] When manufacturing semiconductor devices, defective memory cells may appear in memory arrays or subarrays. Despite the presence of these defective memory cells, redundancy is typically implemented to remedy the semiconductor memory device and thus improve the overall yield of the manufacturing process. Redundant memory cells are located in the memory array, and the memory array may be associated with multiple redundant memory cells. When a defective memory cell is detected in the array, a redundant decoding circuitry system associated with the redundant memory cell can be programmed (e.g., via fuses, antifuse, or other programming techniques) in response to the address of the defective memory cell. When the address of the defective memory cell is selected for access, the redundant memory cell can be accessed (e.g., read from or written to the redundant memory cell), instead of accessing the defective memory cell.

[0022] As disclosed in U.S. Patent Application No. 16 / 782,949, filed February 5, 2020, entitled "Microelectronic Device Testing, and Associated Methods, Apparatus, and Systems," and U.S. Patent Application No. 16 / 685,186, filed November 15, 2019, entitled "Apparatus and Methods to Encode Column Plane Compression Data," an encoded column plane compression system is configured to encode column plane information during read bursts and output encoded data. Furthermore, it should be understood that some semiconductor memory devices may include error detection and / or error correction codes (ECC) to correct errors (e.g., single bit errors). If ECC (i.e., correcting single bits) is used, full visibility (i.e., 1X visibility) may be required to identify which specific bits have failed. As will be understood, if a single bit fails on an ECC word (i.e., no other failures occur on the same word throughout the entire test process), and the single bit can be identified, then that single bit can be tolerated. In other words, it may not be necessary to repair the single bit, but rather it can be corrected via ECC. However, as will be understood, processing fully visible data (including transferring fully visible data from the memory device to the test device) requires significant resources and time.

[0023] As described more fully below, the various embodiments disclosed herein relate to microelectronic device testing, including encoding test data at the microelectronic device. According to the various embodiments, encoded full visibility data (i.e., encoded 1X data) can be generated, which allows a tester to record individual bits (e.g., for single-bit tolerance). More specifically, the various embodiments relate to testing memory devices, identifying defective column planes and / or bits of the memory device (if any), encoding test data, and potentially identifying memory device failures (e.g., if more than one column plane fails for a specific column plane address). Further, in the various embodiments, encoded full visibility data (e.g., 1X visibility for tracking collision bits) can be provided to determine which specific bit failed, enabling the use of error ECC (i.e., tolerating a single bit). Compared to conventional devices, systems, and methods, the various embodiments can reduce test time and the amount of data transferred to test circuitry (e.g., within or outside the memory device). Further, the various embodiments can improve memory device yield and quality by utilizing ECC correction capabilities.

[0024] Although various embodiments have been described herein with reference to memory devices, this disclosure is not limited thereto, and the embodiments can be generally applied to microelectronic devices that may or may not include semiconductor devices and / or memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0025] Figure 1 A block diagram including example memory device 100 according to various embodiments of the present disclosure. Memory device 100, referred to herein or which may be referred to herein as a memory device, may include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), DDR SDRAM (Double Data Rate DRAM, such as DDR4 SDRAM, etc.), or SGRAM (Synchronous Graphics Random Access Memory). Memory device 100, which may be integrated on a semiconductor chip, may include memory cell array 102.

[0026] exist Figure 1 In this embodiment, the memory cell array 102 is shown as comprising eight memory banks BANK0-7. In other embodiments, the memory cell array 102 may contain more or fewer banks. Each memory bank comprises multiple access lines (word lines WL), multiple data lines (bit lines BL) and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL can be performed by the row decoder 104, and the selection of bit lines BL and / BL can be performed by the column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory bank BANK0-7, and column decoder 106 may include a corresponding column decoder for each memory bank BANK0-7.

[0027] Bit lines BL and / BL are coupled to the corresponding sense amplifiers SAMP. Read data from bit lines BL or / BL can be amplified by the sense amplifiers SAMP and transmitted to the read / write amplifier 108 via complementary local data lines (LIOT / B), transmission gates (TG), and complementary main data lines (MIOT / B). Conversely, write data output from the read / write amplifier 108 can be transmitted to the sense amplifiers SAMP via complementary main data lines MIOT / B, transmission gates TG, and complementary local data lines LIOT / B, and written to the memory cell MC coupled to bit lines BL or / BL.

[0028] The memory device 100 can typically be configured to receive various inputs via various terminals such as address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118 (e.g., from an external controller). The memory device 100 may include additional terminals such as power terminals 120 and 122.

[0029] During the considered operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include the valid command ACT and the read / write signal R / W.

[0030] Furthermore, one or more address signals ADD received via address terminal 110 can be transmitted to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to supply row address XADD to row decoder 104 and column address YADD to column decoder 106. Although command input circuit 152 and address input circuit 132 are shown as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0031] The valid command ACT can include a pulse signal activated in response to the command signal COM indicating row access (e.g., a valid command). In response to the valid signal ACT, the row decoder 104 at the specified library address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0032] The read / write signal R / W may include a pulse signal activated in response to a command signal COM indicating column access (e.g., a read command or a write command). In response to the read / write signal R / W, the column decoder 106 may be activated, and the bit line BL specified by the column address YADD may be selected.

[0033] In response to the valid command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output through the sense amplifier SAMP, the transmission gate TG, the read / write amplifier 108, the input / output circuit 162, and the data terminal 116. Further, in response to the valid command ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory cell array 102 through the data terminal 116, the input / output circuit 162, the read / write amplifier 108, the transmission gate TG, and the sense amplifier SAMP. Write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0034] Clock signals CK and / or CK can be received via clock terminal 114. Clock input circuit 170 can generate an internal clock signal ICLK based on clock signals CK and / or CK. The internal clock signal ICLK can be transmitted to various components of memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK that can be transmitted to input / output circuit 162 (e.g., for controlling the operating timing of input / output circuit 162). Further, data mask terminal 118 can receive one or more data mask signals DM. When a data mask signal DM is activated, rewriting the corresponding data can be disabled.

[0035] According to various embodiments, the input / output circuit 162 may include or be coupled to one or more encoders, as described more fully below. The one or more encoders may be configured to receive test data from the memory cell array 102 and, in response thereto, generate one or more signals (e.g., encoded signals) indicating whether one or more column planes are defective, the address of the defective column plane, and / or which bit of the column plane is defective (e.g., if only one column plane is defective and only one bit of the defective column plane is defective).

[0036] As will be understood by those skilled in the art, a “memory mat” generally refers to a sub-cell of a memory bank having multiple memory cells. Each memory mat is defined as the extent of the word line (WL) and bit line (BL) extensions. A memory mat may contain two or more sub-mats. Sub-mats may also be referred to herein as “column planes”.

[0037] Figure 2An example device comprising a portion of a memory array 200 is depicted. The memory array 200 comprises groups (e.g., also referred to herein as “rows”) 202 of memory cells, wherein each group 202 comprises a plurality of memory pads 204. As will be understood, each memory pad 204 may comprise a plurality of (e.g., two) column planes. In other words, each memory pad 204 may comprise a plurality of (e.g., two) sub-pads. Further, each column plane comprises a plurality of column select (CS) lines 206 for accessing memory cells located at column addresses within each column plane. By way of example only, each column plane may comprise 64 CS lines. For example, one or more sense amplifiers ( Figure 2 (Not depicted in the text) can be located between adjacent memory pads in row 202. Further, for example, one or more sub-word line drivers ( Figure 2 (Not depicted in the text) can be positioned between adjacent memory pads in different rows 202.

[0038] Furthermore, each row 202 contains multiple redundant memory cells accessible via redundant column select (RCS) lines. For example, if one or more memory cells accessible via column select line X of the column plane of row 202 fail, those memory cells accessible via column select line X can be replaced with one or more memory cells accessible via column select address X of redundant column plane 208. Similarly, if one or more memory cells accessible via column select line Y of the column plane of row 202 fail, those memory cells accessible via column select line Y can be replaced with one or more memory cells accessible via column select address Y of redundant column plane 208.

[0039] As will be understood, in a conventional apparatus, if a memory cell accessible via a different CS row of a single column plane of row 202 fails, the different CS row of the single column plane can be replaced by the associated column select line of redundant column plane 208. Furthermore, if a memory cell accessible via a first column select line (e.g., CS line A) of the column plane fails, and a memory cell accessible via a second (i.e., a different) column select line (e.g., CS line B) of a second (i.e., different) column plane fails, the first column select line (e.g., CS line A) of the redundant column plane 208 can be replaced by the associated column select line (e.g., CS line A), and the second column select line (e.g., CS line B) of the second column plane can be replaced by the associated column select line (e.g., CS line B) of the redundant column plane 208. More specifically, if one or more memory cells accessible via column select line 61 (CS61) of column plane 220A fail, and one or more memory cells accessible via column select line 50 (CS50) of a second (i.e., different) column plane 220B fail, then column select line 61 (CS61) of redundant column plane 208 can replace column select line 61 (CS61) of column plane 220A, and column select line 50 (CS50) of redundant column plane 208 can replace column select line 50 (CS50) of column plane 220B.

[0040] However, in conventional devices, it may not be possible to replace more than one column select line corresponding to the same column address (i.e., in different memory column planes). For example, if two columns corresponding to the same column address fail, it may not be possible to replace both columns. More specifically, if one or more memory cells accessible via a first column select line (e.g., CS line A) in a first column plane fail, and one or more memory cells accessible via the same column select line (e.g., CS line A) in a second (i.e., different) column plane fail, only one column select line can be replaced. In other words, if one or more memory cells accessible via CS61 in column plane 220A fail, and a memory cell accessible via CS61 in column plane 220B fails, it may not be possible to replace both column select lines (i.e., CS61 in column plane 220A and CS61 in column plane 220B).

[0041] Figure 3Multiple elements of an example memory array 300 are shown. More specifically, the memory array 300 includes groups of elements 304 (e.g., "rows") 302. In some embodiments, each element 304 may include a column plane. In other embodiments, each element 304 may include a memory pad having two (2) column planes (i.e., two sub-pads). In conventional systems and / or devices, each column plane in row 302 is tested sequentially (i.e., one after another) to detect faulty column planes (if any). More specifically, during testing, for each column address, a bit is generated (e.g., sequentially) for each column plane, and based on the generated bit (e.g., output from the column plane), it can be determined whether the column plane is defective for a specific column address (i.e., whether the column plane contains one or more defective memory cells). As will be understood, in at least some instances, N bits of data (e.g., 17*8 bits for 17 column planes or 35*8 bits for 35 column planes) are read from the row to test each column plane in the row for a specific column address (e.g., but not limited to, 17 column planes, 35 column planes). Therefore, it should be understood that conventional systems and methods for detecting defective column planes are time-consuming and resource-intensive.

[0042] As disclosed in U.S. Patent Application Nos. 16 / 782,949 and 16 / 685,186, the column plane code (i.e., generated by coded column plane compression) can include multiple coded bits for multiple column planes (e.g., 5 coded bits for 17 column planes or 6 coded bits for 35 column planes). As will be disclosed more fully below, according to various embodiments, the coded data can include additional bits (e.g., 4 bits) in the read burst to indicate which specific bit in the column plane is invalid (e.g., if only the column plane is invalid and only one bit in the column plane is invalid). As will be understood, the additional bits can allow sufficient visibility for global column compression and ECC collision visibility. More specifically, for example, the additional bits can include four additional bits for coded 1X data, or the additional bits can include three additional bits for XORed 2X data (e.g., by blind comparison). While additional bits may increase test time and / or test data volume (i.e., compared to coded column plane compression), the various embodiments can reduce test time and test data volume compared to conventional 1X testing. For example, instead of a read burst containing 136 bits for 17 column planes (i.e., 1X visibility), according to the various embodiments, the read burst may contain 9 bits for 17 column planes. As another example, instead of a read burst containing 280 bits for 35 column planes (i.e., 1X visibility), according to the various embodiments, the read burst may contain 10 bits for 35 column planes.

[0043] Figure 4A A device 400A is shown that includes a group of elements 404 (e.g., "rows") 402 according to various embodiments of the present disclosure. The device 400A may include a memory device (e.g.,... Figure 1 The memory device 100) and / or may be part of a memory device. For example, line 402 may be a memory bank (e.g., Figure 1 This is part of one of the eight memory banks BANK0-7 shown. In some embodiments, each element 404 may include a column plane. In other embodiments, each element 404 may include a memory pad having two column planes (i.e., two sub-pads).

[0044] During the test operation, for a specific column address, multiple bits (e.g., 8 bits) can be written to each column plane of row 402 via bus 403. Therefore, in an example containing 35 column planes, 280 bits (i.e., 35 * 8) can be written to row 402. Furthermore, multiple bits (e.g., 8 bits) can be read from each column plane of row 402. Therefore, in this example, 280 bits (i.e., 35 * 8) can be read from row 402. Furthermore, the bits written to each column plane of row 402 can be compared with the bits read from each column plane to detect defective column planes (if any) for a specific column address.

[0045] Figure 4B A device 400B comprising an element 404 coupled to an encoder 406 is depicted according to various embodiments of the present disclosure. In some embodiments, the element 404 may be part of a memory array 401, said part being a memory bank (e.g., Figure 1 As a non-limiting example, encoder 406 may be located within a memory device (e.g., BANK0-7). Figure 1 The memory device 100) is located within the outer peripheral circuit region. Furthermore, in some instances, numerous data amplifiers ( Figure 4B (Not shown) can be located between the memory array (e.g., containing row 402) and the encoder 406. For example, the encoder 406 can be an input / output circuit (such as... Figure 1 A portion of the input / output circuitry 162 of the memory device 100 may be coupled to the input / output circuitry.

[0046] Encoder 406 is coupled to and configured to receive data from each element 404 of row 402. More specifically, encoder 406, which may include one or more circuits, is configured to receive (e.g., substantially simultaneously) a first plurality of bits (e.g., N bits) from row 402, encode the first plurality of bits (e.g., substantially simultaneously), and output (e.g., substantially simultaneously) a second plurality of bits (e.g., M bits), wherein the second plurality of bits is less than the first plurality of bits (e.g., M bits). <N)。

[0047] As described above, during the test operation under consideration, for a specific column address, multiple bits (e.g., 8 bits) can be written to each column plane in row 402. More specifically, in one instance, 8 bits, each having a high state (e.g., 1), can be written to the specific column address for each column plane in row 402. Subsequently, 8 bits can be read from the specific column address for each column plane in row 402, and the read bits can be compared with the written bits (i.e., detecting the defective column plane and generating an M-bit result).

[0048] As a more specific example, encoder 406 is configured to receive 8 bits (e.g., 280 bits (i.e., 35 column planes * 8 bits) or 136 bits (i.e., 17 column planes * 8 bits)) from each column plane in row 402 and output M bits (e.g., M bits of encoded data). For example, if row 402 contains 17 column planes, M might be equal to 9. As another example, if row 402 contains 35 column planes, M might be equal to 10.

[0049] More specifically, during the test operation considered in row 402, for each column address, each column plane in row 402 can generate 8 bits, and thus in an instance containing 35 column planes (i.e., 17.5 memory pads), 280 (i.e., 35*8) bits are generated and received (e.g., simultaneously received) at encoder 406. As a non-limiting example, if each bit generated by the column plane has a first state (e.g., "0"), the column plane "passes" the test (i.e., the column plane does not contain any defective memory cells), and if the column plane generates one or more bits with a second state (e.g., "1"), the column plane "fails" the test (i.e., the column plane contains one or more defective memory cells).

[0050] Continuing with the test operation under consideration, if for a specific column address, more than one column plane generates bits with a second state (i.e., more than one column plane fails the test), then encoder 406 generates an M-bit output indicating that more than one column plane has failed. More specifically, for example, if for a specific column address, more than one column plane generates bits with a second state (i.e., more than one column plane fails the test), encoder 406 may generate an M-bit output (also referred to herein as a "result" or "signal") indicating that more than one column plane has failed the test, such as "110XXXXXXX".

[0051] Furthermore, if each bit generated by each column plane has a first state (i.e., each column plane passes the test), the encoder 406 generates an M-bit output indicating that each column plane has passed the test. More specifically, for example, if each bit generated by each column plane of row 402 has a first state (i.e., each column plane passes the test), the encoder 406 can generate an M-bit output indicating that no column plane has failed the test, such as "111XXXXXX".

[0052] Furthermore, if more than one bit fails (i.e., a multi-bit failure), the failed bits may not be tolerated, and a separate code can be generated to indicate a multi-bit failure. More specifically, if for a specific column address, only one column plane fails the test and more than one bit of the column plane has a second state (i.e., two or more bits of a column plane are defective), then encoder 406 generates an M-bit output indicating: 1) which specific column plane failed the test; and 2) a multi-bit failure. More specifically, if only one column plane fails the test and more than one bit of the column plane fails the test, encoder 406 can generate an M-bit value, where some bits of the M-bit value identify the failed column plane, and at least one other bit indicates a multi-bit failure.

[0053] As a more specific example, if column plane 0 (e.g., the first column plane in row 402) is the only column plane in row 402 used to generate bits with the second state (i.e., "1"), and more than one bit in column plane 0 has the second state, then encoder 406 generates "0000001XXX" (i.e., 000000 is the binary value used to identify the "0" in column plane 0, and the third bit (i.e., "1") indicates a multiple bit failure). As another example, if column plane 9 (e.g., the tenth column plane in row 402) is the only column plane in row 402 used to generate bits with the second state (i.e., "1"), and more than one bit in column plane 9 has the second state, then encoder 406 generates "0010011XXX" (i.e., 001001 is the binary value used to identify the "9" in column plane 9, and the third bit (i.e., "1") indicates a multiple bit failure). As yet another example, if column plane 33 (e.g., the 34th column plane in row 402) is the only column plane in row 402 used to generate bits with a second state (i.e., "1"), and more than one bit of column plane 33 has a second state, then encoder 406 generates "1000011XXX" (i.e., 100001 is the binary value of "33" used to identify column plane 33, and the third bit (i.e., "1") indicates that multiple bits are faulty). Further, in this example, the M-bit value (e.g., between "0000001XXX" and "1000101XXX") (i.e., which identifies which column plane failed the test) and the specific column address can be used in the repair process (e.g., to repair the column selection line in the faulty column plane).

[0054] Furthermore, according to some embodiments, if only a single bit out of multiple bits in multiple column planes fails the test (e.g., only a single bit in row 402 fails the test), the M-bit value can indicate which specific bit failed. More specifically, if for a specific column address, only one column plane fails the test, and only one bit in the column plane is defective, the encoder 406 generates an M-bit output indicating which specific column plane failed the test and which specific bit in that column plane failed the test. More specifically, if a column plane fails the test and only one bit in the column plane is defective, the encoder 406 can generate an M-bit value, where some bits of the M-bit value identify the defective column plane, and some bits of the M-bit value identify which bit in the column plane is defective.

[0055] In a more specific instance containing 35 column planes, six bits of the M-bit value (e.g., between "000000" and "100010" (i.e., between 0 and 34)) can indicate which column plane (e.g., the address of the column plane) failed the test. In another instance containing 17 column planes, five bits of the M-bit value (e.g., between "000000" and "10000" (i.e., between 0 and 16)) can indicate which column plane (e.g., the address of the column plane) failed the test. Furthermore, in either instance, several additional bits of the M-bit value (e.g., four bits) can indicate which bit of the column plane failed.

[0056] For example, if column plane 0 (e.g., the first column plane in row 402) is the only column plane in row 402 used to generate the bit with the second state (i.e., "1"), and bit 7 is a bit that is invalid in column plane 0, then encoder 406 can generate "0000000111" (i.e., 000000 is the binary value for the "0" used to identify column plane 0, and 0111 is the binary value for the "7" used to identify bit 7). As another example, if column plane 9 (e.g., the tenth column plane in row 402) is the only column plane in row 402 used to generate the bit with the second state (i.e., "1"), and bit 6 is a bit that is invalid in column plane 9, then encoder 406 can generate "0010010110" (i.e., 001001 is the binary value for the "9" used to identify column plane 9, and 0110 is the binary value for the "6" used to identify bit 6). As yet another example, if column plane 33 (e.g., the 34th column plane in row 402) is the only column plane in row 402 used to generate a bit with a second state (i.e., "1"), and bit 1 is a failed bit of column plane 33, then encoder 406 can generate "1000010001" (i.e., 100001 is the binary value of "33" used to identify column plane 33, and 0001 is the binary value of "1" used to identify bit 1). Further, in this example, the M-bit value (i.e., identifying which column plane failed the test and which bit failed the test) and the specific column address can be used for error tolerance (e.g., via ECC) and / or repair processes (e.g., for repairing column select lines in the failed column plane).

[0057] Figure 5 This is another illustration of a memory array 500 comprising groups 504 (e.g., "rows") 502 of elements 504 according to various embodiments of the present disclosure. For example, Figure 4A or Figure 4BRow 402 may contain row 502. In this example, each element 504 contains multiple column planes 505 (e.g., one or two of them). Further, row 502 contains error correction code (ECC) units 506 and redundancy units 508. Each column plane 505, each ECC unit 506, and each redundancy unit 508 is configured to output multiple bits (e.g., K bits (e.g., 8 bits)). As will be understood, ECC unit 506 can be used to correct errors associated with the row, and redundancy unit 508 can contain redundant memory cells. As a more specific example, ECC unit 506 can be used to tolerate faulty bits in the row (e.g., if only one bit is faulty).

[0058] For example, each column plane 505 in row 502 can be coupled to an input / output (I / O) circuit system (e.g., Figure 1 The I / O circuitry 162 includes input / output (DQ) pads (also referred to herein as “data pads”). Therefore, in some instances, each column plane 505 in row 502 can be configured to read or write 2*K bits (e.g., 2*8 bits) for a single column operation.

[0059] Figure 6 This is a flowchart of an example method 600 for testing a memory device according to various embodiments of the present disclosure. Method 600 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 600 can be performed by, for example... Figure 1 Memory device 100 Figure 4A Device 400A, Figure 4B Device 400B Figure 5 Memory array 500, Figure 8 Memory system 800 and / or Figure 9 The electronic system 900 and other devices or systems or another device or system perform this function. Although shown as discrete blocks, the individual blocks can be divided into other blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0060] Method 600 may begin at block 602, where column addresses of a plurality of column planes of the memory device can be tested, and method 600 may proceed to block 604. For example, for the first column address of the plurality of column addresses, it can be (e.g., by...) Figure 4A The bus 403) is written to the plurality of column planes. Further, data can be read from the plurality of column planes, and can be (e.g., via...) Figure 4B The encoder 406 compares the written data with the read data to determine the state (e.g., defective or non-defective) of each of the plurality of column planes and / or each bit of the plurality of column planes.

[0061] At block 604, a first signal can be generated in response to only one bit of the plurality of column planes failing the test for the column address, and method 600 can proceed to block 606. The first signal can identify the bit and the column plane containing the bit among the plurality of column planes. For example, if the unique bit is determined to be defective (e.g., based on the test performed at block 602), the device (e.g., Figure 4B The encoder 406 can generate an M-bit signal of a column plane that identifies the defect and contains the defect bit. More specifically, for example, if column plane 25 is the only column plane with a defective state, and the fifth bit of column plane 25 is the only bit that failed the test, the device can generate "0110010101", where 011011 is the binary value of "25" and 0101 is the binary value of "5".

[0062] At block 606, a second signal can be generated in response to only one of the plurality of column planes failing the test for the column address and more than one bit of that column plane being defective, wherein the second signal identifies the column plane. For example, if only one column plane is determined to be defective, but more than one bit of that column plane is defective (e.g., based on the test performed at block 602), then the device (e.g., Figure 4B The encoder 406 can generate an M-bit signal identifying a column plane as defective or having multiple bit failures. More specifically, for example, if column plane 25 is the only column plane with a defective state and more than one bit of column plane 25 fails the test, the device can generate "0110011XXX", where 011011 is the binary value of "25" and the third bit "1" indicates multiple bit failures.

[0063] Modifications, additions, or omissions may be made to method 600 without departing from the scope of this disclosure. For example, the operations of method 600 may be performed in a different order. For example, the action at block 606 may occur before the action at block 604. Furthermore, the operations and actions outlined are provided by way of example only, and some of the operations and actions may be optional, combined into fewer operations and actions, or extended into other operations and actions without departing from the essence of the disclosed embodiments. For example, a method may include one or more actions in which test data for each of the plurality of column planes, including a bit (e.g., indicating a defective or non-defective state), may be generated. Further, for example, a method may include one or more actions in which a third signal may be generated in response to each of the plurality of column planes having a non-defective state for a column address. Additionally, for example, a method may include one or more actions in which a fourth signal may be generated in response to two or more of the plurality of column planes having a defective state for a column address. As another example, a method may include one or more actions in which a first signal, a second signal, a third signal, and / or a fourth signal may be transmitted to a test / repair circuitry system (e.g., on or outside the memory device). Further, for example, a method may include one or more actions in which a defective bit can be tolerated via the memory device's ECC. Additionally, for example, a method may include one or more actions in which one or more column select lines of a column plane may be replaced by redundant column lines of a redundant column plane of the memory device.

[0064] As will be understood, some memory devices may not be configured to perform coded column-plane compression. In these cases, to provide, for example, full visibility of 17 column planes, 8 bits are needed to identify which one or more bits out of 136 bits (i.e., 17 * 8 = 136) are invalid. In these typical instances, two sets of column planes can be read in a read burst, and therefore in this example, the read burst for a single read is 16 bits (2 * 8).

[0065] According to some embodiments of this disclosure, more than one set (“set”) of column planes can be tested together (e.g., substantially simultaneously). More specifically, for example, 34 column planes (e.g., two sets of 17 column planes) can be tested together (e.g., even without coded column plane compression) to provide coded 1X data visibility (e.g., tolerance for individual bits).

[0066] Table 1 below shows example bit values ​​for example scenarios using two sets of column planes (i.e., two sets of 17 column planes). As shown in Table 1, 9 bits can be used to identify a "no failure" scenario and a single bit failure (i.e., from bit 0 to bit 271). According to various embodiments, a single bit failure can be tolerated by ECC. Further, continuing to refer to Table 1, 9 bits can be used to identify multiple bit failures in the first set of column planes (i.e., "110000001") and multiple bit failures in the first set of column planes (i.e., "110000010"). In addition, 9 bits can be used to identify multiple bit failures in both sets of column planes (i.e., "110000011"). As will be understood, in embodiments where more than one set of column planes is tested together, instead of 136 bits to achieve full visibility of 17 column planes, only 9 bits are needed.

[0067] invalid address 8th position 7th 6th position Position 5 4th position Position 3 Position 2 Bit 1 Bit 0 No failure 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 … … … … … … … … … … 270 1 0 0 0 0 1 1 1 1 271 1 0 0 0 1 0 0 0 0 Multiple failures - Group 17 column planes 1 1 0 0 0 0 0 0 1 Multiple failures - Group 2, 17 column planes 1 1 0 0 0 0 0 1 0 Multiple failures - two sets of column planes 1 1 0 0 0 0 0 1 1

[0068] Table 1

[0069] For example, refer to again Figure 4A and 4B The encoder 406 can receive multiple bits from multiple sets of column planes (e.g., two of them). More specifically, as a non-limiting example, the encoder 406 can receive multiple bits from a first set of 17 column planes and a second set of 17 column planes. Further, in response to each of the multiple bits passing the test (i.e., each bit having a non-defective state), the encoder 406 can output a signal containing multiple bits indicating that each bit passed (e.g., 000000000; see Table 1). Further, in response to only one of the multiple bits failing (i.e., having a defective state), the encoder 406 can output a signal containing multiple bits (e.g., 100001111; see address 270 in Table 1) indicating the bit address (also referred to herein as "address") of the failed bit. Furthermore, in response to more than one of the plurality of bits failing (i.e., having a defective state), encoder 406 may output a signal containing (e.g., in the first set of column planes and / or the second set of column planes) a plurality of bits indicating multiple bit failures (e.g., 110000001, 110000010 or 110000011; see Table 1 for example).

[0070] Figure 7 This is a flowchart of an example method 700 for testing a memory device according to various embodiments of the present disclosure. Method 700 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 700 can be performed by, for example... Figure 1 Memory device 100 Figure 4A Device 400A, Figure 4B Device 400B Figure 5 Memory array 500, Figure 8Memory system 800 and / or Figure 9 The electronic system 900 and other devices or systems or another device or system perform this function. Although shown as discrete blocks, the individual blocks can be divided into other blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0071] Method 700 may begin at block 702, where column addresses of multiple column planes of the memory array can be tested, and method 700 may proceed to block 704. For example, for the first column address of the multiple column addresses, it can be (e.g., by...) Figure 4A The bus 403) is written to the plurality of column planes. Further, data can be read from the plurality of column planes, and can be (e.g., via...) Figure 4B The encoder 406 compares the written data with the read data to determine the state (e.g., defective or non-defective) of each column plane in the column plane.

[0072] At block 704, a first signal may be generated in response to each bit of the plurality of bits in the plurality of column planes having a non-defective state for the column address, and method 700 may proceed to block 706. For example, a first signal (e.g., 000000000; see Table 1 for example) may be generated in response to each bit in a first set of column planes (e.g., a first set of 17 column planes) and a second set of column planes (e.g., a second set of 17 column planes) having a non-defective state.

[0073] At block 706, a second signal may be generated in response to only one of the plurality of bits having a defective state for the column address, and method 700 may proceed to block 708. For example, a second signal (e.g., 000000010; see Table 1 for example) may be generated in response to only one of the plurality of bits in a first set of column planes (e.g., a first set of 17 column planes) and a second set of column planes (e.g., a second set of 17 column planes) having a defective state.

[0074] At block 708, a third signal may be generated in response to two or more of the plurality of bits having a defective state for the column address. For example, a third signal (e.g., 110000001, 110000010, or 110000011; see Table 1 for example) may be generated in response to two or more of the plurality of bits having a defective state for the first set of column planes (e.g., the first set of 17 column planes) and the second set of column planes (e.g., the second set of 17 column planes).

[0075] Modifications, additions, or omissions may be made to method 700 without departing from the scope of this disclosure. For example, the operations of method 700 may be performed in a different order. Furthermore, the operations and actions outlined are provided as examples only, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into other operations and actions without departing from the essence of the disclosed embodiments.

[0076] If you understand, please use the above reference. Figure 4A , 4B In one or more embodiments disclosed in 5 and / or 6, the burst length may be reduced from, for example, 136 bits to 9 bits (or from 280 bits to 10 bits). Further, using the above references... Figure 4A , 4B In one or more embodiments disclosed in 5 and / or 7, the burst length can be reduced from, for example, from 272 bits to 9 bits. Therefore, encoded 1X data (e.g., for ECC collision bit visibility and single-bit tolerance) can be generated in a shorter test time than the test time required to generate real 1X data.

[0077] A memory system is also disclosed. According to various embodiments, the memory system may include memory devices (e.g., Figure 1 The memory device 100 includes one or more memory cell arrays. Figure 8 This is a simplified block diagram of a memory system 800 implemented according to one or more embodiments described herein. The memory system 800, which may include, for example, semiconductor devices, includes a memory array 802 and a circuit system 804, which may include, by way of example only, an encoder (e.g., Figure 4B The encoder 406, as described herein. The memory array 802, which may contain multiple memory libraries, may contain multiple memory cells. The circuitry 804 may be operatively coupled to the memory array 802 and may be configured to perform one or more embodiments disclosed herein. The memory system 800 may also include a controller coupled to the memory array 802 and / or the circuitry 804. Figure 8 (Not shown in the image).

[0078] An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device comprising a plurality of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0079] Figure 9This is a simplified block diagram of an electronic system 900 implemented according to one or more embodiments described herein. The electronic system 900 includes at least one input device 902, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 900 further includes at least one output device 904, such as a monitor, touchscreen, or speaker. The input device 902 and the output device 904 are not necessarily separable from each other. The electronic system 900 further includes a storage device 906. The input device 902, output device 904, and storage device 906 may be coupled to a processor 908. The electronic system 900 further includes a memory device 910 coupled to the processor 908. The memory device 910 may include… Figure 8 The memory system 800. The electronic system 900 may include, for example, computing, processing, industrial or consumer products. The electronic system 900 may include, for example, but not limited to, personal computers or computer hardware components, servers or other networking hardware components, database engines, intrusion prevention systems, handheld devices, tablet computers, electronic notebooks, cameras, telephones, music players, wireless devices, displays, chipsets, games, vehicles or other known systems.

[0080] Various embodiments of this disclosure may include an apparatus. The apparatus may include: a memory array comprising a plurality of column planes; and at least one circuit coupled to the memory array. The at least one circuit may be configured to receive test result data for a column address of each of the plurality of column planes of the memory array. The at least one circuit may also be configured to convert the test result data into a first result in response to only one bit of a plurality of bits of the plurality of column planes failing the test for the column address, wherein the first result identifies the one bit and the column plane containing the one bit. Furthermore, the at least one circuit may be configured to convert the test result data into a second result in response to only one column plane failing the test for the column address and more than one bit of the one column plane being defective, wherein the second result identifies the one column plane.

[0081] According to another embodiment of this disclosure, a method for testing a memory device may include testing column addresses of a plurality of column planes of a memory array. The method may further include testing column addresses of a plurality of column planes of the memory array. The method may further include generating a first signal in response to only one bit of the plurality of column planes failing the test for the column address, wherein the first signal identifies the one bit and the column plane containing the one bit among the plurality of column planes. Furthermore, the method may include generating a second signal in response to only one column plane of the plurality of column planes failing the test for the column address and more than one bit of the one column plane failing the test for the column address, wherein the second signal identifies the one column plane.

[0082] According to another embodiment of this disclosure, the apparatus may include a memory array comprising a plurality of column planes. The apparatus may also include at least one circuit coupled to the memory array. The at least one circuit may be configured to test column addresses of the plurality of column planes of the memory array, wherein the plurality of column planes comprises a first set of column planes and a second set of column planes, and the first set of column planes and the second set of column planes together comprise a plurality of bits. The at least one circuit may also be configured to generate a first signal in response to each of the plurality of bits having a non-defective state for the column address. Further, the at least one circuit may be configured to generate a second signal in response to only one of the plurality of bits having a defective state for the column address, wherein the second signal identifies the address of the one bit. Additionally, the at least one circuit may be configured to generate a third signal in response to two or more of the plurality of bits having a defective state for the column address.

[0083] Further embodiments of this disclosure include a system. The system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The system may also include at least one memory device operatively coupled to the at least one processor device and include a circuit system. The circuit system may be configured to write data to each of N column planes of the at least one memory device and to read data from each of the N column planes. The circuit system may also be configured to compare the written data with the read data to generate N-bit test data. The circuit system may be configured to convert the N-bit test data into a first M-bit result in response to a defective single bit among a plurality of bits in the N column planes, wherein the first M-bit result identifies the single bit and the column plane among the N column planes containing the single bit. Furthermore, the circuit system can be configured to convert the N-bit test data into different second M-bit results in response to only one of the N column planes being defective and two or more bits of the one column plane being defective, wherein the different second M-bit results identify the one column plane.

[0084] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some figures in the drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0085] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0086] As used herein, unless otherwise stated, the term “semiconductor” should be interpreted broadly to include microelectronic devices and MEMS devices (e.g., magnetic storage, optical devices, etc.) that may or may not employ semiconductor functionality to operate.

[0087] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0088] Furthermore, if the intent is a specific number of introduced claim statements, then such intent will be explicitly stated in the claims, and if no such statements are present, such intent will not be presented. For example, to aid understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introductory claim statement to an embodiment containing only one such statement, even when the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0089] Furthermore, even when a specific number of introduced claim statements are explicitly stated, it should be understood that such statements should be interpreted as meaning at least the number stated (e.g., stating "two statements" without other modifiers means at least two statements or two or more statements). Moreover, where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0090] Furthermore, any separating words or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to account for the possibility of including one, any, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0091] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily imply a specific order or quantity of elements. Generally, the terms "first," "second," and "third" are used to distinguish different elements as general identifiers. Unless otherwise stated, these terms should not be construed as implying a specific order. Similarly, unless otherwise stated, these terms should not be construed as implying a specific number of elements.

[0092] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, in addition to those shown and described herein, various modifications to this disclosure (such as alternative useful combinations of the described elements) will become apparent to those skilled in the art based on the description. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device comprising: A memory array comprising multiple column planes; as well as At least one circuit, coupled to the memory array and configured to: Receive test result data for the column address of each of the plurality of column planes of the memory array; In response to only one bit among the multiple column planes failing the test for the column address, the test result data is converted into a first result, the first result comprising a first number of bits and a second number of bits, the first number of bits identifying the single bit, and the second number of bits identifying the column plane containing the single bit; and In response to only one column plane failing the test for the column address and more than one bit of the column plane being defective, the test result data is converted into a second result, the second result comprising a third number of bits and a fourth number of bits, the third number of bits identifying the column plane and the fourth number of bits identifying the more than one bit.

2. The memory device of claim 1, wherein the at least one circuit is further configured to convert the test result data into a third result in response to two or more of the plurality of column planes failing the test for the column address.

3. The memory device of claim 2, wherein the at least one circuit is further configured to convert the test result data into a fourth result in response to any of the plurality of column planes failing the test for the column address.

4. The memory device of claim 1, wherein the at least one circuit is further configured to convert the test result data into a third result in response to two or more column planes of the plurality of column planes failing the test for the column address or no column plane of the plurality of column planes failing the test for the column address.

5. The memory device of claim 1, wherein the test result data comprises 280 bits, and each of the first result and the second result comprises 10 bits.

6. The memory device of claim 1, wherein the test result data comprises 136 bits, and each of the first result and the second result comprises 9 bits.

7. The memory device of claim 1, wherein the first number of bits comprises four bits identifying the one bit and the second number of bits comprises five or six bits identifying the column plane containing the one bit.

8. A method for encoding test data, comprising: Test the column addresses of multiple column planes of the memory array; A first signal is generated in response to only one bit of the plurality of column planes failing the test for the column address. The first signal comprises a first number of bits and a second number of bits, the first number of bits identifying the single bit and the second number of bits identifying the column plane containing the single bit. A second signal is generated in response to only one of the plurality of column planes failing the test for the column address and more than one bit of the column plane failing the test. The second signal comprises a third number of bits and a fourth number of bits, the third number of bits identifying the column plane and the fourth number of bits identifying the more than one bit.

9. The method of claim 8, further comprising generating a third signal in response to the test performed on the column address for each of the plurality of column planes.

10. The method of claim 9, further comprising generating a fourth signal in response to two or more of the plurality of column planes failing the test for the column address.

11. The method of claim 8, further comprising generating N bits in response to the test, wherein generating the first signal comprises encoding the N bits into M bits, wherein M... <N。 12. The method of claim 11, wherein encoding N bits into M bits includes encoding 136 bits into 9 bits or encoding 280 bits into 10 bits.

13. The method of claim 8, further comprising tolerating the bit by means of an error correction code (ECC) in response to the first signal.

14. The method of claim 8, further comprising replacing one column plane with a redundant column plane in response to the second signal.

15. A memory device comprising: A memory array comprising multiple column planes; as well as At least one circuit, coupled to the memory array and configured to: The column addresses of the plurality of column planes of the memory array are tested. The plurality of column planes include a first group of column planes and a second group of column planes, and the first group of column planes and the second group of column planes together contain a plurality of bits. A first signal is generated in response to each of the plurality of bits having a non-defective state for the column address; A second signal is generated in response to only one of the plurality of bits having a defective state for the column address, the second signal identifying the address of the one bit; and A third signal is generated in response to two or more of the plurality of bits having a defective state for the column address.

16. The memory device of claim 15, wherein the at least one circuit is configured to generate the third signal in response to one of the following: Two or more bits in the first set of column planes have a defective state; Two or more positions in the second set of column planes have defective states; and Two or more bits in each of the first and second column planes are in a defective state.

17. The memory device of claim 15, wherein each of the first set of column planes and the second set of column planes comprises 17 column planes, and each of the first signal, the second signal and the third signal comprises 9 bits.

18. A system for encoding test data, comprising: At least one input device; At least one output device; At least one processor device, the at least one processor device being operatively coupled to the input device and the output device; as well as At least one memory device, operatively coupled to the at least one processor device, and comprising: The circuit system is configured to: Data is written to each of the N column planes of the at least one memory device; Read data from each of the N column planes; The written data is compared with the read data to generate N-bit test data; In response to a defective single bit among the multiple bits of the N column planes, the N-bit test data is converted into a first M-bit result. The first M-bit result comprises a first number of bits and a second number of bits, where the first number of bits identifies the single bit, and the second number of bits identifies the column plane among the N column planes containing the single bit. In response to a defect in only one of the N column planes and a defect in two or more bits of the one column plane, the N-bit test data is converted into a different second M-bit result, the different second M-bit result comprising a third number of bits and a fourth number of bits, the third number of bits identifying the one column plane and the fourth number of bits identifying the two or more bits.

19. The system of claim 18, wherein the circuitry is further configured to convert the N-bit test data into a third M-bit result in response to the absence of a defect in any of the N column planes, wherein the value of N is greater than the value of M.

20. The system of claim 19, wherein the circuitry is further configured to convert the N-bit test data into different fourth M-bit results in response to defects in two or more of the N column planes.

Images