Semiconductor device and method for manufacturing the same

Abstract

The invention discloses a semiconductor device and a method for preparing the same, the method for preparing the semiconductor device comprising: providing a semiconductor substrate, the semiconductor substrate being formed with a groove, a filling layer being formed in the groove, and a void gap being formed in the filling layer; removing part of the filling layer to expose the void gap; forming a plug, the plug blocking the void gap and extending into the void gap to at least a preset value; removing part of the filling layer, retaining at least a preset height of the plug until the filling layer has a preset thickness to form a contact hole. The preparation method according to the embodiment of the present invention can reduce the void gap, avoid the formation of a V-shaped interface, and improve the conductivity of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] The wire connection method between the transistor and the capacitor of the existing DRAM is a polysilicon-metal plug connection. When the process is miniaturized, its size is also miniaturized. The connection resistance and contact surface performance between polysilicon and metal are very important. As the process is miniaturized, the higher the depth-to-width ratio of the bit line trench is filled with polysilicon, the more likely it is that there will be voids in the polysilicon, which greatly increases the resistance of the wire. In order to eliminate the influence of the void gap, the deposition-etching-deposition method is usually used to solve the influence of the void gap. However, when etching the polysilicon layer, the void gap is etched open, and the etching solution and etching gas enter the void gap, so that the polysilicon layer located at the void gap is etched faster, forming a V-shaped interface on the surface of the filling layer. The V-shaped interface will form a large area of ​​natural silicon oxide surface, which greatly affects the conductivity of the semiconductor device. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor device, which can avoid the formation of a V-shaped silicon oxide surface and improve the conductivity of the semiconductor device.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device.

[0005] According to an embodiment of the present invention, a method for preparing a semiconductor device includes: providing a semiconductor substrate, wherein a groove is formed on the semiconductor substrate, a filling layer is formed in the groove, and a void gap is formed in the filling layer; removing part of the filling layer to expose the void gap; forming a plug, wherein the plug blocks the void gap and extends into the void gap to at least a preset value; removing part of the filling layer, retaining at least a preset height of the plug, until the filling layer has a preset thickness to form a contact hole.

[0006] According to some embodiments of the present invention, the plug is formed of silicon nitride material.

[0007] According to some embodiments of the present invention, a depth h of the plug extending into the cavity gap and a depth H of the cavity gap satisfy 2 / 3H≤h≤3 / 4H.

[0008] According to some embodiments of the present invention, the step of forming the blockage includes: depositing a silicon nitride material layer on the surface of the filling layer and in the void gap; removing the silicon nitride material layer located on the surface of the filling layer; and retaining the silicon nitride material located in the void gap to form the blockage.

[0009] Optionally, after removing part of the filling layer to expose the cavity gap, and before depositing silicon nitride material on the surface of the filling layer and in the cavity gap, the method further includes the following steps: partially removing the trench sidewalls.

[0010] Optionally, the silicon nitride material is deposited by low pressure chemical vapor deposition or atomic layer deposition.

[0011] According to some embodiments of the present invention, after removing part of the filling layer and retaining at least the blockage of a preset height until the filling layer reaches a preset thickness to form the contact hole, the following steps are also included: removing the blockage; forming a wire connection structure in the contact hole, the wire connection structure comprising an adhesion layer, a first conductive layer and a second conductive layer.

[0012] Optionally, the adhesion layer is a metal silicide layer.

[0013] Optionally, the adhesion layer is a cobalt silicide layer or a nickel silicide layer.

[0014] Optionally, forming a wire connection structure in the contact hole includes the following steps: forming the adhesion layer on the surface of the filling layer; forming the first conductive layer on the surface of the adhesion layer and the side of the contact hole; and forming the second conductive layer on the surface of the first conductive layer to fill the contact hole.

[0015] Optionally, the step of forming the adhesion layer on the surface of the filling layer includes: sputtering a metal material on the surface of the filling layer, and performing a rapid thermal annealing process to form the adhesion layer on the surface of the filling layer.

[0016] Optionally, the first conductive layer is a titanium nitride layer, and the second conductive layer is a metal tungsten layer.

[0017] According to some embodiments of the present invention, the semiconductor substrate includes a base and a support layer formed above the base, and the groove is formed in the support layer.

[0018] According to some embodiments of the present invention, the filling layer is a polysilicon layer.

[0019] The present invention also proposes a semiconductor device, comprising: a semiconductor substrate, a supporting layer formed on the semiconductor substrate, a groove formed in the supporting layer; a filling layer, the filling layer partially fills the groove and the thickness a of the filling layer and the depth b of the groove satisfy: 1 / 3b≤a≤1 / 2b; an adhesion layer, the adhesion layer is formed on the surface of the filling layer and is located in the groove; a first conductive layer and a second conductive layer, the first conductive layer is formed on the surface of the adhesion layer and the surface of the supporting layer, and the second conductive layer is formed in the first conductive layer and fills the groove.

[0020] According to some embodiments of the present invention, a silicon nitride film is further included, a cavity gap is formed in the filling layer, and the silicon nitride film is formed on the inner wall surface of the cavity gap.

[0021] According to some embodiments of the present invention, the semiconductor device further includes a bit line structure, wherein the bit line structure is formed on the surface of the substrate and is located in the supporting layer.

[0022] Optionally, the semiconductor device further comprises: an oxide layer, wherein the oxide layer is formed in the supporting layer and is located on both sides of the bit line structure.

[0023] The present invention also proposes a semiconductor device, comprising a semiconductor substrate, a supporting layer formed on the semiconductor substrate, a groove formed in the supporting layer; a filling layer, the filling layer partially fills the groove and a hollow gap is formed in the filling layer; a blockage, the blockage is formed in the groove and at least partially extends into the hollow gap.

[0024] According to some embodiments of the present invention, the depth h of the plug extending into the cavity gap and the depth H of the cavity gap satisfy 2 / 3H≤h≤3 / 4H BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1-Figure 12 A schematic structural diagram of a formation process of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0026] Figure 13-Figure 24 is a structural schematic diagram of a formation process of a method for preparing a semiconductor device according to another embodiment of the present invention;

[0027] Fig.25 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Reference numerals:

[0029] 100: semiconductor devices;

[0030] 1: semiconductor substrate, 11: base, 12: silicon oxide layer, 13: support layer, 14: trench, 15: contact hole;

[0031] 2: filling layer, 21: void gap;

[0032] 3: silicon nitride material layer, 31: blocking;

[0033] 4: Adhesion layer;

[0034] 5: wire connection structure, 51: first conductive layer, 52: second conductive layer;

[0035] 6: bit line structure, 61: first bit line layer, 62: second bit line layer;

[0036] 7: Oxide layer. DETAILED DESCRIPTION

[0037] A method for manufacturing a semiconductor device 100 and the semiconductor device 100 proposed in the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0038] A method for manufacturing a semiconductor device 100 according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0039] like Fig.25 As shown, a method for preparing a semiconductor device 100 according to an embodiment of the present invention may include: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 is formed with a groove 14, a filling layer 2 is formed in the groove 14, and a void gap 21 is formed in the filling layer 2; removing a portion of the filling layer 2 to expose the void gap 21; forming a plug 31, wherein the plug 31 blocks the void gap 21 and penetrates into the void gap 21 to at least a preset value; removing a portion of the filling layer 2, and retaining at least a preset height of the plug 31 until the filling layer 2 has a preset thickness to form a contact hole 15.

[0040] like Figure 1 As shown, a semiconductor substrate 1 is provided, which may include a base 11, a silicon oxide layer 12 and a support layer 13, wherein the silicon oxide layer 12 is formed in the base 11, and the support layer 13 is formed on the surfaces of the silicon oxide layer 12 and the base 11, and a groove 14 is formed in the support layer 13 by an etching process to expose the base 11, so as to fill the groove 14 with a filling layer 2.

[0041] The substrate 11 may be made of silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may be other materials, such as III-V group compounds such as gallium arsenide. The support layer 13 may be a nitride layer, such as a silicon nitride layer.

[0042] like Figure 1-Figure 24 As shown, the semiconductor substrate 1 may further include a bit line structure 6, the bit line structure 6 is formed on the surface of the silicon oxide layer 12 and is located in the support layer 13, the support layer 13 includes the bit line structure 6, the bit line structure 6 may include a first bit line layer 61 and a second bit line layer 62 stacked, wherein the first bit line layer 61 may be a titanium nitride layer, the second bit line layer 62 may be a metal tungsten layer, and the second bit line layer 62 is located above the first bit line layer 61. In other examples of the present invention, such as Figure 13-Figure 24As shown, the semiconductor substrate 1 may further include an oxide layer 7, which is formed above the silicon oxide layer 12 and located in the support layer 13, and is formed on both sides of the bit line structure 6. The oxide layer 7 may be a silicon oxide layer, such as Figure 13-Figure 24 The structure of the semiconductor substrate 1 shown is a NON structure, that is, the protection layer of the bit line structure 6 is set to a stacked structure of silicon nitride-silicon oxide-silicon nitride.

[0043] like Figure 2 and Fig.14 As shown, a filling layer 2 is deposited on the surface of the support layer 13 and in the groove 14, and the filling layer 2 fills the groove 14. The filling layer 2 can be a polysilicon layer. As for the formation method of the filling layer 2, the filling layer 2 can be formed by chemical vapor deposition or low-pressure chemical vapor deposition, or the filling layer 2 can also be formed by other step-type covering filling methods, wherein the filling layer 2 can also be doped with arsenic, boron, phosphorus, carbon, etc. or a mixture of multiple elements. As for the doping method, it can be in-situ doping, or the doping elements can be added by implantation or mixed doping.

[0044] Since the groove 14 has a certain depth, during deposition, a void gap 21 is easily formed in the filling layer 2, and the generation of the void gap 21 greatly increases the wire resistance of the semiconductor device 100. Therefore, it is necessary to eliminate or reduce the void gap 21 to reduce the wire resistance of the semiconductor device 100. Optionally, before depositing the filling layer 2, a seed layer may be firstly deposited and then a large amount of the filling layer 2 may be deposited. The seed layer is formed densely and has small grains. In this way, when the filling layer 2 is formed by step-by-step coverage, the formation of the void gap 21 can also be reduced.

[0045] like Figure 3 and Fig.15 As shown, a portion of the filling layer 2 is removed to expose the hollow gap 21. Specifically, the filling layer 2 can be slightly notched and a portion of the filling layer 2 at the top can be removed to open the hollow gap 21. The thickness of the removed filling layer 2 is sufficient as long as the hollow gap 21 can be exposed. Figure 5-Figure 6 as well as Figure 17-Figure 18 As shown, a plug 31 is formed, the plug 31 blocks the hollow gap 21, and extends into the hollow gap 21 to at least a preset value, so that by forming the plug 31, the filling layer 2 is etched, so that the etching solution or etching gas can be prevented from entering the hollow gap 21 during the etching process, thereby preventing the formation of a V-shaped interface. The plug 31 can be formed of silicon nitride material.

[0046] like Figure 4 and Fig.16As shown, after removing part of the filling layer 2, a groove formed after removing part of the filling layer 2 is formed at the upper part of the groove 14, and part of the sidewall of the groove 14 is removed, that is, part of the sidewall of the supporting layer 13 corresponding to the groove is removed, wherein the height of the sidewall of the removed part of the supporting layer 13 corresponds to the removed part of the filling layer 2, so that when the deposition forms the blockage 31, if part of the sidewall of the groove 14 is not removed, the deposition material is deposited at the sidewall of the groove 14, which easily makes the opening of the upper part of the groove 14 smaller, causing the deposition material on the sidewall of the groove 14 to cover the filling layer 2 at the bottom thereof, so that when the filling layer 2 is subsequently etched, it is easy to cause part of the filling layer 2 to fail to be etched. If part of the sidewall of the groove 14 is removed, when the deposition forms the blockage 31, the deposition material is simultaneously deposited at the sidewall of the groove 14 to fill the removed sidewall of the groove 14, and at the same time, it can also avoid blocking the filling layer 2 below it.

[0047] When removing part of the sidewall of the groove 14, wet etching can be used. Specifically, an etching chemical solution such as hydrofluoric acid, phosphoric acid or a mixture of the two can be used, which can etch the support layer 13 and selectively etch the filling layer 2. For example, if the material of the support layer 13 is nitride and the material of the filling layer 2 is polysilicon, the wet etching solution can etch the nitride and selectively etch the polysilicon material, and the etching rate of the polysilicon material is low.

[0048] Please refer to the following Figure 5-Figure 6 as well as Figure 17-Figure 18 The method for forming the plug 31 is described in the figure. The steps of forming the plug 31 may include: depositing a silicon nitride material layer 3 on the surface of the filling layer 2 and in the void gap 21, removing the silicon nitride material layer 3 located on the surface of the filling layer 2; retaining the silicon nitride material located in the void gap 21 to form the plug 31. In this way, the exposed void gap 21 can be filled by depositing the silicon nitride material, and the plug 31 is used as an etching plug to block the void gap 21 during the etching process of the filling layer 2, so as to eliminate the formation of the V-shaped interface of the filling layer 2 and improve the performance of the semiconductor device 100.

[0049] Specifically, Figure 5 and Fig.17 As shown, a silicon nitride material layer 3 is deposited on the surface of the filling layer 2 and in the void gap 21, and the deposition method may be low-pressure chemical vapor deposition or atomic layer deposition. The silicon nitride material layer 3 is deposited and formed on the upper surface of the filling layer 2. Since the void gap 21 is open and exposed, the silicon nitride material layer 3 can be partially deposited in the void gap 21. However, since the void gap 21 is small and narrow, the silicon nitride material cannot completely fill the entire void gap 21, and can be formed on the upper part of the void gap 21 to block the opening of the void gap 21.

[0050] like Figure 6 and Fig.18As shown, the silicon nitride material layer 3 located on the surface of the filling layer 2 is removed, and the silicon nitride material located in the void gap 21 is retained to form a plug 31, wherein the depth h of the plug 31 located in the void gap 21 and the depth H of the void gap 21 satisfy 2 / 3H≤h≤3 / 4H, that is, at this time, the height of the plug 31 located in the void gap 21 is two-thirds to three-quarters of the total height of the void gap 21.

[0051] like Figure 7 and Fig.19 As shown, after the plug 31 is formed, the remaining filling layer 2 is etched, and the plug 31 blocks the hollow gap 21. When the filling layer 2 is etched, the etching solution or gas can be prevented from entering the hollow gap 21. The filling layer 2 can be removed to the target depth by dry etching or other processes, and specifically, one or more mixed etchings of gases such as SF6 / CF4 / Cl2 / Ar can be used. Due to the different etching rates of polysilicon materials and nitride materials, when the filling layer 2 is etched, the etching rate of nitride is lower than the etching rate of polysilicon, and the plug 31 is etched slower than the filling layer 2, so that the plug 31 protrudes relative to the upper surface of the filling layer 2, so that the plug 31 can always block the hollow gap 21. For the etching depth of the filling layer 2, the filling layer 2 can be etched to the lower end of the plug 31, that is, the filling layer 2 can be etched to the upper surface of the filling layer 2 is not lower than the lower surface of the plug 31, so as to avoid the filling layer 2 being over-etched to expose the hollow gap 21. Furthermore, the height of the remaining filling layer 2 can be one half to two thirds of the depth of the groove 14. This not only facilitates the formation of the wire connection structure 5 above the filling layer 2, but also minimizes the height of the remaining filling layer 2 to reduce the void gap 21 therein.

[0052] like Figure 8-Figure 9 as well as Figure 20-21 As shown, the plug 31 is removed to facilitate the formation of the wire connection structure 5 in the groove 14, and to prevent the plug 31 from affecting the conductivity of the semiconductor device 100. In some examples of the present invention, since the plug 31 is small in size, it can be directly etched away by an etching process. In other examples of the present invention, such as Figure 8 and Fig. 20 As shown, a nitride material can be deposited on the surface of the filling layer 2 to cover the upper surface of the filling layer 2, and then as shown in Fig. 9 and Fig.21 As shown, the deposited silicon nitride material and the plug 31 are removed by dry etching or wet etching, which not only facilitates etching of the plug 31 but also prevents the etchant from corroding the sidewall of the trench 14 during the etching process, thereby protecting the sidewall of the trench 14.

[0053] like Figure 10-12 as well as Figure 22-Figure 24As shown, a wire connection structure 5 is formed in the contact hole 15, and the wire connection structure 5 includes an adhesion layer 4, a first conductive layer 51 and a second conductive layer 52, wherein the adhesion layer 4 is formed on the surface of the filling layer 2, the first conductive layer 51 is formed on the surface of the adhesion layer 4 and the side wall of the groove 14, and the second conductive layer 52 is formed in the first conductive layer 51 and fills the contact hole 15, that is, the first conductive layer 51 is formed into a U-shaped structure and wraps the second conductive layer 52, and the adhesion layer 4, the first conductive layer 51 and the second conductive layer 52 fill the contact hole 15.

[0054] The adhesion layer 4 can not only adhere to the first conductive layer 51 above it and the filling layer 2 below it to improve the structural stability, but also has good conductivity and can reduce the resistance reactance of the wire connection structure 5. Optionally, the material of the adhesion layer 4 can be metal silicide, for example, the material of the adhesion layer 4 can be cobalt silicide or nickel silicide.

[0055] Reference below Figure 10-12 as well as Figure 22-Figure 24 The method for forming the wire connection structure 5 is described in the figure. The steps of forming the wire connection structure 5 may include:

[0056] like Fig.10 and Fig. 22 As shown, an adhesion layer 4 is formed on the surface of the filling layer 2; specifically, metal cobalt or metal nickel can be sputtered on the surface of the filling layer 2, and then a rapid annealing process is performed to promote the metal cobalt or nickel to react with the bottom filling layer 2, and then the unreacted metal cobalt or nickel is removed by AMP or SPM wet method to form a metal silicide on the surface of the filling layer 2.

[0057] like Fig.11 and Fig.23 As shown, a first conductive layer 51 is formed on the surface of the adhesion layer 4 and the side of the contact hole 15; Fig.12 and Fig.24As shown, a second conductive layer 52 is formed on the surface of the first conductive layer 51 to fill the contact hole 15. Specifically, the contact hole 15 is formed above the adhesion layer 4, the first conductive layer 51 covers the upper surface of the support layer 13, the side of the contact hole 15 and the upper surface of the adhesion layer 4, and the second conductive layer 52 is formed on the surface of the first conductive layer 51 and fills the contact hole 15 with the first conductive layer 51 to form a wire connection structure 5. The first conductive layer 51 can be formed as a barrier layer, so as to prevent the metal diffusion of the second conductive layer 52. Further, in the process of forming the second conductive layer 52, the precursor of the second conductive layer 52 can be chloride, and the decomposition of chloride will produce chloride ions. The diffusion of chloride ions in the formation process of the second conductive layer 52 can also be prevented by the first conductive layer 51. For example, the first conductive layer 51 can be a titanium nitride material, and the second conductive layer 52 can be a metal tungsten layer. In the process of filling the metal tungsten, the precursor tungsten hexachloride is used, and the dissociation of tungsten hexachloride will produce chloride ions. The diffusion of chloride ions can be prevented by the first conductive layer 51.

[0058] The semiconductor device 100 according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0059] like Fig.12 and Fig.24 As shown, the semiconductor device 100 may include a semiconductor substrate 1 , a filling layer 2 , an adhesion layer 4 , a first conductive layer 51 , and a second conductive layer 52 .

[0060] The semiconductor substrate 1 may include a base 11, a silicon oxide layer 12, and a support layer 13 formed on the silicon oxide layer 12, wherein a groove 14 is formed in the support layer 13 by patterning, and the groove 14 exposes the surface of the base 11 thereunder. A filling layer 2 is formed in the groove 14, and the filling layer 2 partially fills the groove 14, wherein the thickness a of the filling layer 2 and the depth b of the groove 14 satisfy: 1 / 3b≤a≤1 / 2b, that is, the height of the filling layer 2 may be from one third to one half times the depth of the groove 14.

[0061] The adhesion layer 4 is formed on the surface of the filling layer 2 and is located in the groove 14. The first conductive layer 51 is formed on the surface of the adhesion layer 4, the sidewall of the groove 14 and the surface of the support layer 13. The second conductive layer 52 is formed in the first conductive layer 51 and fills the groove 14. The adhesion layer 4 can not only adhere to the first conductive layer 51 above it and the filling layer 2 below it to improve the structural stability, but also has a good conductive effect and can reduce the resistance reactance of the wire connection structure 5. Optionally, the material of the adhesion layer 4 can be metal silicide, for example, the material of the adhesion layer 4 can be cobalt silicide or nickel silicide, the material of the support layer 13 can be silicon nitride, and the material of the filling layer 2 can be polysilicon. The material of the first conductive layer 51 can be titanium nitride, and the material of the second conductive layer 52 can be a metal tungsten material.

[0062] like Fig.12 and Fig.24 As shown, the semiconductor device 100 may further include a bit line structure 6, which is formed on the surface of the substrate 11 and located in the support layer 13. The bit line structure 6 may include a first bit line layer 61 and a second bit line layer 62 which are stacked, wherein the first bit line layer 61 may be a titanium nitride layer, the second bit line layer 62 may be a metal tungsten layer, and the second bit line layer 62 is located above the first bit line layer 61. In some examples of the present invention, such as Fig.24 As shown, the semiconductor substrate 1 may further include an oxide layer 7 formed above the silicon oxide layer 12 and located in the support layer 13 and formed on both sides of the bit line structure 6 , wherein the oxide layer 7 may be a silicon oxide layer.

[0063] like Fig.12 and Fig.24 As shown, the semiconductor device 100 may also include a silicon nitride film, a void gap 21 is formed in the filling layer 2, the depth of the void gap 21 is less than the depth of the filling layer 2, and the silicon nitride film is formed on the inner wall surface of the void gap 21, so that when the filling layer 2 is etched, the etching damage to the side wall of the void gap 21 formed in the filling layer 2 by the etching solution or gas can be reduced.

[0064] The present invention also provides a semiconductor device 100. Figure 6 Shown and Fig.18 As shown, a semiconductor device 100 according to an embodiment of the present invention may include a semiconductor substrate 1 , a filling layer 2 , and a plug 31 .

[0065] The semiconductor substrate 1 may include a base 11, a silicon oxide layer 12, and a support layer 13 formed on the silicon oxide layer 12. A groove 14 is formed in the support layer 13 by patterning, and the groove 14 exposes the surface of the base 11 below. A filling layer 2 is formed in the groove 14, and the filling layer 2 partially fills the groove 14.

[0066] The plug 31 is formed in the groove 14 and at least partially extends into the void gap 21. In this way, the void gap 21 can be sealed by the plug 31. When the filling layer 2 is subsequently etched, the etching solution or gas can be prevented from entering the void gap 21, thereby preventing a V-shaped interface from being formed on the surface of the filling layer 2 in the subsequent process and affecting the performance of the semiconductor device 100.

[0067] The depth h of the plug 31 located in the void gap 21 and the depth H of the void gap 21 satisfy 2 / 3H≤h≤3 / 4H, that is, the height of the plug 31 located in the void gap 21 is two-thirds to three-quarters of the total height of the void gap 21, so that when the plug 31 is deposited, the plug 31 can fill part of the void gap 21 to seal the opening of the void gap 21, and when the subsequent filling layer 2 is etched to form the contact hole 15 of the deposited wire connection structure 5, it can be ensured that before the filling layer 2 is etched to the target depth, the void gap 21 is not exposed, resulting in etching solution or gas entering the void gap 21, so as to avoid the formation of a V-shaped interface and reduce the performance of the semiconductor device 100.

[0068] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A semiconductor substrate is provided, wherein a groove is formed on the semiconductor substrate, a filling layer is formed in the groove, and a cavity gap is formed in the filling layer; Removing part of the filling layer to expose the cavity gap; Forming a blockage, the blockage blocks the hollow gap and extends into the hollow gap to at least a preset value; A portion of the filling layer is removed, and at least a preset height of the blockage is retained until the filling layer reaches a preset thickness, so as to form a contact hole.

2. The method for preparing a semiconductor device according to claim 1, wherein: The plug is formed of silicon nitride material.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The depth h of the plug extending into the cavity gap and the depth H of the cavity gap satisfy 2 / 3H≤h≤3 / 4H.

4. The method for preparing a semiconductor device according to claim 1, wherein: The steps of forming the blockage include: Depositing a silicon nitride material layer on the surface of the filling layer and in the cavity gap; removing the silicon nitride material layer located on the surface of the filling layer; The silicon nitride material in the void gap is retained to form the plug.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: After removing part of the filling layer to expose the cavity gap, and before depositing silicon nitride material on the surface of the filling layer and in the cavity gap, the method further includes the following steps: partially removing the trench sidewall.

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The silicon nitride material is deposited by low pressure chemical vapor deposition or atomic layer deposition.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: After removing part of the filling layer and retaining at least the blockage of a preset height until the filling layer has a preset thickness to form the contact hole, the method further includes the following steps: removing the blockage; A wire connection structure is formed in the contact hole, wherein the wire connection structure includes an adhesion layer, a first conductive layer and a second conductive layer.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The adhesion layer is a metal silicide layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The adhesion layer is a cobalt silicide layer or a nickel silicide layer.

10. The method for preparing a semiconductor device according to claim 7, characterized in that The forming of the wire connection structure in the contact hole comprises the following steps: forming the adhesion layer on the surface of the filling layer; forming the first conductive layer on the surface of the adhesion layer and the side of the contact hole; The second conductive layer is formed on the surface of the first conductive layer to fill the contact hole.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The step of forming the adhesion layer on the surface of the filling layer includes: sputtering a metal material on the surface of the filling layer, and performing a rapid thermal annealing process to form the adhesion layer on the surface of the filling layer.

12. The method for preparing a semiconductor device according to claim 10, characterized in that: The first conductive layer is a titanium nitride layer, and the second conductive layer is a metal tungsten layer.

13. The method for preparing a semiconductor device according to claim 1, characterized in that: The semiconductor substrate includes a base and a support layer formed on the base, wherein the groove is formed in the support layer.

14. The method for preparing a semiconductor device according to claim 1, characterized in that: The filling layer is a polysilicon layer.

15. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein a support layer is formed on the semiconductor substrate, and a groove is formed in the support layer; A filling layer, wherein the filling layer partially fills the groove and a thickness a of the filling layer and a depth b of the groove satisfy: 1 / 3b≤a≤1 / 2b; an adhesion layer, the adhesion layer being formed on the surface of the filling layer and being located in the groove; A first conductive layer and a second conductive layer, wherein the first conductive layer is formed on surfaces of the adhesion layer and the support layer, and the second conductive layer is formed in the first conductive layer and fills the groove.

16. The semiconductor device according to claim 15, characterized in that It also includes a silicon nitride film. A cavity gap is formed in the filling layer, and the silicon nitride film is formed on the inner wall surface of the cavity gap.

17. The semiconductor device according to claim 15, characterized in that Also included is a bit line structure, which is formed on the surface of the semiconductor substrate and located in the supporting layer.

18. The semiconductor device according to claim 17, characterized in that Also includes: An oxide layer is formed in the support layer and is located at two sides of the bit line structure.

19. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein a support layer is formed on the semiconductor substrate, and a groove is formed in the support layer; A filling layer, wherein the filling layer partially fills the groove and a hollow gap is formed in the filling layer; a plugging, wherein the plugging is formed in the groove and at least partially extends into the hollow gap, and a depth h of the plug extending into the hollow gap and a depth H of the hollow gap satisfy 2 / 3H≤h≤3 / 4H.

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