A digital signal processor capable of directly supporting multi-operand addition operations

Abstract

The present invention discloses a digital signal processor that can directly support multi-operand addition operations, including: an input register group, a customized multiplier, a first general multiplier, a second general multiplier, a third general multiplier, a first adder, a second adder, an addition output register, an adder / accumulator, a chain adder, and an output register. The present invention implements a structure by customizing the multiplier in the DSP architecture, and the customized multiplier can be configured into a multiplication mode or support an eight-operand addition mode, so that the DSP can directly support multi-operand addition operations.

Description

Technical Field

[0001] The invention belongs to the technical field of digital integrated circuits, and in particular relates to a digital signal processor that can directly support multi-operand addition operations. Background Art

[0002] With the development of semiconductor technology and microelectronics technology, the information and signal processing technology of circuit systems is becoming more and more advanced, which can transmit faster signals and implement more complex algorithms. At the same time, digital signal processing has also independently developed into a very important and mature technology, and has replaced traditional analog signal processing in many application fields, such as audio and video processing, digital image processing, sonar and radar, biomedical signal analysis, precision-guided weapons, etc., which has a profound impact on the development of contemporary society. However, when faced with large computationally intensive tasks, the cost of circuit operations will increase dramatically, and digital signal processing units have emerged. This unit has a special computing component that can significantly improve the performance of digital signal processing algorithms. As the core component for implementing digital signal algorithms today, digital signal processing units have become basic devices in important fields such as computers and communications.

[0003] Field Programmable Gate Array (FPGA) is a programmable signal processing device. Users can redefine its functions by changing configuration information according to design requirements. It is a product further developed on the basis of programmable devices such as PAL, PLA, CPLD, etc. As a semi-custom programmable logic device, it solves the shortcomings of weak flexibility of application-specific integrated circuits (ASIC) and overcomes the problem of limited number of gate circuits of original programmable devices. In recent years, the market demand for FPGA emphasizes the flexibility and versatility of FPGA structure and requires its ability to process complex algorithms. Algorithms cover digital signal processing, deep learning neural networks and big data acceleration computing, among which digital signal processing involves increasingly complex algorithms, covering digital communication, voice and video processing, biomedical signal processing, sonar radar processing, etc. Algorithm implementation is a computationally intensive task. Such algorithms often require a large number of multiplication and addition operations. The purpose of implementing the algorithm can be achieved by using the logical resources and structural parallelism of FPGA itself. However, since FPGA is a semi-custom circuit, when implementing complex algorithms, comprehensive tools are needed to convert and optimize the code and map it to the lookup table. The mapping process often cannot realize the utilization of resources well, resulting in serious waste of resources, and the performance of algorithm implementation cannot be guaranteed. As an important computing module in FPGA devices, DSP hard core can realize various simple or complex arithmetic and logic operations, which can significantly improve the computing performance of FPGA and greatly broaden the application field of FPGA.

[0004] At present, FPGA products launched by FPGA manufacturers in the domestic and foreign markets are all embedded with DSP hard cores. The DSP structures embedded in different FPGAs are different, but they can all support many basic arithmetic operations, such as multiplication, multiplication and addition, and multiplication and accumulation. However, there is currently no DSP hard core that can directly support multi-operand addition operations. FPGA can only use on-chip logic resources to implement multi-operand addition operations, but this method of implementing multi-operand addition not only consumes too many logic resources but also affects the performance of addition operations. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a digital signal processor that can directly support multi-operand addition operations in view of the deficiencies in the above-mentioned prior art. The digital signal processor realizes the structure by customizing the multiplier in the DSP architecture. The customized multiplier can be configured into a multiplication mode or support an eight-operand addition mode, so that the DSP can directly support multi-operand addition operations.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a digital signal processor that can directly support multi-operand addition operations, comprising:

[0007] An input register group, used to process input data;

[0008] A custom multiplier, whose input terminal is connected to the output terminal of the input register bank, is used to implement a multiplication operation or a multi-operand addition operation;

[0009] A first universal multiplier, an input terminal of which is connected to an output terminal of the input register group, for implementing a multiplication operation;

[0010] A second general multiplier, an input terminal of which is connected to an output terminal of the input register group, for implementing a multiplication operation;

[0011] A third general multiplier, an input terminal of which is connected to an output terminal of the input register group, for implementing a multiplication operation;

[0012] A first adder, whose input end is connected to the output end of the first general multiplier and the output end of the custom multiplier, for implementing an addition operation;

[0013] A second adder, whose input end is connected to the output end of the second general multiplier and the output end of the third general multiplier, for implementing an addition operation;

[0014] An addition output register, whose input end is connected to the output end of the first adder and the output end of the second adder, and is used for processing the output data;

[0015] An adder / accumulator, whose input end is connected to the output end of the adder output register, and is used to accumulate data output by the adder output register;

[0016] A chain adder, whose input end is connected to the output end of the adder / accumulator, for realizing chain addition;

[0017] The output register has an input end connected to the output end of the chain adder and is used to process the output data.

[0018] In the above-mentioned digital signal processor that can directly support multi-operand addition operations, the input register group includes a first multiplexer, a delay register and a second multiplexer connected in sequence.

[0019] In the above-mentioned digital signal processor that can directly support multi-operand addition operations, the first multiplexer and the second multiplexer are both 2-to-1 multiplexers.

[0020] The above-mentioned digital signal processor that can directly support multi-operand addition operations, the customized multiplier includes:

[0021] Data preprocessing module: used to preprocess the data output by the input register group;

[0022] Improved Booth encoding module: used to perform Booth encoding on the data output by the input register group to generate partial products;

[0023] Data post-processing module: connected to the output end of the improved Booth encoding module, used for post-processing the data output by the improved Booth encoding module;

[0024] Data selector: connected to the output end of the data pre-processing module and the output end of the data post-processing module, used to select the output result of the data pre-processing module and the output result of the data post-processing module;

[0025] Compression tree reduction simple element: connected to the output end of the data selector, used to compress the partial product array output by the data selector to obtain the final result.

[0026] The above-mentioned digital signal processor that can directly support multi-operand addition operations, the improved Booth encoding module includes an intermediate result generation module and a final result generation module, the intermediate result generation module includes an XOR gate U1, an XNOR gate U2, an XNOR gate U3 and a NAND gate U4 arranged in parallel, and an AND gate U5 connected to the output end of the NAND gate U4; the final result generation module includes an XNOR gate U6 and an XNOR gate U7 arranged in parallel, an AND gate U8, an AND gate U9 and an AND gate U10 arranged in parallel, and a NOR gate U11 connected to the output ends of the AND gates U8, U9 and U10; the output end of the XNOR gate U6 is connected to the input end of the AND gate U8, and the output end of the XNOR gate U7 is connected to the input end of the AND gate U10.

[0027] The above-mentioned digital signal processor that can directly support multi-operand addition operations, the data post-processing module includes a first data post-processing unit for optimizing the sign bit of each partial product and a second data post-processing unit for implementing 8-input addition operations;

[0028] The calculation formula used by the first data post-processing unit to optimize the sign bit of each partial product is:

[0029]

[0030] Among them, S represents the binary number 0 or 1, the subscript numbers 0 to 8 of S represent the weight, that is, the position of the binary number S; n is the exponent of the number 2;

[0031] Simplifying formula (F1) we get:

[0032]

[0033] Among them, i is the weight, which is the position of the binary number S;

[0034] The second data post-processing unit performs a zero padding operation on each row of low-order data.

[0035] The above-mentioned digital signal processor that can directly support multi-operand addition operations, when the data preprocessing module preprocesses the data output by the input register group, the data output by the input register group is sign-bit extended to obtain the same data bit width as the data output by the data post-processing module.

[0036] The above-mentioned digital signal processor that can directly support multi-operand addition operations, when the compression tree approximation simple element compresses the partial product array output by the data selector, a five-level compression method is adopted, wherein the first-level compression and the second-level compression are compressed by a combination of 3-2 compressors, 4-2 compressors and 5-2 compressors; the third-level compression is compressed by a 3-2 compressor, the fourth-level compression is the result of the third-level compression, and the fifth-level compression is zero-filling processing.

[0037] The above-mentioned digital signal processor that can directly support multi-operand addition operations, the calculation formula of the 3-2 compressor is:

[0038] X1+X2+X3=sum+2*(carry) (F3)

[0039] Among them, X1, X2 and X3 are three data received by the 3-2 compressor, and the weights of X1, X2 and X3 are the same; sum is the sum value calculated by the 3-2 compressor, and the weight of sum is the same as the weights of X1, X2 and X3; carry is the carry calculated by the 3-2 compressor, and the weight of carry is one digit higher than the weight of sum;

[0040] The calculation formula of the 4-2 compressor is:

[0041] cin+X1+X2+X3+X4=sum+2*(cout+carry) (F4)

[0042] Among them, cin, X1, X2, X3 and X4 are 5 data received by the 4-2 compressor, and the weights of cin, X1, X2, X3 and X4 are the same, and cin is the carry number; sum is the sum value calculated by the 4-2 compressor, and the weight of sum is the same as the weights of cin, X1, X2, X3 and X4; cout and carry are the carry calculated by the 4-2 compressor, and the weights of cout and carry are one digit higher than the weight of sum;

[0043] The calculation formula of the 5-2 compressor is:

[0044] c1_in+c1_in+X1+X2+X3+X4+X5=sum+2*(c1_out+c2_out+carry) (F5)

[0045] Among them, c1_in, c1_in, X1, X2, X3, X4 and X5 are 7 data received by the 5-2 compressor, c1_in, c1_in, X1, X2, X3, X4 and X5 have the same weights, and c1_in and c1_in are both carry digits; sum is the sum value calculated by the 5-2 compressor, and the weight of sum is the same as the weight of c1_in, c1_in, X1, X2, X3, X4 and X5; c1_out, c2_out and carry are all carries calculated by the 5-2 compressor, and the weights of c1_out, c2_out and carry are one digit higher than the weight of sum.

[0046] Compared with the prior art, the present invention has the following advantages:

[0047] 1. Only one customized multiplier needs to be implemented in the DSP module to realize the function of multi-input addition operation.

[0048] 2. The customized multiplier structure enables the DSP to fully utilize the module's 8 input ports and directly support the addition operation of up to eight operands. This avoids the waste of resources caused by using FPGA logic resources to implement addition and improves the performance of addition operations.

[0049] 3. You can also selectively insert pipelines into custom multipliers to improve the performance of the multiplier.

[0050] 4. Customized multiplier structure uses different compressors for targeted optimization to reduce the area occupied by the multiplier.

[0051] 5. In the custom multiplier, the Booth coding circuit uses XOR gates and XOR gates to generate intermediate results X1, X2P and ZP, ensuring that they have the same circuit delay. This prevents the intermediate results from changing asynchronously when the coding number changes, causing the partial product values ​​to change continuously, thereby achieving the purpose of reducing power consumption.

[0052] 6. For multi-input addition operations, DSP can support 8 18-bit signed additions. Due to the existence of the accumulator in the DSP, the output results can be registered. The DSP can support the output of up to 8 operand addition results in one beat, and up to 16 operands in two beats. The purpose of resource reuse is achieved, and the performance of the adder is still higher than that of the FPGA logic implementation.

[0053] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a schematic diagram of the architecture of a digital signal processor that can directly support multi-operand addition operations according to the present invention;

[0055] Figure 2 Schematic diagram of the structure of the input register group S101 of the present invention;

[0056] Figure 3 A schematic diagram of the structure of the customized multiplier S102 of the present invention;

[0057] Figure 4 Schematic diagram of the structure of the improved Booth encoding module S202 of the present invention;

[0058] Figure 5 It is a schematic diagram of the processing process of the first data post-processing unit of the present invention;

[0059] Figure 6 A schematic diagram of the data preprocessing module S201 of the present invention preprocessing the data output by the input register group S101;

[0060] Figure 7 It is a schematic diagram of the compression tree simple element S205 of the present invention compressing the partial product array output by the data selector S204;

[0061] Figure 8 It is a schematic diagram of the structure of the compressor S500 of the present invention. DETAILED DESCRIPTION

[0062] like Figure 1 As shown, the digital signal processor of the present invention that can directly support multi-operand addition operation includes:

[0063] Input register group S101, used for processing input data;

[0064] A custom multiplier S102, whose input terminal is connected to the output terminal of the input register group S101, is used to implement a multiplication operation or a multi-operand addition operation;

[0065] A first general multiplier S103a, whose input terminal is connected to the output terminal of the input register group S101, is used to implement a multiplication operation;

[0066] A second general multiplier S103b, whose input terminal is connected to the output terminal of the input register group S101, is used to implement a multiplication operation;

[0067] A third general multiplier S103c, whose input terminal is connected to the output terminal of the input register group S101, is used to implement a multiplication operation;

[0068] A first adder S104a, whose input end is connected to the output end of the first general multiplier S103a and the output end of the custom multiplier S102, for implementing an addition operation;

[0069] A second adder S104b, whose input end is connected to the output end of the second general multiplier S103b and the output end of the third general multiplier S103c, for implementing an addition operation;

[0070] An addition output register S105, whose input end is connected to the output end of the first adder S104a and the output end of the second adder S104b, and is used to process the output data;

[0071] An adder / accumulator S106, whose input end is connected to the output end of the adder output register S105, and is used to accumulate the data output by the adder output register S105;

[0072] A chain adder S107, whose input end is connected to the output end of the adder / accumulator S106, for implementing chain addition;

[0073] The output register S108 has an input end connected to the output end of the chain adder S107 and is used to process the output data.

[0074] A DSP architecture S100 supporting multi-operand addition operations, such as Figure 1As shown, it is a complete DSP architecture that can implement basic arithmetic operations, multiplication, multiply-add, multiply-accumulate, chain addition, and shift register chain functions.

[0075] In this embodiment, the input register group S101 includes a first multiplexer, a delay register, and a second multiplexer connected in sequence.

[0076] In this embodiment, the first multiplexer and the second multiplexer are both 2-to-1 multiplexers.

[0077] like Figure 2 The structure diagram of the input register group S101 is shown. The input register group S101 is configured by the first multiplexer, which can realize input data storage and form a shift register chain, and the length of the shift register chain is 5 levels. By inserting a delay register, it is convenient for the DSP module to process applications such as FIR digital filters. Then the second multiplexer is used to select whether to store, and then the result is sent out to ensure the synchronization of data reaching the custom multiplier S102, the first general multiplier S103a, the second general multiplier S103b and the third general multiplier S103c.

[0078] In this embodiment, the customized multiplier S102 includes:

[0079] Data preprocessing module S201: used to preprocess the data output by the input register group S101;

[0080] Improved Booth encoding module S202: used to perform Booth encoding on the data output by the input register group S101 to generate partial products; Booth encoding can reduce the number of partial products and improve the performance of the multiplier;

[0081] Data post-processing module S203: connected to the output end of the improved Booth encoding module S202, used for post-processing the data output by the improved Booth encoding module S202;

[0082] Data selector S204: connected to the output end of the data pre-processing module S201 and the output end of the data post-processing module S203, used for selecting the output result of the data pre-processing module S201 and the output result of the data post-processing module S203;

[0083] The compression tree reduction simple element S205 is connected to the output end of the data selector S204 and is used to compress the partial product array output by the data selector S204 to obtain the final result.

[0084] In specific implementation, the multiplier S102 (S200) is customized, such as Figure 3As shown, the custom multiplier is also called a multiplier or adder block (MAB). The conventional multiplier implementation steps include Booth encoding, compressed partial products, and partial product summation. However, the conventional multiplier can only implement the multiplication operation of two numbers. The designed custom multiplier can support a maximum of 8 operand addition operations.

[0085] In this embodiment, the improved Booth encoding module S202 includes an intermediate result generation module and a final result generation module, the intermediate result generation module includes an XOR gate U1, an XOR gate U2, an XOR gate U3 and a NAND gate U4 arranged in parallel, and an AND gate U5 connected to the output end of the NAND gate U4; the final result generation module includes an XOR gate U6 and an XOR gate U7 arranged in parallel, an AND gate U8, an AND gate U9 and an AND gate U10 arranged in parallel, and a NOR gate U11 connected to the output ends of the AND gates U8, U9 and U10; the output end of the XOR gate U6 is connected to the input end of the AND gate U8, and the output end of the XOR gate U7 is connected to the input end of the AND gate U10.

[0086] In specific implementation, the circuit structure of the improved Booth encoding module S202 is as follows: Figure 4 As shown, the inputs of XOR gate U1, XOR gate U2 and NAND gate U4 are all y2i and y2i-1, and the inputs of XOR gate U3 are y2i+1 and y2i; wherein y is the multiplier to be encoded, y2i+1, y2i, y2i-1 are three consecutive binary bits (the number represents the weight of the binary number, that is, the position of each bit); the input of AND gate U5 is y2i+1 and the output of NAND gate U4, y2i+1 corresponds to the intermediate result NEG, the output of XOR gate U1 is the intermediate result X1, the output of XOR gate U2 is the intermediate result X2P, the output of XOR gate U3 is the intermediate result ZP, and the output of AND gate U5 is the intermediate result ADD. The improved Booth encoding module S202 generates the intermediate results X1, X2P and ZP through the intermediate result generation module, ensuring that they have the same circuit delay; in addition, it prevents the value of the partial product from changing continuously due to the asynchronous change of the intermediate result when the encoding number changes, thereby achieving the purpose of reducing power consumption. The Booth coding table is shown in Table 1:

[0087] Table 1 Improved Booth coding table

[0088] y2i+1 y2i y2i-1 NEG X1 X2P ZP ADD 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1

[0089] In the final result generation module, the inputs of the XNOR gate U6 are xj and NEG, the inputs of the XNOR gate U7 are xj-1 and NEG, the inputs of the AND gate U8 are X1 and the output of the XNOR gate U6, the inputs of the AND gate U9 are ZP and X2P, the inputs of the AND gate U10 are X2P and the output of the XNOR gate U7, the inputs of the NOR gate U11 are the output of the AND gate U8, the output of the AND gate U9 and the output of the AND gate U10, and the output of the NOR gate U11 is PPj.

[0090] In this embodiment, the partial product generated by the improved Booth encoding module S202 is MP[8:0][18:0].

[0091] In this embodiment, the data post-processing module S203 includes a first data post-processing unit for optimizing the sign bit of each partial product and a second data post-processing unit for implementing an 8-input addition operation;

[0092] The calculation formula used by the first data post-processing unit to optimize the sign bit of each partial product is:

[0093]

[0094] Among them, S represents the binary number 0 or 1, the subscript numbers 0 to 8 of S represent the weight, that is, the position of the binary number S; n is the exponent of the number 2;

[0095] Simplifying formula (F1) we get:

[0096]

[0097] Among them, i is the weight, which is the position of the binary number S;

[0098] The second data post-processing unit performs a zero padding operation on each row of low-order data.

[0099] When implementing it, Figure 5As shown, the processing process of the first data post-processing unit is from S203a to S203b, and the processing process is to simplify the operation and save resources. When the multiplier performs partial product operations, the highest bit needs to be filled with the sign bit, but this operation requires additional circuit resources. The sign bit of each partial product is optimized and summed in advance to optimize the formula, as shown in formula (F1), and formula (F2) is calculated. Therefore, there is no need to expand the sign bit in the subsequent calculations. It is only necessary to invert the highest bit of each partial product and add a new row. The original 9 partial products now have 10 partial products. The newly added row has 18 high bits of 10101010101010101011, and the last 18 bits are the ADD signal when the partial product is generated. The bits with ADD signals are filled with ADD values, and the bits without ADD signals are filled with 0. The second data post-processing unit processes from S203b to S203c, and performs zero padding operation on each row of low-order data, in order to facilitate the subsequent compression operation and realize 8-input addition operation. S203c is a new partial product array.

[0100] The data post-processing module S203 implements post-processing of the data. The results after processing are: BP[0] has 19 bits, BP[1] has 21 bits, BP[2] has 23 bits, BP[3] has 25 bits, BP[4] has 27 bits, BP[5] has 29 bits, BP[6] has 31 bits, BP[7] has 33 bits, BP[8] has 35 bits, and BP[9] has 36 bits.

[0101] In this embodiment, when the data preprocessing module S201 preprocesses the data output by the input register group S101, the data output by the input register group S101 is sign-bit extended to obtain the same data bit width as the data output by the data post-processing module S203.

[0102] When implementing it, Figure 6 As shown, the data preprocessing module S201 performs sign bit extension on the input data ADDOPE[7:0][17:0] to obtain the same data bit width as S203c.

[0103] In this embodiment, the compression tree simple element S205 uses a five-level compression method (such as Figure 7S401, S402, S403, S404 and S405), wherein the first-level compression S401 and the second-level compression S402 are compressed by combining 3-2 compressor S500a, 4-2 compressor S500b and 5-2 compressor S500c; the third-level compression S403 is compressed by 3-2 compressor S500a, the fourth-level compression S404 is the result of the third-level compression (paving the way for the zero-padding processing of the fifth-level compression S405), and the fifth-level compression S405 is zero-padding processing.

[0104] The specific structure of each level is as follows Figure 7 shown.

[0105] In this embodiment, the calculation formula of the 3-2 compressor S500a is:

[0106] X1+X2+X3=sum+2*(carry) (F3)

[0107] Among them, X1, X2 and X3 are three data received by the 3-2 compressor S500a, and the weights of X1, X2 and X3 are the same; sum is the sum value calculated by the 3-2 compressor S500a, and the weight of sum is the same as the weights of X1, X2 and X3; carry is the carry calculated by the 3-2 compressor S500a, and the weight of carry is one digit higher than the weight of sum;

[0108] The calculation formula of the 4-2 compressor S500b is:

[0109] cin+X1+X2+X3+X4=sum+2*(cout+carry) (F4)

[0110] Among them, cin, X1, X2, X3 and X4 are 5 data received by the 4-2 compressor S500b, the weights of cin, X1, X2, X3 and X4 are the same, and cin is the carry digit; sum is the sum value calculated by the 4-2 compressor S500b, and the weight of sum is the same as the weights of cin, X1, X2, X3 and X4; cout and carry are the carry digits calculated by the 4-2 compressor S500b, and the weights of cout and carry are both one digit higher than the weight of sum;

[0111] The calculation formula of the 5-2 compressor S500c is:

[0112] c1_in+c1_in+X1+X2+X3+X4+X5=sum+2*(c1_out+c2_out+carry) (F5)

[0113] Among them, c1_in, c1_in, X1, X2, X3, X4 and X5 are 7 data received by the 5-2 compressor S500c, the weights of c1_in, c1_in, X1, X2, X3, X4 and X5 are the same, and c1_in and c1_in are both carry digits; sum is the sum value calculated by the 5-2 compressor S500c, and the weight of sum is the same as the weight of c1_in, c1_in, X1, X2, X3, X4 and X5; c1_out, c2_out and carry are all carries calculated by the 5-2 compressor S500c, and the weights of c1_out, c2_out and carry are one digit higher than the weight of sum.

[0114] Compressor S500, such as Figure 8 As shown, it includes a 3-2 compressor S500a, a 4-2 compressor S500b, and a 5-2 compressor S500c.

[0115] The final output result of the customized multiplier can be the multiplier result or the result of multi-operand addition. The performance of the customized multiplier is also considered in the design scheme, and registers can be added during the implementation of the multiplier. Of course, registers can also be inserted after each step of S401, S402, S403, and S404. It is theoretically feasible, but considering the circuit area of ​​the multiplier structure and pursuing a higher cost performance, the best choice is to insert a first-level pipeline to register the result of step S401. Another important reason for choosing to insert the result of S401 into the pipeline is that when designing the compression array, the entire circuit path is divided into two as much as possible, and the main compression unit is implemented in the first level, so the performance can be improved as much as possible when inserting the pipeline. However, considering the overall performance of the DSP here, realizing a customized multiplier with full combinational logic has met the DSP's requirements for multiplier performance. The design ideas for pipeline multipliers can be used in future designs.

[0116] The operation after S405 is actually implemented in the form of a 36-bit adder. Since the design is a combinational circuit, the core of selecting the adder is to pursue the speed of the adder. After comparing the performance of various adders, the Koggle_Stone tree adder is selected to achieve the final summation. Since the Koggle_Stone adder is easy to implement 2N-bit width addition, the designed adder is a combination of a 32-bit wide KS adder and a 4-bit wide carry-lookahead adder.

[0117] The first general multiplier S103a, the second general multiplier S103b, and the third general multiplier S103c have the same structure. They only need to implement multiplication operations, so their structures are different from the custom multiplier structures. The general multiplier structure here is not within the scope of discussion, but considering the area, performance, and power consumption of the multiplier implementation, the general multiplier structure is chosen here to be implemented with Booth encoding, Wallance compression tree, and final summation.

[0118] Universal adders S104a and S104b implement addition operations, and the two adders have the same structure. They are used to add the results of the multipliers, so that the DSP can support two-multiply-add operations. Adder / accumulator S106 is used to implement two-level addition or accumulation operations, so that the DSP can support three-multiply-add, four-multiply-add or multiply-accumulate operations. Chain adder S107 supports chain addition operations between DSP blocks. The implementation structure of all adders in the present invention can include commonly used Koggle_Stone, Sklansky, Knowles tree adders, but can still include other types of adders.

[0119] The addition output register S105 stores the results from the two groups of addition operations to increase the frequency of DSP implementation. The output register S108 stores the final output results of the DSP module. Because these pipeline registers are inserted into the DSP module, the performance of the DSP is improved, but at the cost of increasing the area occupied by the DSP.

[0120] The present invention is aimed at the field of digital circuit design, and the DSP hard core structure in FPGA. The purpose of the present invention is to realize a DSP structure that can directly support multi-operand addition operations. The detailed structure of DSP architecture design S100 is referenced Figure 1 ,After designing the DSP architecture, we consider customizing the multiplier implementation structure, which can support eight operand addition operations.,DSP is a fully customized structure, which is used to be embedded in FPGA to improve the performance of FPGA arithmetic operations.

[0121] The specific implementation process is as follows. According to the DSP mode, it can be divided into independent multiplication, double multiplication and addition, quadruple multiplication and addition, and multiplication and accumulation. When selecting different modes, the circuit configuration is performed by software. Because multi-input addition needs to occupy all input data ports, the multi-input addition supported by the design exists in independent multiplication and multiplication and accumulation modes.

[0122] In the independent multiplication mode, the input data is first processed by the input register group S101, and the processing result is sent to the custom multiplier and the general multiplier. If it is a simple multiplication mode, the custom multiplier is configured as a multiplication function, and the result is directly output later. It can support 2 18-bit signed multiplications, 3 12-bit signed multiplications or 4 9-bit signed multiplications. If the multi-input addition mode is supported, the custom multiplier is configured as a multi-input addition mode. The custom multiplier S102 inputs the output data from the input register group, 8 18-bit signed data, and the MAB output result is the result of the addition operation of eight operands. Finally, the result can be directly output or registered for output.

[0123] In the double multiplication-addition mode, the input data is first processed by the input register group S101, and the processing results are sent to the first general multiplier S103a and the custom multiplier S102. The operation results of the above two multipliers are sent to the general adder S104a to obtain the result. The operation results of the second general multiplier S103b and the third general multiplier S103c are sent to the general adder S104b to obtain the result. Then the two results can be directly output or registered for output.

[0124] In the four-multiply-add mode, the results of the four multipliers are added and output. The output result of the first general multiplier S103a and the output result of the custom multiplier S102 are added by the general adder S104a to obtain the output. The output result of the second general multiplier S103b and the output result of the third general multiplier S103c are added by the general adder S104b to obtain the output, and finally the results of the two adders are sent to the adder / accumulator S106 for calculation. The result of the calculation can be used to choose whether to continue the chain addition operation. Finally, the result is directly output or stored for output.

[0125] In the multiplication-accumulation mode, single multiplier multiplication-accumulation, two multipliers multiplication-accumulation, three multipliers multiplication-accumulation, four multipliers multiplication-accumulation and multi-input addition-accumulation can be realized. In the first four functions, the custom multiplier S102 is configured as a multiplier. In the fifth function, the custom multiplier S102 is configured in a multi-input addition mode, and 8 18-bit signed numbers are added each time under the clock drive. The result of the adder / accumulator S106 can also choose whether to continue the chain addition operation. Finally, the result is directly output or stored for output.

[0126] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0127] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0128] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0130] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A digital signal processor that can directly support multi-operand addition operations, characterized in that: include: An input register group (S101), used for processing input data; A custom multiplier (S102), whose input terminal is connected to the output terminal of the input register group (S101), is used to implement a multiplication operation or a multi-operand addition operation; A first universal multiplier (S103a), whose input terminal is connected to the output terminal of the input register group (S101), is used to implement a multiplication operation; A second general multiplier (S103b), whose input terminal is connected to the output terminal of the input register group (S101), is used to implement a multiplication operation; A third general multiplier (S103c), whose input terminal is connected to the output terminal of the input register group (S101), is used to implement a multiplication operation; A first adder (S104a), whose input end is connected to the output end of the first general multiplier (S103a) and the output end of the custom multiplier (S102), for implementing an addition operation; A second adder (S104b), whose input end is connected to the output end of the second general multiplier (S103b) and the output end of the third general multiplier (S103c), for implementing an addition operation; An addition output register (S105), whose input end is connected to the output end of the first adder (S104a) and the output end of the second adder (S104b), and is used to process the output data; An adder / accumulator (S106), whose input end is connected to the output end of the adder output register (S105), and is used to accumulate data output by the adder output register (S105); A chain adder (S107), whose input end is connected to the output end of the adder / accumulator (S106), for implementing chain addition; The output register (S108) has an input end connected to the output end of the chain adder (S107) and is used to process the output data.

2. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 1, characterized in that: The input register group (S101) comprises a first multiplexer, a delay register and a second multiplexer which are connected in sequence.

3. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 2, characterized in that: The first multiplexer and the second multiplexer are both 2-to-1 multiplexers.

4. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 1, characterized in that: The customized multiplier (S102) comprises: Data preprocessing module (S201): used to preprocess the data output by the input register group (S101); Improved Booth encoding module (S202): used for performing Booth encoding on the data output by the input register group (S101) to generate partial products; A data post-processing module (S203) is connected to the output end of the improved Booth encoding module (S202) and is used to post-process the data output by the improved Booth encoding module (S202); A data selector (S204): connected to the output end of the data pre-processing module (S201) and the output end of the data post-processing module (S203), and used to select the output result of the data pre-processing module (S201) and the output result of the data post-processing module (S203); The compression tree reduction simple element (S205) is connected to the output end of the data selector (S204) and is used to compress the partial product array output by the data selector (S204) to obtain the final result.

5. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 4, characterized in that: The improved Booth encoding module (S202) includes an intermediate result generation module and a final result generation module, wherein the intermediate result generation module includes an XOR gate U1, an XOR gate U2, an XOR gate U3 and a NAND gate U4 arranged in parallel, and an AND gate U5 connected to the output end of the NAND gate U4; the final result generation module includes an XOR gate U6 and an XOR gate U7 arranged in parallel, an AND gate U8, an AND gate U9 and an AND gate U10 arranged in parallel, and a NOR gate U11 connected to the output ends of the AND gates U8, U9 and U10; the output end of the XOR gate U6 is connected to the input end of the AND gate U8, and the output end of the XOR gate U7 is connected to the input end of the AND gate U10.

6. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 4, characterized in that: The data post-processing module (S203) comprises a first data post-processing unit for optimizing the sign bit of each partial product and a second data post-processing unit for implementing an 8-input addition operation; The calculation formula used by the first data post-processing unit to optimize the sign bit of each partial product is: Among them, S represents the binary number 0 or 1, the subscript numbers 0 to 8 of S represent the weight, that is, the position of the binary number S; n is the exponent of the number 2; Simplifying formula (F1) we get: Among them, i is the weight, which is the position of the binary number S; The second data post-processing unit performs a zero padding operation on each row of low-order data.

7. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 6, characterized in that: When the data preprocessing module (S201) preprocesses the data output by the input register group (S101), the data output by the input register group (S101) is sign-bit extended to obtain the same data bit width as the data output by the data post-processing module (S203).

8. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 4, characterized in that: When the compression tree approximation simple element (S205) compresses the partial product array output by the data selector (S204), a five-level compression method is adopted, wherein the first-level compression and the second-level compression are compressed by a combination of a 3-2 compressor, a 4-2 compressor and a 5-2 compressor; the third-level compression is compressed by a 3-2 compressor, the fourth-level compression is the result of the third-level compression, and the fifth-level compression is a zero-padding process.

9. A digital signal processor capable of directly supporting multi-operand addition operations according to claim 8, characterized in that: The calculation formula of the 3-2 compressor (S500a) is: X1+X2+X3=sum+2*(carry) (F3) Wherein, X1, X2 and X3 are three data received by the 3-2 compressor (S500a), and the weights of X1, X2 and X3 are the same; sum is the sum value calculated by the 3-2 compressor (S500a), and the weight of sum is the same as the weights of X1, X2 and X3; carry is the carry calculated by the 3-2 compressor (S500a), and the weight of carry is one digit higher than the weight of sum; The calculation formula of the 4-2 compressor (S500b) is: cin+X1+X2+X3+X4=sum+2*(cout+carry) (F4) Wherein, cin, X1, X2, X3 and X4 are 5 data received by the 4-2 compressor (S500b), the weights of cin, X1, X2, X3 and X4 are the same, and cin is the carry digit; sum is the sum value calculated by the 4-2 compressor (S500b), and the weight of sum is the same as the weights of cin, X1, X2, X3 and X4; cout and carry are both the carry digits calculated by the 4-2 compressor (S500b), and the weights of cout and carry are both one digit higher than the weight of sum; The calculation formula of the 5-2 compressor (S500c) is: c1_in+c1_in+X1+X2+X3+X4+X5=sum+2*(c1_out+c2_out+carry) (F5) Among them, c1_in, c1_in, X1, X2, X3, X4 and X5 are 7 data received by the 5-2 compressor (S500c), the weights of c1_in, c1_in, X1, X2, X3, X4 and X5 are the same, and c1_in and c1_in are both carry digits; sum is the sum value calculated by the 5-2 compressor (S500c), and the weight of sum is the same as the weight of c1_in, c1_in, X1, X2, X3, X4 and X5; c1_out, c2_out and carry are all carries calculated by the 5-2 compressor (S500c), and the weights of c1_out, c2_out and carry are one digit higher than the weight of sum.

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