A method for preparing an active region structure, a semiconductor structure and a semiconductor memory

Abstract

The present application provides a method for preparing an active area structure, a semiconductor structure and a semiconductor memory, the method comprising: providing a substrate; forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure comprising an active line; depositing a first barrier layer on the initial semiconductor structure; etching the first barrier layer to form a first groove extending along a first direction; etching the first barrier layer to form a second groove extending along a second direction; forming an etched hole in the overlapping area of ​​the first groove and the second groove, the depth of the etched hole being greater than the depth of the first groove and the second groove; etching the active line using the etched hole as a mask to form a discrete active area mask. The present application can improve the uniformity of the local critical dimension of the active area and improve the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing an active area structure, a semiconductor structure and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technology, the characteristic dimensions of semiconductor devices in integrated circuits, including the critical dimension (CD) of the active area, are constantly shrinking.

[0003] It is often difficult to make the active area uniformly distributed when manufacturing an active area with a smaller critical dimension. As a result, its local critical dimension uniformity (LCDU) is too low, which will have an adverse effect on the electrical performance of the semiconductor device. Summary of the invention

[0004] The embodiments of the present application are intended to provide a method for preparing an active area structure, a semiconductor structure and a semiconductor memory, which can increase the LCDU of the active area, thereby improving the electrical performance of the semiconductor device.

[0005] The technical solution of this application is implemented as follows:

[0006] The present application provides a method for preparing an active region structure, the method comprising:

[0007] providing a substrate;

[0008] forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure comprises an active line;

[0009] depositing a first barrier layer on the initial semiconductor structure;

[0010] Etching the first barrier layer to form a first trench extending along a first direction;

[0011] Etching the first barrier layer to form a second groove extending along a second direction; forming an etched hole in an overlapping area of ​​the first groove and the second groove, wherein the depth of the etched hole is greater than the depth of the first groove and the second groove;

[0012] The active line is etched using the etched hole as a mask to form a separate active area mask.

[0013] An embodiment of the present application further provides a semiconductor structure, which includes an active area structure; the active area structure is prepared by the preparation method in the above scheme.

[0014] An embodiment of the present application also provides a semiconductor memory, comprising the semiconductor structure in the above solution.

[0015] It can be seen that the embodiments of the present application provide a method for preparing an active area structure, a semiconductor structure and a semiconductor memory, which can form an initial semiconductor structure including an active line on the surface of a substrate; then, a first barrier layer is deposited on the initial semiconductor structure; then, the first barrier layer is etched to sequentially form a first groove extending along a first direction and a second groove extending along a second direction, wherein an etched hole is formed in the overlapping area of ​​the first groove and the second groove, and the depth of the etched hole is greater than the depth of the first groove and the second groove; then, the active line is etched using the etched hole as a mask to form a discrete active area mask. Due to the diffraction effect of light, the accuracy of the mask is limited, and the LCDU of the active area formed by the traditional process is relatively low. The embodiments of the present application form the active area mask through a new process method, avoiding the structural problems caused by unclear mask imaging in the traditional process, thereby being able to improve the LCDU of the active area and improve the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A process for preparing an active area structure provided in an embodiment of the present application Figure 1 ;

[0017] Figure 2A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 1 ;

[0018] Figure 2B Schematic diagram 2 of a method for preparing an active area structure provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 ;

[0020] Figure 4A Schematic diagram 4 of a method for preparing an active region structure provided in an embodiment of the present application;

[0021] Figure 4B Schematic diagram 5 of a method for preparing an active region structure provided in an embodiment of the present application;

[0022] Figure 5A Schematic diagram 6 of a method for preparing an active region structure provided in an embodiment of the present application;

[0023] Figure 5B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 7 ;

[0024] Fig. 6A Schematic diagram 8 of a method for preparing an active region structure provided in an embodiment of the present application;

[0025] Figure 6B Schematic diagram 9 of a method for preparing an active region structure provided in an embodiment of the present application;

[0026] Figure 7 Flow chart 2 of a method for preparing an active area structure provided in an embodiment of the present application;

[0027] Fig. 8A Schematic diagram 10 of a method for preparing an active region structure provided in an embodiment of the present application;

[0028] Figure 8B Schematic diagram 11 of a method for preparing an active region structure provided in an embodiment of the present application;

[0029] Fig.9A Schematic diagram 12 of a method for preparing an active region structure provided in an embodiment of the present application;

[0030] Fig. 9B Schematic diagram 13 of a method for preparing an active region structure provided in an embodiment of the present application;

[0031] Fig. 10A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 14 ;

[0032] Fig. 10B Schematic diagram 15 of a method for preparing an active region structure provided in an embodiment of the present application;

[0033] Fig.11A Schematic diagram 16 of a method for preparing an active region structure provided in an embodiment of the present application;

[0034] Fig. 11B Schematic diagram seventeen of a method for preparing an active region structure provided in an embodiment of the present application;

[0035] Fig. 12A Schematic diagram 18 of a method for preparing an active region structure provided in an embodiment of the present application;

[0036] Fig. 12B Schematic diagram 19 of a method for preparing an active region structure provided in an embodiment of the present application;

[0037] Fig.13A Schematic diagram 20 of a method for preparing an active region structure provided in an embodiment of the present application;

[0038] Fig. 13B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 21 ;

[0039] Fig.14A process for preparing an active area structure provided in an embodiment of the present application Figure 3 ;

[0040] Fig.15A Schematic diagram 22 of a method for preparing an active region structure provided in an embodiment of the present application;

[0041] Fig. 15B Schematic diagram 23 of a method for preparing an active region structure provided in an embodiment of the present application;

[0042] Fig.16A Schematic diagram 24 of a method for preparing an active region structure provided in an embodiment of the present application;

[0043] Fig. 16B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 25 ;

[0044] Fig.17A Schematic diagram 26 of a method for preparing an active region structure provided in an embodiment of the present application;

[0045] Fig. 17B Schematic diagram 27 of a method for preparing an active region structure provided in an embodiment of the present application;

[0046] Fig.18A Schematic diagram 28 of a method for preparing an active region structure provided in an embodiment of the present application;

[0047] Fig.18B Schematic diagram 29 of a method for preparing an active area structure provided in an embodiment of the present application;

[0048] Fig.19A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 ten;

[0049] Fig.19B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 eleven;

[0050] Fig. 20A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 twelve;

[0051] Fig. 20B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 Thirteen;

[0052] Fig.21 Flow chart 4 of a method for preparing an active area structure provided in an embodiment of the present application;

[0053] Fig.22A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 fourteen;

[0054] Fig. 22B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 fifteen;

[0055] Fig.23A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 sixteen;

[0056] Fig. 23B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 XVII;

[0057] Fig.24A A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 eighteen;

[0058] Fig. 24B A schematic diagram of a method for preparing an active region structure provided in an embodiment of the present application Figure 3 nineteen;

[0059] Fig.25 A schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0061] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0062] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0064] Dynamic Random Access Memory (DRAM) is a semiconductor element commonly used in electronic devices such as computers. It is composed of multiple storage units, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0065] In semiconductor components such as DRAM, there are multiple active areas arranged in an array. However, with the miniaturization of semiconductor device structures, especially in the manufacturing process of DRAM with a critical dimension less than 15nm, the size of the active area becomes smaller, and the traditional double lithography patterning (lithography etch, LELE) solution has certain limitations and cannot meet the process requirements.

[0066] Figure 1 is an optional flow chart of the method for preparing the active region structure provided in the embodiment of the present application, which will be combined with Figure 1 The steps shown are explained.

[0067] S101, forming an initial semiconductor structure on a substrate surface; the initial semiconductor structure includes an active line.

[0068] In an embodiment of the present application, a semiconductor device can form an initial semiconductor structure on a surface of a substrate, wherein the initial semiconductor structure includes an active line. Figure 2A and Figure 2B The initial semiconductor structure is shown in front cross-sectional view and top view, respectively. Figure 2A and Figure 2B As shown, a plurality of active lines 101 arranged in parallel are formed on a substrate 10. The material of the substrate may be single crystal silicon, and the material of the active lines 101 may be polycrystalline silicon.

[0069] In the embodiment of the present application, the semiconductor device can first form an initial mandrel with a wide interval by a photolithography process, and the initial mask layer is formed along the Figure 2BThe initial sidewalls are formed on both sides of the initial mandrel and then etched to form active lines 101. Since the initial sidewalls are formed in the spacing area of ​​the initial mandrels and the spacing between the initial mandrels is smaller than the spacing between the initial mandrels, the size of the active lines formed by etching is smaller than the size of the initial mandrels, that is, a smaller active line is formed by using a larger mask.

[0070] It should be noted that, since the width and spacing of the active lines 101 formed in the embodiment of the present application are very small, it is difficult to ensure the LCDU of the active area finally formed by adopting the traditional solution.

[0071] S102 , depositing a first barrier layer on the initial semiconductor structure.

[0072] In the embodiment of the present application, the semiconductor device can deposit a first barrier layer on the initial semiconductor structure to prepare for subsequent processes. It should be noted that the barrier layer is used to form a pattern transferred downward as required and to protect areas that do not need to be etched during etching.

[0073] Figure 3 A front cross-sectional view of the first barrier layer is shown as an example. Figure 3 As shown, the first barrier layer 20 is deposited on the substrate 10 and covers the active line 101. The first barrier layer 20 may include a first silicon oxynitride (SiON) layer 201 and a first spin-on hard mask (SOH) layer 202.

[0074] S103 , etching the first barrier layer to form a first trench extending along a first direction.

[0075] In the embodiment of the present application, the semiconductor device can be etched on the first barrier layer to form a first trench extending along a first direction. Figure 4A and Figure 4B The first groove is shown in the example, which is a front cross-sectional view and a top view, respectively. Figure 4A and Figure 4B As shown, a first trench 2011 is formed on the first silicon oxynitride layer 201, and the depth of the first trench 2011 is less than the thickness of the first silicon oxynitride layer 201; the first direction D1 along which the first trench 2011 is formed is Figure 4B Shows that Figure 4B The direction of the oblique lines on the silicon oxynitride layer 201.

[0076] In the embodiment of the present application, the semiconductor device can first form a first mandrel with a wider interval by a photolithography process, such as Fig.9A and Fig. 9B As shown, the first mandrel 401 extends along the first direction D1. Then, first sidewalls may be formed on both sides of the first mandrel, such as Fig.11A and Fig. 11B As shown, the first sidewall 403 covers both sides of the first mandrel 401, and the first sidewall 403 also extends along the first direction D1. Finally, the first sidewall is used as a mask to form a first groove 2011 by etching. Since the first sidewall 403 is formed in the spacing area of ​​the first mandrel 401, the spacing between the first sidewalls is smaller than the spacing between the first mandrels 401, and therefore, the size of the first groove 2011 formed by etching is smaller than the size of the first mandrel 401, that is, a first groove of smaller size is formed by using a mask of larger size.

[0077] S104, etching the first barrier layer to form a second groove extending along the second direction; forming an etched hole in the overlapping area of ​​the first groove and the second groove, and the depth of the etched hole is greater than the depth of the first groove and the second groove.

[0078] In the embodiment of the present application, the semiconductor device can be etched on the first barrier layer to form a second trench extending along the second direction, wherein an etched hole is formed in the overlapping area of ​​the first trench and the second trench, and the depth of the etched hole is greater than the depth of the first trench and the second trench. Figure 5A and Figure 5B The second trench and the etched hole are shown as an example, which are a front cross-sectional view and a top view, respectively. Figure 5A and Figure 5B As shown, a second groove 2012 is formed on the first silicon oxynitride layer 201. The first groove 2011 extends along the first direction D1, and the second groove 2012 extends along the second direction D2. The overlapping area of ​​the first groove 2011 and the second groove 2012 forms a diamond-shaped etching hole 2013 (i.e. Figure 5B The depth of the etched hole 2013 is greater than the depth of the first trench 2011 and the second trench 2012.

[0079] In the embodiment of the present application, the semiconductor device can first form a second mandrel with a wider interval by a photolithography process, such as Fig.16A and Fig. 16B As shown, the second mandrel 701 extends along the second direction D2. Then, second sidewalls may be formed on both sides of the second mandrel, such as Fig.18A and Fig.18B As shown, the second sidewall 703 covers both sides of the second mandrel 701, and the second sidewall 703 also extends along the second direction D2. Finally, the second sidewall is used as a mask to form a second groove 2012 by etching. Since the second sidewall 703 is formed in the spacing area of ​​the second mandrel 701, the spacing between the second sidewalls is smaller than the spacing between the second mandrels 701. Therefore, the size of the second groove 2012 formed by etching is smaller than the size of the second mandrel 701, that is, a second groove of smaller size is formed by using a mask of larger size.

[0080] S105 , using the etched hole as a mask, etching the active line to form a discrete active area mask.

[0081] In the embodiment of the present application, the semiconductor device can use the etched hole as a mask to etch the active line to form a separate active area mask. It should be noted that etching with a certain structure as a mask is to transfer the pattern of the structure to the structure below it.

[0082] In the embodiment of the present application, the position of the etched hole corresponds to the cut-off point on the active line. Since the etched hole is concave downward and the depth of the concave hole is greater than other areas, the cut-off point on the active line will be etched first during etching, and other areas on the active line are protected by the covered mask, so that the active line can be cut off at the cut-off point, thereby forming a discrete active area mask.

[0083] Fig. 6A and Figure 6B The example shows the separate active area mask, which is a front view cross-sectional view and a top view, combined with Figure 2A , Figure 2B , Fig. 6A and Figure 6B , Figure 2A and Figure 2B The active line 101 in Figure 6B After each cut-off point 103 in is cut off, a Fig. 6A and Figure 6B The active area mask 102 is separated in the middle.

[0084] It can be understood that the embodiment of the present application first forms a plurality of active lines arranged in parallel; then, a first barrier layer is deposited on the active line, and a first groove and a second groove are etched on the surface of the first barrier layer to form an etched hole; finally, along the position of the etched hole, the active line is cut off to form a discrete active area mask. In this way, the active area is formed by a new process method, avoiding the structural problems caused by unclear mask imaging in the traditional process, thereby improving the LCDU of the active area and improving the electrical performance of the semiconductor device.

[0085] In some embodiments of the present application, Figure 7 S201 to S204 shown are implemented Figure 1 S103 shown will be described in conjunction with each step.

[0086] S201 , sequentially depositing a second barrier layer and a third barrier layer on the first barrier layer.

[0087] In the embodiment of the present application, the semiconductor device can deposit a second barrier layer and a third barrier layer on the first barrier layer in sequence. It should be noted that the barrier layer is used to form a pattern that is transferred downward as needed, and to protect areas that do not need to be etched during etching. Fig. 8AAs shown, the second barrier layer 30 and the third barrier layer 40 are sequentially deposited on the first barrier layer 20. The materials of the second barrier layer 30 and the third barrier layer 40 may include: SiON and SOH.

[0088] S202, etching the third barrier layer to form first mandrels extending along a first direction; the first mandrels are arranged at intervals.

[0089] In the embodiment of the present application, the semiconductor device can etch the third barrier layer to form first mandrels extending along the first direction, wherein the first mandrels are arranged at intervals.

[0090] In the embodiments of the present application, Fig. 8A and Figure 8B As shown, the semiconductor device can first form a first mask 50 on the third barrier layer 40 by a photolithography process, and the shape of the first mask 50 is characterized by a first etching pattern extending along the first direction D1. Then, the semiconductor device can etch the third barrier layer 40 along the first etching pattern to form Fig.9A and Fig. 9B The first mandrels 401 are shown in FIG. The first mandrels 401 extend along the first direction D1 and are arranged at intervals.

[0091] S203 , covering the side surface of the first mandrel to form a first side wall.

[0092] In the embodiment of the present application, the semiconductor device can cover the side surface of the first core axis to form a first sidewall.

[0093] In the embodiments of the present application, Fig. 10A and Fig. 10B As shown, the semiconductor device may first use an ALD (Atomic Layer Deposition) process to deposit a first hard mask layer 402 to cover the second barrier layer 30 and the first mandrel 401. Then, the semiconductor device may perform back etching on the first hard mask layer 402, remove the top of the first hard mask layer 402 until the first mandrel 401 is exposed, and retain the side of the first hard mask layer 402 as the first spacer 403, as shown in FIG. Fig.11A and Fig. 11B The first sidewall 403 also extends along the first direction D1.

[0094] S204, performing etching using the first sidewall as a mask to remove the second barrier layer, and etching the first barrier layer to form a first trench extending along the first direction.

[0095] In the embodiment of the present application, the semiconductor device can be etched using the first sidewall as a mask to remove the second barrier layer, and the first barrier layer can be etched to form a first trench extending along the first direction.

[0096] In the examples of this application, refer to Fig.11A and Fig. 11B , the first mandrel 401 remains in the middle of the first sidewall 403. The semiconductor device can first be etched using a high selectivity etching rate to remove the first mandrel 401 remaining in the middle of the first sidewall 403. Here, the high selectivity means that the etching rate of the material of the first mandrel 401 is much greater than the etching rate of other materials. The obtained structure is as follows Fig. 12A and Fig. 12B Then, combined with Fig. 12A and Fig.13A The semiconductor device can use the first sidewall 403 as a mask to etch the second barrier layer 30 to form a Fig.13A The first intermediate structure 301 is shown. Fig. 13B As shown, the first intermediate structure 301 and the first side wall 403 also extend along the first direction D1. Fig.13A and Figure 4A The semiconductor device can use the first intermediate structure 301 as a mask to etch the first barrier layer 20, remove the first intermediate structure 301, and etch a Figure 4A The first groove 201 in the embodiment of the present invention.

[0097] It can be understood that, in the embodiment of the present application, after the second barrier layer 30 and the third barrier layer 40 are deposited, the semiconductor device first forms the first mask 50 through a photolithography process, and etches along the first mask 50 to form the first mandrel 401; then, the first sidewall 403 is formed to cover the side of the first mandrel 401; finally, the first sidewall 403 is used as a mask to form the first trench 2011 through etching. Since the first sidewall 403 is formed in the spacing area of ​​the first mandrel 401, the spacing between the first mandrels 401 is smaller than the spacing between the first mandrels 401. Therefore, the width of the first trench 2011 formed by using the first sidewall 403 as a mask is smaller than the spacing between the first mandrels 401. In this way, even if the photolithography process limits the critical size that can be achieved, the first trench 2011 with a smaller critical size can be formed with the help of the first mandrel 401, thereby expanding the process size limit that the semiconductor device can achieve.

[0098] In some embodiments of the present application, S2021 to S2022 can be used to implement Figure 7 S202 shown will be described in conjunction with each step.

[0099] S2021, forming a first mask on the third barrier layer; the first mask includes a first etching pattern extending along a first direction.

[0100] In an embodiment of the present application, the semiconductor device may first form a first mask on the third barrier layer; wherein the first mask may be obtained by a photolithography process and includes a first etching pattern extending along a first direction. Fig. 8A and Figure 8B The first mask is shown in the example, which is a front cross-sectional view and a top view, respectively. Fig. 8A and Figure 8B As shown, a first mask 50 is formed on the third barrier layer 40 , and a first etching pattern of the first mask 50 extends along a first direction D1 .

[0101] S2022, etching the third barrier layer along the first etching pattern to form a first core axis extending along the first direction.

[0102] In the embodiment of the present application, after forming the first mask 50, the semiconductor device can etch the third barrier layer 40 along the first etching pattern to form Fig.9A and Fig. 9B The first mandrels 401 are shown in FIG. 4 ; the first mandrels 401 also extend along the first direction D1 and are arranged at intervals.

[0103] In some embodiments of the present application, S2031 to S2032 can be used to implement Figure 7 S203 shown will be explained in combination with each step.

[0104] S2031, depositing a first hard mask layer; the first hard mask layer covers the second barrier layer and the first mandrel.

[0105] In the present application embodiment, Fig. 10A and Fig. 10B As shown, the semiconductor device may firstly adopt an ALD process to deposit a first hard mask layer 402 to cover the second barrier layer 30 and the first mandrel 401 .

[0106] S2032, etching back the first hard mask layer, removing the top of the first hard mask layer until the first mandrel is exposed, and retaining the side of the first hard mask layer as a first spacer.

[0107] In the embodiment of the present application, after the first hard mask layer 402 is deposited, the semiconductor device can perform back etching on the first hard mask layer 402 to remove the top of the first hard mask layer 402 until the first mandrel 401 is exposed, and the side of the first hard mask layer 402 is retained as the first spacer 403, such as Fig.11A and Fig. 11B shown.

[0108] In some embodiments of the present application, S2041 to S2043 can be used to implement Figure 7 S204 shown will be described in conjunction with each step.

[0109] S2041, removing the first mandrel in the middle of the first side wall.

[0110] In the present application examples, reference Fig.11A and Fig. 11B, the first mandrel 401 remains in the middle of the first sidewall 403. The semiconductor device can first be etched using an etching rate with a high selectivity ratio to remove the first mandrel 401 remaining in the middle of the first sidewall 403, and the resulting structure is as follows: Fig. 12A and Fig. 12B shown.

[0111] S2042, using the first sidewall as a mask, etching the second barrier layer to form a first intermediate structure.

[0112] In the present application embodiment, combined Fig. 12A and Fig.13A After the semiconductor device removes the first mandrel 401 remaining in the middle of the first sidewall 403, the second barrier layer 30 can be etched using the first sidewall 403 as a mask to form a semiconductor device such as Fig.13A The first intermediate structure 301 is shown. Fig. 13B As shown, the first intermediate structure 301 extends along the first direction D1.

[0113] S2043 , using the first intermediate structure as a mask, etching the first barrier layer to form a first trench extending along a first direction.

[0114] In the present application embodiment, combined Fig.13A and Figure 4A , semiconductor devices form Fig.13A After the first intermediate structure 301 is formed, the first barrier layer 20 can be etched using the first intermediate structure 301 as a mask to form Figure 4A A first trench 201 is shown; the first trench 201 extends along a first direction D1.

[0115] In some embodiments of the present application, Fig.14 S301 to S304 shown are implemented Figure 1 S104 shown will be described in conjunction with each step.

[0116] S301 , depositing a fourth barrier layer and a fifth barrier layer in sequence on the first barrier layer; the fourth barrier layer covers the first trench.

[0117] In the embodiment of the present application, after forming the first trench, the semiconductor device can sequentially deposit a fourth barrier layer and a fifth barrier layer on the first barrier layer. It should be noted that the barrier layer is used to form a pattern that is transferred downward as needed, and to protect areas that do not need to be etched during etching. Fig.15A As shown, a fourth barrier layer 60 and a fifth barrier layer 70 are sequentially deposited on the first barrier layer 20, and the fourth barrier layer 60 covers the first trench 2011. The materials of the fourth barrier layer 60 and the fifth barrier layer 70 include: SiON and SOH.

[0118] S302, etching the fifth barrier layer to form second mandrels extending along the second direction; the second mandrels are arranged at intervals.

[0119] In the embodiment of the present application, the semiconductor device can etch the fifth barrier layer to form second mandrels extending along the second direction, wherein the second mandrels are arranged at intervals.

[0120] In the embodiments of the present application, Fig.15A and Fig. 15B As shown, the semiconductor device can first form a second mask 80 on the fifth barrier layer 70 by a photolithography process, and the shape of the second mask 80 is characterized by a second etching pattern extending along the second direction D2. Then, the semiconductor device can etch the fifth barrier layer 70 along the second etching pattern to form Fig.16A and Fig. 16B The second mandrels 701 are shown in FIG. 7 ; the second mandrels 701 extend along the second direction D2 and are arranged at intervals.

[0121] S303 , covering the side surface of the second mandrel to form a second sidewall.

[0122] In the embodiment of the present application, the semiconductor device can cover the side surface of the second core axis to form a second sidewall.

[0123] In the embodiments of the present application, Fig.17A and Fig. 17B As shown, the semiconductor device may first deposit the second hard mask layer 702 by using the ALD process to cover the fourth barrier layer 60 and the second mandrel 701. Then, the semiconductor device may perform back etching on the second hard mask layer 702, remove the top of the second hard mask layer 702 until the second mandrel 701 is exposed, and retain the side of the second hard mask layer 702 as the second spacer 703, as shown in FIG. Fig.18A and Fig.18B The second sidewall 703 also extends along the second direction D2.

[0124] S304, performing etching using the second sidewall spacer as a mask to remove the fourth barrier layer, and etching the first barrier layer to form a second trench extending along the second direction.

[0125] In the embodiment of the present application, the semiconductor device can be etched using the second sidewall as a mask to remove the fourth barrier layer, and the first barrier layer can be etched to form a second trench extending along the second direction.

[0126] In the examples of this application, refer to Fig.18A and Fig.18B , a second mandrel 701 remains in the middle of the second spacer 703. The semiconductor device can first remove the second mandrel 701 remaining in the middle of the second spacer 703, and the obtained structure is as follows Fig.19A and Fig.19B Then, combined with Fig.19A and Fig. 20A The semiconductor device can use the second sidewall 703 as a mask to etch the fourth barrier layer 60 to form a Fig. 20A The second intermediate structure 601 is shown. Fig. 20B As shown, the second intermediate structure 601 and the second side wall 703 also extend along the second direction D2. Fig. 20A and Figure 5A The semiconductor device can use the second intermediate structure 601 as a mask to etch the first barrier layer 20, remove the second intermediate structure 601, and etch a Figure 5A The first groove 2011 and the second groove 2012 overlap to form an etched hole 2013 (i.e. Figure 5B darker part).

[0127] It should be noted that by adjusting the etching rate ratio according to the materials of the first barrier layer 20 and the fourth barrier layer 60 , the depth of the etched hole 2013 can be made greater than the depths of the first trench 2011 and the second trench 2012 .

[0128] It can be understood that, in the embodiment of the present application, after the semiconductor device deposits the fourth barrier layer 60 and the fifth barrier layer 70, the second mask 80 is first formed by a photolithography process, and the second mandrel 701 is formed by etching along the second mask 80; then, the second sidewall 703 is formed to cover the side of the second mandrel 701; finally, the second sidewall 703 is used as a mask to form a second groove 2012, thereby forming an etched hole 2013. Since the second sidewall 703 is formed in the spacing area of ​​the second mandrel 701, the spacing between the second mandrels 701 is smaller than the spacing between the second mandrels 701. Therefore, the width of the second groove 2012 formed by the second sidewall 703 as a mask is smaller than the spacing between the second mandrels 701. In this way, even if the photolithography process limits the critical size that can be achieved, the second groove 2012 with a smaller critical size can be formed by means of the second mandrel 701, and then the etched hole 2013 that can meet the critical size requirements is formed, so as to accurately cut the active line.

[0129] In some embodiments of the present application, S3021 to S3022 can be used to implement Fig.14 S302 shown will be described in conjunction with each step.

[0130] S3021, forming a second mask on the fifth barrier layer, wherein the second mask includes a second etching pattern extending along a second direction.

[0131] In the present application embodiment, Fig.15A and Fig. 15BAs shown, the semiconductor device may first form a second mask 80 on the fifth barrier layer 70 through a photolithography process, and the shape of the second mask 80 is characterized by a second etching pattern extending along the second direction D2.

[0132] S3022, etching the fifth barrier layer along the second etching pattern to form a second mandrel extending along the second direction.

[0133] In the embodiment of the present application, after forming the second mask 80, the semiconductor device can etch the fifth barrier layer 70 along the second etching pattern to form Fig.16A and Fig. 16B The second mandrels 701 are shown in FIG. 7 ; the second mandrels 701 extend along the second direction D2 and are arranged at intervals.

[0134] In some embodiments of the present application, S3031 to S3032 can be used to implement Fig.14 S303 shown will be described in conjunction with each step.

[0135] S3031, depositing a second hard mask layer; the second hard mask layer covers the fourth barrier layer and the second mandrel.

[0136] In the present application embodiment, Fig.17A and Fig. 17B As shown, the semiconductor device may firstly use an ALD process to deposit a second hard mask layer 702 to cover the fourth barrier layer 60 and the second mandrel 701 .

[0137] S3032, etching back the second hard mask layer, removing the top of the second hard mask layer until the second mandrel is exposed, and retaining the side of the second hard mask layer as a second spacer.

[0138] In the embodiment of the present application, after the second hard mask layer 702 is deposited, the semiconductor device can perform back etching on the second hard mask layer 702, remove the top of the second hard mask layer 702 until the second mandrel 701 is exposed, and retain the side of the second hard mask layer 702 as the second spacer 703, such as Fig.18A and Fig.18B The second sidewall 703 also extends along the second direction D2.

[0139] In some embodiments of the present application, S3041 to S3043 can be used to implement Fig.14 S304 shown will be described in conjunction with each step.

[0140] S3041, remove the second mandrel in the middle of the second side wall.

[0141] In the embodiment of the present application, the semiconductor device can first remove the second mandrel 701 remaining in the middle of the second sidewall 703, and the obtained structure is as follows: Fig.19A and Fig.19B shown.

[0142] S3042, using the second sidewall as a mask, etching the fourth barrier layer to form a second intermediate structure.

[0143] In the embodiment of the present application, after removing the second mandrel 701 remaining in the middle of the second sidewall 703, the semiconductor device can use the second sidewall 703 as a mask to etch the fourth barrier layer 60 to form a semiconductor device such as Fig. 20A and Fig. 20B The second intermediate structure 601 shown in the figure, the second intermediate structure 601 and the second side wall 703 also extend along the second direction D2.

[0144] S3043, using the second intermediate structure as a mask, etching the first barrier layer to form a second trench extending along a second direction.

[0145] In the present application embodiment, combined Fig. 20A and Figure 5A After the second intermediate structure 601 is formed, the semiconductor device can use the second intermediate structure 601 as a mask to etch the first barrier layer 20 until a thin film is etched out on the surface of the first barrier layer 20. Figure 5A The second groove 2012 extends along the second direction D2. The overlapping area of ​​the first groove 2011 and the second groove 2012 forms an etched hole 2013 (i.e. Figure 5B darker part).

[0146] In some embodiments of the present application, Fig.21 S1051 to S1502 shown are implemented Figure 1 S105 shown will be described in conjunction with each step.

[0147] S1051, etching is performed using the etching hole as a mask until a cut-off point on the active line is reached; the cut-off point corresponds to a projection position of the etching hole.

[0148] In the present application embodiment, Fig.22A and Fig. 22B As shown, the semiconductor device can be etched using a higher etching selectivity ratio of the first spin-on hard mask 202 to the first silicon oxynitride 201, that is, the etching rate of the material of the first spin-on hard mask 202 is greater than the etching rate of the material of the first silicon oxynitride 201, so that only the projection position corresponding to the etching hole 2013 is penetrated until the cut-off point on the active line 101. The other areas on the active line 101 are still covered with the first spin-on hard mask 202 and the first silicon oxynitride 201, and are protected in subsequent etching.

[0149] S1052, etching the cut-off points to cut off the active lines and form separate active area masks.

[0150] In the present application embodiment, Fig.23A and Fig. 23B As shown, the semiconductor device can be replaced with an active line 101 that is etched at a higher etch selectivity than the first spin-coated hard mask 202, that is, the etch rate of the material of the active line 101 is greater than the etch rate of the material of the first spin-coated hard mask 202, so that the active line 101 is cut off at the cut-off point 103. Then, a high selectivity etching is performed on the first spin-coated hard mask 202, that is, the etch rate of the material of the first spin-coated hard mask 202 is much greater than the etch rate of other materials, and the remaining first spin-coated hard mask 202 is removed to form the following Fig. 6A and Figure 6B An active area mask 102 is shown.

[0151] It can be understood that by using the etching hole as a mask and selecting different etching rate ratios for etching, the active line can be accurately cut off at the cut-off point and the remaining first barrier layer can be removed without causing damage to other areas on the active line, thereby improving the LCDU of the active area mask formed.

[0152] In some embodiments of the present application, it is possible Figure 1 S105 shown in the figure further includes S106, which will be explained in combination with each step.

[0153] S106, etching the substrate along the active area mask to form an active area.

[0154] In the embodiment of the present application, after the active region mask is formed, the semiconductor device can etch the substrate along the active region mask, such as Fig.24A and 24B As shown, the pattern of the active area mask is transferred to the substrate 10 to form discrete active areas 104 .

[0155] It can be understood that the active area mask obtained by the preparation method provided in the above embodiment has a higher LCDU, and the active area etched along the active area mask also has a better LCDU.

[0156] The embodiment of the present application further provides a semiconductor structure 80, which includes an active area structure prepared by the preparation method provided by the aforementioned embodiment, thereby avoiding the structural problems caused by unclear mask imaging in the traditional process, and LCDU is higher.

[0157] The present application embodiment also provides a semiconductor memory 90, such as Fig.25 As shown, the semiconductor memory 90 at least includes a semiconductor structure 80 .

[0158] In some embodiments of the present application, Fig.25 The semiconductor memory 90 shown includes at least a dynamic random access memory DRAM.

[0159] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0160] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0161] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing an active area structure, characterized in that: The method comprises: providing a substrate; forming an initial semiconductor structure on the surface of the substrate; the initial semiconductor structure comprises an active line; depositing a first barrier layer on the initial semiconductor structure; Etching the first barrier layer to form a first trench extending along a first direction; Etching the first barrier layer to form a second groove extending along a second direction; forming an etched hole in an overlapping area of ​​the first groove and the second groove, wherein the depth of the etched hole is greater than the depth of the first groove and the second groove; The active line is etched using the etched hole as a mask to form a separate active area mask.

2. The preparation method according to claim 1, characterized in that: The etching of the first barrier layer to form a first trench extending along a first direction includes: sequentially depositing a second barrier layer and a third barrier layer on the first barrier layer; Etching the third barrier layer to form first mandrels extending along the first direction; the first mandrels are arranged at intervals; Covering the side surface of the first mandrel to form a first side wall; Etching is performed using the first sidewall as a mask to remove the second barrier layer, and the first barrier layer is etched to form the first groove extending along the first direction.

3. The preparation method according to claim 2, characterized in that: The etching of the third barrier layer to form a first mandrel extending along the first direction comprises: forming a first mask on the third barrier layer; the first mask comprising a first etching pattern extending along the first direction; The third barrier layer is etched along the first etch pattern to form the first mandrel extending along the first direction.

4. The preparation method according to claim 2, characterized in that: The side surface covering the first mandrel forms a first side wall, comprising: Depositing a first hard mask layer; the first hard mask layer covers the second barrier layer and the first mandrel; The first hard mask layer is etched back to remove the top of the first hard mask layer until the first mandrel is exposed, and the side of the first hard mask layer is retained as the first sidewall.

5. The preparation method according to claim 2, characterized in that: The etching is performed using the first sidewall as a mask to remove the second barrier layer, and the first barrier layer is etched to form the first groove extending along the first direction, comprising: removing the first mandrel in the middle of the first side wall; Using the first sidewall as a mask, etching the second barrier layer to form a first intermediate structure; The first barrier layer is etched using the first intermediate structure as a mask to form the first trench extending along the first direction.

6. The preparation method according to claim 1, characterized in that: The etching of the first barrier layer to form a second trench extending along a second direction includes: On the first barrier layer, a fourth barrier layer and a fifth barrier layer are sequentially deposited; the fourth barrier layer covers the first groove; Etching the fifth barrier layer to form second mandrels extending along the second direction; the second mandrels are arranged at intervals; Covering the side surface of the second mandrel to form a second side wall; Etching is performed using the second sidewall as a mask to remove the fourth barrier layer, and the first barrier layer is etched to form the second trench extending along the second direction.

7. The preparation method according to claim 6, characterized in that: The etching of the fifth barrier layer to form a second mandrel extending along the second direction comprises: forming a second mask on the fifth barrier layer, wherein the second mask comprises a second etching pattern extending along the second direction; The fifth barrier layer is etched along the second etch pattern to form the second mandrel extending along the second direction.

8. The preparation method according to claim 6, characterized in that: The side surface covering the second mandrel forms a second sidewall, comprising: Depositing a second hard mask layer; the second hard mask layer covers the fourth barrier layer and the second mandrel; The second hard mask layer is etched back to remove the top of the second hard mask layer until the second mandrel is exposed, and the side of the second hard mask layer is retained as the second sidewall.

9. The preparation method according to claim 6, characterized in that: The etching is performed using the second sidewall as a mask to remove the fourth barrier layer, and the first barrier layer is etched to form the second groove extending along the second direction, comprising: removing the second mandrel in the middle of the second side wall; Using the second sidewall as a mask, etching the fourth barrier layer to form a second intermediate structure; The first barrier layer is etched using the second intermediate structure as a mask to form the second trench extending along the second direction.

10. The preparation method according to claim 1, characterized in that: The method of etching the active line using the etching hole as a mask to form a discrete active area mask comprises: Using the etching hole as a mask, etching is performed until a cut-off point on the active line is reached; the cut-off point corresponds to a projection position of the etching hole; The cut-off points are etched to cut off the active lines, thereby forming separate active area masks.

11. The preparation method according to claim 1, characterized in that: After the active line is etched using the etched hole as a mask to form a separate active area mask, the method further comprises: The substrate is etched along the active area mask to form an active area.

12. The preparation method according to any one of claims 1 to 11, characterized in that: The shape of the etching hole is rhombus.

13. A semiconductor structure, characterized in that: The semiconductor structure includes an active region structure; The active area structure is prepared by the preparation method according to any one of claims 1 to 12.

14. A semiconductor memory, characterized in that: Comprising the semiconductor structure as claimed in claim 13.

15. The semiconductor memory according to claim 14, wherein: The semiconductor memory at least includes a dynamic random access memory DRAM.

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