A method and device for quickly invalidating address cache

Abstract

The present invention discloses a method and device for quickly invalidating an address cache. The method comprises: receiving an instruction sent to the address cache; when the current instruction sent to the address cache is an instruction for invalidating the address cache for an ASID, judging whether the previous instruction for invalidating the address cache for an ASID has been executed, and if it has not been executed, continuing to wait; otherwise, recording the value of the ASID in the instruction, and immediately returning a response that the current instruction has been completed; matching the value of the ASID in each table item of the address cache and the value of the recorded ASID item by item, and invalidating the matched table item. The present invention can continue to execute subsequent operations when invalidating the address cache table item of a specific ASID, improves the speed of invalidating the same ASID table item in the address cache, and reduces the waiting time of subsequent instructions.

Description

Technical Field

[0001] The invention relates to a microprocessor, and in particular to a method and a device for quickly invalidating an address cache. Background Art

[0002] In modern microprocessor design, mainstream CPUs support access to program instructions and data through virtual memory addresses. Therefore, address translation mechanisms are designed in mainstream processor architectures to convert virtual addresses into physical addresses for accessing data in interconnected networks. However, since the virtual address range is generally greater than 30 bits, address translation uses a multi-level access method. This results in a relatively large access delay to obtain address translation information.

[0003] In order to reduce access latency, modern CPUs have set up a two-level translation information buffer (Translation Lookaside Buffer, TLB). Among them, the second-level TLB will be set to more than 1,000 entries and implemented using RAM. In addition to storing virtual address and physical address information, each entry also stores address space descriptor (Address Space Identifier, ASID) information to distinguish the process to which the TLB entry belongs. Then, the entries corresponding to the virtual addresses and physical addresses of different processes can coexist in the TLB.

[0004] When you need to invalidate the address cache entry for a specific ASID, such as Figure 1 As shown in the figure, the traditional invalidation process is to match the ASID of each table item in the address cache one by one and perform the invalidation operation. No other operations can be performed during this invalidation operation. Subsequent query, backfill and invalidation operations must wait for the invalidation instruction to be completed before they can be executed. Since the address cache is implemented by RAM, the matching of ASID needs to be polled and invalidated one by one. The waiting time required to poll the entire RAM is long. During this period, subsequent operations cannot be performed, which will cause the program execution time to become longer, limiting the improvement of processor performance. Summary of the invention

[0005] The technical problem to be solved by the present invention is as follows: In view of the above-mentioned problems in the prior art, a method and device for quickly invalidating an address cache are provided. The present invention can continue to execute subsequent operations when invalidating an address cache entry of a specific ASID, thereby improving the speed of invalidating the same ASID entry in the address cache and reducing the waiting time for subsequent instructions.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A method for quickly invalidating an address cache, comprising:

[0008] 1) Receive instructions sent to the address cache;

[0009] 2) When the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID, determine whether the previous instruction for invalidating the address cache for ASID has been executed. If it has not been executed, wait and re-execute step 2); if it has been executed, jump to execute step 3);

[0010] 3) Record the value of ASID in the command and immediately return a response indicating that the current command has been completed;

[0011] 4) Match the ASID value in each table entry of the address cache and the ASID value of the record one by one, and invalidate the matching table entry.

[0012] Optionally, in step 2), determining whether the previous instruction for invalidating the address cache for ASID has been executed means determining whether the to-be-cleared bits of each table entry in the address cache are all 0. If all are 0, it means that the previous instruction for invalidating the address cache for ASID has been executed; step 3) also includes setting the to-be-cleared positions of all table entries to 1; step 4) also includes setting the to-be-cleared position of each table entry in the address cache to 0 when matching the ASID value and the recorded ASID value item by item.

[0013] Optionally, recording the value of the ASID in the instruction in step 3) refers to recording the value of the ASID in the instruction through a designated ASID register.

[0014] Optionally, in step 2), when the current instruction sent to the address cache is an instruction for a query operation, the following steps are performed:

[0015] A1) performing a query operation on all entries in the address cache to obtain a query result;

[0016] A2) determining whether the query result is a hit, if so, jumping to step A3), otherwise jumping to step A4);

[0017] A3) Match the value of the ASID in the hit table entry with the value of the ASID in the corresponding ASID register: if the two do not match, the hit table entry is determined to be a table entry to be invalidated and the query result is missing, the to-be-cleared position of the hit table entry is set to 0 and the valid position is set to 0, and the required information is further obtained by querying the page table, and the process ends and exits; if the two match, the hit table entry is determined to be a valid table entry, the cached data of the hit table entry is returned, and the to-be-cleared position of the hit table entry is set to 0, and the process ends and exits;

[0018] A4) further obtains the required information by confirming the page table query, ends and exits.

[0019] Optionally, in step 2), when the current instruction sent to the address cache is an instruction for a backfill operation, the execution steps are:

[0020] B1) Determine whether the backfill operation is a hit, if it is a hit, jump to step B2), otherwise report an error and exit;

[0021] B2) Set the position to be cleared in the hit table entry to 0 and the valid position to 1, and then end and exit.

[0022] Optionally, before step 1), the step of caching and scheduling instructions to the address cache through an instruction queue is also included.

[0023] In addition, the present invention also provides a device for quickly invalidating address cache, comprising:

[0024] Instruction queue, used to cache and schedule instructions sent to the address cache;

[0025] An instruction judgment module is used to judge whether the previous instruction for invalidating the address cache for ASID has been executed when the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID. If it has not been executed, wait and re-execute the instruction judgment module; if it has been executed, jump to execute the ASID recording module;

[0026] The ASID recording module is used to record the value of the ASID in the instruction based on the ASID register and immediately return a response indicating that the current instruction has been completed;

[0027] An item-by-item matching module, for matching the ASID value in each table entry of the address cache and the ASID value of the record item by item after the ASID record module returns a response indicating that the current instruction has been completed, and invalidating the matched table entry;

[0028] The device for quickly invalidating the address cache also includes a query operation execution module for executing the following steps: A1) executing a query operation on all entries of the address cache to obtain a query result; A2) determining whether the query result is a hit, if it is a hit, jumping to step A3), otherwise jumping to step A4); A3) matching the value of the ASID in the hit entry with the value of the ASID in the corresponding ASID register: if the two do not match, determining that the hit entry is a to-be-invalidated entry and the query result is missing, setting the to-be-cleared position of the hit entry to 0 and the valid position to 0, and further checking the page table to confirm the match. A4) further obtains the required information by confirming the page table query, ends and exits; the device for quickly invalidating the address cache also includes a backfill operation execution module for executing the following steps: B1) determines whether the backfill operation is a hit, if it is a hit, jumps to step B2), otherwise reports an error and exits; B2) sets the to-be-cleared position 0 and the valid position 1 in the hit table entry, ends and exits.

[0029] In addition, the present invention also provides a microprocessor, comprising a two-level translation information buffer consisting of a first-level translation information buffer TLB and multiple second-level translation information buffers TLB connected in cascade, and the second-level translation information buffer TLB is programmed or configured to execute the steps of the method for quickly invalidating the address cache.

[0030] In addition, the present invention also provides a computer device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the steps of the method for quickly invalidating the address cache.

[0031] In addition, the present invention also provides a computer-readable storage medium, in which a computer program programmed or configured to execute the method for fast invalidating address cache is stored.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] 1. The present invention does not need to actually complete the operation of invalidating the table entries, that is, it does not need to complete the table entry traversal of the address cache to return a response that the current instruction has been completed. Therefore, when the address cache table entry of a specific ASID is invalidated, subsequent operations can be continued to be executed, thereby improving the speed of invalidating the same ASID table entry in the address cache and reducing the waiting time of subsequent instructions.

[0034] 2. The logic design required by the present invention is concise and the hardware overhead is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The schematic diagram of the principle of invalidating the address cache in the prior art.

[0036] Figure 2 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0037] Figure 3 The figure is a schematic diagram of the principle of invalidating the address cache according to an embodiment of the present invention.

[0038] Figure 4 The present invention is a flow chart showing the process of returning a completion response after receiving an instruction to invalidate the address cache for an ASID.

[0039] Figure 5 The figure is a flow chart of invalidating the same ASID table entry according to an embodiment of the present invention.

[0040] Figure 6 The figure is a flow chart of executing query and backfill operations in the invalidation process according to an embodiment of the present invention.

[0041] Figure 7 The present invention is a flowchart of an embodiment of the present invention when the next cancel instruction arrives during the cancel process. DETAILED DESCRIPTION

[0042] like Figure 2 and Figure 3 As shown, the method for quickly invalidating the address cache in this embodiment includes:

[0043] 1) Receive instructions sent to the address cache;

[0044] 2) When the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID, determine whether the previous instruction for invalidating the address cache for ASID has been executed. If it has not been executed, wait and re-execute step 2); if it has been executed, jump to execute step 3);

[0045] 3) Record the value of ASID in the instruction and immediately return a response indicating that the current instruction has been completed (after returning the response, the blocking state will be eliminated and the next instruction can be received at this time);

[0046] 4) Match the ASID value in each table entry of the address cache and the ASID value of the record one by one, and invalidate the matching table entry.

[0047] The method of this embodiment does not need to actually complete the operation of invalidating the table entries, that is, it does not need to complete the table entry traversal of the address cache to return a response that the current instruction has been completed. Therefore, it is possible to continue to execute subsequent operations when the address cache table entry of a specific ASID is invalidated, thereby improving the speed of invalidating the same ASID table entry in the address cache and reducing the waiting time of subsequent instructions.

[0048] To increase the parallel execution of instructions and improve execution efficiency, see Figure 3 In step 2) of this embodiment, judging whether the last instruction for ASID invalidating address cache has been executed means judging whether the to-be-cleared bits of each table item of the address cache are all 0, if all are 0, it means that the last instruction for ASID invalidating address cache has been executed; step 3) also includes setting the to-be-cleared positions of all table items to 1; step 4) also includes setting the to-be-cleared positions of each table item when matching item by item when matching the ASID values ​​and the recorded ASID values ​​in each table item of the address cache item by item. By adding the to-be-cleared bit, the query and backfill operations can be performed when the last instruction for ASID invalidating address cache has not been completed, so that the method of this embodiment can only be executed during the invalidation operation of the specific type of instruction (invalidation instruction) for the current instruction to invalidate address cache for ASID, and the query and backfill operations can be run in parallel with the invalidation instruction, thereby greatly improving the execution efficiency. Among them, the to-be-cleared bit is used to record the clearing status of each table item, the initial value is 0, the required size of the to-be-cleared bit in each table item is 1 bit, and the hardware overhead is small.

[0049] See also Figure 3 In step 3) of this embodiment, recording the value of the ASID in the instruction refers to recording the value of the ASID in the instruction through a designated ASID register. The method of using the ASID register to record the value of the ASID in the recording instruction is conducive to improving the efficiency of recording the value of the ASID in the instruction and the efficiency of reading the value of the ASID in the recording instruction. In addition, without considering the above advantages, other methods of recording the value of the ASID in the instruction, such as RAM, etc., can also be used as needed.

[0050] See also Figure 3 Compared with the existing address cache, the following modifications need to be made to the address cache in this embodiment: (1) A new ASID register is added, the initial value of which is 0, and is used to store the value of the ASID in the instruction to invalidate the address cache for the ASID. (2) A new to-be-cleared bit for each table entry is added, which is implemented by a register. The initial value of the to-be-cleared bit is 0, and is used to indicate whether each table entry should be cleared. When an instruction to invalidate the address cache for the ASID arrives, the values ​​of all to-be-cleared bits are set to 1. Figure 4 As shown in the figure, when an instruction to invalidate the address cache arrives, if it is determined that the instruction is an instruction to invalidate the address cache for ASID, the value of ASID in the instruction is written into the ASID register, and all the bits to be cleared are set to 1. At this time, the next instruction to invalidate the address cache for ASID needs to wait until this invalidation is completed, that is, the values ​​of all the bits to be cleared are 0 before it can be executed. Figure 5As shown, if the next instruction does not arrive when the instruction for invalidating the address cache for ASID is not executed, then the invalidation instruction matches the ASID in each table item one by one; if the two do not match, the clear position is set to 0, and the matching with the next table item continues; if the two match, the to-be-cleared position is set to 0, the invalidation operation is performed, the table item is invalidated, and the next table item is polled until all the table items are polled.

[0051] In step 2) of this embodiment, when the current instruction sent to the address cache is an instruction for a query operation, the following steps are executed:

[0052] A1) performing a query operation on all entries in the address cache to obtain a query result;

[0053] A2) determining whether the query result is a hit, if so, jumping to step A3), otherwise jumping to step A4);

[0054] A3) Match the value of the ASID in the hit table entry with the value of the ASID in the corresponding ASID register: if the two do not match, the hit table entry is determined to be a table entry to be invalidated and the query result is missing, the to-be-cleared position of the hit table entry is set to 0 and the valid position is set to 0, and the required information is further obtained by querying the page table, and the process ends and exits; if the two match, the hit table entry is determined to be a valid table entry, the cached data of the hit table entry is returned, and the to-be-cleared position of the hit table entry is set to 0, and the process ends and exits;

[0055] A4) further obtains the required information by confirming the page table query, ends and exits.

[0056] In step 2) of this embodiment, when the current instruction sent to the address cache is an instruction for a backfill operation, the following steps are executed:

[0057] B1) Determine whether the backfill operation is a hit, if it is a hit, jump to step B2), otherwise report an error and exit;

[0058] B2) Set the position to be cleared in the hit table entry to 0 and the valid position to 1, and then end and exit.

[0059] It can be seen that if the next instruction arrives before the instruction for invalidating the address cache for ASID is executed, the corresponding operation is performed according to different situations. The implementation steps are as follows: Case 1: The next instruction is a query operation. Figure 6As shown, when there is a subsequent query operation, if the query result is a hit, it is necessary to further compare the ASID in the instruction with the value in the ASID register. If the two match, it means that the item is to be invalidated, and the query result is determined to be missing. The to-be-cleared position of the table item is 0, and the valid position is 0, and the page table query is continued to obtain the required information; if the two do not match, it means that the table item is not to be invalidated, and the query is determined to be a hit, and the value of the to-be-cleared position is reset to 0. Case 2: A backfill operation occurs during the invalidation process. Figure 6 As shown, for the backfill operation after the page table query, the value of the corresponding entry to be cleared is reset to 0, and the value of the valid bit is set to 1. Case 3: The next instruction is an instruction to invalidate the address cache for ASID. Figure 7 As shown, when the next instruction for ASID invalidation address cache arrives during the invalidation process, the operation is not executed, and the next instruction is executed after the invalidation is completed.

[0060] See also Figure 3 Before step 1) of this embodiment, the step of caching and scheduling instructions sent to the address cache through the instruction queue is also included. It should be noted that the instruction queue can perform mixed caching for different types of instructions for unified scheduling; or multiple instruction queues can be used to achieve separate caching of different types of instructions, and various scheduling strategies similar to polling can be used for scheduling.

[0061] In summary, this embodiment includes adding a to-be-cleared bit implemented by a register to all table entries, with an initial value of 0; when an instruction to invalidate the address cache for ASID arrives, the to-be-cleared bits corresponding to all table entries are set to 1, and the newly added ASID register is used to record the ASID in the instruction, and a response that the instruction has been completed is returned; when there is a subsequent query operation, when the query result is a hit, it is necessary to further compare the ASID in the instruction with the value in the ASID register. If there is no match, the query is determined to be a hit, and the to-be-cleared bit of the hit table entry is reset to 0; if there is a match, the query result bit is determined to be missing, and the required information is continued to be obtained through the page table query, and the valid position of the table entry is set to 0; for the backfill operation after the page table query, the to-be-cleared bit of the corresponding table entry is reset to 0, and the valid position is 1; if there is no query and backfill operation, the address cache is invalidated item by item according to ASID. If the next instruction to invalidate the address cache for ASID arrives during the invalidation process, wait for the execution of this instruction to be completed. This embodiment has the following advantages: (1) The method of this embodiment saves the ASID in each instruction for ASID invalidation address cache by adding an ASID register and a to-be-cleared bit implemented by the register, identifies the clearing status of each table entry, and returns an invalidation completion response, so that the next instruction can be continued to be executed during the process of invalidating the table entry. The method and device of the method of this embodiment improve the rate of invalidating the same ASID table entry in the address cache, and can quickly execute the next instruction after returning the invalidation response, thereby also reducing the waiting time of subsequent instructions. (2) The method of this embodiment has a simple logic design and low hardware overhead. The method of this embodiment only needs to add two smaller registers to effectively improve the execution efficiency of traditional invalidation instructions. The circuit logic is simple and the added hardware overhead is small. Therefore, the method of this embodiment can improve the speed of invalidating the same ASID table entry in the address cache, reduce the waiting time of subsequent instructions, and has the advantages of simple logic design and low hardware overhead.

[0062] See also Figure 3 This embodiment also provides a device for quickly invalidating an address cache, including:

[0063] Instruction queue, used to cache and schedule instructions sent to the address cache;

[0064] An instruction judgment module is used to judge whether the previous instruction for invalidating the address cache for ASID has been executed when the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID. If it has not been executed, wait and re-execute the instruction judgment module; if it has been executed, jump to execute the ASID recording module;

[0065] The ASID recording module is used to record the value of the ASID in the instruction based on the ASID register and immediately return a response indicating that the current instruction has been completed;

[0066] An item-by-item matching module, for matching the ASID value in each table entry of the address cache and the ASID value of the record item by item after the ASID record module returns a response indicating that the current instruction has been completed, and invalidating the matched table entry;

[0067] The device for quickly invalidating the address cache also includes a query operation execution module for executing the following steps: A1) executing a query operation on all entries of the address cache to obtain a query result; A2) determining whether the query result is a hit, if it is a hit, jumping to step A3), otherwise jumping to step A4); A3) matching the value of the ASID in the hit entry with the value of the ASID in the corresponding ASID register: if the two do not match, determining that the hit entry is a to-be-invalidated entry and the query result is missing, setting the to-be-cleared position of the hit entry to 0 and the valid position to 0, and further checking the page table to confirm the match. A4) further obtains the required information by confirming the page table query, ends and exits; the device for quickly invalidating the address cache also includes a backfill operation execution module for executing the following steps: B1) determines whether the backfill operation is a hit, if it is a hit, jumps to step B2), otherwise reports an error and exits; B2) sets the to-be-cleared position 0 and the valid position 1 in the hit table entry, ends and exits.

[0068] In addition, this embodiment also provides a microprocessor, including a two-level translation information buffer consisting of a first-level translation information buffer TLB and multiple (more than two) second-level translation information buffers TLB connected in cascade, and the second-level translation information buffer TLB is programmed or configured to execute the steps of the aforementioned method of quickly invalidating address cache.

[0069] In addition, this embodiment also provides a computer device, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the steps of the aforementioned method for quickly invalidating the address cache.

[0070] In addition, this embodiment further provides a computer-readable storage medium, in which a computer program programmed or configured to execute the aforementioned method for quickly invalidating address cache is stored.

[0071] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for quickly invalidating an address cache, characterized in that: include: 1) Receive instructions sent to the address cache; 2) When the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID, determine whether the previous instruction for invalidating the address cache for ASID has been executed. If not, wait and re-execute step 2); if it has been executed, jump to step 3); 3) Record the value of ASID in the command and immediately return a response indicating that the current command has been completed; 4) Match the ASID values ​​in each entry of the address cache with the ASID values ​​of the record one by one, and invalidate the matching entries; In step 2), when the current instruction sent to the address cache is an instruction for a query operation, the execution steps are as follows: A1) Perform a query operation on all entries in the address cache to obtain the query result; A2) Determine whether the query result is a hit, if it is a hit, jump to step A3), otherwise jump to step A4); A3) Match the ASID value in the hit table entry with the ASID value in the corresponding ASID register: If the two do not match, the hit table entry is determined to be a table entry to be invalidated and the query result is missing, and the to-be-cleared position and valid position of the hit table entry are set to 0, and the required information is further obtained by querying the page table, and the process ends and exits; If the two match, the hit table entry is determined to be a valid table entry, and the cached data of the hit table entry is returned, and the to-be-cleared position of the hit table entry is set to 0, and the process ends and exits; A4) Further obtain the required information by confirming the page table query, end and exit.

2. The method for quickly invalidating address cache according to claim 1, characterized in that: In step 2), judging whether the last instruction for invalidating the address cache for ASID has been executed means judging whether the to-be-cleared bits of each entry in the address cache are all 0. If all are 0, it means that the last instruction for invalidating the address cache for ASID has been executed; step 3) also includes setting the to-be-cleared bits of all entries to 1; step 4) also includes setting the to-be-cleared bits of each entry in the address cache to 0 when matching the ASID values ​​and the recorded ASID values ​​item by item.

3. The method for quickly invalidating address cache according to claim 2, characterized in that: In step 3), recording the value of the ASID in the instruction refers to recording the value of the ASID in the instruction through a designated ASID register.

4. The method for quickly invalidating address cache according to claim 3, characterized in that: In step 2), when the current instruction sent to the address cache is an instruction for a backfill operation, the execution steps are as follows: B1) Determine whether the backfill operation is a hit, if yes, jump to step B2), otherwise report an error and exit; B2) Set the position to be cleared in the hit table entry to 0 and the valid position to 1, and then exit.

5. The method for quickly invalidating address cache according to claim 4, characterized in that: Before step 1), the method also includes the step of caching and scheduling instructions sent to the address cache through the instruction queue.

6. A device for quickly invalidating an address cache, characterized in that: include: Instruction queue, used to cache and schedule instructions sent to the address cache; An instruction judgment module is used to judge whether the previous instruction for invalidating the address cache for ASID has been executed when the current instruction sent to the address cache is an instruction for invalidating the address cache for ASID. If it has not been executed, wait and re-execute the instruction judgment module; if it has been executed, jump to execute the ASID recording module; The ASID recording module is used to record the value of the ASID in the instruction based on the ASID register and immediately return a response indicating that the current instruction has been completed; An item-by-item matching module, for matching the ASID value in each table entry of the address cache and the ASID value of the record item by item after the ASID record module returns a response indicating that the current instruction has been completed, and invalidating the matched table entry; The device for quickly invalidating the address cache also includes a query operation execution module for executing the following steps: A1) executing a query operation on all entries of the address cache to obtain a query result; A2) determining whether the query result is a hit, if so, jumping to step A3), otherwise jumping to step A4); A3) Match the ASID value in the hit table entry with the ASID value in the corresponding ASID register: If the two do not match, the hit table entry is determined to be a table entry to be invalidated and the query result is missing, the to-be-cleared position of the hit table entry is set to 0 and the valid position is set to 0, and the required information is further obtained by confirming the page table query, and the process ends and exits; If the two match, the hit table entry is determined to be a valid table entry, the cached data of the hit table entry is returned, and the to-be-cleared position of the hit table entry is set to 0, and the process ends and exits; A4) Further obtain the required information by confirming the page table query, and the process ends and exits; The device for quickly invalidating the address cache also includes a backfill operation execution module for executing the following steps: B1) Determine whether the backfill operation is a hit, if it is a hit, jump to step B2), otherwise report an error and exit; B2) Set the position to be cleared in the hit table entry to 0 and the valid position to 1, and then exit.

7. A microprocessor comprising a two-level translation information buffer consisting of a first-level translation information buffer TLB and a plurality of second-level translation information buffers TLB connected in cascade, characterized in that: The second-level translation information buffer TLB is programmed or configured to execute the steps of the method for fast invalidation of address cache as claimed in any one of claims 1 to 5.

8. A computer device comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the steps of the method for quickly invalidating the address cache as claimed in any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program programmed or configured to execute the method for quickly invalidating address cache as claimed in any one of claims 1 to 5.

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