PAM-NRZ signal conversion circuit, conversion method, device and medium

Abstract

The present invention provides a PAM-NRZ signal conversion circuit, comprising a signal comparison unit, a first OR gate, a delay unit, and a second OR gate. The signal comparison unit has an input for receiving a PAM signal, an output electrically connected to the input of the first OR gate, an output of the first OR gate electrically connected to the input of the second OR gate and the input of the delay unit, an output of the delay unit electrically connected to the input of the second OR gate, and an output of the second OR gate electrically connected to the input of the second OR gate. The output of the second OR gate is configured to output only an NRZ signal resulting from the conversion of the PAM signal's short edge. The PAM-NRZ signal conversion circuit of the present invention suppresses the conversion of the PAM signal's long edge to output a signal, outputting only an NRZ signal resulting from the conversion of the PAM signal's short edge, thereby ensuring the accuracy of the data period of the PAM signal-to-NRZ signal conversion and eliminating the problem of different duty cycles of the NRZ signal caused by different conversion times between the PAM signal's long edge and the PAM signal's short edge.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a PAM-NRZ signal conversion circuit, a conversion method, an electronic device, a non-transitory computer-readable storage medium, and a computer program product. Background Art

[0002] The standard 100BASE-T1 protocol transmits a three-level pulse amplitude modulation (PAM3) signal. PAM3 signals have three levels: -1, 0, and 1. To recover the signal clock from these three-level data, the PAM3 signal must be converted into a two-level non-return-to-zero (NRZ) signal during reception. Generally speaking, transition edges between adjacent PAM3 levels are called short edges, i.e., 0 to 1, 0 to -1, 1 to 0, and -1 to 0. The resulting NRZ signal is called a short-edge conversion output signal. Transition edges between non-adjacent PAM3 levels are called long edges, i.e., 1 to -1 and -1 to 1. The resulting NRZ signal is called a long-edge conversion output signal. PAM3-NRZ signal conversion circuits require that the edge period of the NRZ signal accurately reflect the clock edge period of the PAM3 signal.

[0003] The traditional signal conversion method is to input the PAM3 signal into the input terminals of two comparators (for ease of description, the two comparators are named comparator A and comparator B below). Comparator A is used to extract PAM3 signal edges from -1 to 1, 0 to 1, 1 to 0, and 1 to -1. Comparator B is used to extract PAM3 signal edges from -1 to 1, 0 to -1, -1 to 0, and 1 to -1. The output terminals of comparators A and B are electrically connected to the same OR gate. The signal output by the OR gate after performing the OR logic operation is the NRZ signal.

[0004] When using this traditional signal conversion method, it was found that when the short edge of the input PAM3 signal changes from 1 to 0 and from 0 to 1, the output of comparator A generates a change signal and comparator B outputs a low level; when the short edge of the PAM3 signal changes from -1 to 0 and from 0 to -1, the output of comparator B generates a change signal and comparator A outputs a low level; but when the long edge of the PAM3 signal changes from 1 to -1 and from -1 to 1, the outputs of both comparator A and comparator B generate change signals.

[0005] Therefore, the NRZ signal conversion between the two comparators is highly susceptible to the long edge of the PAM3 signal. To convert the PAM3 signal to the NRZ signal, the OR gate places extremely stringent requirements on the PAM3 signal edge conversion time. Once the conversion time of the PAM3 signal's long edge slows down, the crossover point of the two comparator output edges will fall below the OR gate's high and low level thresholds, vth. This results in a negative pulse signal, converting one long edge into two. This means that the NRZ signal actually converts the PAM3 signal's long edge twice, changing the data period.

[0006] To avoid this situation, some people have suggested having one of the comparators always output 0. For example, comparator B can continuously output 0. In this way, the resulting NRZ signal is converted from the signal output by comparator A. However, this NRZ signal may also be converted from two PAM3 signal edges: -1 to 1 and 0 to 1. The -1 to 1 edge belongs to the long edge of the PAM3 signal, and the 0 to 1 edge belongs to the short edge of the PAM3 signal. The conversion times of the two are different, and the duty cycle output by comparator A is also different. The NRZ signal obtained by this conversion becomes composed of two signals with different duty cycles, which does not fundamentally improve the signal conversion method.

[0007] Therefore, in order to prevent the conversion of the long edge of the PAM3 signal from changing the clock period of the NRZ signal, and to eliminate the problem of different NRZ signal duty cycles caused by the different conversion times of the long edge of the PAM3 signal and the short edge of the PAM3 signal, it is necessary to remove the output signal converted by the long edge of the PAM3 signal. Summary of the Invention

[0008] The present invention provides a PAM-NRZ signal conversion circuit, a conversion method, an electronic device, a non-transitory computer-readable storage medium, and a computer program product, which achieve the goal of suppressing the conversion output signal of the long edge of the PAM signal (the PAM signal edge from -1 to 1 and 1 to -1), and outputting only the NRZ signal obtained by converting the output signal by the short edge of the PAM signal. This prevents the conversion of the NRZ signal from being affected by the long edge of the PAM signal, ensures the accuracy of the data period of the PAM signal conversion to the NRZ signal, and eliminates the problem of different NRZ signal duty cycles caused by different conversion times of the long edge of the PAM signal and the short edge of the PAM3 signal.

[0009] The present invention provides a PAM-NRZ signal conversion circuit, comprising a signal comparison unit, a first OR gate, a delay unit, and a second OR gate. The input end of the signal comparison unit is used to receive a PAM signal, and the output end is electrically connected to the input end of the first OR gate. The output end of the first OR gate is electrically connected to the input end of the second OR gate and the input end of the delay unit. The output end of the delay unit is electrically connected to the input end of the second OR gate. The output end of the second OR gate is used to output only an NRZ signal obtained by converting the short edge of the PAM signal.

[0010] According to a PAM-NRZ signal conversion circuit provided by the present invention, the delay unit is an even-stage inverter.

[0011] According to a PAM-NRZ signal conversion circuit provided by the present invention, the delay unit includes a DC power supply and an even number of inverting modules. The even number of inverting modules are electrically connected in sequence, and the input end of the first inverting module is electrically connected to the output end of the first OR gate, and the output end of the last inverting module is electrically connected to the input end of the second OR gate. The even number of inverting modules are all electrically connected to the positive pole of the DC power supply, and the negative pole of the DC power supply is grounded.

[0012] According to a PAM-NRZ signal conversion circuit provided by the present invention, the inverting module includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor and the gate of the NMOS transistor serve as the signal input end of the inverting module, for receiving the signal output by the output end of the first OR gate. The source of the PMOS transistor is electrically connected to the positive electrode of the DC power supply, and the drain is electrically connected to the drain of the NMOS transistor. The source of the NMOS transistor is grounded. The drain of the PMOS transistor and the drain of the NMOS transistor serve as the signal output end of the inverting unit, for outputting the output signal of the inverting unit to the input end of the second OR gate. Adjacent inverting modules are electrically connected in sequence through the signal input end and the signal output end of the inverting module.

[0013] According to a PAM-NRZ signal conversion circuit provided by the present invention, the signal comparison unit includes a first comparator and a second comparator, the positive input terminal of the first comparator and the negative input terminal of the second comparator are used to receive the PAM signal, the negative input terminal of the first comparator is connected to a high threshold level, and the positive input terminal of the second comparator is connected to a low threshold level, and the output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the input terminal of the first OR gate.

[0014] The present invention also provides a PAM-NRZ signal conversion method implemented by the PAM-NRZ signal conversion circuit described in any one of the above, comprising the following steps:

[0015] Converting the input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate;

[0016] Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged;

[0017] The second OR gate is used to perform an OR high-level logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

[0018] According to a PAM-NRZ signal conversion method provided by the present invention, the delay time of the long-edge conversion output signal and the short-edge conversion output signal by the delay unit is greater than the negative pulse width of the long-edge conversion output signal converted by the signal comparison unit and the first OR gate, and is less than the positive pulse width of the short-edge conversion output signal.

[0019] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-described PAM-NRZ signal conversion methods are implemented.

[0020] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above-described PAM-NRZ signal conversion methods.

[0021] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any one of the above-mentioned PAM-NRZ signal conversion methods are implemented.

[0022] The PAM-NRZ signal conversion circuit, conversion method, electronic device, non-transitory computer-readable storage medium, and computer program product of the present invention first convert an input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal using a signal comparison unit and a first OR gate. The long-edge conversion output signal and the short-edge conversion output signal are then delayed using a delay unit so that the edge of the long-edge conversion output signal before the delay corresponds in time to the high level of the long-edge conversion output signal after the delay, the edge of the long-edge conversion output signal after the delay corresponds in time to the high level of the long-edge conversion output signal before the delay, and the edge change of the short-edge conversion output signal before and after the delay remains unchanged. Then, a second OR gate is used to perform an OR high-level logic operation on the long-edge conversion output signal and the short-edge conversion output signal before and after the delay. The edges of the long-edge conversion output signal before and after the delay are eliminated after being output by the second OR gate, and thus no NRZ signal is converted. The short-edge conversion output signal remains unchanged. Therefore, the present invention only outputs the NRZ signal converted from the PAM signal short-edge conversion output signal.

[0023] The present invention suppresses the long edge of the PAM signal (the PAM signal edge from -1 to 1 and from 1 to -1) from converting the output signal, avoids the conversion of the NRZ signal from being affected by the long edge of the PAM signal, ensures the accuracy of the data cycle of the PAM signal conversion to the NRZ signal, and at the same time, because only the short edge is left to convert the output signal, it eliminates the problem of different NRZ signal duty cycles caused by different conversion times of the long edge of the PAM signal and the short edge of the PAM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 This is a module schematic diagram of the PAM-NRZ signal conversion circuit provided by the present invention;

[0026] Figure 2 1 is another module schematic diagram of the PAM-NRZ signal conversion circuit provided by the present invention, which shows the specific structure of the signal comparison unit;

[0027] Figure 3 This is a waveform diagram of the PAM3 signal in actual transmission;

[0028] Figure 4(a) is a schematic diagram of the waveforms of the output signals of each module when a traditional signal conversion circuit is used to convert a PAM3 signal. Part A shows the waveform of the output signal of the first comparator in the traditional signal conversion circuit, Part B shows the waveform of the output signal of the second comparator in the traditional signal conversion circuit, and Part C shows the waveform of the output signal of the OR gate in the traditional signal conversion circuit. Figure 4 (b) Yes Figure 4 (a) Schematic diagram of edge changes of the output of the first comparator and the output of the second comparator, where A' represents the first comparator and B' represents the second comparator;

[0029] Figure 5 This is a schematic diagram of the waveforms of the output signals of each module when the PAM-NRZ signal conversion circuit provided by the present invention converts a PAM3 signal, wherein portion D represents the waveform of the output signal of the first comparator in the PAM-NRZ signal conversion circuit of the present invention, portion E represents the waveform of the output signal of the second comparator in the PAM-NRZ signal conversion circuit of the present invention, portion F represents the waveform of the output signal of the first OR gate in the PAM-NRZ signal conversion circuit of the present invention, portion G represents the waveform of the output signal of the delay unit in the PAM-NRZ signal conversion circuit of the present invention, and portion H represents the waveform of the output signal of the second OR gate in the PAM-NRZ signal conversion circuit of the present invention, wherein the edge changes of portions F and G are highlighted;

[0030] Figure 6 The present invention provides a circuit diagram of a delay unit for implementing a PAM-NRZ signal conversion circuit. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0032] The following combination Figures 1-6 The PAM-NRZ signal conversion circuit of the present invention is described, wherein Vin represents the input signal, Vout represents the output signal, VL represents the low threshold level, and VH represents the high threshold level.

[0033] like Figure 1As shown, the PAM-NRZ signal conversion circuit of the present invention includes a signal comparison unit, a first OR gate, a delay unit, and a second OR gate. The input end of the signal comparison unit is used to receive the PAM signal, and the output end is electrically connected to the input end of the first OR gate. The output end of the first OR gate is electrically connected to the input end of the second OR gate and the input end of the delay unit. The output end of the delay unit is electrically connected to the input end of the second OR gate. The output end of the second OR gate is used to output only the NRZ signal obtained by converting the short edge of the PAM signal.

[0034] Specifically, the PAM signal in this embodiment is a PAM3 signal.

[0035] The PAM-NRZ signal conversion circuit of the present invention first converts an input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal using a signal comparison unit and a first OR gate, then delays the long-edge conversion output signal and the short-edge conversion output signal using a delay unit, so that the edge of the long-edge conversion output signal before the delay corresponds in time to the high level of the long-edge conversion output signal after the delay, and the edge of the long-edge conversion output signal after the delay corresponds in time to the high level of the long-edge conversion output signal before the delay, and the edge change of the short-edge conversion output signal before and after the delay remains unchanged. The second OR gate is used to perform an OR high-level logic operation on the long-edge conversion output signal and the short-edge conversion output signal before and after the delay to eliminate the edge of the long-edge conversion output signal. Therefore, the present invention only outputs the NRZ signal obtained by converting the PAM signal into the short-edge conversion output signal.

[0036] Specifically, see Figure 5The edges of the long-edge conversion output signals before and after the delay are ORed with the high level using the second OR gate to obtain a constant level, that is, the edge is eliminated. This high level is due to the fact that the long-edge conversion output signal is a narrow negative pulse, and the high levels before and after the negative pulse are both high (named as the front high level and the back high level). When the delay time of the delay unit is greater than the pulse width of this negative pulse, the rising and falling edges of the delayed negative pulse will be aligned in time with the back high level before the delay. At this time, the rising and falling edges of the negative pulse before the delay will also be aligned in time with the front high level after the delay, that is, the OR operation eliminates the edge. The edges of the short-edge conversion output signals before and after the delay are ORed with the low level using the second OR gate, and the obtained edge remains unchanged. This low level is because the short-edge conversion output signal is considered a positive-width pulse. The positive pulse is preceded and followed by low levels (named the front low level and the back low level). When the delay unit's delay time is less than the positive pulse width, the delayed falling edge of the positive pulse will be aligned in time with the back low level before the delay, and the delayed rising edge of the positive pulse will be aligned in time with the high level of the positive pulse before the delay. At this time, the rising edge of the positive pulse before the delay will also be aligned in time with the front low level after the delay, and the falling edge of the positive pulse before the delay will also be aligned in time with the high level of the positive pulse after the delay. In other words, the OR operation eliminates the falling edge of the positive pulse before the delay and the rising edge of the positive pulse after the delay, while retaining the rising edge of the positive pulse before the delay and the falling edge of the positive pulse after the delay. In other words, the edge variation of the short-edge conversion output signal remains unchanged; only the pulse width changes.

[0037] The present invention suppresses the conversion of the long edge of the PAM signal (the PAM signal edge from -1 to 1 and from 1 to -1) into the output signal, avoids the conversion of the NRZ signal from being affected by the long edge of the PAM signal, and ensures the accuracy of the data cycle of the PAM signal conversion into the NRZ signal. At the same time, since only the short edge is left to convert the output signal, the problem of different NRZ signal duty cycles caused by different conversion times of the long edge of the PAM3 signal and the short edge of the PAM3 signal is eliminated.

[0038] Further, if Figure 2 As shown, the signal comparison unit includes a first comparator and a second comparator, the positive input terminal of the first comparator and the negative input terminal of the second comparator are used to receive the PAM signal, the negative input terminal of the first comparator is connected to the high threshold level VH, and the positive input terminal of the second comparator is connected to the low threshold level VL, and the output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the input terminal of the first OR gate.

[0039] Specifically, the first comparator is used to extract PAM3 signal edges of -1 to 1, 0 to 1, 1 to 0, and 1 to -1, and the second comparator is used to extract PAM3 signal edges of -1 to 1, 0 to -1, -1 to 0, and 1 to -1.

[0040] Figure 3 The waveform of a PAM3 signal during actual transmission is shown. The PAM3 signal has three levels: 1, 0, and 1. When the level of the PAM3 signal is converted, the comparison unit and the first OR gate of the present invention generate two types of edge conversions: a long-edge conversion output signal and a short-edge conversion output signal, depending on whether the input levels are adjacent.

[0041] The signal conversion unit and the first OR gate of the present invention can form a traditional signal conversion circuit, but the NRZ signal obtained by such conversion includes an NRZ signal obtained by converting the long edge of the PAM signal and the short edge of the PAM signal, and the conversion of the NRZ signal between the two comparators is easily affected by the long edge of the PAM3 signal, which can easily lead to conversion data errors.

[0042] Figure 4 (a) shows the waveforms of the output signals of each module when a conventional signal conversion circuit is used to convert a PAM3 signal. Part A shows the waveform of the output signal of the first comparator in the conventional signal conversion circuit, Part B shows the waveform of the output signal of the second comparator in the conventional signal conversion circuit, and Part C shows the waveform of the output signal of the OR gate in the conventional signal conversion circuit. Figure 4 (b) shows Figure 4 (a) is a schematic diagram of the edge changes of the first comparator output and the second comparator output, where A' represents the first comparator and B' represents the second comparator.

[0043] according to Figure 4 (a) It can be seen that when the input is a short edge, only one comparator outputs an edge signal. When the input is a long edge, both comparators output edge signals. For example, when the input edge is from -1 to 1, the first comparator outputs a rising edge signal that reaches a logic high level at time t2, and the second comparator outputs a falling edge signal from a logic high level at time t1. Similarly, when the input edge is from 1 to -1, the first comparator outputs a falling edge signal from a logic high level at time t3, and the second comparator outputs a rising edge signal that reaches a logic high level at time t4. Figure 4(b) As can be seen, when t2 is close to t1, the level at point M, where the falling edge signal output by the second comparator intersects the rising edge signal output by the first comparator, is higher than the logic high / low threshold vth. Similarly, when t4 is close to t3, the level at point N, where the falling edge signal output by the first comparator intersects the rising edge signal output by the second comparator, is higher than the logic high / low threshold vth. At this point, the output of the OR operation is high, eliminating the long-edge conversion output signal. However, when the input edge slows down, the distance between t2 and t1 increases, the level at point M falls below the logic high / low threshold vth, and the distance between t4 and t3 increases, the level at point N falls below the logic high / low threshold vth. At this point, the output of the OR operation is a low pulse, indicating two edges. The resulting NRZ signal actually converts the long edge of the PAM3 signal twice, changing the data period.

[0044] In contrast, Figure 5 The figure shows the waveforms of the output signals of each module when the PAM-NRZ signal conversion circuit provided by the present invention converts a PAM3 signal. Part D shows the waveform of the output signal of the first comparator in the PAM-NRZ signal conversion circuit of the present invention, part E shows the waveform of the output signal of the second comparator in the PAM-NRZ signal conversion circuit of the present invention, part F shows the waveform of the output signal of the first OR gate in the PAM-NRZ signal conversion circuit of the present invention, part G shows the waveform of the output signal of the delay unit in the PAM-NRZ signal conversion circuit of the present invention, and part H shows the waveform of the output signal of the second OR gate in the PAM-NRZ signal conversion circuit of the present invention.

[0045] The invention as a whole can make the edge of the long edge conversion output signal before the delay correspond to the high level of the long edge conversion output signal after the delay in time, the edge of the long edge conversion output signal after the delay corresponds to the high level of the long edge conversion output signal before the delay in time, and the edge change of the short edge conversion output signal before and after the delay remains unchanged; the second OR gate is used to perform an OR logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay. Since the edge of the long edge conversion output signal is eliminated through the OR high level operation, only the NRZ signal obtained by converting the short edge conversion output signal remains, thereby ensuring the accuracy of the process and result of converting the PAM signal to the NRZ signal.

[0046] Preferably, the delay unit is an even-stage inverter.

[0047] Specifically, the delay unit includes a DC power supply and an even number of inverting modules, the even number of inverting modules are electrically connected in sequence, and the input end of the first inverting module among them is electrically connected to the output end of the first OR gate, the output end of the last inverting module is electrically connected to the input end of the second OR gate, and the even number of inverting modules are all electrically connected to the positive pole of the DC power supply, and the negative pole of the DC power supply is grounded.

[0048] The delay of the delay unit of the present invention is proportional to the number of stages of the even-stage inverter, so as to eliminate the conversion error of the NRZ signal caused by the long edge of the corresponding PAM signal by adjusting the delay time.

[0049] Further, if Figure 6 As shown, the inverting module includes a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor serve as the signal input end of the inverting module, for receiving the signal output from the output end of the first OR gate, the source of the PMOS transistor is electrically connected to the positive pole of the DC power supply, and the drain is electrically connected to the drain of the NMOS transistor, the source of the NMOS transistor is grounded, the drain of the PMOS transistor and the drain of the NMOS transistor serve as the signal output end of the inverting unit, for outputting the output signal of the inverting unit to the input end of the second OR gate, and adjacent inverting modules are electrically connected in sequence through the signal input end and the signal output end of the inverting module.

[0050] Figure 6 In the figure, MP1 represents the first PMOS transistor, MP2n represents the 2nth PMOS transistor, MN1 represents the NMOS transistor, MN2n represents the 2nth NMOS transistor, where n is an integer to represent an even number of inverter modules; DC represents a direct current power supply.

[0051] The inversion module configured in this way can calculate the required number of stages based on the delay of each inversion unit and the required total delay, and controllably delay the long edge conversion output signal and the short edge conversion output signal output by the signal conversion unit and the first OR gate, so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge change of the short edge conversion output signal before and after the delay remains unchanged. In the present invention, the delay time of the delay unit is positively correlated with the conversion time of the long edge of the PAM signal. However, the traditional method of converting the PAM signal into a long edge conversion output signal using a signal comparison unit and a first OR gate does not have this delay unit, so the maximum PAM long edge input conversion time required is limited. Figure 4In (b), the voltage levels at points M and N must be greater than the judgment threshold vth. This requires a very short long-edge input transition time. When the transition time of the PAM signal's long edge slows down, the delay time needs to be increased to correct the NRZ signal transition errors caused by the long edge of the PAM3 signal.

[0052] The PAM-NRZ signal conversion circuit of the present invention is simple in overall structure, complete in structure, highly practical, low in manufacturing cost, and low in technical difficulty, and can be widely used.

[0053] In addition, according to actual application conditions, the PAM signal may also be other PAM signals, and the relevant units may be adaptively adjusted according to actual use.

[0054] The present invention also discloses a PAM-NRZ signal conversion method implemented based on the above-mentioned PAM-NRZ signal conversion circuit, comprising the following steps:

[0055] Converting the input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate;

[0056] Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged;

[0057] The second OR gate is used to perform an OR logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

[0058] Furthermore, the delay time of the long edge conversion output signal and the short edge conversion output signal by the delay unit is greater than the negative pulse width of the PAM signal converted into the long edge conversion output signal by using the signal comparison unit and the first OR gate, and is less than the positive pulse width of the short edge conversion output signal.

[0059] The PAM-NRZ signal conversion electronic device provided by the present invention is described below. The PAM-NRZ signal conversion electronic device described below and the PAM-NRZ signal conversion method described above can be referenced to each other.

[0060] The electronic device may include: a processor, a communications interface, a memory, and a communications bus, wherein the processor, the communications interface, and the memory communicate with each other via the communications bus. The processor may call logic instructions in the memory to execute a PAM-NRZ signal conversion method, the method including:

[0061] Converting the input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate;

[0062] Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged;

[0063] The second OR gate is used to perform an OR logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

[0064] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code signals.

[0065] On the other hand, the present invention further provides a computer program product, comprising a computer program. The computer program may be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the PAM-NRZ signal conversion method provided by the above methods, the method comprising:

[0066] The input PAM signal is converted into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate.

[0067] Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged;

[0068] The second OR gate is used to perform an OR logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

[0069] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for converting a PAM-NRZ signal provided by the above methods is implemented. The method includes:

[0070] The input PAM signal is converted into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate.

[0071] Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged;

[0072] The second OR gate is used to perform an OR logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

[0073] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0074] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A PAM-NRZ signal conversion circuit, characterized in that: include: A signal comparison unit, a first OR gate, a delay unit, and a second OR gate, wherein the input end of the signal comparison unit is used to receive a PAM signal, and the output end is electrically connected to the input end of the first OR gate, the output end of the first OR gate is electrically connected to the input end of the second OR gate and the input end of the delay unit, the output end of the delay unit is electrically connected to the input end of the second OR gate, and the output end of the second OR gate is used to output only an NRZ signal obtained by converting the short edge of the PAM signal. The delay unit is an even-stage inverter. The signal comparison unit includes a first comparator and a second comparator. The positive input end of the first comparator and the negative input end of the second comparator are used to receive the PAM signal.

2. The PAM-NRZ signal conversion circuit according to claim 1, characterized in that: The even-level inverter includes a DC power supply and an even number of inverter modules, the even number of inverter modules are electrically connected in sequence, and the input end of the first inverter module among them is electrically connected to the output end of the first OR gate, the output end of the last inverter module is electrically connected to the input end of the second OR gate, and the even number of inverter modules are all electrically connected to the positive pole of the DC power supply, and the negative pole of the DC power supply is grounded.

3. The PAM-NRZ signal conversion circuit according to claim 2, characterized in that: The inverting module includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor and the gate of the NMOS transistor serve as the signal input end of the inverting module, which is used to receive the signal output by the output end of the first OR gate. The source of the PMOS transistor is electrically connected to the positive pole of the DC power supply, and the drain is electrically connected to the drain of the NMOS transistor. The source of the NMOS transistor is grounded. The drain of the PMOS transistor and the drain of the NMOS transistor serve as the signal output end of the inverting module, which is used to output the output signal of the inverting module to the input end of the second OR gate. Adjacent inverting modules are electrically connected in sequence through the signal input end and the signal output end of the inverting module.

4. The PAM-NRZ signal conversion circuit according to any one of claims 1 to 3, characterized in that: The negative input terminal of the first comparator is connected to a high threshold level, the positive input terminal of the second comparator is connected to a low threshold level, and the output terminals of the first comparator and the second comparator are both electrically connected to the input terminal of the first OR gate.

5. A PAM-NRZ signal conversion method implemented by the PAM-NRZ signal conversion circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: Converting the input PAM signal into a long-edge conversion output signal and a short-edge conversion output signal by using the signal comparison unit and the first OR gate; Delaying the long edge conversion output signal and the short edge conversion output signal by a delay unit so that the edge of the long edge conversion output signal before the delay corresponds in time to the high level of the long edge conversion output signal after the delay, and the edge of the long edge conversion output signal after the delay corresponds in time to the high level of the long edge conversion output signal before the delay, and the edge changes of the short edge conversion output signal before and after the delay remain unchanged; The second OR gate is used to perform an OR high-level logic operation on the long edge conversion output signal and the short edge conversion output signal before and after the delay, so as to output only the NRZ signal converted from the short edge conversion output signal.

6. The PAM-NRZ signal conversion method according to claim 5, characterized in that: The delay time of the long edge conversion output signal and the short edge conversion output signal by the delay unit is greater than the negative pulse width of the long edge conversion output signal converted by the signal comparison unit and the first OR gate, and is less than the positive pulse width of the short edge conversion output signal.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the PAM-NRZ signal conversion method according to claim 5 or 6 are implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the PAM-NRZ signal conversion method according to claim 5 or 6 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the PAM-NRZ signal conversion method according to claim 5 or 6 are implemented.

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