Detection circuit and sensor

Abstract

A detection circuit for detecting the influence of stress on electrical characteristics, comprising: a PMOS tube-dominant self-oscillation ring (101), an NMOS tube-dominant self-oscillation ring (102), and a frequency reading module (103); the number of PMOS tubes in the signal path of the PMOS tube-dominant self-oscillation ring (101) is greater than the number of NMOS tubes; the number of NMOS tubes in the signal path of the NMOS tube-dominant self-oscillation ring (102) is greater than the number of PMOS tubes; the frequency reading module (103) is used to read the frequency signal output by the PMOS tube-dominant self-oscillation ring (101) or the NMOS tube-dominant self-oscillation ring (102). The frequency signal output by the NMOS tube-dominant self-oscillation ring (102) represents the influence of stress on the electrical characteristics of the NMOS tube, and the frequency signal output by the PMOS tube-dominant self-oscillation ring (101) represents the influence of stress on the electrical characteristics of the PMOS tube. The manufacturing process of the circuit can be improved according to the influence of stress on the NMOS tube and the influence of stress on the PMOS tube, so as to reduce the influence of stress on the electrical characteristics of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of electricity, and in particular to a detection circuit and a sensor. Background Art

[0002] Stress is inevitably generated during the manufacturing and packaging of integrated circuits. In particular, the influence of stress on semiconductor devices will have a significant impact on the carrier mobility of semiconductor devices, which in turn affects the behavior of analog and digital circuits and may even cause circuit failure.

[0003] In a complementary metal oxide semiconductor (CMOS) inverter self-oscillation ring based on a 45° active region orientation, the ratio of the frequencies of the CMOS inverter self-oscillation rings in two different orientations, R0 and R45, can be used to determine the effect of stress at the location of the CMOS inverter on the frequency, thereby reflecting the effect of stress at the location of the CMOS inverter on the device's electrical characteristics.

[0004] The above implementation reflects the effect of stress on the electrical characteristics of a CMOS inverter. A CMOS inverter includes both NMOS and PMOS transistors. The effect of stress on the electrical characteristics of NMOS transistors may differ from that of PMOS transistors. This solution cannot distinguish the effects of stress on the electrical characteristics of NMOS transistors from those of PMOS transistors. Summary of the Invention

[0005] The present application provides a detection circuit and a sensor. The detection circuit is used to detect the influence of stress on the current of an NMOS transistor and a PMOS transistor in a circuit. The detection circuit includes:

[0006] A PMOS transistor-dominated self-oscillating ring, an NMOS transistor-dominated self-oscillating ring, and a frequency reading module; the number of PMOS transistors in the signal path of the PMOS transistor-dominated self-oscillating ring is greater than the number of NMOS transistors; the number of NMOS transistors in the signal path of the NMOS transistor-dominated self-oscillating ring is greater than the number of PMOS transistors; the frequency reading module is used to read the frequency signal output by the PMOS transistor-dominated self-oscillating ring or the NMOS transistor-dominated self-oscillating ring. As can be seen from the first aspect, the detection circuit provided in this embodiment includes a PMOS transistor-dominated self-oscillating ring and an NMOS transistor-dominated self-oscillating ring, wherein the frequency signal output by the NMOS transistor-dominated self-oscillating ring represents the effect of stress on the electrical characteristics of the NMOS transistor, and the frequency signal output by the PMOS transistor-dominated self-oscillating ring represents the effect of stress on the electrical characteristics of the PMOS transistor. The circuit manufacturing process can be improved based on the effect of stress on the NMOS transistor and the effect on the PMOS transistor to reduce the effect of stress on the electrical characteristics of the circuit.

[0007] Based on the first aspect of the embodiments of the present application, in a first implementation method of the first aspect of the embodiments of the present application, the PMOS tube-dominated self-oscillation ring includes an even number of NOR gates connected in series, and the number of PMOS tubes connected in series on the signal path in each of the even number of NOR gates is greater than the number of NMOS tubes; the NMOS tube-dominated self-oscillation ring includes an even number of NAND gates connected in series, and the number of NMOS tubes connected in series on the signal path in each of the even number of NAND gates is greater than the number of PMOS tubes.

[0008] Based on the first implementation of the first aspect of the embodiment of the present application, in the second implementation of the first aspect of the embodiment of the present application, the PMOS tube dominant self-oscillation ring includes a first NAND gate, the output of the first NAND gate is coupled to the input end of the even number of NOR gates connected in series, the first NAND gate includes a first input end and a second input end, the first input end is connected to the control signal, and the second input end is connected to the output end of the even number of NOR gates connected in series.

[0009] Based on the second implementation of the first aspect of the embodiment of the present application, in the third implementation of the first aspect of the embodiment of the present application, each NOR gate of the even number of NOR gates includes P input terminals, where P is an integer greater than or equal to 2; the third input terminal of the P input terminals is connected to the output terminal of the first NAND gate, and the other input terminals of the P input terminals except the third input terminal are connected to a low level, and the third input terminal is any one of the P input terminals.

[0010] Based on the first possible implementation of the first aspect of the embodiment of the present application, in a fourth implementation of the first aspect of the embodiment of the present application, the NMOS tube-dominated self-oscillation loop includes a second NAND gate, the output of the second NAND gate is coupled to the input end of the even number of NAND gates connected in series, the second NAND gate includes a fourth input end and a fifth input end, the fourth input end is connected to the control signal, and the fifth input end is connected to the output end of the even number of NAND gates connected in series.

[0011] Based on the fourth possible implementation of the first aspect of the embodiment of the present application, in a fifth implementation of the first aspect of the embodiment of the present application, each NAND gate of the even number of NAND gates includes L input terminals, where L is an integer greater than or equal to 2; a sixth input terminal of the L input terminals is connected to the output of the second NAND gate, and the other input terminals of the L input terminals except the sixth input terminal are connected to a high level, and the sixth input terminal is any one of the L input terminals.

[0012] Based on the second possible implementation of the first aspect to the fifth possible implementation of the first aspect of the embodiments of the present application, in the sixth possible implementation of the first aspect, the circuit also includes an inverter, which is used to invert the control signal and then couple it to the first input terminal of the first NAND gate.

[0013] Based on the first aspect to the fifth possible implementation of the first aspect of the embodiments of the present application, in a seventh possible implementation of the first aspect, the circuit further includes a multiplexer MUX, which is used to select the output of the PMOS-dominated self-oscillation ring or the NMOS-dominated self-oscillation ring to be provided to the frequency reading module.

[0014] Based on the seventh possible implementation of the first aspect of the embodiment of the present application, in an eighth possible implementation of the first aspect, the frequency reading module includes a frequency divider, a register and a system clock, the frequency divider is connected to the output ends of the PMOS tube dominant self-oscillation ring and the NMOS tube dominant self-oscillation ring, and the frequency divider is also connected to the register and the system clock respectively.

[0015] A second aspect of an embodiment of the present application provides a sensor, which includes the detection circuit in the first aspect and any possible implementation manner of the first aspect.

[0016] A third aspect of an embodiment of the present application provides a chip, which includes the detection circuit in the first aspect and any possible implementation of the first aspect.

[0017] This embodiment provides a detection circuit for detecting the impact of stress on electrical characteristics. The detection circuit includes: a PMOS transistor-dominant self-oscillating ring, an NMOS transistor-dominant self-oscillating ring, and a frequency reading module. The number of PMOS transistors in the signal path of the PMOS transistor-dominant self-oscillating ring is greater than the number of NMOS transistors; the number of NMOS transistors in the signal path of the NMOS transistor-dominant self-oscillating ring is greater than the number of PMOS transistors. The frequency reading module is configured to read the frequency signal output by the PMOS transistor-dominant self-oscillating ring or the NMOS transistor-dominant self-oscillating ring. The detection circuit provided in this embodiment includes a PMOS transistor-dominant self-oscillating ring and an NMOS transistor-dominant self-oscillating ring. The frequency signal output by the NMOS transistor-dominant self-oscillating ring represents the impact of stress on the electrical characteristics of the NMOS transistor, and the frequency signal output by the PMOS transistor-dominant self-oscillating ring represents the impact of stress on the electrical characteristics of the PMOS transistor. The circuit manufacturing process can be improved based on the impact of stress on the NMOS transistor and the impact on the PMOS transistor to reduce the impact of stress on the electrical characteristics of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A schematic diagram of a circuit for detecting the effect of stress on electrical characteristics provided by an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of a NOR gate 1012 provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of a NAND gate 1022 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0022] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Embodiments of the present application provide a detection circuit and sensor. This detection circuit generates a high-frequency signal through a PMOS transistor-dominated self-oscillating loop and an NMOS transistor-dominated self-oscillating loop. After the high-frequency signal is reduced in frequency by a frequency divider, a system clock counts the reduced frequency signal and stores the resulting frequency value in a register. This detection circuit can compare the change in frequency value before and after packaging the circuit being tested, thereby detecting the impact of the packaging process on the stress of the tested circuit.

[0024] In an embodiment of the present application, a detection circuit can be placed in the integrated circuit being detected. When the PMOS transistor in the detection circuit is in an operating state and the self-oscillating ring is in an operating state, the detection circuit is used to detect the effect of stress on the PMOS transistor in the integrated circuit. When the NMOS transistor in the detection circuit is in an operating state and the self-oscillating ring is in an operating state, the detection circuit is used to detect the effect of stress on the NMOS transistor in the integrated circuit.

[0025] Please refer to Figure 1 , Figure 1 A schematic diagram of a detection circuit provided in an embodiment of the present application is shown in FIG. Figure 1As shown, the detection circuit includes: a PMOS-dominated self-oscillating ring 101, an NMOS-dominated self-oscillating ring 102, and a frequency reading module 103. In this embodiment, the PMOS-dominated self-oscillating ring 101 refers to a self-oscillating ring in which the number of PMOS transistors on the signal path is greater than the number of NMOS transistors, and the NMOS-dominated self-oscillating ring 102 refers to a self-oscillating ring in which the number of NMOS transistors on the signal path is greater than the number of PMOS transistors.

[0026] The PMOS-dominant self-oscillating ring 101 and the NMOS-dominant self-oscillating ring 102 provided in the embodiments of the present application are described in detail below.

[0027] like Figure 1 As shown, the PMOS dominant self-oscillation ring 101 includes an even number of NOR gates 1012 connected in series and a first NAND gate 1011, wherein each NOR gate 1012 in the even number of NOR gates includes P input terminals, where P is an integer greater than or equal to 2, and one of the P input terminals is connected to the output terminal of the first NAND gate 1011. The first NAND gate 1011 includes a first input terminal and a second input terminal, wherein the first input terminal is connected to a control signal, and an inverter can be provided between the first input terminal and the control signal. The second input terminal of the first NAND gate 1011 is connected to the output terminal Z1 of the even number of NOR gates connected in series. Figure 1 The illustrated PMOS-dominated self-oscillating ring 101 only illustrates two four-input NOR gates 1012. The four inputs of the NOR gates 1012 are A1, A2, A3, and A4, respectively. It should be noted that in practical applications, the number of NOR gates 1012 connected in series is an even number, for example, four or eight NOR gates 1012, etc., without specific limitation herein. Furthermore, the even number of NOR gates 1012 connected in series is illustrated in the figure as an example of the A1 input of each NOR gate 1012 being connected to the output of the previous NOR gate 1012. In actual production, the other inputs of each NOR gate 1012 may also be connected to the output of the previous NOR gate 1012.

[0028] In this embodiment, the number of PMOS transistors connected in series on the signal path in each of the even number of NOR gates 1012 is greater than the number of NMOS transistors. For details, please refer to Figure 2 As shown, Figure 2 A schematic diagram of one of the NOR gates 1012 of the even number of NOR gates 1012 provided in this embodiment is shown in FIG. Figure 2 As shown, the NOR gate 1012 provided in this embodiment is composed of an NMOS tube and a PMOS tube. It can be understood that in the digital cell library, there are many types of NOR gates, including different numbers of input pins and different numbers of N / P MOS. In this embodiment, only the NOR gate 1012 is used. Figure 2The 4-input NOR gate 1012 is shown as an example. Of course, in actual applications, the NOR gate 1012 may also have an even number of inputs, such as 2 or 8. It should be noted that in this embodiment, the input terminals of each of the even number of NOR gates, except for the one input used to connect to the adjacent NOR gate, are connected to a low level.

[0029] Specifically, if Figure 2 Three input pins A2, A3, and A4 of the NOR gate 1012 shown are connected to a low level 0, and the three PMOS transistors whose gates are connected to A2, A3, and A4 are in an open state, while the three NMOS transistors whose gates are connected to A2, A3, and A4 are in a closed state.

[0030] When A1 input is low level 0, Figure 2 In the NOR gate 1012 shown, all PMOS transistors are in the open state, and all NMOS transistors are in the closed state. When A1 inputs a high level 1, the PMOS transistor connected to A1 is in the closed state, and the NMOS transistor connected to A1 is in the open state. At this time, Figure 2 In the NOR gate 1012 shown, three PMOS transistors are in an on state and one NMOS transistor is in an on state. Therefore, in both cases, the number of PMOS transistors in an on state in the NOR gate 1012 exceeds the number of NMOS transistors.

[0031] Therefore, in this embodiment, when stress causes changes in the electrical characteristics of the PMOS transistor, the frequency signal output by the PMOS transistor's main self-oscillation ring 101 reflects the changes in the electrical characteristics of the PMOS transistor. Obviously, the circuit for detecting the influence of stress on the electrical characteristics provided in this embodiment can determine the influence of stress on the PMOS transistor based on the frequency signal output by the PMOS transistor's main self-oscillation ring 101. Therefore, the manufacturing process of the integrated circuit can be improved based on the influence of stress on the PMOS transistor, thereby improving the manufacturing process accuracy of the integrated circuit and reducing the influence of stress on the electrical characteristics of the PMOS transistor of the integrated circuit.

[0032] like Figure 1 As shown, the NMOS dominant self-oscillating ring 102 includes an even number of NAND gates 1022 and a second NAND gate 1021 connected in series. Each of the even number of NAND gates 1022 includes L input terminals, where L is an integer greater than or equal to 2. One of the L input terminals is connected to the output terminal of the second NAND gate 1021. The second NAND gate 1021 includes a fourth input terminal and a fifth input terminal. The fourth input terminal is connected to the control signal, and the fifth input terminal is connected to the output terminal Z2 of the even number of NAND gates connected in series. Figure 1The NMOS-dominated self-oscillating ring 102 shown in FIG. 1 only illustrates two 4-input segment NAND gates 1022. Figure 1 As shown, the four inputs of NAND gate 1022 are A1, A2, A3, and A4, respectively. It should be noted that in actual applications, the number of NAND gates 1022 connected in series is an even number, for example, four NAND gates 1022 or eight NAND gates 1022, etc., which is not specifically limited here. Furthermore, the even number of NAND gates 1022 connected in series is illustrated in the figure as an example of the A1 input of each NAND gate 1022 being connected to the output of the previous NAND gate 1022. In actual production, the other inputs of each NOR gate 1012 can also be connected to the output of the previous NOR gate 1012.

[0033] It should be noted that the inverter 104, the first NAND gate 1011 in the PMOS transistor dominant oscillator ring 101, and the second NAND gate 1021 in the NMOS transistor dominant oscillator ring 102 control the entire detection circuit. When the control signal is high, the inverter 104 sets the first input of the first NAND gate 1011 to a low level, and the fourth input of the second NAND gate 1021 to a high level. In this case, only the NMOS transistor dominant oscillator ring 102 in the detection circuit operates, while the PMOS transistor dominant oscillator ring 101 does not operate. In this case, the detection circuit can detect the effects of stress on the NMOS transistor.

[0034] Similarly, when the control signal is low, the inverter 104 sets the first input of the first NAND gate 1011 to a high level, and the fourth input of the second NAND gate 1021 to a low level. In this case, in the detection circuit, only the PMOS transistor-driven oscillation ring 101 operates, while the NMOS transistor-driven oscillation ring 102 does not operate. In this case, the detection circuit can detect the impact of stress on the PMOS transistor.

[0035] In this embodiment, the number of NMOS transistors connected in series on the signal path in each of the even number of NAND gates 1022 is greater than the number of PMOS transistors. Figure 3 A schematic diagram of one of the NAND gates 1022 of the even number of NAND gates 1022 provided in this embodiment is shown in FIG. Figure 3 As shown, the NAND gate 1022 provided in this embodiment is composed of an NMOS tube and a PMOS tube. It can be understood that in the digital cell library, there are many types of NOR gates, including different numbers of input pins and different numbers of N / P MOS. In this embodiment, only the NAND gate 1022 is used. Figure 3The 4-input NAND gate 1022 is shown as an example. Of course, in actual applications, the NAND gate 1022 can also have 2 inputs or 8 inputs. It should be noted that in this embodiment, among the input terminals of each NAND gate with an even number of NAND gates, except for the one input used to connect to the adjacent NAND gate, the other input terminals are connected to a high level.

[0036] Specifically, Figure 3 Three input pins A2, A3, and A4 of the NAND gate 1022 are connected to a high level 1, and the three PMOS transistors whose gates are connected to A2, A3, and A4 are in a closed state, while the three NMOS transistors whose gates are connected to A2, A3, and A4 are in an open state.

[0037] When A1 input is low level 0, Figure 3 In the NAND gate 1022 shown, all NMOS transistors are in the open state, and all PMOS transistors are in the closed state. When A1 inputs a high level 1, the NMOS transistors connected to A1 are in the closed state, and the PMOS transistors connected to A1 are in the open state. At this time, Figure 2 In the NAND gate 1022 shown, three NMOS transistors are turned on and one PMOS transistor is turned on. Therefore, in both cases, the number of NMOS transistors turned on in the NOR gate 1012 exceeds the number of PMOS transistors.

[0038] Therefore, in this embodiment, when stress causes changes in the electrical characteristics of the NMOS transistor, the frequency signal output by the NMOS leading self-oscillation ring 102 reflects the changes in the electrical characteristics of the NMOS transistor. Obviously, the circuit for detecting the influence of stress on the electrical characteristics provided in this embodiment can determine the influence of stress on the NMOS transistor based on the frequency signal output by the NMOS leading self-oscillation ring 102, thereby improving the manufacturing process of the integrated circuit based on the influence of stress on the PMOS transistor, improving the manufacturing process accuracy of the integrated circuit, and reducing the influence of stress on the electrical characteristics of the NMOS transistor of the integrated circuit.

[0039] The PMOS dominant self-oscillating ring 101 and the NMOS dominant self-oscillating ring 102 provided in this embodiment are described in detail above. The frequency reading module 103 provided in this embodiment will be described below.

[0040] like Figure 1As shown, the frequency reading module 103 includes a frequency divider 1032, a register 1031 and a system clock 1033, wherein the frequency divider 1032 is connected to the output ends of the PMOS-dominant self-oscillating ring 101 and the NMOS-dominant self-oscillating ring 102 respectively through the multiplexer MUX105, and the frequency divider 1032 is also connected to the register 1031 and the system clock 1033 respectively. In this embodiment, the frequency divider 1032 is used to reduce the frequency of the output frequency signals of the PMOS-dominant self-oscillating ring 101 and the NMOS-dominant self-oscillating ring 102. The frequency divider 1032 outputs a frequency signal with a reduced frequency, and the frequency signal is converted into a digital signal, which is stored in the register 1031 array and can be read in real time using the system clock 1033.

[0041] It should be noted that the MUX 105 provided in this embodiment is used to selectively provide the outputs of the PMOS-dominant self-oscillating ring 101 and the NMOS-dominant self-oscillating ring 102 to the frequency reading module. For example, when the control signal is at a high level of 1, this high level 1 is simultaneously input to the NMOS-dominant self-oscillating ring 102 and to the MUX 105. The MUX 105 can then selectively provide the output of the NMOS-dominant self-oscillating ring 102 to the frequency reading module.

[0042] The circuit for detecting the influence of stress on electrical characteristics provided in this embodiment may further include an inverter 104. When the control signal is at a low level 0, the low level 0 passes through the inverter 104, and the inverter 104 outputs a high level 1. The high level 1 output by the inverter 104 is input to the PMOS dominant self-oscillation ring 101, and the low level 0 is input to the MUX 105. The MUX 105 thereby selects to provide the output of the PMOS dominant self-oscillation ring 101 to the frequency reading module.

[0043] In practical applications, the circuit for detecting the effects of stress on electrical characteristics can be placed at different locations on a semiconductor chip to determine the distribution of stress on the semiconductor chip based on the frequency signals read by the frequency reading module 103 when the circuit is placed at different locations on the semiconductor chip. For example, the circuit can be placed at the center or around the periphery of the semiconductor chip, and the distribution of stress on the semiconductor chip can be determined based on the frequency signals read by the frequency reading module 103 at the center and around the periphery of the semiconductor chip.

[0044] Of course, this embodiment can also determine the impact of the packaging process on the electrical characteristics through wafer circuit probing (CP) testing and functional testing (FT). For example, the frequency signal read by the frequency reading module 103 is obtained through CP testing, and the frequency signal read by the frequency reading module 103 is obtained through FT testing. The frequency signal read by the frequency reading module 103 obtained through CP testing and the frequency signal read by the frequency reading module 103 obtained through FT testing are compared to determine the impact of the packaging process on the electrical characteristics of the device. It should be noted that CP testing is performed before semiconductor packaging, and FT testing is performed after semiconductor packaging.

[0045] In this embodiment, the influence of stress of different packaging forms on the electrical characteristics of the device can be obtained by comparing the frequency signals read by the frequency reading modules 103 of different packaging forms, or the influence of the package bump stress on the electrical characteristics of the device can be obtained by comparing the frequency signals read by the frequency reading modules 103 when the circuit is placed directly below the bump and near the bump, or in scenarios such as chip dropping, the influence of stress on the electrical characteristics can be analyzed by the difference in the frequency signals read by the frequency reading module 103 before and after the drop.

[0046] The circuit provided in this embodiment for detecting the effect of stress on electrical properties can also be used in 3D integrated circuits (ICs), for example, in 3D ICs containing through silicon vias (TSVs) or through dielectric vias (TDVs) to detect the effect of stress in TSVs or TDVs on the electrical properties of surrounding devices.

[0047] The circuit for detecting the influence of stress on electrical characteristics provided in the embodiment of the present application is described above. The sensor provided in the embodiment of the present application is described below.

[0048] The embodiment of the present application further provides a sensor, which includes Figure 1 The circuit for detecting the influence of stress on electrical characteristics shown in the figure, wherein the function and structure of the circuit for detecting the influence of stress on electrical characteristics included in the sensor are the same as those of the aforementioned Figure 1 、 Figure 2 and Figure 3 Similar to the above, please refer to Figure 1 、 Figure 2 and Figure 3 , I will not go into details here.

[0049] The embodiment of the present application further provides a chip, which includes Figure 1The circuit for detecting the influence of stress on electrical characteristics shown in the figure, wherein the function and structure of the circuit for detecting the influence of stress on electrical characteristics included in the chip are the same as those of the aforementioned Figure 1 、 Figure 2 and Figure 3 Similar to the above, please refer to Figure 1 、 Figure 2 and Figure 3 , I will not go into details here.

[0050] In the embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0051] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0052] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0053] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A detection circuit, characterized in that: include: The PMOS tube leads the self-oscillation loop, the NMOS tube leads the self-oscillation loop and the frequency reading module; The number of PMOS transistors in the signal path of the PMOS-dominated self-oscillation loop is greater than the number of NMOS transistors; The number of NMOS transistors in the signal path of the NMOS-dominated self-oscillation loop is greater than the number of PMOS transistors; The frequency reading module is used to read the frequency signal output by the PMOS tube's dominant self-oscillation ring or the NMOS tube's dominant self-oscillation ring. The frequency signal output by the PMOS tube's dominant self-oscillation ring represents the impact of stress on the electrical characteristics of the PMOS tube, and the frequency signal output by the NMOS tube's dominant self-oscillation ring represents the impact of stress on the electrical characteristics of the NMOS tube.

2. The circuit according to claim 1, wherein: The PMOS tube-dominant self-oscillation ring includes an even number of NOR gates connected in series, and the number of PMOS tubes connected in series on the signal path in each of the even number of NOR gates is greater than the number of NMOS tubes; the NMOS tube-dominant self-oscillation ring includes an even number of NAND gates connected in series, and the number of NMOS tubes connected in series on the signal path in each of the even number of NAND gates is greater than the number of PMOS tubes.

3. The circuit according to claim 2, characterized in that The PMOS tube-dominated self-oscillation loop includes a first NAND gate, the output of which is coupled to the input of the even-numbered NOR gates connected in series, the first NAND gate including a first input and a second input, the first input being connected to a control signal, and the second input being connected to the output of the even-numbered NOR gates connected in series.

4. The circuit according to claim 3, characterized in that Each of the even-numbered NOR gates includes P input terminals, where P is an integer greater than or equal to 2; The third input terminal among the P input terminals is connected to the output terminal of the first NAND gate, and the other input terminals among the P input terminals except the third input terminal are connected to a low level, and the third input terminal is any one of the P input terminals.

5. The circuit according to claim 2, characterized in that The NMOS tube-dominated self-oscillation loop includes a second NAND gate, the output of the second NAND gate is coupled to the input end of the even number of NAND gates connected in series, the second NAND gate includes a fourth input end and a fifth input end, the fourth input end is connected to the control signal, and the fifth input end is connected to the output end of the even number of NAND gates connected in series.

6. The circuit according to claim 5, characterized in that Each of the even-numbered NAND gates includes L input terminals, where L is an integer greater than or equal to 2; The sixth input terminal among the L input terminals is connected to the output of the second NAND gate, and the other input terminals among the L input terminals except the sixth input terminal are connected to a high level. The sixth input terminal is any one of the L input terminals.

7. The circuit according to claim 3 or 4, characterized in that The circuit further includes an inverter configured to invert the control signal and then couple the inverted control signal to the first input terminal of the first NAND gate.

8. The circuit according to any one of claims 1 to 6, characterized in that The circuit further includes a multiplexer MUX configured to select and provide an output of the PMOS-dominant self-oscillating ring or an output of the NMOS-dominant self-oscillating ring to the frequency reading module.

9. The circuit according to claim 8, characterized in that The frequency reading module includes a frequency divider, a register and a system clock. The frequency divider is connected to the output ends of the PMOS tube self-oscillation ring and the NMOS tube self-oscillation ring. The frequency divider is also connected to the register and the system clock respectively.

10. A sensor, characterized in that: The sensor comprises the detection circuit according to any one of claims 1 to 9.

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