Fan-out packaging method and fan-out packaging structure

Abstract

The embodiment of the present invention provides a fan-out packaging method and a fan-out packaging structure, which relate to the field of semiconductor packaging technology. By setting a second carrier, combined with a first carrier, it can provide strong support in the subsequent plastic packaging process, and the second carrier can reduce the backflow impact during plastic packaging, thereby preventing the plastic packaging body from warping. In addition, the second carrier cover is arranged outside the semiconductor device, the lower part of the semiconductor device is shielded by the first carrier, and the upper part is shielded by the second carrier, so that dust can be shielded during preparation or transportation, and ESD breakdown or defects in packaging caused by dust contacting the internal semiconductor device before plastic packaging can be avoided. In addition, the second carrier can also be used as a clamping object during the transportation process to prevent the semiconductor device from being touched and damaged, and realize the front grip of the wafer, which can avoid the wafer flip grip, and greatly improve the wafer processing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging method and a fan-out packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, various packaging structures have been fully developed, among which fan-out wafer level package (FOWLP) is widely used in the semiconductor industry. In this packaging technology, a single chip is generally cut from a wafer and then packaged on a carrier wafer. The main advantages are high-density integration, small package product size, superior product performance, fast signal transmission frequency, etc. Fan-out technology mainly realizes multi-pin output and small output pin spacing.

[0003] The inventors have found through research that during the fan-out wafer chip packaging process, there is a problem of plastic seal warping. At the same time, fan-out wafer-level chip packaging has strict dust control. Tiny dust on the chip can easily cause ESD breakdown or defects in the package (such as voids, chip surface cracks, etc.), affecting product quality. In addition, conventional fan-out crystal chips require multiple flipping actions during the manufacturing process to perform front or back processing. In the prior art (chip face up, chip face down), there is only one type of carrier to prevent warping problems in the chip manufacturing process and protect the bottom of the chip (for easy clamping). The chip on the other side cannot be protected and clamped, resulting in many transportation problems. Summary of the invention

[0004] The objects of the present invention include, for example, providing a fan-out packaging method and a fan-out packaging structure, which can solve the problem of plastic packaging warping, prevent defects caused by dust, improve product quality, and facilitate transportation and flipping, thereby helping to improve production efficiency.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a fan-out packaging method, comprising:

[0007] Mounting a semiconductor device on a first carrier;

[0008] Mounting a second carrier provided with supporting feet on the first carrier, and making the second carrier cover outside the semiconductor device, the supporting feet being provided on the first carrier and being located on both sides of the semiconductor device;

[0009] Plastic-sealing the first carrier to form a plastic-sealed body, and making the plastic-sealed body cover the semiconductor device, and the second carrier is embedded in the plastic-sealed body;

[0010] Exposing the semiconductor device so that the semiconductor device is exposed from the plastic package;

[0011] A wiring assembly layer is formed on one side of the plastic package, wherein the wiring assembly layer is electrically connected to the semiconductor device;

[0012] Balls are implanted on a side of the wiring assembly layer away from the plastic package body to form solder balls on the wiring assembly layer.

[0013] In an optional embodiment, the step of exposing the semiconductor device includes:

[0014] Peeling off the first carrier to expose the semiconductor device from the plastic package;

[0015] Wherein, a conductive pad is disposed on a surface of the semiconductor device on one side for mounting the first carrier.

[0016] In an optional embodiment, the step of forming a wiring assembly layer on one side of the plastic package body includes:

[0017] Forming a first dielectric layer on one side of the plastic package, wherein the first dielectric layer covers the semiconductor device;

[0018] Grooving the first dielectric layer to form a first groove, wherein the first groove penetrates the first dielectric layer and reaches the conductive pad;

[0019] forming a first metal layer in the first groove, wherein the first metal layer is electrically connected to the conductive pad;

[0020] forming a second dielectric layer on a side of the first dielectric layer away from the plastic package body, wherein the second dielectric layer covers the first metal layer;

[0021] Grooving the second dielectric layer to form a second groove, wherein the second groove penetrates the second dielectric layer and reaches the first metal layer;

[0022] forming a second metal layer in the second groove, wherein the second metal layer is electrically connected to the first metal layer;

[0023] forming a third dielectric layer on a side of the second dielectric layer away from the plastic package body, wherein the third dielectric layer covers the second metal layer;

[0024] Grooving the third dielectric layer to form a third groove, wherein the third groove penetrates the third dielectric layer and reaches the second metal layer;

[0025] forming a third metal layer in the third groove, wherein the third metal layer is electrically connected to the second metal layer;

[0026] Wherein, the third metal layer is used to set the solder balls.

[0027] In an optional embodiment, the step of forming a third metal layer in the third groove includes:

[0028] A conductive column is formed by electroplating in the third groove, and the conductive column is protruded from the third dielectric layer.

[0029] In an optional embodiment, the step of forming a wiring assembly layer on one side of the plastic package body includes:

[0030] Forming a first dielectric layer on one side of the plastic package, wherein the first dielectric layer covers the semiconductor device;

[0031] Grooving the first dielectric layer to form a first groove, wherein the first groove penetrates the first dielectric layer and reaches the conductive pad;

[0032] forming a first metal layer in the first groove, wherein the first metal layer is electrically connected to the conductive pad;

[0033] forming a second dielectric layer on a side of the first dielectric layer away from the plastic package body, wherein the second dielectric layer covers the first metal layer;

[0034] Grooving the second dielectric layer to form a second groove, wherein the second groove penetrates the second dielectric layer and reaches the first metal layer;

[0035] forming a second metal layer in the second groove, wherein the second metal layer is electrically connected to the first metal layer;

[0036] Wherein, the second metal layer is used to set the solder ball.

[0037] In an optional embodiment, the step of exposing the semiconductor device includes:

[0038] Cutting a groove on the first carrier to form a base groove penetrating to the semiconductor device so that the semiconductor device is exposed from the plastic package;

[0039] forming a base metal layer in the base groove, wherein the base metal layer is electrically connected to the semiconductor device;

[0040] Wherein, a conductive pad is arranged on a surface of one side of the semiconductor device for mounting the first carrier.

[0041] In an optional embodiment, the step of exposing the semiconductor device includes:

[0042] A plastic sealing groove is formed on one side surface of the plastic sealing body, wherein the plastic sealing groove passes through the semiconductor device so that the semiconductor device is exposed from the plastic sealing body;

[0043] Forming a plastic encapsulation metal layer in the plastic encapsulation groove, wherein the plastic encapsulation metal layer is electrically connected to the semiconductor device;

[0044] Wherein, a conductive pad is disposed on a surface of the semiconductor device which is away from the first carrier.

[0045] In an optional embodiment, before the step of exposing the semiconductor device, the method further includes:

[0046] Grinding the plastic package body until the supporting feet are exposed;

[0047] Wherein, the supporting feet are hollow, so that conducting holes are formed on the plastic package body at both sides of the semiconductor device.

[0048] In an optional embodiment, after the step of planting balls on a side of the wiring assembly layer away from the plastic package body, the method further comprises:

[0049] The plastic package body and the wiring assembly layer are cut along the area between the supporting foot and the semiconductor device.

[0050] In an optional embodiment, before the step of mounting the semiconductor device on the first carrier, the method further includes:

[0051] A mounting groove is formed on the first carrier, and the mounting groove is used to adaptively mount a semiconductor device.

[0052] In a second aspect, the present invention provides a fan-out packaging structure, which is prepared using the fan-out packaging method described in any of the aforementioned embodiments.

[0053] The beneficial effects of the embodiments of the present invention include, for example:

[0054] The fan-out packaging structure provided by the present invention has a semiconductor device arranged on a first carrier, and a second carrier is mounted on the first carrier, the second carrier cover is arranged outside the semiconductor device, and a support foot is arranged at the same time, the support foot is arranged on the first carrier, and is located on both sides of the semiconductor device, and then the plastic sealing, wiring and ball planting actions are performed. By arranging the second carrier, combined with the first carrier, it is possible to provide strong support in the subsequent plastic sealing process, and the second carrier can reduce the backflow impact during the plastic sealing, thereby preventing the plastic sealing body from warping. In addition, the second carrier cover is arranged outside the semiconductor device, the lower part of the semiconductor device is shielded by the first carrier, and the upper part is shielded by the second carrier, so that dust can be shielded during preparation or transportation, and ESD breakdown or defects in the package caused by dust contacting the internal semiconductor device before plastic sealing is avoided. In addition, the second carrier can also be used as a clamping object during the transportation process to prevent the semiconductor device from being touched and damaged, and realize the front grip of the wafer, which can avoid the wafer flip grip, and greatly improve the wafer processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 A flowchart of a fan-out packaging method according to a first embodiment of the present invention;

[0057] Figures 2 to 14 A process flow chart of a fan-out packaging method provided by the first embodiment of the present invention;

[0058] Fig.15 A schematic diagram of a fan-out packaging structure provided by a first embodiment of the present invention;

[0059] Fig.16 is a schematic structural diagram of the second carrier in the first embodiment of the present invention;

[0060] Fig.17 A schematic diagram of a fan-out packaging structure provided by a second embodiment of the present invention;

[0061] Figure 18 to Figure 19 A partial process flow chart of a fan-out packaging method provided by a third embodiment of the present invention;

[0062] Figure 20 to Figure 22 A partial process flow chart of a fan-out packaging method provided by a fourth embodiment of the present invention;

[0063] Fig.23 A schematic diagram of a fan-out packaging structure provided by a fourth embodiment of the present invention;

[0064] Fig.24 and Fig.25 A partial process flow chart of the fan-out packaging method provided in the fifth embodiment of the present invention.

[0065] Icon: 100-fan-out packaging structure; 110-plastic package body; 111-conducting hole; 113-plastic package groove; 115-plastic package metal layer; 120-adhesive layer; 130-semiconductor device; 131-conductive pad; 150-wiring assembly layer; 151-first dielectric layer; 1511-first groove; 152-first metal layer; 153-second dielectric layer; 1531-second groove; 154-second metal layer; 155-third dielectric layer; 1551-third groove; 156-third metal layer; 170-solder ball; 200-first carrier; 210-base groove; 230-base metal layer; 250-mounting groove; 300-second carrier; 310-support foot. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0069] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0070] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0071] As disclosed in the background technology, the existing fan-out wafer chip packaging process usually has the following problems:

[0072] 1. When the etching process is performed using the existing technology, oxides are easily generated, which in turn affects the edge pads, causing the grounding resistance to be unstable.

[0073] 2. In the process of fan-out wafer chip packaging, plastic packaging warping problems are prone to occur due to the mismatch of CTE of various materials.

[0074] 3. Fan-out wafer-level chip packaging has strict control over dust. Tiny dust on the chip can easily cause ESD breakdown or defects in the package (for example, voids, chip surface cracks, etc.).

[0075] 4. In the prior art (chip face up or chip face down), there is only one type of carrier to prevent chip warping during the manufacturing process and protect the bottom of the chip. The other side of the chip cannot be protected and cannot be grasped, resulting in many transportation problems.

[0076] In order to solve the above problems, the present invention provides a novel fan-out packaging method and a fan-out packaging structure 100. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0077] First embodiment

[0078] See also Figure 1 : This embodiment provides a fan-out packaging method, which is used to prepare a fan-out packaging structure 100. It can solve the problem of plastic packaging warping during the packaging process, prevent defects caused by dust, improve product quality, and facilitate transportation and flipping, which helps to improve production efficiency.

[0079] The fan-out packaging method provided in this embodiment includes the following steps:

[0080] S1 : mounting the semiconductor device 130 on the first carrier 200 .

[0081] See also Figure 2 Specifically, in this embodiment, the fan-out package structure 100 is prepared by a method of simultaneously manufacturing multiple devices. First, a carrier is provided, on which multiple semiconductor devices 130 are mounted simultaneously. The multiple semiconductor devices 130 are arranged in a uniform array to facilitate subsequent cutting to form multiple fan-out package structures 100.

[0082] It should be noted that, in this embodiment, the semiconductor device 130 is a chip structure, such as a control chip or a memory chip. Of course, the semiconductor device 130 here can also be other electronic components, such as a resistor or a capacitor. At the same time, in this embodiment, a conductive pad 131 for achieving electrical connection is provided on the semiconductor device 130, and the conductive pad 131 is arranged downward, that is, the conductive pad 131 on the semiconductor device 130 is bonded to the surface of the first carrier 200.

[0083] In this embodiment, before executing step S1, the following steps need to be performed: mounting the adhesive layer 120 on the surface of the first carrier 200. After mounting the adhesive layer 120, directly mounting the semiconductor device 130 on the surface of the adhesive layer 120. Preferably, the adhesive layer 120 may be provided with a plurality of marks or alignment marks, so as to facilitate accurate alignment and mounting of the plurality of semiconductor devices 130.

[0084] In this embodiment, the first carrier 200 can be made of glass, silicon oxide, metal and other materials. The adhesive layer 120 here can be a UV adhesive layer, which is convenient for subsequent peeling of the first carrier 200, and can be separated by irradiating UV light. Of course, the adhesive layer 120 here can also be at least one of adhesive, epoxy resin, and polyimide, which is made by UV curing or thermal curing and used as a separation layer.

[0085] S2: Mounting the second carrier 300 provided with the supporting legs 310 on the first carrier 200 .

[0086] See also Figure 3 Specifically, after the mounting of multiple semiconductor devices 130 is completed, the second carrier 300 is mounted to cover the upper part of the semiconductor device 130. That is, the second carrier 300 is covered outside the semiconductor device 130, and the supporting feet 310 are arranged on the first carrier 200 and located on both sides of the semiconductor device 130.

[0087] It should be noted that in this embodiment, the second carrier 300 is a cover structure as a whole and has a plurality of support legs 310 for support. Support legs 310 are provided on both sides of each semiconductor device 130, so that the top of each semiconductor device 130 is covered with the second carrier 300.

[0088] In this embodiment, the material of the second carrier 300 is consistent with the structural material of the first carrier 200. It covers the upper part of the semiconductor device 130, which can effectively reduce the pollution of the semiconductor device 130 by dust around the semiconductor device 130, and avoid ESD problems and process problems (chip crushing, cracking, plastic sealing voids, etc.) caused by dust. At the same time, the joint action of the second carrier 300 and the first carrier 200 can provide strong support for the subsequent plastic sealing, and the second carrier 300 can effectively reduce the reflow impact during plastic sealing, and further reduce the warping phenomenon. In addition, the second carrier 300 can play a grasping role, which is convenient for transportation during the process and avoids the first carrier 200 from flipping over for grasping, thereby greatly improving the processing efficiency.

[0089] It should be noted that the second carrier 300 may also be made of a different material from the first carrier 200, and the material selection may be adaptively improved to cooperate with the first carrier 200 to achieve a better structural support effect and further prevent warping. For example, the second carrier 300 may be made of a material with greater rigidity.

[0090] In this embodiment, the second carrier 300 may also be made of metal material, such as copper, and is covered on the upper part of the semiconductor device 130 to simultaneously achieve an electromagnetic shielding effect.

[0091] S3: Forming a plastic package body 110 by plastic packaging on the first carrier 200 .

[0092] See also Figure 4 Specifically, the plastic encapsulation body 110 is coated on the outside of the semiconductor device 130, and the second carrier 300 is embedded in the plastic encapsulation body 110. The plastic encapsulation body 110 is coated on the outside of the semiconductor device 130 and the second carrier 300 at the same time, wherein a vacuum plastic encapsulation process can be used during plastic encapsulation, so that the plastic encapsulation material can be filled on the inside and outside of the second carrier 300 at the same time. Of course, a plastic encapsulation machine can also be used here to perform conventional filling operations, and at this time, a number of flow holes can be opened on the second carrier 300, so that the plastic encapsulation material can flow into the inside of the second carrier 300 quickly and smoothly to prevent the generation of internal voids.

[0093] It should be noted that in this embodiment, the bottom structure formed by the semiconductor device 130 is protected by the plastic package 110 , and the molding height of the plastic package material should be higher than the second carrier 300 , so that the second carrier 300 can be molded therein at the same time.

[0094] It should also be noted that in other preferred embodiments of the present invention, the plastic encapsulation step can also be omitted, and before mounting the second carrier 300, the second carrier 300 is directly coated with adhesive, and then the second carrier 300 with adhesive is mounted on the first carrier 200, so that the semiconductor device 130 is covered with glue, and a glue layer is formed after curing, which can also achieve the role of the plastic encapsulation body 110 in this embodiment. The specific scheme will not be described in detail here.

[0095] S4: Grinding the plastic package body 110 until the supporting feet 310 are exposed.

[0096] See also Figure 5 Specifically, after the plastic packaging is completed, a grinding process is performed on the top of the plastic packaging body 110 until the support foot 310 structure is exposed. The grinding process can be performed to the top of the second carrier 300, and the top of the second carrier 300 is ground off.

[0097] Specifically, when the second carrier 300 uses a metal component to achieve electromagnetic shielding, the second carrier 300 can be retained as a whole, that is, it only needs to be ground until the second carrier 300 is exposed, so as to ensure the electromagnetic shielding effect.

[0098] See also Fig.16 In this embodiment, the second carrier 300 adopts a hollow plate structure, that is, the plurality of support legs 310 are all hollow tubular structures. After the top of the second carrier 300 is ground off, the plurality of hollow support legs 310 are exposed. The support legs 310 are hollow so that the plastic package 110 on both sides of the semiconductor device 130 has conductive holes 111. Of course, in other preferred embodiments of the present invention, the second carrier 300 may also adopt a solid structure, that is, the support legs 310 are columnar structures.

[0099] It should be noted that the top of the second carrier 300 here serves as a grinding stop layer, and the multiple support feet 310 here can serve as position markers to facilitate the subsequent cutting process. At the same time, the multiple support feet 310 can also serve as structural supports, so that the plastic package body 110 and the packaging structure will not be deformed in the subsequent process.

[0100] In this embodiment, the edge support pin 310 adopts a hollow design, which can reduce the accumulation of etching solution in the edge pad area during the subsequent etching process, avoid the impact of the generated oxide on the edge pad, and alleviate the problem of unstable grounding resistance.

[0101] S5 : exposing the semiconductor device 130 so that the semiconductor device 130 is exposed outside the plastic package 110 .

[0102] See also Figure 6Specifically, when performing step S5 in this embodiment, the method of peeling off the first carrier 200 can be adopted to expose the semiconductor device 130 to the plastic package 110. Specifically, after the grinding is completed, the first carrier 200 is turned over, and then UV light is irradiated to separate the adhesive layer 120 from the plastic package structure, that is, the first carrier 200 is separated from the plastic package 110 and the semiconductor device 130, so that the conductive pad 131 on the semiconductor device 130 is exposed at the bottom of the plastic package 110.

[0103] S6 : forming a wiring assembly layer 150 on one side of the plastic package body 110 .

[0104] See also Figures 7 to 13 Specifically, the wiring assembly layer 150 is electrically connected to the semiconductor device 130 , that is, the wiring assembly layer 150 is electrically connected to the exposed conductive pad 131 , and the wiring operation is completed by setting the wiring assembly layer 150 .

[0105] In this embodiment, the wiring combination layer 150 includes a first dielectric layer 151, a second dielectric layer 153 and a third dielectric layer 155. The first dielectric layer 151 is provided with a first metal layer 152, the second dielectric layer 153 is provided with a second metal layer 154, and the third dielectric layer 155 is provided with a third metal layer 156. The first metal layer 152 is electrically connected to the conductive pad 131, the second metal layer 154 is a wiring layer and is electrically connected to the first metal layer 152, and the third metal layer 156 is a conductive column and is electrically connected to the second metal layer 154. The wiring and pin extension steps are completed by providing the first metal layer 152, the second metal layer 154 and the third metal layer 156.

[0106] In this embodiment, the first metal layer 152, the second metal layer 154 and the third metal layer 156 are all made of copper materials with excellent electrical conductivity. At the same time, the first dielectric layer 151, the second dielectric layer 153 and the third dielectric layer 155 can also be made of one of silicon nitride, silicon oxynitride, polyimide, benzocyclobutene and the like.

[0107] It should be noted that, in this embodiment, since the support foot 310 adopts a hollow design, the hollow design can serve as a buffer (produce a certain displacement), reduce the displacement of the plastic package 110 caused by the patterning, exposure, and development processes of each dielectric layer when preparing the wiring assembly layer 150, and fully buffer the stress between the wiring assembly layer 150 and the plastic package 110.

[0108] In this embodiment, when step S6 is actually performed, the following steps may be adopted:

[0109] S61 : forming a first dielectric layer 151 on one side of the plastic package body 110 .

[0110] See also Figure 7 Specifically, the first dielectric layer 151 covers the semiconductor device 130, that is, covers the plastic package 110, and shields the conductive pad 131 on the semiconductor device 130. The first dielectric layer 151 can be formed by spin coating the dielectric layer, or by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0111] S62 : Grooving the first dielectric layer 151 to form a first groove 1511 .

[0112] See also Figure 8 Specifically, the first groove 1511 penetrates the first dielectric layer 151 and reaches the conductive pad 131. Here, the first dielectric layer 151 can be grooved by etching, and the groove positions correspond to the positions of the plurality of conductive pads 131, so that each conductive pad 131 is formed with a first groove 1511, and the first groove 1511 exposes the conductive pad 131 again. Of course, the first groove 1511 can also be formed on the first dielectric layer 151 by laser groove process, and during laser groove, the support foot 310 can also play a positioning role, thereby improving the groove accuracy of the first groove 1511.

[0113] S63 : forming a first metal layer 152 in the first groove 1511 .

[0114] See also Fig. 9 Specifically, the first metal layer 152 is electrically connected to the conductive pad 131. Specifically, the first metal layer 152 can be formed by electroplating in the first groove 1511 by electroplating, wherein the first metal layer 152 can be a copper layer. Of course, the copper layer here can also be prepared by a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), sputtering or chemical plating.

[0115] In this embodiment, the thickness of the first metal layer 152 is preferably equal to the depth of the first groove 1511 , so that the first metal layer 152 is flush with the surface of the first dielectric layer 151 .

[0116] S64 : forming a second dielectric layer 153 on a side of the first dielectric layer 151 away from the plastic package body 110 .

[0117] Specifically, the second dielectric layer 153 covers the first metal layer 152, that is, covers the first dielectric layer 151, and shields the first metal layer 152. The preparation process of the second dielectric layer 153 is the same as that of the first dielectric layer 151, and will not be described in detail here.

[0118] S65 : Grooving the second dielectric layer 153 to form a second groove 1531 .

[0119] See also Fig.10 Specifically, the second groove 1531 penetrates the second dielectric layer 153 and reaches the first metal layer 152. A patterned conductive layer can be formed on the second dielectric layer 153, that is, a patterned opening is formed by an exposure and development process, and then a groove is formed by an etching process to form the second groove 1531, wherein the groove position corresponds to the position of the plurality of first metal layers 152, so that a second groove 1531 is formed at each first metal layer 152, and the second groove 1531 exposes the first metal layer 152 again.

[0120] S66 : forming a second metal layer 154 in the second groove 1531 .

[0121] See also Fig.11 Specifically, the second metal layer 154 is electrically connected to the first metal layer 152. The preparation process of the second metal layer 154 is the same as that of the first metal layer 152, and will not be described in detail here. In this embodiment, the thickness of the second metal layer 154 is equivalent to the depth of the second groove 1531, so that the second metal layer 154 is flush with the surface of the second dielectric layer 153.

[0122] S67 : forming a third dielectric layer 155 on a side of the second dielectric layer 153 away from the plastic package body 110 .

[0123] Specifically, the third dielectric layer 155 covers the second metal layer 154, that is, covers the second dielectric layer 153, and shields the second metal layer 154. The preparation process of the third dielectric layer 155 is the same as that of the first dielectric layer 151, and will not be described in detail here.

[0124] S68 : Grooving the third dielectric layer 155 to form a third groove 1551 .

[0125] See also Fig.12 Specifically, the third groove 1551 penetrates the third dielectric layer 155 and reaches the second metal layer 154. Here, the third dielectric layer 155 can be grooved by laser or by etching, and the groove positions correspond to the positions of the plurality of second metal layers 154, so that each second metal layer 154 is provided with a third groove 1551, and the third groove 1551 exposes the second metal layer 154 again.

[0126] It should be noted that, since the support foot 310 here adopts a hollow design, the hollow design can act as a buffer (produce a certain displacement), reduce the displacement of the plastic package 110 caused by the heat generated by the laser grooving process, and fully buffer the stress between the wiring combination layer 150 and the plastic package 110.

[0127] S69 : forming a third metal layer 156 in the third groove 1551 .

[0128] See also Fig.13 Specifically, the third metal layer 156 is electrically connected to the second metal layer 154. In this embodiment, the third metal layer 156 is a copper column, which is formed by electroplating the copper column and protrudes from the third dielectric layer 155. A conductive column can be formed by electroplating in the third groove 1551, and the conductive column is protruding from the third dielectric layer 155.

[0129] S7: Planting balls on the side of the wiring assembly layer 150 away from the plastic package body 110 .

[0130] See also Fig.14 Specifically, a conventional ball implantation process is used to form solder balls 170 on the wiring assembly layer 150. The solder may be a tin-containing solder, such as SnAg or SnAgCu, so as to form solder balls on the wiring assembly layer 150. Of course, in other preferred embodiments of the present invention, the solder balls 170 may also be formed on the wiring assembly layer 150 by stencil printing.

[0131] After forming the third metal layer 156, step S7 is performed, that is, solder balls 170 are implanted on the third metal layer 156. By forming the copper pillars and forming a UBM layer at the bottom, the UBM layer can improve the welding performance of the solder balls 170.

[0132] S8 : Cutting the plastic package body 110 and the wiring assembly layer 150 along the area between the supporting pins 310 and the semiconductor device 130 .

[0133] See also Fig.15 Specifically, cutting track lines can be set on both sides of the support foot 310, and a cutting path is formed between the two cutting track lines. The width of the cutting path is greater than the width of the support foot 310. At this time, the support foot 310 can play a role in marking and positioning, and the support foot 310 needs to be removed during cutting. After cutting, a single product is formed, and the preparation of the fan-out packaging structure 100 is completed.

[0134] Please continue to see Fig.15The present embodiment further provides a fan-out packaging structure 100, which includes a plastic package 110, a semiconductor device 130 and a wiring assembly layer 150, wherein the wiring assembly layer 150 includes a first dielectric layer 151, a second dielectric layer 153 and a third dielectric layer 155, wherein the plastic package 110 is coated on the outside of the semiconductor device 130, the first dielectric layer 151 is arranged on one side of the plastic package 110, one side of the semiconductor device 130 is attached to the first dielectric layer 151, and a conductive pad 131 is arranged, the first dielectric layer 151 is arranged on the first metal layer 152, and the third dielectric layer 155 is arranged on the first dielectric layer 153. A metal layer 152 is connected to the conductive pad 131 battery core, a second dielectric layer 153 is arranged on a side of the first dielectric layer 151 away from the plastic package 110, a second metal layer 154 is arranged on the second dielectric layer 153, the second metal layer 154 is electrically connected to the first metal layer 152, a third dielectric layer 155 is arranged on a side of the second dielectric layer 153 away from the plastic package 110, a third metal layer 156 is arranged on the third dielectric layer 155, the third metal layer 156 is electrically connected to the second metal layer 154, and a solder ball 170 is arranged on the third metal layer 156.

[0135] In summary, the fan-out packaging method and fan-out packaging structure 100 provided in the present embodiment are provided with a semiconductor device 130 on a first carrier 200, and a second carrier 300 is mounted on the first carrier 200, the second carrier 300 is covered outside the semiconductor device 130, and a support foot 310 is provided, the support foot 310 is provided on the first carrier 200, and is located on both sides of the semiconductor device 130, and then the plastic encapsulation, wiring and ball planting are performed. By providing the second carrier 300, combined with the first carrier 200, strong support can be provided in the subsequent plastic encapsulation process, and the second carrier 300 can reduce the reflow impact during the plastic encapsulation, thereby preventing the plastic encapsulation body 110 from warping. In addition, the second carrier 300 is set outside the semiconductor device 130, the lower part of the semiconductor device 130 is shielded by the first carrier 200, and the upper part is shielded by the second carrier 300, so as to shield the dust during the preparation or transportation process, and avoid the ESD breakdown or defects in the package caused by the dust before the plastic packaging contacting the internal semiconductor device 130. In addition, the second carrier 300 can also be used as a clamping object during the transportation process to prevent the semiconductor device 130 from being touched and damaged, and realize the front grip of the wafer, which can avoid the wafer flip grip, and greatly improve the wafer processing efficiency.

[0136] Second embodiment

[0137] The present embodiment provides a fan-out packaging method for preparing a fan-out packaging structure 100, and the basic steps of the method are the same as those of the first embodiment. For matters not mentioned in the present embodiment, please refer to the first embodiment for details.

[0138] The difference between this embodiment and the first embodiment lies in step S6. In this embodiment, when step S6 is executed, the following steps may be specifically included:

[0139] S61 : forming a first dielectric layer 151 on one side of the plastic package body 110 .

[0140] Specifically, the first dielectric layer 151 covers the semiconductor device 130 and shields the conductive pad 131 on the semiconductor device 130. The first dielectric layer 151 may be formed by spin coating the dielectric layer, or by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0141] S62 : Grooving the first dielectric layer 151 to form a first groove 1511 .

[0142] Specifically, the first groove 1511 penetrates the first dielectric layer 151 and reaches the conductive pad 131 .

[0143] S63 : forming a first metal layer 152 in the first groove 1511 .

[0144] Specifically, the first metal layer 152 is electrically connected to the conductive pad 131 .

[0145] S64 : forming a second dielectric layer 153 on a side of the first dielectric layer 151 away from the plastic package body 110 .

[0146] Specifically, the second dielectric layer 153 covers the first metal layer 152 .

[0147] S65 : Grooving the second dielectric layer 153 to form a second groove 1531 .

[0148] Specifically, the second groove 1531 penetrates the second dielectric layer 153 and reaches the first metal layer 152 .

[0149] S66 : forming a second metal layer 154 in the second groove 1531 .

[0150] Specifically, the second metal layer 154 is electrically connected to the first metal layer 152 . After the second metal layer 154 is formed, the solder ball 170 may be directly disposed on the second metal layer 154 , thereby forming a single-layer RDL circuit.

[0151] Compared with the first embodiment, this embodiment omits steps S67-S69, so that the process is simplified, and at the same time, it can ensure the completion of the wiring action and electrical connection. Of course, in other preferred embodiments of the present invention, step S66 can be omitted again, and after the second groove 1531 is completed, the solder ball 170 is directly set in the second groove 1531, and the solder ball 170 protrudes from the second dielectric layer 153, and the wiring is realized through the first metal layer 152.

[0152] See also Fig.17 The present embodiment further provides a fan-out packaging structure 100, which includes a plastic package 110, a semiconductor device 130 and a wiring assembly layer 150, wherein the wiring assembly layer 150 includes a first dielectric layer 151 and a second dielectric layer 153, wherein the plastic package 110 is coated on the outside of the semiconductor device 130, the first dielectric layer 151 is arranged on one side of the plastic package 110, one side of the semiconductor device 130 is attached to the first dielectric layer 151, and a conductive pad 131 is arranged thereon, a first metal layer 152 is arranged on the first dielectric layer 151, the first metal layer 152 is connected to the conductive pad 131, the second dielectric layer 153 is arranged on the side of the first dielectric layer 151 away from the plastic package 110, a second metal layer 154 is arranged on the second dielectric layer 153, and a solder ball 170 is arranged on the second metal layer 154.

[0153] Third embodiment

[0154] The present embodiment provides a fan-out packaging method for preparing a fan-out packaging structure 100, and the basic steps of the method are the same as those of the first embodiment. For matters not mentioned in the present embodiment, please refer to the first embodiment for details.

[0155] The difference between this embodiment and the first embodiment lies in step S5 and step S6.

[0156] See also Fig.18 and Fig.19 In the present embodiment, during the step of exposing the semiconductor device 130 , ie, performing step S5 , a groove may be formed on the first carrier 200 to form a substrate groove 210 penetrating to the semiconductor device 130 .

[0157] Specifically, a groove is directly made on the first carrier 200, so that the semiconductor device 130 is exposed from the plastic package 110. Specifically, a substrate can be selected as the first carrier 200, and a base groove 210 is formed by directly making a groove on the substrate, and the base groove 210 passes through the conductive pad 131 on the semiconductor device 130, so that the semiconductor device 130 is exposed.

[0158] Furthermore, in this embodiment, since there is no need to peel off the first carrier 200 , the step of peeling off the first carrier 200 is omitted, thereby preventing the adhesive layer 120 from leaving residual adhesive on the surface of the plastic package 110 after peeling off the first carrier 200 to affect subsequent processes.

[0159] After forming the substrate groove 210 , the following steps need to be performed: forming a substrate metal layer 230 in the substrate groove 210 .

[0160] Specifically, the base metal layer 230 is electrically connected to the semiconductor device 130 , that is, the base metal layer 230 is electrically connected to the conductive pad 131 on the semiconductor device 130 .

[0161] Meanwhile, when executing step S6, the present embodiment may adopt the following steps:

[0162] S61 : forming a second dielectric layer 153 on a side of the first carrier 200 away from the plastic package body 110 .

[0163] S62 : Grooving the second dielectric layer 153 to form a second groove 1531 .

[0164] S63 : forming a second metal layer 154 in the second groove 1531 .

[0165] S64 : forming a third dielectric layer 155 on a side of the second dielectric layer 153 away from the plastic package body 110 .

[0166] S65 : Grooving the third dielectric layer 155 to form a third groove 1551 .

[0167] S66 : forming a third metal layer 156 in the third groove 1551 .

[0168] Compared with the first embodiment, the step of disposing the first dielectric layer 151 is omitted in this embodiment, and the first dielectric layer 151 in the first embodiment is replaced by the first carrier 200 , thereby saving materials and reducing the process flow.

[0169] The present embodiment further provides a fan-out packaging structure 100 . Compared with the first embodiment, in the fan-out packaging structure 100 of the present embodiment, the first dielectric layer 151 is replaced by the first carrier 200 , and the first metal layer 152 is replaced by the base metal layer 230 .

[0170] Fourth embodiment

[0171] The present embodiment provides a fan-out packaging method for preparing a fan-out packaging structure 100, and the basic steps of the method are the same as those of the first embodiment. For matters not mentioned in the present embodiment, please refer to the first embodiment for details.

[0172] The fan-out packaging method provided in this embodiment includes the following steps:

[0173] S1 : mounting the semiconductor device 130 on the first carrier 200 .

[0174] See also Fig. 20 In this embodiment, a conductive pad 131 for achieving electrical connection is disposed on the semiconductor device 130 , and the conductive pad 131 is disposed upward, that is, the conductive pad 131 on the semiconductor device 130 is disposed away from the first carrier 200 .

[0175] S2: Mount the second carrier 300 provided with supporting legs 310 on the first carrier 200.

[0176] S3: Forming a plastic package body 110 by plastic packaging on the first carrier 200 .

[0177] S4: Grinding the plastic package body 110 until the supporting feet 310 are exposed.

[0178] It should be noted that the basic operations of step S1 to step S4 in this embodiment are the same as those in the first embodiment, except that in step S1 the semiconductor device 130 is arranged upward.

[0179] S5 : exposing the semiconductor device 130 so that the semiconductor device 130 is exposed outside the plastic package 110 .

[0180] See also Fig.21 Specifically, when performing step S5 in this embodiment, a plastic sealing groove 113 can be formed on one side surface of the plastic sealing body 110, and the plastic sealing groove 113 penetrates to the semiconductor device 130, so that the semiconductor device 130 is exposed from the plastic sealing body 110. That is, the conductive pad 131 on the semiconductor is exposed.

[0181] It should be noted that, before step S5, the first carrier 200 needs to be peeled off, so as to make the entire structure more streamlined. Of course, the first carrier 200 may not be peeled off and may be retained in the packaging structure.

[0182] In this embodiment, since the molding groove 113 is formed by directly slotting the molding body 110, the molding groove passes through the semiconductor device 130, so that after the first carrier 200 is peeled off, the residual glue of the adhesive layer 120 will not affect the semiconductor device 130 or the subsequent wiring.

[0183] It should also be noted that the adhesive layer 120 in this embodiment is made of heat dissipation adhesive. After peeling off the first carrier 200, on the one hand, the adhesive layer 120 can play a role in heat dissipation, and on the other hand, the adhesive layer 120 can effectively protect the semiconductor device 130 to prevent the semiconductor device 130 from being directly exposed to the outside.

[0184] See also Fig. 22 After the molding groove 113 is completed, a molding metal layer 115 can be formed in the molding groove 113. The molding metal layer 115 is electrically connected to the semiconductor device 130. In this embodiment, a conductive pad 131 is provided on the surface of the semiconductor device 130 away from the first carrier 200. Therefore, the molding metal layer 115 is electrically connected to the conductive pad 131 on the semiconductor device 130.

[0185] S6 : forming a wiring assembly layer 150 on one side of the plastic package body 110 .

[0186] When step S6 is actually performed, steps S61 to S63 in the first embodiment may be omitted, and the second dielectric layer 153 may be directly formed on the plastic package body 110 .

[0187] S7: Planting balls on the side of the wiring assembly layer 150 away from the plastic package body 110 .

[0188] S8 : Cutting the plastic package body 110 and the wiring assembly layer 150 along the area between the supporting pins 310 and the semiconductor device 130 .

[0189] In summary, the difference between this embodiment and the first embodiment is that the semiconductor device 130 is arranged upward, and a groove is directly opened on the plastic package body 110 to replace the first dielectric layer 151 in the first embodiment, which simplifies the process steps and saves materials.

[0190] At the same time, see Fig.23 The present embodiment further provides a fan-out package structure 100, which includes a plastic package 110, a semiconductor device 130 and a wiring assembly layer 150, wherein the wiring assembly layer 150 includes a second dielectric layer 153 and a third dielectric layer 155, the plastic package 110 is coated on the outside of the semiconductor device 130, the semiconductor device 130 is arranged upward, so that the conductive pad 131 is arranged upward, a plastic package metal layer 115 is arranged on the plastic package 110, and the plastic package metal layer 115 is electrically connected to the conductive pad 131, a second dielectric layer 153 is arranged on the grooved side of the plastic package 110, a second metal layer 154 is arranged on the second dielectric layer 153, and the second metal layer 154 is electrically connected to the plastic package metal layer 115, and a third metal layer 156 is arranged on the side of the second dielectric layer 153 away from the plastic package 110, and the third metal layer 156 is electrically connected to the second metal layer 154. A solder ball 170 is arranged on the third metal layer 156.

[0191] Fifth embodiment

[0192] The present embodiment provides a fan-out packaging method for preparing a fan-out packaging structure 100, and the basic steps of the method are the same as those of the third embodiment. For matters not mentioned in the present embodiment, please refer to the third embodiment for details.

[0193] The difference between this embodiment and the third embodiment lies in step S1.

[0194] See also Fig.24 and Fig.25 In this embodiment, when executing step S1, it is first necessary to form a mounting groove 250 by cutting a groove in the first carrier 200, and then adaptively install the semiconductor device 130 in the mounting groove 250. The subsequent steps are the same as those in the first embodiment.

[0195] Compared with the third embodiment, this embodiment can reduce the overall packaging height and the packaging size by making grooves on the first carrier 200. On the other hand, in the subsequent step of forming the substrate groove 210, the groove depth becomes shallower, which reduces the difficulty of making grooves and makes it easier to form the substrate groove 210.

[0196] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A fan-out packaging method, characterized in that: include: Mounting a semiconductor device on a first carrier; Mounting a second carrier provided with supporting feet on the first carrier, and making the second carrier cover outside the semiconductor device, the supporting feet being provided on the first carrier and being located on both sides of the semiconductor device; Plastic-sealing the first carrier to form a plastic-sealed body, so that the plastic-sealed body covers the semiconductor device, and the second carrier is embedded in the plastic-sealed body; Exposing the semiconductor device so that the semiconductor device is exposed from the plastic package; A wiring assembly layer is formed on one side of the plastic package, wherein the wiring assembly layer is electrically connected to the semiconductor device; Planting balls on a side of the wiring assembly layer away from the plastic package body to form solder balls on the wiring assembly layer; Wherein, before the step of exposing the semiconductor device, the method further comprises: Grinding the plastic package body until the supporting feet are exposed; Wherein, the supporting feet are hollow, so that conducting holes are formed on the plastic package body at both sides of the semiconductor device.

2. The fan-out packaging method according to claim 1, characterized in that: The step of exposing the semiconductor device comprises: Peeling off the first carrier to expose the semiconductor device from the plastic package; Wherein, a conductive pad is disposed on a surface of the semiconductor device on one side for mounting the first carrier.

3. The fan-out packaging method according to claim 2, characterized in that: The step of forming a wiring assembly layer on one side of the plastic package body comprises: Forming a first dielectric layer on one side of the plastic package, wherein the first dielectric layer covers the semiconductor device; Grooving the first dielectric layer to form a first groove, wherein the first groove penetrates the first dielectric layer and reaches the conductive pad; forming a first metal layer in the first groove, wherein the first metal layer is electrically connected to the conductive pad; forming a second dielectric layer on a side of the first dielectric layer away from the plastic package body, wherein the second dielectric layer covers the first metal layer; Grooving the second dielectric layer to form a second groove, wherein the second groove penetrates the second dielectric layer and reaches the first metal layer; forming a second metal layer in the second groove, wherein the second metal layer is electrically connected to the first metal layer; forming a third dielectric layer on a side of the second dielectric layer away from the plastic package body, wherein the third dielectric layer covers the second metal layer; Grooving the third dielectric layer to form a third groove, wherein the third groove penetrates the third dielectric layer and reaches the second metal layer; forming a third metal layer in the third groove, wherein the third metal layer is electrically connected to the second metal layer; Wherein, the third metal layer is used to set the solder balls.

4. The fan-out packaging method according to claim 3, characterized in that: The step of forming a third metal layer in the third groove comprises: A conductive column is formed by electroplating in the third groove, and the conductive column is protruded from the third dielectric layer.

5. The fan-out packaging method according to claim 2, characterized in that: The step of forming a wiring assembly layer on one side of the plastic package body comprises: Forming a first dielectric layer on one side of the plastic package, wherein the first dielectric layer covers the semiconductor device; Grooving the first dielectric layer to form a first groove, wherein the first groove penetrates the first dielectric layer and reaches the conductive pad; forming a first metal layer in the first groove, wherein the first metal layer is electrically connected to the conductive pad; forming a second dielectric layer on a side of the first dielectric layer away from the plastic package body, wherein the second dielectric layer covers the first metal layer; Grooving the second dielectric layer to form a second groove, wherein the second groove penetrates the second dielectric layer and reaches the first metal layer; forming a second metal layer in the second groove, wherein the second metal layer is electrically connected to the first metal layer; Wherein, the second metal layer is used to set the solder ball.

6. The fan-out packaging method according to claim 1, characterized in that: The step of exposing the semiconductor device comprises: Cutting a groove on the first carrier to form a base groove penetrating to the semiconductor device so that the semiconductor device is exposed from the plastic package; forming a base metal layer in the base groove, wherein the base metal layer is electrically connected to the semiconductor device; Wherein, a conductive pad is arranged on a surface of one side of the semiconductor device for mounting the first carrier.

7. The fan-out packaging method according to claim 1, characterized in that: The step of exposing the semiconductor device comprises: A plastic sealing groove is formed on one side surface of the plastic sealing body, wherein the plastic sealing groove passes through the semiconductor device so that the semiconductor device is exposed from the plastic sealing body; Forming a plastic encapsulation metal layer in the plastic encapsulation groove, wherein the plastic encapsulation metal layer is electrically connected to the semiconductor device; Wherein, a conductive pad is disposed on a surface of the semiconductor device which is away from the first carrier.

8. The fan-out packaging method according to claim 1, characterized in that: After the step of planting a ball on a side of the wiring assembly layer away from the plastic package body, the method further includes: The plastic package body and the wiring assembly layer are cut along the area between the supporting foot and the semiconductor device.

9. The fan-out packaging method according to claim 1, characterized in that: Before the step of mounting the semiconductor device on the first carrier, the method further comprises: A mounting groove is formed on the first carrier, and the mounting groove is used to adaptively mount a semiconductor device.

10. A fan-out packaging structure, characterized in that: It is prepared by the fan-out packaging method as described in any one of claims 1 to 9.

Images