Display device

Abstract

A display device includes: a first pixel region in which a first pixel is positioned and a second pixel region in which a second pixel region is positioned, and the display device may include a lower connecting line, which connects the first pixel and the second pixel and spans the first pixel region and the second pixel region; an inorganic insulating layer, which is arranged on the lower connecting line and has a groove between the first pixel region and the second pixel region; and an organic insulating layer, which fills the groove of the inorganic insulating layer.

Description

Technical Field

[0001] The present invention relates to a display device and more particularly to a display device that resists external impact. Background Art

[0002] Generally, a display device may include a light emitting element and a circuit element for controlling an electrical signal applied to the light emitting element. The circuit element may include a transistor, a capacitor, or a wire, etc.

[0003] In order to accurately control whether a light-emitting element emits light and the degree of light emission, the number of transistors electrically connected to a light-emitting element increases, and the number of lines that transmit electrical signals to the transistors also increases. Therefore, research is actively being conducted on methods for achieving high integration of display devices and reducing the occurrence of defects. Summary of the invention

[0004] Technical issues

[0005] An object of the present invention is to provide a display device capable of resisting external impact.

[0006] However, the objects of the present invention are not limited to these objects, and various extensions can be made without departing from the spirit and scope of the present invention.

[0007] Technical Solution

[0008] In order to achieve the above-mentioned purpose of the present invention, the display device may include: a first pixel area, a first pixel is positioned on the first pixel area; a second pixel area, a second pixel is positioned on the second pixel area; a lower connecting line, the lower connecting line connects the first pixel and the second pixel and spans the first pixel area and the second pixel area; an inorganic insulating layer, the inorganic insulating layer is arranged on the lower connecting line and has a groove between the first pixel area and the second pixel area; and an organic insulating layer, the organic insulating layer fills the groove of the inorganic insulating layer.

[0009] In an embodiment, the lower connection line may extend along a first direction, and the groove of the inorganic insulating layer may extend along a second direction crossing the first direction.

[0010] In an embodiment, the first pixel and the second pixel may include a first conductive line and a second conductive line disposed on the lower connecting line, respectively, and the organic insulating layer is between the first conductive line and the second conductive line.

[0011] In an embodiment, the first conductive line and the second conductive line may be connected via the lower connecting line.

[0012] In an embodiment, the lower connection line may be configured to transmit a scan signal or an emission control signal.

[0013] In an embodiment, the first pixel and the second pixel may include a third wire and a fourth wire respectively disposed on the first wire and the second wire, with the organic insulating layer being between the third wire and the fourth wire.

[0014] In an embodiment, the third conductive line and the fourth conductive line may be connected via the lower connecting line.

[0015] In an embodiment, the lower connection line may be configured to transmit an initialization voltage.

[0016] In an embodiment, the lower connection line may include: a first lower connection line connecting the first conductive line and the second conductive line; and a second lower connection line connecting the third conductive line and the fourth conductive line.

[0017] In an embodiment, an elongation rate of the lower connecting wire may be greater than an elongation rate of the third conductive wire and an elongation rate of the fourth conductive wire.

[0018] In an embodiment, an elongation rate of the lower connecting wire may be greater than an elongation rate of the first conductive wire and an elongation rate of the second conductive wire.

[0019] In an embodiment, the display device may further include: a third pixel area, a third pixel is positioned on the third pixel area; and an upper connecting line, which is arranged on the inorganic insulating layer and the organic insulating layer, connecting the first pixel and the third pixel, and spanning the first pixel area and the third pixel area.

[0020] In an embodiment, the groove of the inorganic insulating layer may extend along a first direction. The upper connection line may extend along a second direction crossing the first direction.

[0021] In an embodiment, the upper connection line may be configured to transmit a data voltage or a power voltage.

[0022] In an embodiment, the melting point of the lower connection line may be greater than the melting point of the upper connection line.

[0023] In order to achieve the above-mentioned purpose of the present invention, the display device may include: a first pixel area and a second pixel area; a substrate; a first lower connecting line, which is arranged on the substrate and crosses the first pixel area and the second pixel area; a first inorganic insulating layer, which is arranged on the first lower connecting line and has a first opening between the first pixel area and the second pixel area; a first conductive line, which is arranged on the first inorganic insulating layer in the first pixel area and contacts the first lower connecting line through a first contact hole passing through the first inorganic insulating layer; a second conductive line, which is arranged on the first inorganic insulating layer in the second pixel area and contacts the first lower connecting line through a second contact hole passing through the first inorganic insulating layer; a second inorganic insulating layer, which is arranged on the first conductive line and the second conductive line and has a second opening overlapping with the first opening; and an organic insulating layer, which fills the first opening of the first inorganic insulating layer and the second opening of the second inorganic insulating layer.

[0024] In an embodiment, the display device may further include: a second lower connecting line, which is arranged on the same layer as the first lower connecting line and spans the first pixel region and the second pixel region; a third conductive line, which is arranged on the second inorganic insulating layer in the first pixel region and contacts the second lower connecting line through a third contact hole passing through the first inorganic insulating layer and the second inorganic insulating layer; and a fourth conductive line, which is arranged on the second inorganic insulating layer in the second pixel region and contacts the second lower connecting line through a fourth contact hole passing through the first inorganic insulating layer and the second inorganic insulating layer.

[0025] In an embodiment, the display device may further include: a third pixel region; and an upper connection line, the upper connection line being disposed on the second inorganic insulating layer and crossing the first pixel region and the third pixel region.

[0026] In order to achieve the above-mentioned purpose of the present invention, the display device may include: a plurality of pixel regions; a lower connecting line, which spans the plurality of pixel regions; an inorganic insulating layer, which is arranged on the lower connecting line and has grooves between the plurality of pixel regions; and an organic insulating layer, which fills the grooves of the inorganic insulating layer.

[0027] In an embodiment, the organic insulating layer may surround at least a portion of the plurality of pixel regions in a plan view.

[0028] In an embodiment, the organic insulating layer may surround each of the plurality of pixel regions in a plan view.

[0029] In an embodiment, the display device may further include an upper connection line, which is disposed on the inorganic insulating layer and the organic insulating layer, spans across the plurality of pixel regions, and intersects the lower connection line.

[0030] In order to achieve the above-mentioned purpose of the present invention, the display device may include a first pixel area and a second pixel area, the first pixel is positioned on the first pixel area, the second pixel is positioned on the second pixel area, the first pixel and the second pixel are each defined by an opening of a pixel defining layer, and the emission layer is positioned between the pixel electrode and the counter electrode in the opening of the pixel defining layer; a substrate; a lower connecting line, the lower connecting line is arranged on the substrate and spans the first pixel area and the second pixel area; an inorganic insulating layer, the inorganic insulating layer is arranged on the lower connecting line and has a groove between the first pixel area and the second pixel area; and an organic insulating layer, the organic insulating layer is arranged between the lower connecting line and the pixel defining layer and fills the groove of the inorganic insulating layer.

[0031] Effects of the Invention

[0032] In the display device according to the embodiment of the present invention, since a lower connection line electrically connecting the pixels is arranged under the organic insulating layer filling the groove of the inorganic insulating layer between the pixels, the flexibility of the display device is increased, and a display device resistant to external impact can be realized.

[0033] However, the effects of the present invention are not limited to the above-described effects, and various extensions can be made without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a plan view showing a display device according to an embodiment.

[0035] Figure 2 It is shown Figure 1 Block diagram of a display device in FIG.

[0036] Figure 3 is shown to be included in Figure 1 Circuit diagram of a pixel in a display device in FIG.

[0037] Figure 4 is shown to be included in Figure 1 Layout diagram of adjacent pixels in a display device.

[0038] Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 It shows that for Figure 4 A diagram showing the layout of components on each layer.

[0039] Fig.10 It is shown Figure 4 A cross-sectional view of a portion between a first pixel region and a second pixel region in FIG.

[0040] Fig.11 It is shown Figure 4 A cross-sectional view of another portion between the first pixel region and the second pixel region.

[0041] Fig.12 It is shown Figure 4 A cross-sectional view of a portion between the first pixel region and the third pixel region in FIG.

[0042] Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment.

[0043] Fig.18 and Fig.19 is a plan view showing a display device according to an embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, a display device according to an embodiment of the present invention will be explained in detail with reference to the accompanying drawings.

[0045] Figure 1 is a plan view showing a display device 1 according to the embodiment.

[0046] Reference Figure 1 , the display device 1 may include a display area DA and a peripheral area PA outside the display area DA. For example, the peripheral area PA may surround the display area DA. The display area DA may include a plurality of pixels PX (see Figure 2 ) are respectively disposed in a plurality of pixel areas PXA therein. Lines transmitting electrical signals applied to the display area DA may be disposed in the peripheral area PA.

[0047] Figure 2 It is shown Figure 1 1 is a block diagram of the display device 1.

[0048] Reference Figure 1 and Figure 2 The display device 1 may include: a display unit 10 including a plurality of pixels PX, a scan driver 20 , a data driver 30 , and an emission control driver 40 ; and a controller 50 .

[0049] The display unit 10 may be disposed in a display area DA, and may include a plurality of pixels PX positioned at the intersection of a plurality of scan lines SL1, SL2, SL3, ..., SLn-1, SLn to SLn+1, a plurality of data lines DL1, DL2, ... to DLm, and a plurality of emission control lines EL1, EL2, ... to ELn. Therefore, a plurality of pixels PX may be arranged in a basic matrix form. The scan lines SL1 to SLn+1 and the emission control lines EL1 to ELn may extend in a first direction DR1 as a row direction, and the data lines DL1 to DLm and the first power supply voltage line ELVDDL may extend in a second direction DR2 as a column direction. Each pixel PX may include a light emitting element such as an organic light emitting diode (OLED).

[0050] Each pixel PX may be connected to three scan lines among the scan lines SL1 to SLn+1. The scan driver 20 may transmit three scan signals to each pixel PX through the scan lines SL1 to SLn+1. In other words, the scan driver 20 may sequentially supply scan signals to the scan lines SL2 to SLn, the front scan lines SL1 to SLn-1, and the rear scan lines SL3 to SLn+1.

[0051] Each pixel PX may be connected to one of the data lines DL1 to DLm. The data driver 30 may transmit a data voltage (or a data signal) to each pixel PX through the data lines DL1 to DLm. When a scan signal is supplied to the scan lines SL2 to SLn, the data voltage may be supplied to the pixel PX selected by the scan signal.

[0052] Each pixel PX may be connected to one of the emission control lines EL1 to ELn. The emission control driver 40 may transmit an emission control signal to each pixel PX through the emission control lines EL1 to ELn. The emission control signal may control the emission time of the pixel PX. The emission control driver 40 may be omitted according to the internal structure of the pixel PX.

[0053] The controller 50 may convert a plurality of image signals IR, IG, and IB transmitted from the outside into a plurality of image data signals DR, DG, and DB, and transmit the converted image data signals DR, DG, and DB to the data driver 30. In addition, the controller 50 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, and may generate control signals for controlling the scan driver 20, the data driver 30, and the emission control driver 40. In other words, the controller 50 may generate a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and an emission drive control signal ECS for controlling the emission control driver 40.

[0054] Each pixel PX may receive a first power voltage ELVDD and a second power voltage ELVSS from an external power source. The first power voltage ELVDD may be a predetermined high level voltage, and the second power voltage ELVSS may be a voltage lower than the first power voltage ELVDD or a ground voltage. The first power voltage ELVDD may be supplied to each pixel PX through a first power voltage line ELVDDL. The initialization voltage line IL may receive an initialization voltage VINT from an external power source and supply the initialization voltage VINT to each pixel PX.

[0055] Each pixel PX may emit light having predetermined brightness by a driving current supplied to the light emitting element according to a data voltage transmitted through the data lines DL1 to DLm.

[0056] Figure 3 is shown to be included in Figure 1 0 is a circuit diagram of a pixel PX in the display device 1 in FIG.

[0057] Reference Figure 3 , each pixel PX may include: signal lines 151, 152, 153 and 181; a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to the signal lines 151, 152, 153 and 181; a storage capacitor Cst; an initialization voltage line 164; a first power supply voltage line 182; and a light emitting element EE.

[0058] Figure 3 The signal lines 151, 152, 153 and 181, the initialization voltage line 164 and the first power supply voltage line 182 provided for each pixel PX are shown, however, the present invention is not limited thereto. In another embodiment, at least one of the signal lines 151, 152, 153 and 181 and / or the initialization voltage line 164 can be shared by adjacent pixels.

[0059] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may include a driving transistor T1 , a switching transistor T2 , a compensation transistor T3 , a first initialization transistor T4 , an operation control transistor T5 , an emission control transistor T6 , and a second initialization transistor T7 .

[0060] The signal lines 151, 152, 153, and 181 may include a scan line 151 transmitting a scan signal Sn to the switching transistor T2 and the compensation transistor T3, a front scan line 152 transmitting a front scan signal Sn-1 to the first initialization transistor T4 and the second initialization transistor T7, an emission control line 153 transmitting an emission control signal En to the operation control transistor T5 and the emission control transistor T6, and a data line 181 crossing the scan line 151 and transmitting a data voltage Dm. The first power supply voltage line 182 may transmit a first power supply voltage ELVDD to the driving transistor T1, and the initialization voltage line 164 may transmit an initialization voltage VINT for initializing the driving transistor T1 and the anode of the light emitting element EE.

[0061] The driving gate electrode G1 of the driving transistor T1 can be connected to the first electrode Cst1 of the storage capacitor Cst, the driving source electrode S1' of the driving transistor T1 can be connected to the first power supply voltage line 182 via the operation control transistor T5, and the driving drain electrode D1' of the driving transistor T1 can be electrically connected to the anode of the light emitting element EE via the emission control transistor T6. The driving transistor T1 can receive the data voltage Dm according to the switching operation of the switching transistor T2 and drive the driving current I EE Supplied to the light emitting element EE.

[0062] The switching gate electrode G2 of the switching transistor T2 may be connected to the scan line 151, the switching source electrode S2' of the switching transistor T2 may be connected to the data line 181, and the switching drain electrode D2' of the switching transistor T2 may be connected to the driving source electrode S1' of the driving transistor T1, and connected to the first power supply voltage line 182 via the operation control transistor T5. The switching transistor T2 may perform a switching operation in which the switching transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, and the data voltage Dm transmitted through the data line 181 is transmitted to the driving source electrode S1' of the driving transistor T1.

[0063] The compensation gate electrode G3 of the compensation transistor T3 may be connected to the scan line 151, the compensation source electrode S3' of the compensation transistor T3 may be connected to the driving drain electrode D1' of the driving transistor T1 and to the anode of the light emitting element EE via the emission control transistor T6, and the compensation drain electrode D3' of the compensation transistor T3 may be connected to the first electrode Cst1 of the storage capacitor Cst, the first initialization source electrode S4' of the first initialization transistor T4, and the driving gate electrode G1 of the driving transistor T1. The compensation transistor T3 may be turned on according to the scan signal Sn transmitted through the scan line 151, and the driving gate electrode G1 and the driving drain electrode D1' of the driving transistor T1 are electrically connected so as to diode-connect the driving transistor T1.

[0064] A first initialization gate electrode G4 of the first initialization transistor T4 may be connected to the front scan line 152, a first initialization drain electrode D4' of the first initialization transistor T4 may be connected to the second initialization drain electrode D7' of the second initialization transistor T7 and the initialization voltage line 164, and a first initialization source electrode S4' of the first initialization transistor T4 may be connected to the first electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3' of the compensation transistor T3, and the driving gate electrode G1 of the driving transistor T1. The first initialization transistor T4 may perform an initialization operation in which the first initialization transistor T4 is turned on according to the front scan signal Sn-1 transmitted through the front scan line 152, and the initialization voltage VINT is transmitted to the driving gate electrode G1 of the driving transistor T1 to initialize the voltage of the driving gate electrode G1 of the driving transistor T1.

[0065] The operation control gate electrode G5 of the operation control transistor T5 can be connected to the emission control line 153, the operation control source electrode S5' of the operation control transistor T5 can be connected to the first power supply voltage line 182, and the operation control drain electrode D5' of the operation control transistor T5 can be connected to the driving source electrode S1' of the driving transistor T1 and the switching drain electrode D2' of the switching transistor T2.

[0066] The emission control gate electrode G6 of the emission control transistor T6 can be connected to the emission control line 153, the emission control source electrode S6' of the emission control transistor T6 can be connected to the driving drain electrode D1' of the driving transistor T1 and the compensation source electrode S3' of the compensation transistor T3, and the emission control drain electrode D6' of the emission control transistor T6 can be connected to the second initialization source electrode S7' of the second initialization transistor T7 and the anode of the light emitting element EE.

[0067] According to the emission control signal En transmitted through the emission control line 153, the operation control transistor T5 and the emission control transistor T6 may be turned on at the same time, and thus, the first power supply voltage ELVDD may be transmitted to the light emitting element EE so that the driving current I EE can flow through the light emitting element EE.

[0068] The second initialization gate electrode G7 of the second initialization transistor T7 may be connected to the front scan line 152, the second initialization source electrode S7' of the second initialization transistor T7 may be connected to the emission control drain electrode D6' of the emission control transistor T6 and the anode of the light emitting element EE, and the second initialization drain electrode D7' of the second initialization transistor T7 may be connected to the first initialization drain electrode D4' of the first initialization transistor T4 and the initialization voltage line 164. The second initialization transistor T7 may be turned on according to the front scan signal Sn-1 transmitted through the front scan line 152 to initialize the anode of the light emitting element EE.

[0069] Figure 3 The first initialization transistor T4 and the second initialization transistor T7 are shown to be connected to the front scan line 152, however, the present invention is not limited thereto. In another embodiment, the first initialization transistor T4 may be connected to the front scan line 152 and driven according to the front scan signal Sn-1, and the second initialization transistor T7 may be connected to a separate signal line (e.g., a rear scan line) and driven according to a signal transmitted to the separate signal line. The transistor type (p-type or n-type) may be changed. Figure 3 The positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 in the.

[0070] A specific operation of each pixel PX according to the embodiment is as follows.

[0071] During the initialization period, when the front scan signal Sn- 1 is supplied through the front scan line 152 , the initialization transistor T4 may be turned on in response to the front scan signal Sn- 1 , and the driving transistor T1 may be initialized by the initialization voltage VINT supplied from the initialization voltage line 164 .

[0072] During the data programming period, when the scan signal Sn is supplied through the scan line 151, the switching transistor T2 and the compensation transistor T3 may be turned on in response to the scan signal Sn. In this case, the driving transistor T1 may be diode-connected and forward biased by the turned-on compensation transistor T3.

[0073] Then, a compensation voltage (Dm+Vth, Vth is a negative value) by which the data voltage Dm supplied from the data line 181 lowers the threshold voltage Vth of the driving transistor T1 may be applied to the driving gate electrode G1 of the driving transistor T1. In this case, the first power supply voltage ELVDD and the compensation voltage Dm+Vth may be applied to the opposite electrodes Cst1 and Cst2 of the storage capacitor Cst, and charges corresponding to the voltage difference between the opposite electrodes Cst1 and Cst2 may be stored in the storage capacitor Cst.

[0074] During the emission period, the operation control transistor T5 and the emission control transistor T6 may be turned on by the emission control signal En supplied from the emission control line 153. The driving current I may be generated according to the voltage difference between the voltage of the driving gate electrode G1 of the driving transistor T1 and the first power supply voltage ELVDD. EE , and the driving current I EE It can be supplied to the light emitting element EE through the emission control transistor T6.

[0075] Figure 4 is shown to be included in Figure 1 Layout diagram of adjacent pixels PX in the display device 1.

[0076] Reference Figure 4 , the display area DA of the display device 1 may include a plurality of pixel areas PXA1, PXA2, and PXA3 on which a plurality of pixels PX1, PX2, and PX3 are respectively arranged. The pixel areas PXA1, PXA2, and PXA3 may be arranged in a basic matrix form along a first direction DR1 and a second direction DR2. The pixel areas PXA1, PXA2, and PXA3 may include: a first pixel area PXA1 on which a first pixel PX1 is arranged; a second pixel area PXA2, which is positioned in the first direction DR1 from the first pixel area PXA1 and on which a second pixel PX2 is arranged; and a third pixel area PXA3, which is positioned in the second direction DR2 from the first pixel area PXA1 and on which a third pixel PX3 is arranged. Transistors T1 to T7 may be arranged in each of the pixel areas PXA1, PXA2, and PXA3.

[0077] Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 It shows that for Figure 4 A diagram showing the layout of components on each layer. Fig.10 It is shown Figure 4 2 is a cross-sectional view of a portion between the first pixel area PXA1 and the second pixel area PXA2. Fig.11 It is shown Figure 42 is a cross-sectional view of another portion between the first pixel area PXA1 and the second pixel area PXA2. Fig.12 It is shown Figure 4 A cross-sectional view of a portion between the first pixel region PXA1 and the third pixel region PXA3 in FIG. Figures 4 to 12 Describe in detail.

[0078] Reference Figures 4 to 12 The display device 1 may include a substrate 100, a lower connection line 120 disposed on the substrate 100, an inorganic insulating layer 130 disposed on the lower connection line 120 and having a groove GR between the pixel areas PXA1, PXA2 and PXA3, an organic insulating layer 170 filling the groove GR of the inorganic insulating layer 130, and an upper connection line 180 disposed on the inorganic insulating layer 130 and the organic insulating layer 170.

[0079] The substrate 100 may include glass, metal or plastic. In an embodiment, the substrate 100 may include a material having a flexible or bendable property. When the substrate 100 has a flexible or bendable property, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate 100 may have a single-layer structure or a multi-layer structure of the above-mentioned materials, and may also include an inorganic layer in the case of a multi-layer structure. In an embodiment, the substrate 100 may have an organic / inorganic / organic structure.

[0080] The barrier layer 110 may be disposed on the substrate 100. The barrier layer 110 may prevent or minimize upward penetration of impurities from the substrate 100. The barrier layer 110 may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single layer or multilayer structure.

[0081] The lower connection line (or first conductive layer) 120 may be disposed on the barrier layer 110. The lower connection line 120 may connect pixels arranged in the first direction DR1. For example, the lower connection line 120 may connect the first pixel PX1 and the second pixel PX2. The lower connection line 120 may be used as a line for transmitting an electrical signal to the pixels arranged in the first direction DR1. Since the lower connection line 120 connects the pixels arranged in the first direction DR1, the lower connection line 120 may extend relatively long. Therefore, stress may be applied to the lower connection line 120.

[0082] The lower connection line 120 may include a material having a high elongation. Therefore, defects in the lower connection line 120 such as cracks in the lower connection line 120 or disconnection of the lower connection line 120 may not occur. In an embodiment, the elongation of the lower connection line 120 may be greater than the elongation of the conductive layer disposed inside the inorganic insulating layer 130.

[0083] In an embodiment, after the lower connection line 120 is formed on the substrate 100, the semiconductor layer 140 may be formed on the lower connection line 120. In addition, a high temperature process for thermally treating the semiconductor layer 140 may be performed before forming the upper connection line 180. Therefore, the lower connection line 120 may be exposed to the high temperature process for thermally treating the semiconductor layer 140.

[0084] The lower connection line 120 may include a material having a high melting point. Therefore, damage to the connection line 120 caused by a high temperature process can be prevented. For example, the lower connection line 120 may include a metal having a relatively high melting point such as molybdenum (Mo) or titanium (Ti). The lower connection line 120 may have a multilayer structure. For example, the lower connection line 120 may have a multilayer structure of Ti-TiN. In an embodiment, the melting point of the lower connection line 120 may be greater than the melting point of the upper connection line 180.

[0085] The lower connection lines 120 may include scan connection lines 121, front scan connection lines 122, emission control connection lines 123, initialization voltage connection lines 124, and mesh connection lines 125. The scan connection lines 121, front scan connection lines 122, emission control connection lines 123, initialization voltage connection lines 124, and mesh connection lines 125 may include the same material.

[0086] The scan connection line 121 may connect the scan line 151 of the first pixel PX1 and the scan line 151 of the second pixel PX2. The scan connection line 121 may extend in the first direction DR1 while overlapping the scan line 151 of the first pixel PX1 and the scan line 151 of the second pixel PX2.

[0087] The front scan connection line 122 may connect the front scan line 152 of the first pixel PX1 and the front scan line 152 of the second pixel PX2. The front scan connection line 122 may extend in the first direction DR1 while overlapping the front scan line 152 of the first pixel PX1 and the front scan line 152 of the second pixel PX2.

[0088] The emission control connection line 123 may connect the emission control line 153 of the first pixel PX1 and the emission control line 153 of the second pixel PX2. The emission control connection line 123 may extend in the first direction DR1 while overlapping the emission control line 153 of the first pixel PX1 and the emission control line 153 of the second pixel PX2.

[0089] The initialization voltage connection line 124 may connect the initialization voltage line 164 of the first pixel PX1 and the initialization voltage line 164 of the second pixel PX2. The initialization voltage connection line 124 may extend in the first direction DR1 while overlapping the initialization voltage line 164 of the first pixel PX1 and the initialization voltage line 164 of the second pixel PX2.

[0090] The grid connection line 125 may connect the second electrode 165 of the storage capacitor Cst of the first pixel PX1 and the second electrode 165 of the storage capacitor Cst of the second pixel PX2. Since the second electrode 165 of the storage capacitor Cst is connected to the first power voltage line 182 to receive the first power voltage ELVDD (see Figure 3 ), so the grid connection line 125 can be used to transmit the first power voltage ELVDD across a plurality of pixels arranged in the first direction DR1. The first power voltage line 182 having a grid structure can be formed by the grid connection line 125 without ensuring a space for arranging a separate first power voltage line 182 extending in the first direction DR1. Therefore, a space for the storage capacitor Cst can be further ensured, so that a high-definition display device 1 can be implemented.

[0091] The scanning connection line 121, the front scanning connection line 122, the emission control connection line 123, the initialization voltage connection line 124, and the grid connection line 125 may connect the first pixel PX1 and the second pixel PX2 while extending from the first pixel area PXA1 to the second pixel area PXA2. The scanning connection line 121, the front scanning connection line 122, the emission control connection line 123, the initialization voltage connection line 124, and the grid connection line 125 may connect a plurality of pixels arranged in the first direction DR1.

[0092] In the present embodiment, the conductive layer such as the scan line 151, the front scan line 152, the emission control line 153, the initialization voltage line 164 and the second electrode 165 of the storage capacitor Cst disposed above the lower connection line 120 can be formed separately for each pixel. Therefore, it is possible to prevent the stress generated in one pixel from being transferred to another pixel. The lower connection line 120 can connect a plurality of pixels while crossing over the pixels, thereby connecting the conductive layer formed separately for each pixel.

[0093] The inorganic insulating layer 130 may be disposed on the lower connection line 120. The inorganic insulating layer 130 may include a buffer layer 131, a first inorganic insulating layer 132, a second inorganic insulating layer 133, and a third inorganic insulating layer 134 sequentially disposed on the substrate 100.

[0094] The buffer layer 131 may be disposed on the lower connection line 120. The buffer layer 131 may be formed on the barrier layer 110 while covering the lower connection line 120. The buffer layer 131 may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer 131 may be used to increase the smoothness of the upper surface of the substrate 100.

[0095] The semiconductor layer 140 may be disposed on the buffer layer 131. The semiconductor layer 140 may be formed of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The semiconductor layer 140 may be bent into various shapes. The semiconductor layer 140 may include a driving semiconductor portion AS1 of the driving transistor T1, a switching semiconductor portion AS2 of the switching transistor T2, a compensation semiconductor portion AS3 of the compensation transistor T3, a first initialization semiconductor portion AS4 of the first initialization transistor T4, an operation control semiconductor portion AS5 of the operation control transistor T5, an emission control semiconductor portion AS6 of the emission control transistor T6, and a second initialization semiconductor portion AS7 of the second initialization transistor T7.

[0096] The semiconductor layer 140 of each pixel may be formed to be separated from each other. For example, the semiconductor layer 140 of the first pixel PX1 may be formed to be spaced apart from the semiconductor layer 140 of the second pixel PX2.

[0097] Each of the semiconductor portions AS1 to AS7 may include a channel region, and a source region and a drain region on opposite sides of the channel region. In an embodiment, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may correspond to the source electrode and the drain electrode, respectively, and are therefore represented by the same reference numerals as the source electrode and the drain electrode, respectively.

[0098] The driving semiconductor portion AS1 may include a driving channel region A1, and a driving source region S1 and a driving drain region D1 on opposite sides of the driving channel region A1. The driving semiconductor portion AS1 may have a curved shape, and the driving channel region A1 may be formed to be longer than the other channel regions A2 to A7. For example, when the driving semiconductor portion AS1 has a shape that is bent multiple times, such as 'Ω' or 'S', a long channel length may be formed in a narrow space. Since a long driving channel region A1 is formed, the driving range of the gate voltage applied to the driving gate electrode G1 may be widened, so that the grayscale of the light emitted from the light emitting element EE may be more accurately controlled, and the display quality of the display device 1 may be improved.

[0099] The switching semiconductor portion AS2 may include a switching channel region A2, and a switching source region S2 and a switching drain region D2 on opposite sides of the switching channel region A2. The switching drain region D2 may be connected to the driving source region S1.

[0100] The compensation semiconductor portion AS3 may include compensation channel regions A3a and A3c, and compensation source regions S3 and compensation drain regions D3 on opposite sides of the compensation channel regions A3a and A3c. The compensation transistor T3 is a dual transistor, and the compensation semiconductor portion AS3 may include two compensation channel regions A3a and A3c. A region A3b between the compensation channel regions A3a and A3c may be a region doped with impurities, and may correspond to a source region of one transistor in the dual transistor and a drain region of the other transistor in the dual transistor.

[0101] The first initialization semiconductor portion AS4 may include first initialization channel regions A4a and A4c, and first initialization source regions S4 and first initialization drain regions D4 on opposite sides of the first initialization channel regions A4a and A4c. The first initialization transistor T4 is a dual transistor, and the first initialization semiconductor portion AS4 may include two first initialization channel regions A4a and A4c. A region A4b between the first initialization channel regions A4a and A4c may be a region doped with impurities, and may correspond to a source region of one transistor in the dual transistor and a drain region of the other transistor in the dual transistor.

[0102] The operation control semiconductor portion AS5 may include an operation control channel region A5, and an operation control source region S5 and an operation control drain region D5 on opposite sides of the operation control channel region A5. The operation control drain region D5 may be connected to the driving source region S1.

[0103] The emission control semiconductor portion AS6 may include an emission control channel region A6, and an emission control source region S6 and an emission control drain region D6 on opposite sides of the emission control channel region A6. The emission control source region S6 may be connected to the driving drain region D1.

[0104] The second initialization semiconductor portion AS7 may include a second initialization channel region A7, and a second initialization source region S7 and a second initialization drain region D7 on opposite sides of the second initialization channel region A7. The second initialization drain region D7 may be connected to the first initialization drain region D4.

[0105] The first inorganic insulating layer 132 may be disposed on the semiconductor layer 140. The first inorganic insulating layer 132 may be formed on the buffer layer 131 while covering the semiconductor layer 140. The first inorganic insulating layer 132 may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, or the like.

[0106] The second conductive layer 150 may be disposed on the first inorganic insulating layer 132. The second conductive layer 150 may include molybdenum (Mo) or copper (Cu), etc., and may be formed of a single layer or a plurality of layers.

[0107] The second conductive layer 150 may include a scan line 151, a front scan line 152, an emission control line 153, and a driving gate electrode G1. The scan line 151, the front scan line 152, the emission control line 153, and the driving gate electrode G1 may include the same material.

[0108] The driving gate electrode G1 may be an island type and may overlap the driving channel region A1 of the driving semiconductor portion AS1. The driving gate electrode G1 may function not only as the driving gate electrode G1 of the driving transistor T1 but also as the first electrode 154 of the storage capacitor Cst.

[0109] A portion or a protruding portion of the scan line 151, the front scan line 152, and the emission control line 153 may correspond to the gate electrode G2 of the transistor T2 to the gate electrode G7 of the transistor T7. The area of ​​the scan line 151 overlapping the switch channel region A2 and the compensation channel regions A3a and A3c may correspond to the switch gate electrode G2 and the compensation gate electrodes G3a and G3b, respectively. The area of ​​the front scan line 152 overlapping the first initialization channel regions A4a and A4c and the second initialization channel region A7 may correspond to the first initialization gate electrodes G4a and G4b and the second initialization gate electrode G7, respectively. The area of ​​the emission control line 153 overlapping the operation control channel region A5 and the emission control channel region A6 may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0110] In the present embodiment, the scan line 151, the front scan line 152, the emission control line 153, and the driving gate electrode G1 of each pixel may be formed to be separated from each other. For example, the scan line 151, the front scan line 152, the emission control line 153, and the driving gate electrode G1 of the first pixel PX1 may be formed to be spaced apart from the scan line 151, the front scan line 152, the emission control line 153, and the driving gate electrode G1 of the second pixel PX2.

[0111] The scan line 151, the front scan line 152, and the emission control line 153 of the first pixel PX1 may be connected to the scan line 151, the front scan line 152, and the emission control line 153 of the second pixel PX2, respectively, through the lower connection line 120. The scan line 151 of the first pixel PX1 and the scan line 151 of the second pixel PX2 may be connected to the scan connection line 121 through the contact holes CNT1a and CNT1b passing through the buffer layer 131 and the first inorganic insulating layer 132, and the front scan line 152 of the first pixel PX1 and the front scan line 152 of the second pixel PX2 may be connected to the front scan connection line 122 through the contact holes CNT2a and CNT2b passing through the buffer layer 131 and the first inorganic insulating layer 132. The emission control line 153 of the first pixel PX1 and the emission control line 153 of the second pixel PX2 may be connected to the emission control connection line 123 through the contact holes CNT3a and CNT3b passing through the buffer layer 131 and the first inorganic insulating layer 132.

[0112] like Fig.10 As shown in , the first conductive line 150a of the first pixel PX1 and the second conductive line 150b of the second pixel PX2 disposed on the first inorganic insulating layer 132 may be connected through the first lower connecting line 120a. For example, the first conductive line 150a may be any one of the scan line 151, the front scan line 152, and the emission control line 153 of the first pixel PX1, and the second conductive line 150b may be any one of the scan line 151, the front scan line 152, and the emission control line 153 of the second pixel PX2, and the second conductive line 150b corresponds to the first conductive line 150a. The first lower connecting line 120a may be any one of the scan connecting line 121, the front scan connecting line 122, and the emission control connecting line 123, and the first lower connecting line 120a corresponds to the first conductive line 150a and the second conductive line 150b.

[0113] The first conductive line 150a may contact the first lower connection line 120a through the first contact hole CNTa passing through the buffer layer 131 and the first inorganic insulating layer 132, and the second conductive line 150b may contact the first lower connection line 120a through the second contact hole CNTb passing through the buffer layer 131 and the first inorganic insulating layer 132. Therefore, the first lower connection line 120a may connect the first conductive line 150a and the second conductive line 150b spaced apart from each other under the inorganic insulating layer 130. The first lower connection line 120a connected to the scan line 151 or the front scan line 152 may transmit a scan signal, and the first lower connection line 120a connected to the emission control line 153 may transmit an emission control signal. The elongation of the first lower connection line 120a may be greater than the elongation of the first conductive line 150a and the elongation of the second conductive line 150b.

[0114] The second inorganic insulating layer 133 may be disposed on the second conductive layer 150. The second inorganic insulating layer 133 may be formed on the first inorganic insulating layer 132 while covering the second conductive layer 150. The second inorganic insulating layer 133 may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0115] The third conductive layer 160 may be disposed on the second inorganic insulating layer 133. The third conductive layer 160 may include molybdenum (Mo) or copper (Cu), etc., and may be formed of a single layer or a plurality of layers.

[0116] The third conductive layer 160 may include an initialization voltage line 164 and a second electrode 165 of the storage capacitor Cst. The initialization voltage line 164 and the second electrode 165 of the storage capacitor Cst may include the same material.

[0117] The initialization voltage line 164 and the second electrode 165 of the storage capacitor Cst of each pixel may be formed to be separated from each other. For example, the initialization voltage line 164 and the second electrode 165 of the storage capacitor Cst of the first pixel PX1 and the initialization voltage line 164 and the second electrode 165 of the storage capacitor Cst of the second pixel PX2 may be formed to be separated from each other.

[0118] The initialization voltage line 164 of the first pixel PX1 and the second electrode 165 of the storage capacitor Cst may be connected to the initialization voltage line 164 of the second pixel PX2 and the second electrode 165 of the storage capacitor Cst, respectively, through the lower connection line 120. The initialization voltage line 164 of the first pixel PX1 and the initialization voltage line 164 of the second pixel PX2 may be connected to the initialization voltage connection line 124 through the contact holes CNT4a and CNT4b passing through the buffer layer 131, the first inorganic insulating layer 132, and the second inorganic insulating layer 133, and the second electrode 165 of the storage capacitor Cst of the first pixel PX1 and the second electrode 165 of the storage capacitor Cst of the second pixel PX2 may be connected to the mesh connection line 125 through the contact holes CNT5a, CNT5b, CNT6a, and CNT6b passing through the buffer layer 131, the first inorganic insulating layer 132, and the second inorganic insulating layer 133.

[0119] like Fig.11As shown in , the third wire 160a of the first pixel PX1 and the fourth wire 160b of the second pixel PX2 disposed on the second inorganic insulating layer 133 may be connected through the second lower connection line 120b. For example, the third wire 160a may be any one of the initialization voltage line 164 of the first pixel PX1 and the second electrode 165 of the storage capacitor Cst, and the fourth wire 160b may be any one of the initialization voltage line 164 of the second pixel PX2 and the second electrode 165 of the storage capacitor Cst, and the fourth wire 160b corresponds to the third wire 160a. The second lower connection line 120b may be any one of the initialization voltage connection line 124 and the grid connection line 125, and the second lower connection line 120b corresponds to the third wire 160a and the fourth wire 160b.

[0120] The third conductive line 160a may contact the second lower connection line 120b through the third contact hole CNTc passing through the buffer layer 131, the first inorganic insulating layer 132, and the second inorganic insulating layer 133, and the fourth conductive line 160b may contact the second lower connection line 120b through the fourth contact hole CNTd passing through the buffer layer 131, the first inorganic insulating layer 132, and the second inorganic insulating layer 133. Therefore, the second lower connection line 120b may connect the third conductive line 160a and the fourth conductive line 160b spaced apart from each other under the inorganic insulating layer 130. The second lower connection line 120b connected to the initialization voltage line 164 may transmit the initialization voltage. The elongation of the second lower connection line 120b may be greater than the elongation of the third conductive line 160a and the elongation of the fourth conductive line 160b.

[0121] The third inorganic insulating layer 134 may be disposed on the third conductive layer 160. The third inorganic insulating layer 134 may be formed on the second inorganic insulating layer 133 while covering the third conductive layer 160. The third inorganic insulating layer 134 may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0122] The inorganic insulating layer 130 may have a groove GR between adjacent pixel regions PXA1, PXA2, and PXA3. The groove GR may refer to a trench formed in the inorganic insulating layer 130. The buffer layer 131, the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134 may have openings 131a, 132a, 133a, and 134a corresponding to the groove GR of the inorganic insulating layer 130. The openings 131a, 132a, 133a, and 134a may overlap with each other.

[0123] The width GRW of the groove GR of the inorganic insulating layer 130 may be several micrometers (μm). For example, the width GRW of the groove GR of the inorganic insulating layer 130 may be about 5 μm to about 10 μm.

[0124] The organic insulating layer 170 may be filled in the groove GR of the inorganic insulating layer 130. Between the pixel areas PXA1, PXA2, and PXA3 where the organic insulating layer 170 is located, the lower connection line 120 may be located below the organic insulating layer 170. The organic insulating layer 170 may include an organic material such as acrylic acid, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, or hexamethyldisiloxane.

[0125] The organic insulating layer 170 may be disposed between the pixel regions PXA1, PXA2, and PXA3 to fill at least a portion of the groove GR of the inorganic insulating layer 130. In an embodiment, the organic insulating layer 170 may completely fill the groove GR of the inorganic insulating layer 130. In order for the organic insulating layer 170 to absorb external impact, it may be desirable to completely fill the groove GR.

[0126] In an embodiment, the organic insulating layer 170 may be formed to extend to the upper surface of the inorganic insulating layer 130. In this embodiment, the upper surface of the organic insulating layer 170 may be provided in a convex shape due to the characteristics of the organic insulating layer 170. In other words, the maximum height h of the organic insulating layer 170 may be greater than the depth d of the groove GR.

[0127] In an embodiment, the angle between the upper surface of the organic insulating layer 170 and the upper surface of the inorganic insulating layer 130 may be less than about 45 degrees. If the slope of the boundary where the upper surface of the inorganic insulating layer 130 and the upper surface of the organic insulating layer 170 contact is not gentle, the conductive material used in the process of forming the upper connection line 180 by patterning the conductive layer may remain on the boundary without being removed therefrom. In this case, a short circuit may occur between the remaining conductive material and the other conductive layers. Therefore, it is desirable that the upper surface of the organic insulating layer 170 is formed to have a gentle slope relative to the upper surface of the inorganic insulating layer 130.

[0128] The groove GR of the inorganic insulating layer 130 and the organic insulating layer 170 may be positioned in at least a portion between the pixel regions PXA1, PXA2, and PXA3. Figure 4As shown in , the groove GR of the inorganic insulating layer 130 and the organic insulating layer 170 may be arranged to surround each of the pixel regions PXA1, PXA2, and PXA3. In other words, the organic insulating layer 170 may be arranged to surround the periphery of the first pixel PX1 and the periphery of the second pixel PX2. For example, the groove GR of the inorganic insulating layer 130 and the organic insulating layer 170 may extend in the second direction DR2 between the first pixel region PXA1 and the second pixel region PXA2, and extend in the first direction DR1 between the first pixel region PXA1 and the third pixel region PXA3. However, the present invention is not limited thereto. In another embodiment, the groove GR of the inorganic insulating layer 130 and the organic insulating layer 170 may not surround each of the pixel regions PXA1, PXA2, and PXA3, and may be formed to extend in the second direction DR2 or in the first direction DR1 between the pixel regions PXA1, PXA2, and PXA3.

[0129] The groove GR of the inorganic insulating layer 130 and the organic insulating layer 170 can minimize the influence of external impact on the display device 1. Since the inorganic insulating layer 130 has a higher hardness than the organic insulating layer 170, the possibility that the inorganic insulating layer 130 is cracked by the external impact may be relatively high. When the inorganic insulating layer 130 is cracked, the crack may also occur in the signal line disposed inside or on the inorganic insulating layer 130, and defects such as disconnection may occur.

[0130] However, in the display device 1 according to the present embodiment, the inorganic insulating layer 130 may have a groove GR between the plurality of pixel regions PXA1, PXA2, and PXA3, and the organic insulating layer 170 may fill the groove GR of the inorganic insulating layer 130, so that the possibility of crack extension may be reduced despite the occurrence of an external impact. In addition, since the organic insulating layer 170 has a lower hardness than that of the inorganic insulating layer 130, the organic insulating layer 170 may absorb stress caused by the external impact, and stress concentration on the lower connection line 120 disposed below the organic insulating layer 170 may be effectively reduced.

[0131] The upper connection line (or fourth conductive layer) 180 may be disposed on the inorganic insulating layer 130 and the organic insulating layer 170. The upper connection line 180 may connect pixels arranged in the second direction DR2. For example, the upper connection line 180 may connect the first pixel PX1 and the third pixel PX3. Therefore, in a plan view, the upper connection line 180 may cross the lower connection line 120. The upper connection line 180 may be used as a line for transmitting an electrical signal to pixels arranged in the second direction DR2. Since the upper connection line 180 may connect pixels arranged in the second direction DR2, the upper connection line 180 may be relatively longer than other lines. Therefore, there is a possibility that high stress is applied to the upper connection line 180.

[0132] The upper connection line 180 may include a material having a high elongation. For example, the upper connection line 180 may include aluminum (Al). In an embodiment, the upper connection line 180 may have a multilayer structure of Ti / Al / Ti. Therefore, defects such as cracks or disconnections may not occur in the upper connection line 180. In an embodiment, the elongation of the upper connection line 180 may be greater than the elongation of the line provided in the inorganic insulating layer 130.

[0133] The upper connection line 180 may include a data line 181, a first power voltage line 182, a first node connection line 183, a second node connection line 184, and an intermediate connection line 185. The data line 181, the first power voltage line 182, the first node connection line 183, the second node connection line 184, and the intermediate connection line 185 may include the same material.

[0134] The data line 181 may be connected to the switching source region S2 of the switching transistor T2 via a contact hole CNT7 passing through the first, second, and third inorganic insulating layers 132, 133, and 134. The data line 181 may connect a plurality of pixels arranged in the second direction DR2, for example, the first and third pixels PX1 and PX3.

[0135] The first power supply voltage line 182 may be connected to the operation control source region S5 of the operation control transistor T5 via a contact hole CNT8 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134. In addition, the first power supply voltage line 182 may be connected to the second electrode 165 of the storage capacitor Cst via a contact hole CNT9 passing through the third inorganic insulating layer 134. The first power supply voltage line 182 may connect a plurality of pixels arranged in the second direction DR2, for example, the first pixel PX1 and the third pixel PX3.

[0136] The first node connection line 183 may transmit an initialization voltage for initializing the driving transistor T1 and the pixel electrode 200. The first node connection line 183 may be connected to the first initialization transistor T4 and the second initialization transistor T7 via a contact hole CNT10 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134, and may be connected to the initialization voltage line 164 via a contact hole CNT11 passing through the third inorganic insulating layer 134.

[0137] The second node connection line 184 may be connected to the compensation drain region D3 of the compensation transistor T3 via a contact hole CNT12 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134, and may be connected to the driving gate electrode G1 via a contact hole CNT13 passing through the second inorganic insulating layer 133 and the third inorganic insulating layer 134. The island type driving gate electrode G1 may be electrically connected to the compensation transistor T3 via the second node connection line 184.

[0138] The intermediate connection line 185 may be connected to the second initialization source region S7 of the second initialization transistor T7 via a contact hole CNT14 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134, and may be connected to the emission control drain region D6 of the emission control transistor T6 via a contact hole CNT15 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134. Fig.12 As shown in the figure, the first end of the intermediate connecting line 185 can be connected to the second initialization source region S7 of the second initialization transistor T7 of the first pixel PX1 via the contact hole CNT14, and the second end of the intermediate connecting line 185 can be connected to the emission control drain region D6 of the emission control transistor T6 of the third pixel PX3 via the contact hole CNT15.

[0139] The data line 181, the first power supply voltage line 182 and the intermediate connection line 185 may connect the first pixel PX1 and the third pixel PX3 while crossing the first pixel area PXA1 and the third pixel area PXA3. In other words, the data line 181, the first power supply voltage line 182 and the intermediate connection line 185 may connect a plurality of pixels arranged in the second direction DR2.

[0140] The planarization layer 191 may be disposed on the upper connection line 180. The planarization layer 191 may be formed on the third inorganic insulating layer 134 while covering the upper connection line 180. The planarization layer 191 may include an organic material such as acrylic acid, benzocyclobutene (BCB), polyimide (PI), or hexamethyldisiloxane (HMDSO). The planarization layer 191 may be provided as a single layer or multiple layers. The planarization layer 191 may be used to substantially planarize the upper portion of the transistors T1 to T7.

[0141] The light emitting element EE including the pixel electrode 200 , the opposite electrode 220 , and the intermediate layer 210 interposed between the pixel electrode 200 and the opposite electrode 220 and including an emission layer may be disposed on the planarization layer 191 .

[0142] The pixel electrode 200 may be connected to the intermediate connection line 185 through a contact hole defined in the planarization layer 191. The pixel electrode 200 may be electrically connected to the emission control drain region D6 of the emission control transistor T6 through the intermediate connection line 185.

[0143] The pixel defining layer 192 may be disposed on the planarization layer 191. The pixel defining layer 192 may be used to define pixels by having an opening OP corresponding to each pixel (i.e., an opening OP exposing at least a central portion of the pixel electrode 200). The emission layer included in the intermediate layer 210 may be positioned between the pixel electrode 200 and the counter electrode 220 in the opening OP of the pixel defining layer 192, and each of the pixels of, for example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be defined by the opening OP of the pixel defining layer 192. In addition, the pixel defining layer 192 may increase the distance between the edge of the pixel electrode 200 and the counter electrode 220 above the pixel electrode 200, so that arcing may be prevented from being generated at the edge of the pixel electrode 200. The pixel defining layer 192 may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0144] The intermediate layer 210 may include a low molecular weight material or a high molecular weight material. When the intermediate layer 210 includes a low molecular weight material, the intermediate layer 210 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single or complex structure, and may include copper phthalocyanine (CuPc), N,N-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (N,N'-Di(naphthalene-1-yl)-N,N'-diphenyl-benzidine:NPB) or tris-8-hydroxyquinoline aluminum (tris-8-hydroxyquinoline aluminum) (Alq3), etc.

[0145] When the intermediate layer 210 includes a high molecular weight material, the intermediate layer 210 may have a structure including a hole transport layer (HTL) and an emission layer (EML). In this case, the HTL may include PEDOT, and the EML may include a high molecular weight material such as polyphenylene vinylene (PPV) and polyfluorene. The intermediate layer 210 may include a layer integrally formed above the plurality of pixel electrodes 200, or may include a layer patterned to correspond to each of the plurality of pixel electrodes 200.

[0146] The counter electrode 220 may be disposed to cover the display area DA. In other words, the counter electrode 220 may be integrally formed above the plurality of light emitting elements EE to correspond to the plurality of pixel electrodes 200.

[0147] In an embodiment, the pixel electrode 200 and the counter electrode 220 may be the anode and cathode of the light emitting element EE, respectively. However, the present invention is not limited thereto, and in another embodiment, the pixel electrode 200 and the counter electrode 220 may be the cathode and anode of the light emitting element EE, respectively.

[0148] Since the light emitting element EE may be easily damaged by moisture or oxygen from the outside, the encapsulation layer 300 may cover and protect the light emitting element EE. The encapsulation layer 300 may cover the display area DA and extend to the outside of the display area DA. The encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0149] The first inorganic encapsulation layer 310 may cover the counter electrode 220 and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide, tin oxide, indium tin oxide (ITO), silicon oxide, silicon nitride and / or silicon oxynitride. If necessary, other layers such as a capping layer may be interposed between the first inorganic encapsulation layer 310 and the counter electrode 220. Since the first inorganic encapsulation layer 310 is formed along the lower structure, the upper surface of the first inorganic encapsulation layer 310 may not be flattened.

[0150] The organic encapsulation layer 320 may cover the first inorganic encapsulation layer 310, and unlike the first inorganic encapsulation layer 310, the upper surface of the organic encapsulation layer 320 may be substantially planarized. Specifically, the upper surface of the organic encapsulation layer 320 may be substantially planarized in a portion corresponding to the display area DA. The organic encapsulation layer 320 may include one or more materials selected from the group consisting of acrylic acid, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonic acid, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0151] The second inorganic encapsulating layer 330 may cover the organic encapsulating layer 320 and may include ceramic, metal oxide, metal nitride, metal carbide, metal oxynitride, indium oxide, tin oxide, indium tin oxide (ITO), silicon oxide, silicon nitride, and / or silicon oxynitride.

[0152] As described above, since the encapsulation layer 300 has a multi-layer structure including the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330, although cracks occur inside the encapsulation layer 300, the cracks may not be connected between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Therefore, the formation of a path through which moisture or oxygen from the outside penetrates into the display area DA can be prevented or minimized.

[0153] Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 Can show manufacturing Fig.10 A method for displaying a device 1 in the present invention.

[0154] Reference Figure 5 and Fig.13 , a lower connection line (first conductive layer) 120 may be formed on the substrate 100 .

[0155] First, the barrier layer 110 may be formed by depositing an inorganic insulating material on the substrate 100. Then, a conductive material may be deposited on the barrier layer 110 and patterned to form the lower connection line 120.

[0156] Since the lower connection line 120 may be exposed to a high temperature process for heat-treating the semiconductor layer 140, the conductive material may include a metal having a relatively high melting point, such as molybdenum (Mo) or titanium (Ti). In addition, since the lower connection line 120 extends relatively long, the conductive material may include a material having a high elongation.

[0157] Reference Figure 6 , Figure 7 , Figure 8 and Fig.14 An inorganic insulating layer 130 including a buffer layer 131, a first inorganic insulating layer 132, a second inorganic insulating layer 133 and a third inorganic insulating layer 134, a semiconductor layer 140, a second conductive layer 150 and a third conductive layer 160 may be formed on the substrate 100 on which the lower connecting line 120 is formed.

[0158] First, the buffer layer 131 may be formed by depositing an inorganic insulating material on the barrier layer 110 on which the lower connection line 120 is formed. Then, a semiconductor material may be deposited on the buffer layer 131 and patterned to form the semiconductor layer 140. Then, the first inorganic insulating layer 132 may be formed by depositing an inorganic insulating material on the buffer layer 131 on which the semiconductor layer 140 is formed.

[0159] Then, contact holes CNT1a, CNT1b, CNT2a, CNT2b, CNT3a, and CNT3b may be formed through the buffer layer 131 and the first inorganic insulating layer 132 by a photomask process, etc. Then, a conductive material may be deposited on the first inorganic insulating layer 132 and patterned to form the second conductive layer 150. Then, the second inorganic insulating layer 133 may be formed by depositing an inorganic insulating material on the first inorganic insulating layer 132 having the second conductive layer 150 formed thereon.

[0160] Then, contact holes CNT4a, CNT4b, CNT5a, CNT5b, CNT6a, and CNT6b may be formed through the buffer layer 131, the first inorganic insulating layer 132, and the second inorganic insulating layer 133 by a photomask process, etc. Then, a conductive material may be deposited on the second inorganic insulating layer 133 and patterned to form the third conductive layer 160. Then, the third inorganic insulating layer 134 may be formed by depositing an inorganic insulating material on the second inorganic insulating layer 133 having the third conductive layer 160 formed thereon.

[0161] Reference Fig.15 , a groove GR may be formed in the inorganic insulating layer 130. The groove GR of the inorganic insulating layer 130 may be formed between the pixel areas PXA1, PXA2, and PXA3. In order to form the groove in the inorganic insulating layer 130, a photomask process and an etching process may be performed. The openings 131a, 132a, 133a, and 134a of the buffer layer 131, the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134 may be formed by an etching process. For example, the etching process may be a dry etching process.

[0162] Reference Fig.16 , the organic insulating layer 170 filling the groove GR of the inorganic insulating layer 130 may be formed. For example, an organic insulating material may be deposited on the third inorganic insulating layer 134 and patterned to form the organic insulating layer 170 .

[0163] Reference Fig. 9 and Fig.17 , an upper connection line (fourth conductive layer) 180 may be formed on the inorganic insulating layer 130 in which the groove GR is filled with the organic insulating layer 170 .

[0164] Then, contact holes CNT7, CNT8, CNT10, CNT12, CNT14, and CNT15 passing through the first inorganic insulating layer 132, the second inorganic insulating layer 133, and the third inorganic insulating layer 134, contact holes CNT13 passing through the second inorganic insulating layer 133 and the third inorganic insulating layer 134, and contact holes CNT9 and CNT11 passing through the third inorganic insulating layer 134 may be formed by a photomask process or the like. Then, a conductive material may be deposited on the inorganic insulating layer 130 and the organic insulating layer 170 and patterned to form an upper connection line 180. Since the upper connection line 180 extends relatively long, the conductive material may include a material having a high elongation. A high temperature process for heat treating the semiconductor layer 140 may be performed after the semiconductor layer 140 is formed and before the upper connection line 180 is formed.

[0165] Fig.18 and Fig.19 is a plan view showing a display device according to an embodiment.

[0166] Reference Fig.18 and Fig.19 , the groove GR of the inorganic insulating layer and the organic insulating layer 170 may be arranged to surround a plurality of pixels by grouping the plurality of pixels. Fig.18 As shown in FIG. 1 , the groove GR of the inorganic insulating layer and the organic insulating layer 170 may be disposed to surround two pixels, ie, the first pixel PX1 and the second pixel PX2. Fig.19 As shown in FIG. 1 , the groove GR of the inorganic insulating layer and the organic insulating layer 170 may be disposed to surround four pixels PX1 , PX2 , PX3 , and PX4 . However, the embodiments of the present invention are not limited thereto, and the number of pixels to be grouped may be variously modified.

[0167] Depending on the position in a display device, the number of pixels to be grouped may be the same or different. For example, the groove GR of the inorganic insulating layer and the organic insulating layer 170 may be arranged to surround one pixel in a region with a high risk of cracking or stress, and may be arranged to surround multiple pixels in the remaining region.

[0168] Possibility of industrial applications

[0169] The display device according to the embodiment of the present invention may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0170] Although the display device according to the embodiment of the present invention has been described with reference to the accompanying drawings, the illustrated embodiment is an example and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the technical spirit of the present invention described in the following scope of claims.

[0171] Description of Reference Numerals

[0172] 100: Base

[0173] 120: Lower connecting line

[0174] 130: Inorganic insulation layer

[0175] 170: Organic insulation layer

[0176] 180: Upper connection line

[0177] PXA1: First pixel area

[0178] PXA2: Second pixel area

[0179] PXA3: Third pixel area

Claims

1. A display device, in, The display device comprises: a first pixel region, the first pixel being positioned on the first pixel region; a second pixel region, the second pixel being positioned on the second pixel region; a lower connection line, the lower connection line connecting the first pixel and the second pixel and spanning the first pixel region and the second pixel region; an inorganic insulating layer disposed on the lower connecting line and having a groove disposed between the first pixel region and the second pixel region and exposing an upper surface of the lower connecting line; and An organic insulating layer fills the groove of the inorganic insulating layer.

2. The display device according to claim 1, in, The lower connecting line extends along a first direction, and The groove of the inorganic insulating layer extends along a second direction intersecting the first direction.

3. The display device according to claim 1, in, The first pixel and the second pixel include a first conductive line and a second conductive line respectively disposed on the lower connecting line, and the organic insulating layer is between the first conductive line and the second conductive line.

4. The display device according to claim 3, in, The first conductive line and the second conductive line are connected through the lower connecting line.

5. The display device according to claim 4, in, The lower connection line is configured to transmit a scan signal or an emission control signal.

6. The display device according to claim 3, in, The first pixel and the second pixel include a third wire and a fourth wire respectively disposed on the first wire and the second wire, and the organic insulating layer is between the third wire and the fourth wire.

7. The display device according to claim 6, in, The third wire and the fourth wire are connected through the lower connecting line.

8. The display device according to claim 7, in, The lower connection line is configured to transmit an initialization voltage.

9. The display device according to claim 6, in, The lower connecting line comprises: a first lower connecting line, the first lower connecting line connecting the first conductive line and the second conductive line; and A second lower connecting line is provided, wherein the second lower connecting line connects the third conductive line and the fourth conductive line.

10. The display device according to claim 6, in, The elongation rate of the lower connecting wire is greater than the elongation rates of the third conductive wire and the fourth conductive wire.

11. The display device according to claim 3, in, The elongation rate of the lower connecting wire is greater than the elongation rates of the first conductive wire and the second conductive wire.

12. The display device according to claim 1, in, The display device further comprises: a third pixel region on which the third pixel is positioned; and An upper connection line is disposed on the inorganic insulating layer and the organic insulating layer, connects the first pixel and the third pixel, and spans the first pixel region and the third pixel region.

13. The display device according to claim 12, in, The groove of the inorganic insulating layer extends along a first direction, and Wherein, the upper connecting line extends along a second direction intersecting with the first direction.

14. The display device according to claim 12, in, The upper connection line is configured to transmit a data voltage or a power supply voltage.

15. The display device according to claim 12, in, The melting point of the lower connecting line is greater than the melting point of the upper connecting line.

16. A display device, in, The display device comprises: a first pixel region and a second pixel region; substrate; a first lower connection line, which is disposed on the substrate and crosses the first pixel region and the second pixel region; a first inorganic insulating layer, the first inorganic insulating layer being disposed on the first lower connecting line and having a first opening between the first pixel region and the second pixel region; a first conductive line, the first conductive line being disposed on the first inorganic insulating layer in the first pixel region and contacting the first lower connecting line through a first contact hole penetrating the first inorganic insulating layer; a second conductive line, the second conductive line being disposed on the first inorganic insulating layer in the second pixel region and contacting the first lower connecting line through a second contact hole penetrating the first inorganic insulating layer; a second inorganic insulating layer disposed on the first conductive line and the second conductive line and having a second opening overlapping the first opening; and An organic insulating layer fills the first opening of the first inorganic insulating layer and the second opening of the second inorganic insulating layer.

17. The display device according to claim 16, in, The display device further comprises: a second lower connection line, which is disposed on the same layer as the first lower connection line and crosses the first pixel region and the second pixel region; a third conductive line disposed on the second inorganic insulating layer in the first pixel region and contacting the second lower connecting line through a third contact hole penetrating the first inorganic insulating layer and the second inorganic insulating layer; and A fourth conductive line is disposed on the second inorganic insulating layer in the second pixel region and contacts the second lower connecting line through a fourth contact hole passing through the first inorganic insulating layer and the second inorganic insulating layer.

18. The display device according to claim 16, in, The display device further comprises: a third pixel region; and An upper connection line is disposed on the second inorganic insulating layer and crosses the first pixel region and the third pixel region.

19. A display device, in, The display device comprises: Multiple pixel regions; a lower connecting line, the lower connecting line spanning across the plurality of pixel regions; an inorganic insulating layer disposed on the lower connecting line and having a groove disposed between the plurality of pixel regions and exposing an upper surface of the lower connecting line; and An organic insulating layer fills the groove of the inorganic insulating layer.

20. The display device according to claim 19, in, The organic insulating layer surrounds at least a portion of the plurality of pixel regions in a plan view.

21. The display device according to claim 19, in, The organic insulating layer surrounds each of the plurality of pixel regions in a plan view.

22. The display device according to claim 19, in, The display device further comprises: An upper connection line is disposed on the inorganic insulating layer and the organic insulating layer, spans across the plurality of pixel regions, and intersects the lower connection line.

23. A display device, in, The display device comprises: a first pixel region and a second pixel region, a first pixel being positioned on the first pixel region, a second pixel being positioned on the second pixel region, the first pixel and the second pixel being each defined by an opening of a pixel defining layer, and an emission layer being positioned between a pixel electrode and a counter electrode in the opening of the pixel defining layer; substrate; a lower connecting line, the lower connecting line being disposed on the substrate and crossing the first pixel region and the second pixel region; an inorganic insulating layer disposed on the lower connecting line and having a groove disposed between the first pixel region and the second pixel region and exposing an upper surface of the lower connecting line; and An organic insulating layer is disposed between the lower connecting line and the pixel defining layer and fills the groove of the inorganic insulating layer.

Images