Optoelectronic integrated chip and manufacturing method thereof

Abstract

The present invention provides an optoelectronic integrated chip and a manufacturing method thereof. The optoelectronic integrated chip includes: a gain chip and a silicon photonic chip spot converter; the gain chip includes a passive waveguide part and an active waveguide part; a first thin film layer is grown below the passive waveguide region of the passive waveguide part, and a second thin film layer is grown below the quantum well gain region of the active waveguide part; a third thin film layer is grown above the silicon waveguide of the silicon photonic chip spot converter; the TE fundamental mode supported by the passive waveguide part is greater than the mode field of the first threshold; the TE fundamental mode supported by the active waveguide part is greater than the mode field of the second threshold; the TE fundamental mode supported by the silicon photonic chip spot converter is greater than the mode field of the third threshold. The problem of small end face coupling tolerance of integrating light sources on silicon substrates through hybrid integration technology in the prior art is solved, and not only high-efficiency coupling can be achieved, but also the docking tolerance is greatly increased, and the tolerance can meet the accuracy of the automatic placement machine, and passive end face docking coupling can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated photon technology, and in particular to an optoelectronic integrated chip and a manufacturing method thereof. Background Art

[0002] The optoelectronic integration technology that integrates photonic devices and electronic devices on the same silicon wafer can effectively solve many problems faced by microelectronic chips and continue Moore's Law. Silicon luminescence is a world problem that has lasted for half a century. At present, there are three main technical routes for integrating light sources on silicon substrates. The first is monolithic integration technology, that is, directly epitaxially growing gain materials (quantum wells or quantum dots) on SOI. Although there have been many advances, there is still no substantial breakthrough. The second is heterogeneous integration technology. This technical solution is to bond the unprocessed III-V group luminescent materials to the silicon photonic chip, remove the substrate, and then etch and process them to form evanescent wave coupling between the III-V waveguide and the silicon photonic waveguide. This technology has a high degree of integration and can be mass-produced. At present, Intel in the industry has applied this technology, and John Bowers' group is leading in academia. There are still two problems with this solution. One is that the III-V process is difficult to be compatible with the CMOS process, and the technical threshold is very high. The second is the heat dissipation problem. The silicon oxide box layer in SOI is heat-insulating, and the III-V chip has poor heat dissipation, so the performance of the laser produced is limited. The third is hybrid integration technology, which couples the well-made III-V chip with the silicon photonic chip end-to-end. This solution has a lower threshold than the previous two, good heat dissipation, and can optimize the gain chip and silicon photonic chip separately. It has the best overall performance, but the coupling tolerance is small and the alignment accuracy requirements are high.

[0003] In summary, among the three technologies mentioned above, hybrid integration technology has the lowest technical threshold and better performance, but it has the problem of small end face coupling tolerance. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides an optoelectronic integrated chip and a method for manufacturing the same, so as to solve the problem of small end face coupling tolerance in the prior art of integrating a light source on a silicon substrate through hybrid integration technology.

[0005] In a first aspect, the present invention provides an optoelectronic integrated chip, comprising:

[0006] Gain chip and silicon photonic chip mode spot converter;

[0007] The gain chip includes a passive waveguide part and an active waveguide part; a first thin film layer is grown below the passive waveguide region of the passive waveguide part, and a second thin film layer is grown below the quantum well gain region of the active waveguide part;

[0008] A third thin film layer is grown on the silicon waveguide of the silicon photonic chip spot converter;

[0009] The TE fundamental mode supported by the passive waveguide part has a mode field greater than a first threshold; the TE fundamental mode supported by the active waveguide part has a mode field greater than a second threshold; and the TE fundamental mode supported by the silicon photonic chip mode spot converter has a mode field greater than a third threshold.

[0010] Optionally, the bandgap widths of the first thin film layer and the second thin film layer correspond to an absorption wavelength of 1.05 um, and the third thin film layer is a silicon oxynitride thin film layer or a silicon nitride thin film layer.

[0011] Optionally, a thickness of at least one of the first film layer, the second film layer and the third film layer is between 0.05 um and 0.15 um.

[0012] Optionally, one side of the gain chip is coated with a high-reflection film; and / or the other side of the gain chip is coated with an anti-reflection film.

[0013] Optionally, the refractive index of the first thin film layer and the second thin film layer is the same as the refractive index of the passive waveguide region.

[0014] Optionally, the thickness of the passive waveguide zone in the passive waveguide part is 0.2-0.4um, the thickness of the first thin film layer is 0.05-0.09um, the waveguide spacing is 1-1.3um, the upper cladding thickness is 1.5-1.7um, the waveguide tip width is 0.6-0.9um, and the passive waveguide refractive index is 3.2-3.3.

[0015] Optionally, the second film layer has a thickness of 0.05-0.09 um.

[0016] Optionally, the thickness of the silicon oxide cladding in the silicon photonic chip spot converter is 5 to 8 um, the height of the bottom surface of the third thin film layer from the bottom surface of the silicon waveguide is 1.65 to 1.75 um, the thickness of the third thin film layer is 0.13 to 0.15 um, the refractive index of the third thin film layer is 1.500 to 1.650, the first tip width of the silicon waveguide is 0.13 to 0.16 um, the second tip width of the silicon waveguide is 0.22 to 0.25 um, the first tip length of the silicon waveguide is 150 to 230 um, the second tip length of the silicon waveguide is 45 to 60 um, and the third tip width of the silicon waveguide is 0.4 to 0.55 um.

[0017] A second aspect of the present invention provides a method for manufacturing an optoelectronic integrated chip, comprising:

[0018] Making a gain chip: starting from an InP substrate, epitaxially growing a first InP layer, a first thin film layer, a second thin film layer, a second InP layer and a quantum well layer in sequence, wherein the first thin film layer and the second thin film layer are at the same level, and the first thin film layer and the second thin film layer together constitute a layer, etching away a quantum well layer having the same area as the first thin film layer and a part of the thickness of the second InP layer directly above the first thin film layer, epitaxially growing a passive waveguide layer structure again, etching away the passive waveguide layer structure above the quantum well layer, forming a butt-joint structure of a passive waveguide and a quantum well gain region, and epitaxially growing a layer of InP to cover the chip, thereby obtaining a gain chip;

[0019] Making a silicon photonic chip spot converter: etching the silicon layer on the SOI substrate into a silicon waveguide, then growing a layer of silicon oxide and grinding it flat, and sequentially growing a third thin film layer and a silicon oxide cover layer on the silicon oxide layer to obtain a silicon photonic chip spot converter;

[0020] The gain chip is coupled to the end face of the silicon photonic chip spot converter.

[0021] Optionally, the method further comprises coating one side of the gain chip with a high reflection film and the other side with an anti-reflection film.

[0022] One or more technical solutions provided in the embodiments of the present application solve the problem of small end face coupling tolerance when integrating light sources on a silicon substrate through hybrid integration technology in the prior art. Not only can high-efficiency coupling be achieved, but the docking tolerance is also greatly increased. This tolerance is already able to meet the accuracy of automatic placement machines, and passive end face docking coupling can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 shows a gain chip structure diagram according to an exemplary embodiment of the present disclosure;

[0025] Figure 2 A structural diagram of a silicon photonic chip pattern spot converter according to an exemplary embodiment of the present disclosure is shown;

[0026] Figure 3a shows the TE fundamental mode field distribution diagram supported by the gain chip waveguide;

[0027] Figure 3b The figure shows the TE fundamental mode field distribution diagram supported by the silicon photonic chip mode spot converter;

[0028] Figure 4 shows a flow chart for making a gain chip;

[0029] Figure 5The manufacturing flow chart of silicon photonic chip pattern spot converter is shown. DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0031] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0032] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0033] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0034] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0035] The embodiment of the present invention provides an optoelectronic integrated chip, including: a gain chip and a silicon photonic chip spot converter. The structure of the gain chip is as follows Figure 1 As shown in Figure 2, the structure of the silicon photonic chip spot converter is as follows: Figure 2The gain chip includes a passive waveguide part and an active waveguide part, a first thin film layer is grown below the passive waveguide region of the passive waveguide part, a second thin film layer is grown below the quantum well gain region of the active waveguide part, a third thin film layer is grown above the silicon waveguide of the silicon photonic chip mode spot converter, the TE fundamental mode supported by the passive waveguide part is greater than the mode field of the first threshold, the TE fundamental mode supported by the active waveguide part is greater than the mode field of the second threshold, and the TE fundamental mode supported by the silicon photonic chip mode spot converter is greater than the mode field of the third threshold.

[0036] Specifically, Figure 1 As shown, a thin film layer with a thickness of ht is grown below the quantum well gain region and the passive waveguide region. In this embodiment, the first thin film layer and the second thin film layer are made of the same material, and the bandgap width of the first thin film layer and the second thin film layer corresponds to an absorption wavelength of 1.05um, that is, the first thin film layer and the second thin film layer are both Q1.05 material thin film layers with a refractive index of 3.2525. The first thin film layer and the second thin film layer have the same thickness, both ht. The composite structure composed of the thin film and the passive waveguide can support the film thickness ht value and the distance hg of the thin film from the passive waveguide can adjust the size of the TE fundamental mode. The size of the mode field is related to ht, hg and the refractive index of the film. The size of the TE fundamental mode supported by this structure can be calculated using the mode solution software of Lumerical Company. By selecting reasonable parameters, the composite structure composed of the thin film and the passive waveguide can support a TE fundamental mode with a larger mode field. In this embodiment, the parameters shown in Table 1 are used, and the gain chip expands the output mode spot to 6um. The TE fundamental mode supported by the passive waveguide part is a 6um diameter mode field, and the TE fundamental mode supported by the active waveguide part is a 6um diameter mode field. The active waveguide in the quantum well region is connected to the passive waveguide through the butt-joint process (butt joint welding process) of the prior art, which can achieve efficient coupling of the TE mode field.

[0037] The structure of the pattern converter of silicon photonic chip is as follows: Figure 2 As shown in FIG. 2 , the basic structure is to grow a third film layer at a certain height above the silicon waveguide taper. In this embodiment, the third film layer is a silicon oxynitride film. By adjusting the structural parameters (such as the parameters shown in Table 2), the TE fundamental mode of the structure is Figure 1 The TE fundamental mode of the medium gain chip (III-V chip) can be highly similar and achieve a high degree of matching. Using the parameters shown in Table 2, the composite structure composed of the third film layer and the tip of the silicon waveguide taper supports a TE fundamental mode with a mode field of 6um diameter, which also has a large mode field.

[0038] As a specific implementation case, the specific parameters of the gain chip (III-V chip) structure and the silicon photonic chip spot converter structure parameters are respectively shown in Table 1 and Table 2. The thickness hp of the passive waveguide region in the passive waveguide part is 0.3um, the thickness ht of the first film layer and the second film layer is 0.07um, the waveguide spacing hg is 1.115um, the upper cladding thickness hc is 1.6um, the waveguide tip width wt is 0.8um, and the passive waveguide refractive index Np is 3.2525. The thickness H of the silicon oxide cladding in the silicon photonic chip spot converter is 6um, the height h1 of the bottom surface of the third film layer from the bottom surface of the silicon waveguide is 1.75um, the thickness h0 of the third film layer is 0.14um, the refractive index n of the third film layer is 1.60, the first tip width w1 of the silicon waveguide is 0.15um, the second tip width w2 of the silicon waveguide is 0.24um, the first tip length L1 of the silicon waveguide is 200um, the second tip length L2 of the silicon waveguide is 50um, and the third tip width w3 of the silicon waveguide is 0.45um. The third film layer is a silicon oxynitride film layer.

[0039] Table 1

[0040] Parameter name significance Value hp Passive waveguide area thickness 0.3um ht Thickness of the first film layer and the second film layer 0.07um hg Waveguide spacing 1.115um hc Upper cladding thickness 1.6um wt Waveguide tip width 0.8um Np Passive waveguide refractive index 3.2525

[0041] Table 2

[0042]

[0043]

[0044] Figure 3a The TE fundamental mode field distribution diagram of the gain chip waveguide supported by the parameter data shown in Table 1 is shown in Table 1. Figure 3b The TE fundamental mode field distribution diagram supported by the silicon photonic chip mode spot converter using the parameter data shown in Table 2 is compared with Figure 3a and Figure 3b , the distribution forms of the two mode fields are similar, which makes it easy to achieve a high matching degree and high coupling efficiency.

[0045] Through the calculation of the existing software lumenical mode solution, the mode matching degree of the III-V chip and the silicon photonic mode spot converter formed by applying the parameters in Table 1 and Table 2 can reach 97%, and the matching degree 1dB tolerance can reach 2um in the horizontal direction and 1um in the vertical direction. The 1dB tolerance of the end face coupling between the general III-V chip and the silicon photonic chip is generally less than 0.5um in both the horizontal and vertical directions, and the mode spot matching degree does not reach the level of the embodiment of the present invention.

[0046] Through the above embodiments, the gain chip and the silicon photonic chip are collaboratively designed. Both adopt similar structures (i.e., thin films) to expand the TE fundamental mode of the waveguide, and can expand the output mode spot to a gain chip structure of 6um. At the same time, a corresponding silicon photonic chip end face coupling structure is proposed, which can not only increase the end face coupling position tolerance, but also achieve high-efficiency mode field matching. The 1dB position tolerance of the conventional end face coupling scheme is less than 0.5um, and it is difficult for a general chip mounter to meet this accuracy. However, the 1dB position tolerance of the end face coupling scheme can be slightly greater than 1um in the vertical direction and close to 2um in the horizontal direction (this data is calculated by the existing software lumeircal), which can meet the accuracy of the chip mounter and achieve passive docking coupling.

[0047] As long as the passive waveguide part, the active waveguide part and the silicon photonic chip mode spot converter can support the TE fundamental mode with a larger mode field, the first film layer, the second film layer or the third film layer can be made of a variety of materials. In some optional embodiments, the first film layer and the second film layer can be Q1.05 material film layers, and the third film layer can be a silicon oxynitride film layer or a silicon nitride film layer.

[0048] As long as the passive waveguide part, the active waveguide part and the silicon photonic chip spot converter can support the TE fundamental mode with a larger mode field, the first film layer, the second film layer and the third film layer can be selected in a suitable thickness range. In some optional embodiments, the thickness of the first film layer, the second film layer and the third film layer is between 0.05um and 0.15um.

[0049] like Figure 1 As shown, in some optional embodiments, one side of the gain chip is coated with a high-reflection film to serve as a reflector of the laser. In other optional embodiments, the other side of the gain chip is coated with an anti-reflection film to couple with a tunable filter made of silicon-based photonic devices to form a tunable external cavity laser.

[0050] In some optional embodiments, the refractive index of the first film layer and the second film layer is the same as the refractive index of the passive waveguide region. The same refractive index makes the manufacturing process simpler without adjusting the two refractive indices.

[0051] This embodiment also provides a method for manufacturing an optoelectronic integrated chip, comprising:

[0052] Making gain chip: Figure 4As shown, starting from the InP substrate in a, the first InP layer, the first thin film layer and the second thin film layer, the second InP layer and the quantum well layer are epitaxially grown in sequence, wherein the first thin film layer and the second thin film layer are at the same level, the first thin film layer and the second thin film layer together constitute a layer, the first thin film layer and the second thin film layer are both made of Q1.05 material, and the first thin film layer and the second thin film layer have the same thickness, forming the structure shown in b; the quantum well layer with the same area as the first thin film layer and the second InP layer with a part of the thickness are etched off directly above the first thin film layer to form the structure shown in c; the passive waveguide layer structure is epitaxially grown again, and the passive waveguide layer also uses Q1.05 material to form the structure shown in d; the passive waveguide layer structure above the quantum well layer is etched off to form a butt-joint structure of the passive waveguide and the quantum well gain region, as shown in e; an InP covering chip is epitaxially grown on the outermost layer to obtain a gain chip, as shown in f.

[0053] The method also includes coating one side of the gain chip with a high reflection film and the other side with an anti-reflection film.

[0054] Making silicon photonic chip spot converter: Figure 5 As shown, the silicon layer on the SOI substrate shown in a is etched into a silicon waveguide to form the structure shown in b; then a layer of silicon oxide is grown and polished, and the silicon oxide completely covers the SOI substrate and the silicon waveguide to form the structure shown in c; a third thin film layer and a silicon oxide covering layer are sequentially grown on the silicon oxide layer to obtain a silicon photonic chip pattern converter, as shown in d.

[0055] The gain chip is coupled to the end face of the silicon photonic chip spot converter.

[0056] In summary, the embodiment of the present invention proposes a hybrid integration technology, a gain chip design scheme and a corresponding silicon photonic chip spot converter, which can not only achieve high-efficiency coupling but also greatly increase the docking tolerance. This tolerance can already meet the accuracy of the automatic placement machine and can achieve passive end-face docking coupling.

[0057] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An optoelectronic integrated chip, characterized in that: include: Gain chip and silicon photonic chip mode spot converter; The gain chip includes a passive waveguide part and an active waveguide part; a first thin film layer is grown below the passive waveguide region of the passive waveguide part, and a second thin film layer is grown below the quantum well gain region of the active waveguide part; A third thin film layer is grown on the silicon waveguide of the silicon photonic chip spot converter; The TE fundamental mode supported by the passive waveguide part is greater than the mode field of the first threshold; the TE fundamental mode supported by the active waveguide part is greater than the mode field of the second threshold; the TE fundamental mode supported by the silicon photonic chip mode spot converter is greater than the mode field of the third threshold; One side of the gain chip is coated with a high-reflection film; and / or the other side of the gain chip is coated with an anti-reflection film.

2. The optoelectronic integrated chip according to claim 1, characterized in that: The bandgap widths of the first thin film layer and the second thin film layer correspond to an absorption wavelength of 1.05 um, and the third thin film layer is a silicon oxynitride thin film layer or a silicon nitride thin film layer.

3. The optoelectronic integrated chip according to claim 1, characterized in that: The thickness of at least one of the first film layer, the second film layer and the third film layer is between 0.05um and 0.15um.

4. The optoelectronic integrated chip according to claim 1, characterized in that: The refractive index of the first thin film layer and the second thin film layer is the same as the refractive index of the passive waveguide region.

5. The optoelectronic integrated chip according to claim 1, characterized in that: The thickness of the passive waveguide area in the passive waveguide part is 0.2-0.4um, the thickness of the first thin film layer is 0.05-0.09um, the waveguide spacing is 1-1.3um, the upper cladding thickness is 1.5-1.7um, the waveguide tip width is 0.6-0.9um, and the passive waveguide refractive index is 3.2-3.

3.

6. The optoelectronic integrated chip according to claim 1, characterized in that: The thickness of the second film layer is 0.05-0.09 um.

7. The optoelectronic integrated chip according to any one of claims 1 to 6, characterized in that: The thickness of the silicon oxide cladding in the silicon photonic chip spot converter is 5 to 8 um, the height of the bottom surface of the third thin film layer from the bottom surface of the silicon waveguide is 1.65 to 1.75 um, the thickness of the third thin film layer is 0.13 to 0.15 um, the refractive index of the third thin film layer is 1.500 to 1.650, the first tip width of the silicon waveguide is 0.13 to 0.16 um, the second tip width of the silicon waveguide is 0.22 to 0.25 um, the first tip length of the silicon waveguide is 150 to 230 um, the second tip length of the silicon waveguide is 45 to 60 um, and the third tip width of the silicon waveguide is 0.4 to 0.55 um.

8. A method for manufacturing an optoelectronic integrated chip according to any one of claims 1 to 7, characterized in that: include: Making a gain chip: starting from an InP substrate, epitaxially growing a first InP layer, a first thin film layer, a second thin film layer, a second InP layer and a quantum well layer in sequence, wherein the first thin film layer and the second thin film layer are at the same level, and the first thin film layer and the second thin film layer together constitute a layer, etching away a quantum well layer having the same area as the first thin film layer and a part of the thickness of the second InP layer directly above the first thin film layer, epitaxially growing a passive waveguide layer structure again, etching away the passive waveguide layer structure above the quantum well layer, forming a butt-joint structure of a passive waveguide and a quantum well gain region, and epitaxially growing a layer of InP to cover the chip, thereby obtaining a gain chip; Making a silicon photonic chip spot converter: etching the silicon layer on the SOI substrate into a silicon waveguide, then growing a layer of silicon oxide and grinding it flat, and sequentially growing a third thin film layer and a silicon oxide cover layer on the silicon oxide layer to obtain a silicon photonic chip spot converter; The gain chip is coupled to the end face of the silicon photonic chip spot converter.

9. The method for manufacturing an optoelectronic integrated chip according to claim 8, characterized in that: The method also includes coating one side of the gain chip with a high reflection film and the other side with an anti-reflection film.

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