The invention provides a high-speed
comparator offset front-end self-calibration circuit, and belongs to the technical field of analog-to-
digital converter circuits in
integrated circuit design. The self-calibration circuit comprises a calibration logic circuit, a calibration
voltage generation circuit, a back gate bias of a
comparator differential input geminate
transistor and a
comparator. Wherein the comparator and the back gate bias of the comparator differential input geminate
transistor are constituent parts of the ADC circuit; and the calibration
voltage generation circuit comprises a p-end calibration
voltage generation circuit and an n-end calibration voltage generation circuit, and the two end calibration voltage generation circuits are symmetrical in structure. An original ADC circuit is multiplexed, only a small amount of calibration
control logic and a counter are introduced to achieve self-calibration logic, a simple calibration voltage generation circuit is combined, calibration voltage is fed back to a back gate of a comparator differential input geminate
transistor, the offset voltage of the comparator is adjusted in an approximation mode through the bulk effect, and the self-calibration logic is achieved. On the premise that the speed of the comparator is not influenced, low cost and high calibration precision are realized.