Fan-out packaging method and packaging structure

Abstract

The present invention provides a fan-out packaging method and a packaging structure. The method includes: respectively providing a wafer carrier and a panel carrier; fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array through a hybrid bonding structure, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrier, cutting the multiple groups of first chips, and fixing the first surfaces of the multiple groups of first chips on the surface of the panel carrier in the form of a second array; forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier; separating the multiple groups of first chips from the panel carrier, and forming an interconnect wiring layer on the hybrid bonding structure. The packaging method of the present invention can not only greatly improve the interconnect density, reduce the interconnect pitch, but also provide a lower cost under the condition of the same interconnect density, and can also provide a higher interconnect density to meet the requirements of high-performance devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out packaging method and a packaging structure. Background Art

[0002] With the development of semiconductor technology, packaging technology has been developing towards high density / high integration. Currently, the fan-out technology has become an important development direction for high-density interconnection. By using the redistribution layer to connect single-chip and multi-chip, the flexibility of packaging integration has been greatly improved. The fan-out technology has been applied to fields such as high-performance computing (HPC) and mobile phone processors.

[0003] Currently, there are two main development directions for the fan-out technology. One is the fan-out wafer-level packaging (FOWLP) based on wafer technology, and the other is the fan-out panel-level packaging (FOPLP) based on panel technology. The wiring density of the fan-out wafer-level packaging can be higher. Currently, mass production with a line width of 2um has been achieved, but the yield is low and the cost is high. For the fan-out panel-level packaging, due to the high yield and low cost, but because of the large panel size and the difficulty in realizing fine line widths, the currently mass-producible line widths are all above 5um.

[0004] In view of the above problems, it is necessary to propose a fan-out packaging method and a packaging structure with reasonable design that can effectively solve the above problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a fan-out packaging method and a packaging structure.

[0006] One aspect of the present invention provides a fan-out packaging method, and the method includes:

[0007] Providing a wafer carrier and a panel carrier respectively;

[0008] Fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array through a hybrid bonding structure, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips;

[0009] Separating the multiple groups of first chips from the wafer carrier, cutting the multiple groups of first chips, and fixing the first surfaces of the multiple groups of first chips on the surface of the panel carrier in the form of a second array;

[0010] Forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier;

[0011] Separating the multiple groups of first chips from the panel carrier, and forming an interconnect wiring layer on the hybrid bonding structure.

[0012] Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad disposed on the first surface of multiple groups of first chips, and a second passivation layer and a second metal pad disposed on the side of the wafer carrier facing the multiple groups of first chips; wherein,

[0013] The first passivation layer is hybrid-bonded to the second passivation layer, and the first metal pad is hybrid-bonded to the second metal pad.

[0014] Optionally, separating the multiple groups of first chips from the wafer carrier includes:

[0015] Removing the wafer carrier by grinding and etching methods to expose the second passivation layer and the second metal pad.

[0016] Optionally, forming an interconnect wiring layer on the hybrid bonding structure includes:

[0017] Forming a first dielectric layer on the second passivation layer, the second metal pad, and the second encapsulation layer;

[0018] Patterning the first dielectric layer to form multiple first openings;

[0019] Forming a metal interconnect layer on the surface of the patterned first dielectric layer;

[0020] Patterning the metal interconnect layer to form the interconnect wiring layer.

[0021] Optionally, after forming the interconnect wiring layer, the method further includes:

[0022] Forming a second dielectric layer on the surface of the patterned metal interconnect layer;

[0023] Patterning the second dielectric layer to form multiple second openings;

[0024] Performing ball implantation at the multiple second openings to form multiple solder balls;

[0025] Cutting the multiple groups of first chips to form a single-group chip package structure.

[0026] Optionally, after forming multiple solder balls, the method further includes: polishing the side of the second encapsulation layer facing away from the multiple groups of first chips; or,

[0027] After forming the second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier, the method further includes: polishing the side of the second encapsulation layer facing away from the multiple groups of first chips.

[0028] Optionally, the first surface of the multiple groups of first chips is one of the front and back surfaces of the multiple groups of first chips, and the second surface of the multiple groups of first chips is the other of the front and back surfaces of the multiple groups of first chips.

[0029] Another aspect of the present invention provides a fan-out package structure, which includes a first chip, a hybrid bonding structure, an interconnect wiring layer, and a molding compound layer.

[0030] The hybrid bonding structure is disposed on the first surface of the first chip and the surface of the molding compound layer.

[0031] The interconnect wiring layer is disposed on the hybrid bonding structure.

[0032] The molding compound layer encapsulates the first chip.

[0033] Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad disposed on the first surface of the first chip, and a second passivation layer and a second metal pad sandwiched between the molding compound layer and the interconnect wiring layer.

[0034] The first passivation layer is hybrid-bonded to the second passivation layer, and the first metal pad is hybrid-bonded to the second metal pad.

[0035] Optionally, the interconnect wiring layer includes a first dielectric layer disposed on the second passivation layer and the second metal pad, and a metal interconnect layer disposed on the first dielectric layer.

[0036] Optionally, the package structure further includes a second dielectric layer and solder balls.

[0037] The second dielectric layer is disposed on the metal interconnect layer.

[0038] The solder balls are disposed on the second dielectric layer.

[0039] The fan-out packaging method according to an embodiment of the present invention fixes the first surfaces of multiple groups of first chips on the surface of a wafer carrier in the form of a first array through a hybrid bonding structure. By means of hybrid bonding, the interconnection density is greatly increased and the interconnection pitch is reduced. The wafer-level packaging technology can well meet the requirements of high-density interconnection. Separate multiple groups of first chips from the wafer carrier, cut the multiple groups of first chips, and fix the first surfaces of the multiple groups of first chips on the surface of a panel carrier in the form of a second array; form a second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier; separate the multiple groups of first chips from the panel carrier, and form an interconnection wiring layer on the hybrid bonding structure. The panel-level packaging technology can provide lower costs under the condition of the same interconnection density. The packaging method successively passes through fan-out wafer-level packaging and fan-out panel-level packaging. Compared with the current traditional fan-out wafer-level packaging, the fan-out packaging method of the present invention can provide lower costs and higher yield under the condition of the same interconnection density. Compared with the traditional fan-out panel-level packaging, the packaging method of the fan-out packaging structure of the present invention can provide higher interconnection density to meet the requirements of high-performance devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic flowchart of a fan-out packaging method according to an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the chip arrangement area in the wafer carrier according to another embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of the second array B on the panel carrier according to another embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of the first array A on the wafer carrier according to another embodiment of the present invention;

[0044] Figures 5 to 17 is a schematic diagram of the packaging process of a fan-out packaging structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0046] As Figure 1 shown, one aspect of the present invention provides a fan-out packaging method S100, and the packaging method S100 includes:

[0047] S110. Provide a wafer carrier and a panel carrier respectively.

[0048] Specifically, as Figure 2 , Figure 3 andFigure 4 As shown, the main materials of the wafer carrier 110 are glass, silicon wafers or metals. The main materials of the panel carrier 120 are glass, metal or fiberglass resin sheets. The materials of the wafer carrier 110 and the panel carrier 120 can also be other materials, which are not specifically limited in this embodiment.

[0049] S120. Fix the first surfaces of multiple groups of first chips in the form of a first array on the surface of the wafer carrier through a hybrid bonding structure, and form a first encapsulation layer on the second surfaces of the multiple groups of first chips.

[0050] Exemplarily, the hybrid bonding structure includes a first passivation layer and a first metal pad provided on the first surfaces of multiple groups of first chips, and a second passivation layer and a second metal pad provided on the side of the wafer carrier facing the multiple groups of first chips; wherein,

[0051] The first passivation layer is hybrid-bonded to the second passivation layer, and the first metal pad is hybrid-bonded to the second metal pad.

[0052] Specifically, as Figure 5 shown, a first passivation layer 131 and a first metal pad 132 are provided on the first surfaces of multiple groups of first chips 130, and a second passivation layer 111 and a second metal pad 112 are provided on the side of the wafer carrier 110 facing the multiple groups of first chips 130. In this embodiment, the materials of the first passivation layer 131 and the second passivation layer 111 can be silicon dioxide, or other materials that can play a passivation role, which are not specifically limited in this embodiment. In this embodiment, the materials of the first metal pad 132 and the second metal pad 112 are copper, or other materials, which are not specifically limited in this embodiment.

[0053] As Figure 5 shown, the first surfaces of multiple groups of first chips 130 are hybrid-bonded and fixed on the surface of the wafer carrier 110. That is to say, under the action of heat and pressure, the first passivation layer 131 on the first surface of the first chip 130 forms a bond with the second passivation layer 111 on the side of the wafer carrier 110 facing the first chip 130, and the first metal pad 132 on the first surface of the first chip 130 forms a bond with the second metal pad 112 on the side of the wafer carrier 110 facing the first chip 130. The first chip 130 is fixed on the wafer carrier 110 through hybrid bonding. Through the hybrid bonding method, the interconnection density of the first chip is greatly improved, and the interconnection pitch is reduced; by adopting the wafer-level packaging technology, the high-density interconnection requirements can be well realized, meeting the requirements of high-performance devices.

[0054] As Figure 4 shown, multiple groups of first chips 130 after hybrid bonding form a first array A, and the first array A is a square array. AsFigure 6 As shown, encapsulation is performed on the second surfaces of multiple groups of first chips 130 using encapsulant to form a first encapsulation layer 140. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process, and no specific limitation is made in this embodiment.

[0055] It should be noted that the first surface of multiple groups of first chips 130 can be the front side or the back side of multiple groups of first chips 130. Correspondingly, the second surface of multiple groups of first chips 130 is the other side of the front side and the back side of multiple groups of first chips 130. In this embodiment, the front sides of multiple groups of first chips 130 are fixed on the surface of the wafer carrier 110 through hybrid bonding.

[0056] It should be further noted that each group of first chips 130 includes one or more first chips 130. In this embodiment, each group of first chips includes one first chip 130.

[0057] S130. Separate the multiple groups of first chips from the wafer carrier, cut the multiple groups of first chips, and fix the first surfaces of the multiple groups of first chips on the surface of the panel carrier in the form of a second array.

[0058] Exemplarily, the separating the multiple groups of first chips from the wafer carrier includes:

[0059] Removing the wafer carrier by grinding and etching methods to expose the second passivation layer and the second metal pads.

[0060] Specifically, as Figure 7 shown, first, remove the wafer carrier 110 by grinding and etching methods to expose the second passivation layer 111 and the second metal pads 112 on the surface of the wafer carrier 110, so as to prepare for the subsequent steps. It should be noted that the etching method can be wet etching or dry etching, and no specific limitation is made in this embodiment. Of course, other methods can also be used to remove the wafer carrier 110 as long as the second passivation layer 111 and the second metal pads 112 on the surface of the wafer carrier 110 can be exposed.

[0061] Secondly, as Figure 8 and Figure 9 shown, cut the multiple groups of first chips 130 according to the area size of the panel carrier 120.

[0062] Then, fix the cut multiple groups of first chips 130 on the surface of the panel carrier 120 in the form of the second array B shown in Figure 3 , that is, the second passivation layer 111 and the second metal pads 112 are in contact with the adhesive 121. The panel-level packaging technology is adopted to improve the yield rate, and it can also provide lower cost under the condition of the same interconnect density.

[0063] S140. Form a second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier.

[0064] Specifically, as Figure 9 shown, use encapsulant to wrap the multiple groups of first chips 130 fixed on the panel carrier 120 to form a second encapsulation layer 150. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process, and this embodiment does not make specific limitations.

[0065] S150. Separate the multiple groups of first chips from the panel carrier and form an interconnection wiring layer on the hybrid bonding structure.

[0066] First, as Figure 11 shown, separate the panel carrier 120 and the adhesive 121. The separation method can adopt thermal separation, laser separation, ultraviolet light separation, mechanical separation and other methods. These methods are all currently commonly used temporary bonding separation methods, and this embodiment does not make specific limitations on the separation method, which can be selected according to actual needs.

[0067] Secondly, form an interconnection wiring layer on the hybrid bonding structure, including: forming a first dielectric layer on the second passivation layer, the second metal pad and the second encapsulation layer, patterning the first dielectric layer to form a plurality of first openings, forming a metal interconnection layer on the surface of the patterned first dielectric layer, and patterning the metal interconnection layer to form the interconnection wiring layer.

[0068] Specifically, as Figure 12 shown, coat a first dielectric layer 160 on the second passivation layer 111, the second metal pad 112 and the second encapsulation layer 150. The material of the first dielectric layer 160 is photosensitive dielectric layer (PID) or Ajinomoto Build-up Film (ABF), etc. The process can be vacuum laminating or printing process. The first dielectric layer 160 plays a protective role for the second passivation layer 111 and the second metal pad 112. This embodiment does not make specific limitations on the material of the first dielectric layer 160 and the coating process, which can be selected according to actual requirements.

[0069] Pattern the first dielectric layer 160 through a photolithography process to form a plurality of first openings (not marked in the figure) on the first dielectric layer 160.

[0070] Deposit a metal interconnection layer 170 on the surface of the patterned first dielectric layer. The deposition method can adopt processes such as electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. The metal material is usually titanium and copper. This embodiment does not make specific limitations on the deposition method and the metal material.

[0071] As Figure 12 shown, the metal interconnect layer 170 is patterned through a photolithography and etching process to form an interconnect wiring layer. The etching process can be wet etching or dry etching, and no specific limitation is made in this embodiment.

[0072] Exemplarily, after forming the interconnect wiring layer, the method further includes:

[0073] forming a second dielectric layer on the surface of the patterned metal interconnect layer, patterning the second dielectric layer to form a plurality of second openings, and performing ball implantation at the plurality of second openings to form a plurality of solder balls.

[0074] Specifically, as Figure 13 shown, a second dielectric layer 180 is coated on the surface of the patterned metal interconnect layer 170. The material of the second dielectric layer 180 can use photosensitive solder resist (PSR), and the process can be vacuum laminating or printing process. No specific limitation is made in this embodiment for the material and coating process of the first dielectric layer 160, and it can be selected according to actual requirements.

[0075] As Figure 13 shown, the second dielectric layer 180 is patterned by a photolithography process to form a plurality of second openings 181 on the second dielectric layer 180.

[0076] As Figure 14 shown, ball implantation is performed at the plurality of second openings 181 to form a plurality of solder balls 190.

[0077] As Figure 15 shown, after forming the plurality of solder balls 190, the multi-group first chips 130 are diced to form a single-group chip package structure as shown.

[0078] Exemplarily, as Figure 16 shown, after forming the plurality of solder balls 190, the side of the second encapsulation layer 150 facing away from the multi-group first chips 130 is polished to reduce the encapsulation thickness. In this embodiment, the side of the second encapsulation layer 150 facing away from the multi-group first chips 130 is completely removed after polishing, and then after dicing, the encapsulation structure as shown in Figure 17 is finally formed.

[0079] Alternatively, after forming the second encapsulation layer on the side of the multi-group first chips facing away from the panel carrier, the method further includes:

[0080] As Figure 10As shown, the side of the second encapsulation layer 170 facing away from the multiple groups of first chips 130 is polished to reduce the encapsulation thickness. In this embodiment, the side of the second encapsulation layer 170 facing away from the multiple groups of first chips 130 is completely removed. Then, through the various steps described above, an encapsulation structure as shown in Figure 17 is finally formed.

[0081] It should be noted that in the given embodiment, it is a 3-layer or 4-layer dielectric layer structure. Actually, the present invention can be applied to multiple layers and can be adjusted according to actual design requirements. The number of interconnect layers used in wafer-level and panel-level processes can also be adjusted according to actual design needs. For example, when high-density interconnect is also required for the second interconnect layer (which cannot be achieved by panel-level processes), two interconnect layers can be fabricated using wafer-level processes and then transferred to panel-level processes for subsequent processing.

[0082] It should be further noted that in the present invention, as shown in Figure 2 , the middle area of the wafer carrier 110 is the chip layout area 113. The chip layout area 113 is distributed in the form of a first array A as shown in Figure 3 . The chip layout area 113 is a square structure, and the length of its diagonal is equivalent to the diameter of the wafer carrier 110. Through temporary bonding and wafer-level redistribution, a high-density interconnect wiring layer is formed in the middle area. The chip layout area 113 with completed high-density interconnect is cut and then integrally built onto the panel carrier 120 in the form of a second array B as shown in Figure 4 .

[0083] As shown in Figure 4 , the currently commonly used size of the panel carrier 120 is 510×515 mm. In this case, 4 chip layout areas 113 can be placed simultaneously. By using panel-level packaging interconnect technology to complete the subsequent processes, the production efficiency can reach 4 times that of wafer-level packaging technology. In the future, if LCD panel technology is used, the production efficiency can be increased to 6 - 8 times, and the cost will be greatly reduced.

[0084] As shown in Figure 2 , since the area of the chip layout area 113 is smaller than the area of the wafer carrier 110, there will be a certain area loss. Considering that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, and the short side dimension of it is 28 mm. For samples with a packaging size close to or larger than 28 mm, this area is an invalid area. However, for samples with a packaging size close to or smaller than 28 mm, the blank area 114 can still be used. Therefore, the design of the chip layout area 113 will not increase the cost of wafer-level packaging. Since high-density interconnect is mainly applied in fields such as high-performance computing, and the packaging in this field is moving towards larger sizes, the present invention has a significant effect of reducing costs.

[0085] In the package design, usually, the interconnect layer density is high near the chip, while the interconnect layer density is low far from the chip, and the line width of the connecting lines shows a trend of gradually increasing. Taking advantage of this feature, in the packaging method of the fan-out package structure provided by the present invention, the fan-out wafer-level packaging technology and the fan-out panel-level packaging technology are integrally used to complete the production of the fan-out package. For the interconnect layer near the chip, the wafer-level packaging technology can well meet the high-density interconnect requirements, while for the interconnect layer far from the chip, the panel-level packaging technology can improve the yield and reduce the manufacturing cost. At the same time, the interconnect layer near the chip adopts the hybrid bonding method, which greatly improves the interconnect density and reduces the interconnect pitch.

[0086] As Figure 17 shown, on the other hand, the present invention provides a fan-out package structure 100, and the package structure 100 includes a first chip 130, a hybrid bonding structure (not marked in the figure), an interconnect wiring layer (not marked in the figure), and a molding compound layer 140.

[0087] The hybrid bonding structure is disposed on the first surface of the first chip 130 and the surface of the molding compound layer 140, the interconnect wiring layer is disposed on the hybrid bonding structure, and the molding compound layer 140 wraps the first chip 130.

[0088] It should be noted that the first surfaces of multiple groups of the first chips 130 can be the front sides of multiple groups of the first chips 130, or the back sides. Correspondingly, the second surfaces of multiple groups of the first chips 130 are the other sides among the front sides and the back sides of multiple groups of the first chips 130. In this embodiment, the first surfaces of multiple groups of the first chips 130 are the front sides.

[0089] It should be further noted that each group of the first chips 130 includes one or more first chips 130. In this embodiment, each group of the first chips includes one first chip 130.

[0090] Exemplarily, as Figure 17 shown, the hybrid bonding structure includes a first passivation layer 131 and a first metal pad 132 disposed on the first surface of the first chip 130, and a second passivation layer 111 and a second metal pad 112 sandwiched between the molding compound layer 140 and the interconnect wiring layer. The first passivation layer 131 is hybrid-bonded to the second passivation layer 111, and the first metal pad 132 and the second metal pad 112 are hybrid-bonded. By the hybrid bonding method, the interconnect density can be greatly improved and the interconnect pitch can be reduced.

[0091] Exemplarily, as Figure 17 shown, the interconnect wiring layer includes a first dielectric layer 160 disposed on the second passivation layer 111 and the second metal pad 112, and a metal interconnect layer 170 disposed on the first dielectric layer 160.

[0092] It should be noted that the material of the first dielectric layer 160 is a photosensitive dielectric layer (PID) or an Ajinomoto build-up film (ABF), etc., and no specific limitation is made in this embodiment. The material of the metal interconnect layer 170 is usually metal titanium and metal copper, and no specific limitation is made on the metal material in this embodiment.

[0093] Exemplarily, as Figure 17 shown, the packaging structure 100 further includes a second dielectric layer 180 and solder balls 190. The second dielectric layer 180 is disposed on the metal interconnect layer 170, and the solder balls 190 are disposed on the second dielectric layer 180.

[0094] The fan-out packaging structure of the present invention not only has low cost and high yield, but also can greatly improve the interconnect density and reduce the interconnect pitch.

[0095] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A fan-out packaging method, characterized in that, The method includes: providing a wafer carrier and a panel carrier respectively; fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array through a hybrid bonding structure, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrier, cutting the multiple groups of first chips, and fixing the first surfaces of the multiple groups of first chips on the surface of the panel carrier in the form of a second array; forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier; separating the multiple groups of first chips from the panel carrier, and forming an interconnect wiring layer on the hybrid bonding structure.

2. The method according to claim 1, wherein The hybrid bonding structure includes a first passivation layer and a first metal pad provided on the first surface of multiple groups of first chips, and a second passivation layer and a second metal pad provided on the side of the wafer carrier facing the multiple groups of first chips; wherein, the first passivation layer is hybrid bonded to the second passivation layer, and the first metal pad is hybrid bonded to the second metal pad.

3. The method according to claim 2, wherein The separating the multiple groups of first chips from the wafer carrier includes: removing the wafer carrier by grinding and etching methods to expose the second passivation layer and the second metal pad.

4. The method according to claim 2, wherein The forming the interconnect wiring layer on the hybrid bonding structure includes: forming a first dielectric layer on the second passivation layer, the second metal pad, and the second encapsulation layer; patterning the first dielectric layer to form a plurality of first openings; forming a metal interconnect layer on the surface of the patterned first dielectric layer; patterning the metal interconnect layer to form the interconnect wiring layer.

5. The method according to claim 4, wherein After forming the interconnect wiring layer, the method further includes: forming a second dielectric layer on the surface of the patterned metal interconnect layer; patterning the second dielectric layer to form a plurality of second openings; performing ball implantation at the plurality of second openings to form a plurality of solder balls; cutting the multiple groups of first chips to form a single-group chip package structure.

6. The method according to any one of claims 1 to 5, characterized in that, After forming the plurality of solder balls, the method further includes: polishing the side of the second encapsulation layer facing away from the multiple groups of first chips; or, after forming the second encapsulation layer on the side of the multiple groups of first chips facing away from the panel carrier, the method further includes: polishing the side of the second encapsulation layer facing away from the multiple groups of first chips.

7. The method according to any one of claims 1 to 5, characterized in that, The first surface of the multiple groups of first chips is one of the front and back surfaces of the multiple groups of first chips, and the second surface of the multiple groups of first chips is the other of the front and back surfaces of the multiple groups of first chips.

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