System on chip and method for regulating voltage and frequency

Abstract

Provided are a system on chip and a method for adjusting voltage and frequency. The system on chip includes: a sensor component; a processing unit, which is used to periodically send frequency modulation instructions at a predetermined time interval, and the frequency modulation instructions include adjacent first frequency modulation instructions and second frequency modulation instructions; an AVFS controller, coupled to the sensor component, which is used to start the sensor component to acquire and cache detection data for a set time after sending or receiving the first frequency modulation instruction, and determine the power supply voltage of the system on chip according to the target frequency and detection data in the second frequency modulation instruction, wherein the set time is less than the predetermined time interval; an on-chip bus, which couples the processing unit and the AVFS controller. Compared with the prior art, the AVFS controller directly uses the cached detection data to determine the power supply voltage in the frequency modulation and voltage regulation operation, thereby saving the detection data acquisition time and improving the processing speed of the frequency modulation and voltage regulation operation.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular to a system on chip and a method for adjusting voltage and frequency. Background Art

[0002] The trend of miniaturization of integrated circuits has made processor manufacturers enthusiastic about how to reduce power consumption. Adaptive Voltage Frequency Scaling (AVFS) is one of the methods for processors to reduce power consumption. It determines the supply voltage by measuring the detection data in real time through sensors.

[0003] In the AVFS system, the operating system usually performs frequency and voltage modulation operations by defining an independent timer to initiate an interrupt at a certain interval (usually 20ms). The interrupt handler is executed by the processor, which operates the AVFS controller to start the sensor to measure the detection data, then reads the detection data, and then adjusts the supply voltage and clock frequency.

[0004] The disadvantage of this solution is that the entire process is controlled serially by software, which results in a waste of speed. Summary of the invention

[0005] In view of this, an object of the present disclosure is to provide a system on chip and a method for adjusting voltage and frequency to solve the problems in the prior art.

[0006] In a first aspect, an embodiment of the present disclosure provides a system on a chip.

[0007] Sensor components;

[0008] A processing unit, configured to periodically send a frequency modulation instruction at a predetermined time interval, wherein the frequency modulation instruction includes a first adjacent frequency modulation instruction and a second adjacent frequency modulation instruction;

[0009] an AVFS controller, coupled to the sensor component, configured to start the sensor component to acquire and cache detection data for a set time after sending or receiving the first frequency modulation instruction, and determine a supply voltage of the system on chip according to a target frequency in the second frequency modulation instruction and the detection data, wherein the set time is less than the predetermined time interval;

[0010] An on-chip bus couples the processing unit and the AVFS controller.

[0011] Optionally, the AVFS controller is coupled to a timer, and the AVFS controller further includes a control unit, wherein the timer is configured to start timing when the first frequency modulation instruction is sent or received, and notify the control unit when the timer continues for a set period of time, so that the control unit starts the sensor component.

[0012] Optionally, the timer is set inside the AVFS controller, or the timer is set inside the system on chip but outside the AVFS controller.

[0013] Optionally, the processing unit notifies the timer to start timing when sending the first frequency modulation instruction, or the AVFS controller notifies the timer to start timing when receiving the first frequency modulation instruction.

[0014] Optionally, the AVFS controller is configured with at least one frequency and multiple voltage table entries corresponding to each frequency, and the AVFS controller also includes a voltage determination unit, which is used to determine a first voltage from the multiple voltage table entries as the power supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data.

[0015] Optionally, the AVFS controller is configured with at least one frequency, and the AVFS controller further includes a voltage determination unit, which is used to calculate the power supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data based on a predefined voltage calculation rule.

[0016] Optionally, the sensor assembly further includes: at least one of a temperature sensor assembly, a process sensor assembly and a voltage sensor assembly.

[0017] In a second aspect, an embodiment of the present disclosure provides a method for adjusting voltage and frequency, including:

[0018] The processing unit periodically sends a frequency modulation instruction at a predetermined time interval, wherein the frequency modulation instruction includes a first adjacent frequency modulation instruction and a second adjacent frequency modulation instruction;

[0019] The AVFS controller starts the sensor component for a set time period after sending or receiving the first frequency modulation instruction to acquire and cache detection data, and determines the supply voltage of the system on chip based on the target frequency in the second frequency modulation instruction and the detection data, and the set time period is less than the predetermined time interval.

[0020] Optionally, the AVFS controller is coupled to a timer, and the timer is used to start timing when the first frequency modulation instruction is sent or received, and to notify the AVFS controller to start the sensor component when the time lasts for a set period of time.

[0021] Optionally, the processing unit notifies the timer to start timing when sending the first frequency modulation instruction, or the AVFS controller notifies the timer to start timing when receiving the first frequency modulation instruction.

[0022] In a third aspect, an embodiment of the present disclosure provides a computing device, including:

[0023] The system on chip as described in any one of the above items;

[0024] Off-chip bus;

[0025] a storage device coupled to the system on chip via the off-chip bus;

[0026] A power management circuit is coupled to the AVFS controller in the system on chip.

[0027] Compared with the prior art, the system on chip provided by the embodiment of the present disclosure saves the time for collecting detection data and improves the processing speed of frequency and voltage modulation operations because the AVFS controller directly uses cached detection data to determine the supply voltage during frequency and voltage modulation operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0029] Figure 1 is a schematic diagram of the structure of a system on a chip provided by an embodiment of the present disclosure;

[0030] Figure 2 It is a timing diagram of the processing unit sending the frequency modulation instruction and the AVFS controller starting the sensor component in the embodiment of the present disclosure;

[0031] Figure 3 is a schematic diagram of an exemplary structure of an AVFS controller;

[0032] Figure 4 is another exemplary structural diagram of an AVFS controller;

[0033] Figure 5 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure;

[0034] Figure 6 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure;

[0035] Figure 7 It is a schematic diagram of the structure of the embedded system used in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0037] The system on chip of the present disclosure

[0038] Figure 1 Schematic diagram of the structure of the system on chip 100 used in the embodiment of the present disclosure.

[0039] As shown in the reference figure, the on-chip bus 102 couples various components to the processing unit 101. The on-chip bus 102 is, for example, an AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM. It is an on-chip bus oriented to high performance, high bandwidth, and low latency. The AIX bus separates the address / control and data phases, supports unaligned data transmission, and supports burst transmission and out-of-order transmission, thereby meeting the requirements of ultra-high performance and complex on-chip system design.

[0040] As shown in the figure, the AVFS controller 103 and the high-speed memory 104 are coupled to the processing unit 101 via the on-chip bus 102. The AVFS controller 103 is coupled to the clock management unit 105, the sensor 106, and the power management circuit 211 located outside the chip.

[0041] In some embodiments, the power management circuit 211 may also be located inside the system on chip 100. One or more sensors 106 are used to obtain detection data of the system on chip in real time. The system on chip 100 may also include an interface circuit not shown, which is coupled to an external device outside the chip through the interface circuit. The external device may be, for example, an input / output device for text, audio and video and various other memories. The system on chip 100 may access the external device outside the chip through the interface circuit. Unlike the high-speed memory 104 provided in the system on chip, the memory outside the chip may have a larger capacity but a slower speed and a lower cost. In some implementations, the high-speed memory 104 may be a static random access memory (SRAM), while the memory outside the chip is a DRAM (dynamic random access memory) and a flash memory. Designers may also configure the system on chip so that the communication between the various components in the system on chip is secure.

[0042] As shown in the figure, basic software (such as embedded control system 121) and application programs (such as application program AN) are embedded in system on chip 100. Other application programs not shown can be stored in a memory outside system on chip 100, and these application programs can be copied to high-speed memory 104 in system on chip 100 through interface circuits for execution, or access resources on system on chip 100 through interface circuits.

[0043] When the AVFS controller 103 is working, it receives a configuration instruction and a frequency modulation instruction from the on-chip bus 102. The configuration instruction includes at least one frequency. The frequency modulation instruction includes a target frequency, that is, the on-chip system 100 is to be adjusted from the current frequency to the target frequency. The AVFS controller 103 reads at least one frequency from the configuration instruction and stores it in the AVFS controller 103. At the same time, the AVFS controller 103 obtains the target frequency from the frequency modulation instruction, and compares the target frequency with each frequency in the configuration table 1031. When a certain frequency matches the target frequency, it indicates that the target frequency is a legal frequency. Then, the target frequency and the detection data of the system on chip 100 are used to determine the power supply voltage provided to the system on chip 100, and a voltage adjustment signal REGV is generated according to the power supply voltage, and sent to the power management circuit 211. The power management circuit 211 thus provides the power supply voltage VCPU to the system on chip 100. At the same time, the AVFS controller 103 generates a frequency modulation signal REGF and sends it to the clock management unit 105, and the clock management unit 105 adjusts the clock frequency FCPU of the system on chip 100. The AVFS controller 103 also refuses frequency adjustment when the target frequency does not match any frequency in the at least one frequency, and generates an alarm signal ALARM.

[0044] The processing unit 101 generates configuration instructions and frequency modulation instructions. For example, the configuration instructions may be generated when the boot program is executed. The boot program is used to load the embedded control system 121 after the machine is powered on. That is, during the period from when the machine is powered on to when the embedded control system 121 is working normally, the configuration instructions are generated when the boot program is executed. The advantage of this is that since various interface circuits may not work normally when the boot program is running, it is not easy for external attack software to attack the configuration instructions. For another example, the processing unit 101 generates a frequency modulation instruction when executing the executable code from the embedded control system 121, and the frequency modulation instruction can be generated periodically by the processing unit 101. The embedded control system 121 executes the following computer code at intervals of T: first, collect signals related to the system load and calculate the current system load; then, based on the current load of the system, predict the performance required by the system in the next time period; then convert the predicted performance into the required frequency, and then call the system interface to modify the system clock frequency to the required frequency. The system interface is an interface provided by the embedded control system for calling the underlying hardware unit. When decoding and executing the above computer code, the processing unit 101 generates a frequency modulation instruction sent to the hardware AVFS controller by calling the system interface.

[0045] It should be noted that the at least one frequency specified by the configuration instruction is a verified frequency that enables the system on chip 100 to operate normally.

[0046] In the on-chip system provided in the above embodiment, at least one frequency is configured through configuration instructions to limit the allowable value range of the system's clock frequency. If the modification of the clock frequency by the frequency modulation instruction is within the allowable value range, the frequency and voltage modulation operations can be carried out normally. If it is outside the allowable value range, an alarm is processed to improve the safety of the frequency and voltage modulation operations.

[0047] In one implementation, the system on chip 100 includes a static storage unit, which contains a plurality of frequencies that enable the system on chip 100 to operate normally, and at least one frequency specified in the configuration instruction is included in the plurality of frequencies.

[0048] Figure 2It is a timing diagram of the processing unit sending the frequency modulation instruction and the AVFS controller starting the sensor component of the embodiment of the present disclosure. As shown in the figure, the processing unit 101 periodically sends the frequency modulation instruction at intervals of time length T, wherein at time S0, the first frequency modulation instruction indicates that the system clock frequency is to be adjusted to Fs0, at time S1, the second frequency modulation instruction indicates that the system clock frequency is to be adjusted to Fs1, and at time S2, the third frequency modulation instruction indicates that the system clock frequency is to be adjusted to Fs2. If the time delay is not considered, the AVFS controller receives the first frequency modulation instruction at time S0, starts timing, and starts the sensor component to collect and cache the detection data at time H1 (the time length from time S0 is t0). Therefore, when the AVFS controller receives the second frequency modulation instruction at time S1, it can determine the power supply voltage of the system on chip 100 according to the detection data cached at time H1. Similarly, the AVFS controller starts timing at time S1, and starts the sensor component to collect and cache detection data at time H2 (the time length from time S1 is t0). Therefore, when the AVFS controller receives the third frequency modulation instruction at time S2, it can determine the power supply voltage of the system on chip 100 based on the detection data cached at time H2.

[0049] In summary, in the system on chip provided by the above embodiment, the AVFS controller directly uses the cached detection data to determine the supply voltage during the frequency and voltage modulation operation, thereby saving the detection data collection time and improving the processing speed of the frequency and voltage modulation operation.

[0050] It should be understood that this method of starting the sensor component in advance to cache detection data can be used not only for frequency and voltage regulation operations, but also for other aspects. For example, it can be used to periodically detect whether there is an abnormality in the on-chip system. Specifically, the sensor is started to collect and cache detection data at a set time before each cycle, and then the cached detection data is used to detect whether there is an abnormality in the on-chip system.

[0051] Figure 3 is a schematic diagram of an exemplary structure of an AVFS controller.

[0052] As shown in the figure, the AVFS controller 103 includes a register group for storing a configuration table 1031 , a voltage determination unit 202 , a frequency conversion control unit 206 , a register group 212 , a control unit 211 , a timer 213 , and a plurality of sensor components.

[0053] The configuration table 1031 includes multiple frequencies 1-n, which are generated by the AVFS controller 103 according to the configuration instruction. For example, the AVFS controller 103 reads the multiple frequencies 1-n from the one-time programmable storage unit according to the configuration instruction and stores them in the configuration table 1031.

[0054] The control unit 211 determines the start time of the sensor component through the timer 213 and starts the sensor component to obtain the detection data. The sensor component caches the detection data in the register group 212. Figure 2 As described above, as an implementation, the control unit 211 notifies the timer 213 to start timing when receiving the first frequency modulation instruction, and starts multiple sensor components to obtain detection data and cache it in the register group 212 when the duration is t0.

[0055] The control unit 211 is also used to start the voltage determination unit 202 and the frequency conversion control unit 206. When receiving the frequency modulation instruction, the control unit 211 obtains the target frequency from the frequency modulation instruction and determines whether the target frequency is included in the configuration table 1031. If yes, it means that the target frequency is legal. If not, it means that the target frequency is illegal. When the target frequency is legal, the control unit 211 starts the voltage determination unit 202 and the frequency conversion control unit 206.

[0056] The voltage determination unit 202 reads the detection data from the register group 212, calculates the power supply voltage of the system on chip 100 based on the detection data and the target frequency according to a predefined voltage calculation rule, and generates a voltage regulation signal REGV according to the power supply voltage. For example, based on a given formula, the real-time detection data and the target frequency are substituted into the calculation formula to obtain the power supply voltage.

[0057] The frequency conversion control unit 206 generates a frequency modulation signal REGF according to the target frequency. Optionally, the AVFS controller 103 may further include an alarm unit (not shown) for performing alarm processing when the target frequency is illegal or otherwise abnormal.

[0058] As shown in the figure, the multiple different sensor components include a temperature sensor component, a process sensor component and a voltage sensor component. The temperature sensor component includes a temperature sensor controller 203 and a temperature sensor 206. The process sensor component includes a process sensor controller 204 and a process sensor 207. The voltage sensor component includes a voltage sensor controller 205 and a voltage sensor 208. The temperature sensor 206, the process sensor 207 and the voltage sensor 208 respectively collect analog signals of the real-time temperature, process deviation and real-time voltage of the system on chip 100, and convert the analog signals into digital signals. The temperature sensor controller 203, the process sensor controller 204 and the voltage sensor controller 205 respectively control the temperature sensor 206, the process sensor 207 and the voltage sensor 208, for example, to control the start and stop of the sensor to collect detection data. Among them, the process deviation represents the gap between the actual process of the system and the standard process, and the process deviation will affect the power supply voltage.

[0059] Accordingly, the voltage determination unit 202 is used to calculate the supply voltage based on the target frequency and the real-time temperature of the system and the process deviation according to the predefined voltage calculation rules, or first calculate the supply voltage based on the target frequency and the real-time temperature of the system according to the predefined voltage calculation rules, and then bias the supply voltage according to the process deviation. After completing the voltage regulation, the voltage determination unit 202 can also obtain the current real-time voltage through the voltage sensor 208, and compare the real-time voltage with the supply voltage determined by the voltage determination unit 202, in order to determine whether the voltage regulation operation is successful. If it is unsuccessful, for example, the difference between the real-time voltage and the supply voltage determined by the voltage determination unit 202 is too large, the voltage calculation rules can be adjusted so that the adjusted voltage calculation formula can be used in subsequent voltage calculations.

[0060] Figure 4 1 is another exemplary structural diagram of the AVFS controller. As shown in the figure, the AVFS controller 103 includes a register group for storing a configuration table 1032, a voltage determination unit 212 and a frequency conversion control unit 206, a register group 212, a control unit 211, and a plurality of different sensor components for measuring detection data. The timer 214 is located inside the system on chip 100 but outside the AVFS controller 103.

[0061] As shown in the figure, the configuration table 1032 stores multiple frequencies 1-n and voltage table items 1-k corresponding to each of the multiple frequencies 1-n, where n and k are positive integers greater than or equal to 1. The configuration table 1032 can be generated by the AVFS controller 103 according to the configuration instruction. For example, the AVFS controller 103 reads multiple frequencies 1-n and voltage table items 1-k corresponding to each frequency from the one-time programmable storage unit according to the configuration instruction and stores them in the configuration table 1031.

[0062] The control unit 211 determines the start time of the sensor component through the timer 214 and starts the sensor component to obtain the detection data. The sensor component caches the detection data in the register group 212. Figure 2 As described above, as an implementation, the control unit 211 notifies the timer 213 to start timing when receiving the first frequency modulation instruction, and starts multiple sensor components to obtain detection data and cache it in the register group 212 when the duration is t0.

[0063] The control unit 211 is also used to start the voltage determination unit 202 and the frequency conversion control unit 206. When receiving the frequency modulation instruction, the control unit 211 obtains the target frequency from the frequency modulation instruction and determines whether the target frequency is included in the configuration table 1031. If yes, it means that the target frequency is legal. If not, it means that the target frequency is illegal. When the target frequency is legal, the control unit 211 starts the voltage determination unit 202 and the frequency conversion control unit 206.

[0064] The voltage determination unit 212 determines the supply voltage by table lookup. Specifically, the voltage determination unit 202 selects a voltage table item from multiple voltage table items corresponding to the target frequency as the supply voltage of the system on chip 100 based on the detection data collected by multiple sensor components.

[0065] The frequency conversion control unit 206 generates a frequency modulation signal REGF according to the target frequency in the frequency modulation instruction, so as to adjust the clock frequency of the system on chip 100 .

[0066] It should be understood that Figure 3 and 4 The structure diagram of the AVFS controller shown is only an exemplary structure diagram. Those skilled in the art can also conceive of the structure diagram of the AVFS controller as long as it meets the requirements. Figure 2 The inventive principles shown should all be within the protection scope of the embodiments of the present disclosure.

[0067] Method for adjusting voltage and frequency according to the embodiment of the present disclosure

[0068] Figure 5 1 is a flow chart of a method for adjusting voltage and frequency provided by an embodiment of the present disclosure. The method is executed by the above-mentioned system on chip. As shown in the figure, the method includes the following steps.

[0069] In step S501, the processing unit periodically sends frequency modulation instructions at a predetermined time interval, wherein the frequency modulation instructions include adjacent first frequency modulation instructions and second frequency modulation instructions. That is, the processing unit periodically sends frequency modulation instructions at a predetermined time interval when processing the software program.

[0070] In step S502, after receiving the first frequency modulation instruction, the AVFS controller starts the sensor component for a set period of time to acquire and cache detection data, and determines the supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data.

[0071] In this embodiment, the timer starts timing when sending or receiving the first frequency modulation instruction, and starts the sensor component to obtain and cache the detection data when the set duration is continued, so that the cached detection data can be directly used to determine the power supply voltage of the system on chip and adjust the power supply voltage accordingly when responding to the second frequency modulation instruction. The first frequency modulation instruction and the second frequency modulation instruction are adjacent frequency modulation instructions sent periodically at a predetermined time interval. Compared with the prior art, the AVFS controller saves the detection data collection time in the frequency modulation and voltage regulation operation, thereby improving the processing speed of the frequency modulation and voltage regulation operation.

[0072] It should be understood that in this embodiment, the set duration must be less than the predetermined time interval. In practice, the R&D personnel determine the set duration based on the time it takes for the sensor component to collect the detection data. For example, if the processing unit sends the frequency modulation instruction periodically at 20ms, and the average time it takes for the sensor component to cache the detection data in the register from startup to cache the detection data is 3ms, the sensor component can be started at 17ms of each time interval, so that the detection data can be cached in time and the real-time nature of the detection data can be basically guaranteed.

[0073] In some embodiments, the AVFS controller is coupled to a timer, and the timer is configured to start timing from when the first frequency modulation instruction is sent or received, and notify the AVFS controller to start the sensor component when the time lasts for a set period of time.

[0074] In some embodiments, the processing unit notifies the timer to start timing when sending the first frequency modulation instruction, or the AVFS controller notifies the timer to start timing when receiving the first frequency modulation instruction.

[0075] Specific Applications of System-on-Chip

[0076] Figure 6 6 is a schematic diagram of the structure of a general computer system used in the embodiments of the present disclosure. As shown in the figure, the computer system 600 may include one or more processors 12 and a memory 14. The system on chip provided in the above embodiments may be used as the processor 12.

[0077] The memory 14 in the computer system 600 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0078] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 600 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0079] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and other parts. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory. The write access request specifies the write data and the corresponding physical address that need to be written into the memory; the memory management unit 122 is used to translate the virtual addresses specified by these instructions into the physical addresses mapped by the virtual addresses. The physical address specified by the write access request may be consistent with the physical address specified by the corresponding instruction.

[0080] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0081] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 600.

[0082] In addition, the computer system 600 may also include input / output devices such as a storage device 16, a display device 13, an audio device 19, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0083] The computer system 600 also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication that complies with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication that complies with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module that uses other protocols, such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0084] Of course, the structure of different computer systems may vary according to the motherboard, operating system and instruction set architecture. For example, many computer systems are currently provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated into the processor 12 or independent of the processor 12.

[0085] Figure 7 701 is a structural diagram of an embedded system used in the embodiment of the present disclosure. The system on chip provided in the above embodiment can be used as the processor 701.

[0086] Although embedded systems are highly similar to computer systems in hardware structure, the characteristics of embedded system applications make them quite different from general computer systems in hardware composition and implementation.

[0087] First, in order to meet the requirements of the embedded system 700 in terms of speed, volume and power consumption, the operating system, application software, special data and other data that need to be stored for a long time usually do not use storage media such as disks with large capacity and slow speed, but mostly use random access memory 702 or flash memory (Flash Memory) 703.

[0088] In addition, in the embedded system 700, an A / D (analog / digital conversion) interface 705 and a serial interface 706 are required for the needs of measurement and control, which are rarely used in general-purpose computers. The A / D interface 705 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in the test. When the embedded system 700 is applied to industrial production, it often needs to be tested. Since the single-chip microcomputer generates digital signals, it needs to be converted into analog signals for testing during testing. Therefore, unlike general-purpose computers, an A / D (analog / digital conversion) interface 705 is required to complete the relevant conversion. In addition, in industry, multiple embedded systems are often required to be connected in series to complete relevant functions, so a serial interface 706 is required for connecting multiple embedded systems in series, which is mostly not required in general-purpose computers.

[0089] In addition, as a basic processing unit, the embedded system 700 often needs to connect multiple embedded systems 700 into a network in industrial design, so it is necessary to connect the embedded system 700 to the network interface 707. This is also not required in general-purpose computers. In addition, according to the actual application and scale, some embedded systems 700 need to use external buses 704. With the rapid expansion of the application field of embedded systems 700, embedded systems 700 are becoming more and more personalized, and the types of buses used according to their own characteristics are also increasing. In addition, in order to test the internal circuits of the embedded processor 701, the processor chip generally adopts boundary scan test technology. In order to adapt to this test, a debugging interface 708 is adopted.

[0090] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above embedded systems can be implemented on a silicon chip, namely, an embedded system on chip (SoC).

[0091] The commercial value of the disclosed embodiments

[0092] The system-on-chip provided by the embodiment of the present disclosure can be used to form a computing device used in a variety of scenarios, such as a large number of cloud servers in a data center. In this scenario, the power consumption of each cloud server is reduced by reducing the power consumption of the processor, thereby reducing the operating cost of each cloud server and the entire data center. For example, electronic devices used in daily life, including terminal devices such as notebooks and mobile phones and certain consumer electronic products, can improve the system life of electronic devices by reducing power consumption, thereby improving user experience. It can be seen that the system-on-chip of the embodiment of the present disclosure and the computing device constructed by the system-on-chip have commercial value and economic value on the basis of practical value.

[0093] Those skilled in the art will appreciate that the present disclosure may be implemented as systems, methods, and computer program products. Therefore, the present disclosure may be specifically implemented in the following forms, namely complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0094] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, a device or a device, or used in combination with the program.

[0095] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0096] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0097] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or combinations. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet).

[0098] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A system on chip, comprising: Sensor components; A processing unit, configured to periodically send a frequency modulation instruction at a predetermined time interval, wherein the frequency modulation instruction includes a first adjacent frequency modulation instruction and a second adjacent frequency modulation instruction; an AVFS controller, coupled to the sensor component, configured to start the sensor component to acquire and cache detection data for a set time after sending or receiving the first frequency modulation instruction, and determine a supply voltage of the system on chip according to a target frequency in the second frequency modulation instruction and the detection data, wherein the set time is less than the predetermined time interval; An on-chip bus couples the processing unit and the AVFS controller.

2. The system on chip according to claim 1, wherein: The AVFS controller is coupled to a timer, and the AVFS controller further includes a control unit. The timer is used to start timing when the first frequency modulation instruction is sent or received, and to notify the control unit when the timer continues for a set time, so that the control unit starts the sensor component.

3. The system on chip according to claim 2, wherein: The timer is set inside the AVFS controller, or the timer is set inside the system on chip but outside the AVFS controller.

4. The system on chip according to any one of claims 2 to 3, wherein: The processing unit notifies the timer to start timing when sending the first frequency modulation instruction, or the AVFS controller notifies the timer to start timing when receiving the first frequency modulation instruction.

5. The system on chip according to claim 1, wherein: The AVFS controller is configured with at least one frequency and multiple voltage table entries corresponding to each frequency. The AVFS controller also includes a voltage determination unit, which is used to determine a first voltage from the multiple voltage table entries as the power supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data.

6. The system on chip according to claim 1, wherein: The AVFS controller is configured with at least one frequency, and further comprises a voltage determination unit, wherein the voltage determination unit is configured to calculate the supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data based on a predefined voltage calculation rule.

7. The system on chip according to claim 1, wherein: The sensor assembly further includes at least one of a temperature sensor assembly, a process sensor assembly, and a voltage sensor assembly.

8. A method for regulating voltage and frequency, comprising: The processing unit periodically sends a frequency modulation instruction at a predetermined time interval, wherein the frequency modulation instruction includes a first adjacent frequency modulation instruction and a second adjacent frequency modulation instruction; The AVFS controller starts the sensor component for a set time period after sending or receiving the first frequency modulation instruction to acquire and cache the detection data, and determines the power supply voltage of the system on chip according to the target frequency in the second frequency modulation instruction and the detection data, wherein the set time period is less than the predetermined time interval, wherein the system on chip includes the processing unit, the AVFS controller and the sensor component.

9. The method according to claim 8, wherein: The AVFS controller is coupled to a timer, and the timer is used to start timing when the first frequency modulation instruction is sent or received, and to notify the AVFS controller to start the sensor component when the timer lasts for a set period of time.

10. The method according to claim 9, wherein: The processing unit notifies the timer to start timing when sending the first frequency modulation instruction, or the AVFS controller notifies the timer to start timing when receiving the first frequency modulation instruction.

11. A computing device comprising: The system on chip according to any one of claims 1 to 7; Off-chip bus; a storage device coupled to the system on chip via the off-chip bus; A power management circuit is coupled to the AVFS controller in the system on chip.

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