Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region; forming a first mask structure on the substrate in the first region; forming a second fin material layer in the substrate in the second region; forming a second mask structure on the second fin material layer, the second mask structure being made of a different material from the first mask structure; forming a plurality of discretely arranged fin patterns on the first mask structure and the second mask structure; etching the second mask structure and the second fin material layer using the fin pattern as a mask to form a second fin on the substrate in the second region; forming a protective layer covering the sidewalls of the second fin; etching the first mask structure and the substrate in the first region using the fin pattern as a mask to form a first fin on the substrate in the first region. The method for forming a semiconductor structure provided by an embodiment of the present invention can form fins on the NMOS region and the PMOS region respectively, which is conducive to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the integration of integrated circuits continues to increase and the size of devices continues to decrease, it is difficult to continue to reduce the critical dimensions of traditional planar CMOS (complementary metal oxide semiconductor) devices. Three-dimensional devices such as FINFET (fin field effect transistor) and nanowire channel devices are gradually becoming the mainstream trend.

[0003] In CMOS integrated circuits, carrier mobility affects the magnitude of the current in the channel, and carrier mobility is the main factor affecting the performance of field effect transistors. Generally, in CMOS integrated circuit manufacturing technology, enhanced electron mobility in silicon will improve the performance of NMOS (n-type metal oxide semiconductor) devices, while enhanced hole mobility in silicon germanium will improve the performance of PMOS (p-type metal oxide semiconductor) devices.

[0004] However, the performance of CMOS devices formed by existing technologies still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other; forming a first mask structure on the substrate in the first region; forming a second fin material layer in the substrate in the second region, the top surface of the second fin material layer being flush with the top surface of the substrate in the first region; forming a second mask structure on the second fin material layer, the second mask structure being made of a different material from the first mask structure; forming a plurality of discretely arranged fin patterns on the first mask structure and the second mask structure; using the fin pattern as a mask, etching the second mask structure and the second fin material layer until the surface of the substrate is exposed, and forming a second fin on the substrate in the second region; forming a protective layer covering the sidewalls of the second fin; using the fin pattern as a mask, etching the first mask structure and the substrate in the first region, and forming a first fin on the substrate in the first region.

[0007] Optionally, the first mask structure includes: a first mask layer located on the surface of the substrate in the first region and a second mask layer located on the surface of the first mask layer.

[0008] Optionally, the second mask layer and the first mask layer are made of different materials, the first mask layer is made of silicon nitride, silicon oxynitride, silicon oxycarbide or silicon carbon oxynitride; the second mask layer is made of silicon carbide, silicon oxynitride, silicon oxycarbide or silicon carbon oxynitride.

[0009] Optionally, the method further includes: forming a third mask layer on the second mask layer.

[0010] Optionally, the steps of forming the first mask structure and the third mask layer include: forming a first mask material film, a second mask material film and a third mask material film in sequence on the substrate of the first area and the second area; forming a patterned layer on the third mask material film, wherein the patterned layer is located on the third mask material film of the first area; using the patterned layer as a mask, etching the third mask material film, the second mask material film and the first mask material film until the substrate surface of the second area is exposed.

[0011] Optionally, the step of forming a second fin material layer in the substrate of the second zone includes: using the third mask layer and the first mask structure as masks, etching the substrate of the second zone to form a first opening in the substrate of the second zone; forming an initial second fin material layer in the first opening, and the top surface of the initial second fin material layer is flush with the top surface of the third mask layer; etching the initial second fin material layer until the top surface of the initial second fin material layer is flush with the top surface of the substrate of the first zone to form a second fin material layer.

[0012] Optionally, the second mask structure includes: a fourth mask layer; the material of the fourth mask layer includes silicon oxide.

[0013] Optionally, the step of forming the second mask structure includes: forming a fourth mask material film on the second fin material layer, the fourth mask material film also being located on the first mask structure; and planarizing the fourth mask material film until a surface of the first mask structure is exposed.

[0014] Optionally, the method of forming the fin pattern includes a self-aligned multiple patterning process.

[0015] Optionally, the step of etching the second mask structure and the second fin material layer using the fin pattern as a mask includes: etching the second mask structure using the fin pattern as a mask until the surface of the second fin material layer is exposed; and continuing to etch the second fin material layer until the surface of the substrate in the second region is exposed.

[0016] Optionally, the step of forming a protective layer covering the sidewalls of the second fin includes: forming an initial protective layer on the sidewalls of the second fin, the initial protective layer also covering the sidewalls and top surfaces of the fin pattern; planarizing the initial protective layer to expose the top surface of the fin pattern; etching the initial protective layer to expose the top surface of the first mask structure to form the protective layer.

[0017] Optionally, the material of the protective layer includes silicon oxide.

[0018] Optionally, the method for etching the initial protective layer is a SiCoNi etching process, and the process parameters of the SiCoNi etching process include: the etching atmosphere includes H2 and NF3, wherein the H2 gas flow rate is 5-100 sccm, the NF3 gas flow rate is 5-100 sccm, and the etching power is 100-200W.

[0019] Optionally, the step of etching the first mask structure and the substrate of the first area using the fin pattern as a mask includes: using the fin pattern as a mask, etching the second mask layer until the surface of the first mask layer is exposed to form a patterned second mask layer; removing the fin pattern; using the patterned second mask layer as a mask, etching the first mask layer until the surface of the substrate of the first area is exposed to form a patterned first mask layer; removing the patterned second mask layer; using the patterned first mask layer as a mask, etching the substrate of the first area to form a first fin on the substrate of the first area.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] First, a first mask structure is formed on the substrate of the first region, and a second mask structure is formed on the second fin material layer of the second region, and the material of the second mask structure is different from that of the first mask structure. When the second mask structure and the second fin material layer are etched using the fin pattern as a mask, due to the etching selectivity between the first mask structure and the second mask structure, etching will not occur on the first mask structure, and the second fin can be formed independently. Then, after the second fin is formed, a protective layer covering the side wall of the second fin is formed. When the first mask structure and the substrate of the first region are etched using the fin pattern as a mask, the protective layer and the second mask structure on the top of the second fin jointly protect the second fin from etching damage. In the process of forming the first fin, the second fin is ensured not to be damaged, thereby achieving the purpose of forming the first fin and the second fin separately, which is conducive to better controlling the patterns of the first fin and the second fin, and is conducive to improving the performance of the semiconductor structure. No additional mask plates are required, thereby simplifying the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 17 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background technology, in CMOS integrated circuits, the enhanced electron mobility in silicon will improve the performance of NMOS devices, while the enhanced hole mobility in silicon germanium will improve the performance of PMOS devices. Therefore, forming silicon fins in the NMOS region and forming silicon germanium fins in the PMOS region is beneficial to improving the performance of CMOS devices.

[0024] At present, a method for forming silicon fins in an NMOS region and silicon germanium fins in a PMOS region includes: providing a silicon substrate, wherein the silicon substrate includes an NMOS region and a PMOS region; etching the silicon substrate in the PMOS region to form a first opening; forming a silicon germanium layer in the first opening; forming a mask layer on the silicon substrate and the silicon germanium layer; using the mask layer as a mask, etching the silicon substrate in the NMOS region and the silicon germanium layer in the PMOS region to form silicon fins in the NMOS region and silicon germanium fins in the PMOS region.

[0025] The inventors have found that in the process of forming silicon fins and silicon germanium fins by the above method, due to the different etching rates of silicon materials and silicon germanium materials, etching the silicon substrate and the silicon germanium layer to form the fins at the same time will result in the morphology of the formed silicon fins and silicon germanium fins being non-uniform, which is not conducive to the performance of the semiconductor structure. If the silicon substrate and the silicon germanium material are etched separately, a mask needs to be added, which complicates the process and increases the production cost.

[0026] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a first mask structure is formed on a substrate in a first region, and after a second fin material layer is formed in the substrate in a second region, a second mask structure is formed on the second fin material layer, and the material of the second mask structure is different from that of the first mask structure. When the second mask structure and the second fin material layer are etched using the fin pattern as a mask, the first mask structure can protect the substrate in the first region and will not etch the substrate in the first region; after the second fin is formed, the second mask structure is still present on the top of the second fin, and then a protective layer is formed on the sidewall of the second fin, so that when the first mask structure and the substrate in the first region are etched, the second mask structure and the protective layer can protect the second fin from damage, thereby achieving the purpose of forming the first fin and the second fin respectively, making the morphology of the formed first fin and the second fin consistent, which is beneficial to improving the performance of the semiconductor structure, and does not require the addition of an additional mask plate, thereby simplifying the process flow.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figures 1 to 17 It is a schematic structural diagram corresponding to each step of a formation process of a semiconductor structure in one embodiment of the present invention.

[0029] refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes adjacent first region I and second region II.

[0030] The substrate 100 provides a process operation basis for subsequent processes.

[0031] In this embodiment, the substrate 100 is used to subsequently form a CMOS device, wherein the first region I is used to subsequently form an NMOS device, and the second region II is used to subsequently form a PMOS device.

[0032] In this embodiment, the substrate 100 is a silicon substrate.

[0033] refer to Figures 2 to 3 , forming a first mask structure on the substrate 100 in the first region I.

[0034] refer to Figure 3 In this embodiment, the first mask structure includes: a first mask layer 110 located on the surface of the substrate 100 in the first region I and a second mask layer 120 located on the surface of the first mask layer 110 .

[0035] In this embodiment, the first mask layer 110 and the second mask layer 120 are made of different materials. The first mask layer 110 is made of silicon nitride, and the second mask layer 120 is made of silicon carbide.

[0036] The etching selection ratio of the first mask layer 110 and the second mask layer 120 is greater than 10:1.

[0037] In other embodiments, the material of the first mask layer 110 may also be silicon oxynitride, silicon oxycarbide or silicon carbon oxynitride; the material of the second mask layer 120 may also be silicon oxynitride, silicon oxycarbide or silicon carbon oxynitride.

[0038] Continue to refer Figure 3 In this embodiment, the method further includes: forming a third mask layer 130 on the second mask layer 120 .

[0039] In this embodiment, the material of the third mask layer 130 is different from the material of the second mask layer 120 , and the material of the third mask layer 130 is silicon nitride.

[0040] The etching selection ratio of the third mask layer 130 and the second mask layer 120 is greater than 10:1.

[0041] In other embodiments, the material of the third mask layer 130 may also be silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride.

[0042] In this embodiment, the steps of forming the first mask structure and the third mask layer 130 include:

[0043] refer to Figure 2 A first mask material film 101, a second mask material film 102 and a third mask material film 103 are sequentially formed on the substrate 100 in the first area I and the second area II.

[0044] In this embodiment, the process for forming the first mask material film 101, the second mask material film 102 and the third mask material film 103 is a chemical vapor deposition process; in other embodiments, an atomic layer deposition process or a physical vapor deposition process can also be used to form the first mask material film 101, the second mask material film 102 and the third mask material film 103.

[0045] Continue to refer Figure 2 , forming a patterned layer 104 on the third mask material film 103, wherein the patterned layer 104 is located on the third mask material film 103 in the first region I.

[0046] Specifically, the patterned layer 104 has a pattern opening 105, and the pattern opening 105 exposes the surface of the third mask material film 103 in the second region II.

[0047] In this embodiment, the patterned layer 104 is used to define the position and size of the second region II.

[0048] In this embodiment, the patterned layer 104 is a photoresist layer.

[0049] refer to Figure 3 , using the patterned layer 104 as a mask, the third mask material layer 103, the second mask material layer 102 and the first mask material layer 101 are etched until the surface of the substrate 100 in the second region II is exposed, and a first mask layer 110, a second mask layer 120 and a third mask layer 130 are formed on the substrate 100 in the first region I.

[0050] In this embodiment, the process of etching the third mask material layer 103, the second mask material layer 102 and the first mask material layer 101 is a dry etching process.

[0051] After forming the first mask structure and the third mask layer 130 , the patterned layer 104 is removed.

[0052] After removing the patterned layer 104 , a second fin material layer is formed in the substrate 100 in the second region II.

[0053] In this embodiment, the steps of forming the second fin material layer specifically include:

[0054] refer to Figure 4 , using the third mask layer 130 and the first mask structure as masks, etching the substrate 100 in the second region II to form a first opening 201 in the substrate 100 in the second region II.

[0055] In this embodiment, the process of etching the substrate 100 in the second region II is a dry etching process.

[0056] In this embodiment, the depth of the first opening 201 is If the depth of the first opening 201 is too deep, the second fin material layer 202 formed subsequently will be too thick and will have more defects; if the depth of the first opening 201 is too shallow, the second fin material layer 202 formed subsequently will be too thin, resulting in a shorter second fin and a shallower channel area, which is not conducive to semiconductor performance.

[0057] refer to Figure 5 , an initial second fin material layer 202 is formed in the first opening 201 , and a top surface of the initial second fin material layer 202 is flush with a top surface of the third mask layer 130 .

[0058] In this embodiment, the initial second fin material layer 202 is used to subsequently form a second fin material layer.

[0059] In this embodiment, the material of the initial second fin material layer 202 is silicon germanium.

[0060] In this embodiment, the process of forming the initial second fin material layer 202 is a chemical vapor deposition process; in other embodiments, the initial second fin material layer 202 may also be formed by a physical vapor deposition process or an atomic layer deposition process.

[0061] refer to Figure 6 , etching the initial second fin material layer 202 until the top surface of the initial second fin material layer 202 is flush with the top surface of the substrate 100 in the first region I, to form a second fin material layer 210 .

[0062] In this embodiment, the second fin material layer 210 is used to subsequently form a second fin.

[0063] In this embodiment, the process of etching the initial second fin material layer 202 is a wet etching process; in other embodiments, the initial second fin material layer 202 may also be etched by a dry etching process.

[0064] In this embodiment, the top surface of the second fin material layer 210 is flush with the top surface of the substrate 100 in the first region I, which is beneficial for the subsequently formed second fin to have the same height as the first fin, thereby improving the performance of the semiconductor structure.

[0065] refer to Figure 7 After forming the second fin material layer 210 , a second mask structure is formed on the second fin material layer 210 , and the material of the second mask structure is different from the material of the first mask structure.

[0066] In this embodiment, the second mask structure includes: a fourth mask layer 220 .

[0067] In this embodiment, specifically, the material of the fourth mask layer 220 is different from the material of the second mask layer 120 , and the material of the fourth mask layer 220 is different from the material of the first mask layer 110 .

[0068] In this embodiment, the material of the fourth mask layer 220 is silicon oxide.

[0069] In this embodiment, the top surface of the second mask structure is flush with the top surface of the first mask structure.

[0070] In this embodiment, the step of forming the second mask structure includes: forming a fourth mask material film (not shown) on the second fin material layer 210, and the fourth mask material film is also located on the first mask structure; and planarizing the fourth mask material film until the surface of the first mask structure is exposed to form the second mask structure.

[0071] In this embodiment, specifically, the fourth mask material film covers the surface of the third mask layer 130 on the first mask structure, and the third mask layer 130 is removed while the fourth mask material film is planarized.

[0072] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0073] In this embodiment, the fourth mask layer 220 and the second mask layer 120 and the first mask layer 110 are made of different materials. When the fourth mask layer 220 is subsequently etched, due to the etching selectivity, the second mask layer 120 and the first mask layer 110 will not be etched, and the substrate 100 in the first area I covered by the first mask layer 110 will not be etched. The fourth mask layer 220 and the second fin material layer 210 can be etched first, and the second fin is first formed on the substrate 100 in the second area II, and then the first fin is formed on the substrate 100 in the first area I. By forming the first fin and the second fin respectively, the morphology of the first fin and the second fin is better controlled, thereby improving the performance of the semiconductor structure. In addition, due to the etching selectivity among the fourth mask layer 220, the second mask layer 120 and the first mask layer 110, no additional mask is required during the etching process, thereby simplifying the process flow.

[0074] refer to Figure 8 , a plurality of discretely arranged fin patterns 300 are formed on the first mask structure and the second mask structure.

[0075] In this embodiment, the fin pattern 300 is used to define the position and size of the first fin and the second fin to be formed.

[0076] In this embodiment, the process for forming the fin pattern 300 is a self-aligned double patterning process. The specific steps of forming the fin pattern 300 include: forming a core material layer (not shown) and a patterned photoresist layer (not shown) on the first mask structure and the second mask structure in sequence; etching the core material layer using the patterned photoresist layer as a mask to form a core layer, wherein the core layer defines the spacing between the fin patterns to be formed; forming a sidewall on the sidewall of the core layer, wherein the sidewall defines the position and size of the first fin and the second fin to be formed; and removing the core layer to form the fin pattern 300.

[0077] In this embodiment, after the core layer is removed, the remaining sidewalls serve as the fin pattern 300 .

[0078] In other embodiments, the fin pattern 300 may also be formed by a self-aligned quadruple patterning process.

[0079] In this embodiment, the material of the fin pattern 300 is silicon nitride; in other embodiments, the material of the fin pattern 300 may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.

[0080] refer to Fig. 9 , using the fin pattern 300 as a mask, etching the second mask structure until the surface of the second fin material layer 210 is exposed.

[0081] In this embodiment, the fourth mask layer 220 is specifically etched until the surface of the second fin material layer 210 is exposed.

[0082] In this embodiment, the etching process is a dry etching process, and the process parameters include: the etching atmosphere includes C4F6 and O2, or C4F8 and O2, wherein the gas flow rate of O2 is 2 to 20 sccm, the gas flow rate of C4F6 or C4F8 is 5 to 50 sccm, the etching power is 100 to 2000 W, and the etching pressure is 2 to 200 mTorr.

[0083] In this embodiment, since the fourth mask layer 220 and the second mask layer 120 have an etching selectivity ratio, the second mask layer 120 will not be etched when the fourth mask layer 220 is etched, so that the second fin material layer 210 and the substrate 100 of the first region I can be etched separately without adding an additional mask.

[0084] refer to Fig.10 , the second fin material layer 210 is continuously etched until the surface of the substrate 100 in the second region II is exposed, and a second fin 400 is formed on the substrate 100 in the second region II.

[0085] In this embodiment, the process of etching the second fin material layer 210 is a dry etching process, and the process parameters include: the etching atmosphere includes Cl2 and O2, wherein the gas flow rate of O2 is 10-200 sccm, the gas flow rate of Cl2 is 50-500 sccm, the etching power is 100-2000 W, and the etching pressure is 2-200 mTorr. .

[0086] After the second fin 400 is formed, a protection layer is formed on the sidewalls of the second fin 400 .

[0087] In this embodiment, after etching to form the second fin 400, the top of the second fin 400 is still covered by the second mask structure, while the side walls of the second fin 400 are exposed. In order to avoid etching damage to the second fin 400 during the subsequent etching of the substrate 100 in the first region I, a protective layer needs to be formed on the side walls of the second fin 400 to protect the second fin 400 from etching damage.

[0088] In this embodiment, the steps of forming the protective layer specifically include:

[0089] refer to Fig.11 , an initial protection layer 401 is formed on the sidewalls of the second fin 400 , and the initial protection layer 401 also covers the sidewalls and the top surface of the fin pattern 300 .

[0090] In this embodiment, specifically, an initial protection layer 401 is deposited between the second fins 400 and between the second fins 400 and the substrate 100 in the first region I.

[0091] In this embodiment, the material of the initial protection layer 401 is silicon oxide.

[0092] In this embodiment, the method for depositing the initial protection layer 401 is chemical vapor deposition; in other embodiments, the initial protection layer 401 may also be formed by physical vapor deposition or atomic layer deposition.

[0093] The initial protective layer 401 is used to subsequently form a protective layer. The material of the initial protective layer 401 is different from the material of the second mask layer 120. The material of the initial protective layer 401 is different from the material of the first mask layer 110. When the second mask layer 120, the first mask layer 110 and the substrate 100 of the first zone I are subsequently etched, the protective layer formed by the initial protective layer 401 can protect the side wall of the second fin 400, prevent the second fin 400 from being etched and damaged, affect the morphology of the second fin 400, and be beneficial to the performance of the semiconductor structure.

[0094] refer to Fig.12 , the initial protection layer 401 is planarized until the top surface of the fin pattern 300 is exposed.

[0095] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0096] refer to Fig.13 , etching the initial protection layer 401 until the top surface of the first mask structure is exposed to form a protection layer 410.

[0097] In this embodiment, the initial protection layer 401 is specifically etched until the top surface of the second mask layer 120 is exposed to form the protection layer 410 .

[0098] In this embodiment, the process of etching the initial protection layer 401 is a SiCoNi etching process, and the process parameters include: the etching atmosphere includes H2 and NF3, wherein the H2 gas flow rate is 5-100 sccm, the NF3 gas flow rate is 5-100 sccm, and the etching power is 100-200W.

[0099] In this embodiment, the initial protective layer 401 is etched using a SiCoNi etching process, which can achieve a higher etching selectivity ratio between silicon oxide and silicon nitride and silicon carbide, thereby avoiding damage to the fin pattern 300 and the second mask layer 120, ensuring the integrity of the fin pattern 300, and thus ensuring that the pattern of the first fin formed subsequently is intact.

[0100] In this embodiment, the protection layer 410 also covers the sidewalls of the second mask structure, specifically covers the sidewall surfaces of the fourth mask layer 220 .

[0101] In this embodiment, the material of the protective layer 410 is the same as the material of the fourth mask layer 220, and is different from the materials of the second mask layer 120 and the first mask layer 110. The fourth mask layer 220 is located on the top of the second fin 400, and the protective layer 410 covers the side wall of the second fin 400. In the subsequent etching of the second mask layer 120 and the first mask layer 110 to form the first fin, the second fin 400 can be protected from etching damage, thereby ensuring the good morphology of the second fin 400, which is beneficial to the performance of the semiconductor structure.

[0102] refer to Fig.14 , using the fin pattern 300 as a mask, the second mask layer 120 is etched until the top surface of the first mask layer 110 is exposed to form a patterned second mask layer 121 .

[0103] In this embodiment, the process of etching the second mask layer 120 is a dry etching process.

[0104] refer to Fig.15 , removing the fin pattern 300; using the patterned second mask layer 121 as a mask, etching the first mask layer 110 until the surface of the substrate 100 in the first region I is exposed to form a patterned first mask layer 111.

[0105] In this embodiment, an ashing process is used to remove the fin pattern 300 .

[0106] In this embodiment, the process of etching the first mask layer 110 is a dry etching process, and the process parameters include: the etching atmosphere includes O2 and CH3F, wherein the O2 gas flow rate is 5-500sccm, the CH3F gas flow rate is 50-500sccm, the etching power is 100-2000W, and the etching pressure is 2-200 mTorr.

[0107] refer to Fig.16 , removing the patterned second mask layer 121; using the patterned first mask layer 111 as a mask, etching the substrate 100 in the first region I to form a first fin 500 on the substrate 100 in the first region I.

[0108] In this embodiment, the process of etching the substrate 100 in the first zone I is a dry etching process, and the process parameters include: the etching atmosphere includes Cl2 and O2, wherein the Cl2 gas flow rate is 5-1000sccm, the O2 gas flow rate is 10-100sccm, the etching power is 100-2000W, and the etching pressure is 2-200 mTorr.

[0109] In this embodiment, a bottom plane of the first fin 500 is flush with a bottom plane of the second fin 400 .

[0110] In this embodiment, by forming a second mask structure on the second fin material layer 210, and the material of the second mask structure is different from that of the first mask structure, when the second mask structure and the second fin material layer are etched to form the second fin 400, the first mask structure will not be etched, and the second fin can be formed first and then the first fin. When the first mask structure and the substrate 100 of the first region I are subsequently etched, the second mask structure and the second fin 400 will not be etched either. Therefore, the first fin 500 in the NMOS region and the second fin 400 in the PMOS region can be formed respectively, which is conducive to better controlling the morphology of the fins, making the patterns of the first fin and the second fin more consistent, thereby improving the performance of the semiconductor structure; and there is no need to add additional mask plates, which simplifies the process flow and reduces production costs.

[0111] refer to Fig.17 After forming the first fins 500 , the isolation material layer (not shown) is filled between adjacent first fins 500 , and the isolation material layer is planarized to form an isolation layer 510 .

[0112] In this embodiment, the material of the isolation layer 510 is silicon oxide.

[0113] In this embodiment, the isolation layer 510 is formed by fluid chemical vapor deposition, which can make the formed isolation layer 510 have better filling performance.

[0114] In this embodiment, the fourth mask layer 220 and the protection layer 410 also play an isolation role, and there is no need to remove them and then form a new isolation layer, which simplifies the process flow.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising adjacent first and second regions; forming a first mask structure on the substrate in the first region; forming a second fin material layer in the substrate in the second region, wherein a top surface of the second fin material layer is flush with a top surface of the substrate in the first region; forming a second mask structure on the second fin material layer, wherein the second mask structure is made of a material different from that of the first mask structure; forming a plurality of discretely arranged fin patterns on the first mask structure and the second mask structure; Using the fin pattern as a mask, etching the second mask structure and the second fin material layer until the surface of the substrate is exposed, and forming a second fin on the substrate in the second region; forming a protective layer covering the sidewall of the second fin; The first mask structure and the substrate in the first region are etched using the fin pattern as a mask to form a first fin on the substrate in the first region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first mask structure includes: a first mask layer located on the surface of the substrate in the first region and a second mask layer located on the surface of the first mask layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The second mask layer and the first mask layer are made of different materials. The first mask layer is made of silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbon oxynitride; the second mask layer is made of silicon carbide, silicon oxynitride, silicon oxycarbide, or silicon carbon oxynitride.

4. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: A third mask layer is formed on the second mask layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The steps of forming the first mask structure and the third mask layer include: sequentially forming a first mask material film, a second mask material film and a third mask material film on the substrate in the first and second regions; forming a patterned layer on the third mask material film, wherein the patterned layer is located on the third mask material film in the first area; The third mask material film, the second mask material film and the first mask material film are etched using the patterned layer as a mask until the substrate surface in the second region is exposed.

6. The method for forming a semiconductor structure according to claim 4, wherein: The step of forming a second fin material layer in the substrate in the second region comprises: Using the third mask layer and the first mask structure as masks, etching the substrate in the second region to form a first opening in the substrate in the second region; forming an initial second fin material layer in the first opening, wherein a top surface of the initial second fin material layer is flush with a top surface of the third mask layer; The initial second fin material layer is etched until a top surface of the initial second fin material layer is flush with a top surface of the substrate in the first region, so as to form a second fin material layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The second mask structure includes: a fourth mask layer; the material of the fourth mask layer includes silicon oxide.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the second mask structure comprises: forming a fourth mask material film on the second fin material layer, wherein the fourth mask material film is also located on the first mask structure; The fourth mask material film is planarized until the surface of the first mask structure is exposed.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the fin pattern includes a self-aligned multiple patterning process.

10. The method for forming a semiconductor structure according to claim 1, wherein: The step of etching the second mask structure and the second fin material layer using the fin pattern as a mask includes: Using the fin pattern as a mask, etching the second mask structure until the surface of the second fin material layer is exposed; The second fin material layer is continuously etched until the surface of the substrate in the second region is exposed.

11. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a protection layer covering the sidewall of the second fin portion includes: forming an initial protection layer on the sidewalls of the second fin, wherein the initial protection layer also covers the sidewalls and top surface of the fin pattern; performing a planarization process on the initial protection layer until a top surface of the fin pattern is exposed; The initial protection layer is etched until the top surface of the first mask structure is exposed to form the protection layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the protection layer includes silicon oxide.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for etching the initial protective layer is a SiCoNi etching process, and the process parameters of the SiCoNi etching process include: The etching atmosphere includes H2 and NF3, wherein the H2 gas flow rate is 5-100 sccm, the NF3 gas flow rate is 5-100 sccm, and the etching power is 100-200W.

14. The method for forming a semiconductor structure according to claim 2, wherein: The step of etching the first mask structure and the substrate of the first region using the fin pattern as a mask comprises: Using the fin pattern as a mask, etching the second mask layer until the surface of the first mask layer is exposed to form a patterned second mask layer; removing the fin pattern; Using the patterned second mask layer as a mask, etching the first mask layer until the surface of the substrate in the first region is exposed to form a patterned first mask layer; removing the patterned second mask layer; The substrate in the first region is etched using the patterned first mask layer as a mask to form a first fin on the substrate in the first region.

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