A switching control circuit, a charging chip, an electronic device and related methods

Abstract

The present invention provides a switching control circuit, including an oscillator circuit, a delay calibration and timing circuit, a target current acquisition circuit and a current switching circuit. The oscillator circuit is used to generate a clock signal, the delay calibration and timing circuit is used to perform delay calibration on the clock signal to output at least one control signal, and the target current acquisition circuit is used to respond to the at least one control signal to obtain a target current, and the target current is used to reflect the target constant power current in the constant power mode. The current switching circuit is used to receive the target current and a first preset current for reflecting the target constant current current in the constant current mode, and control the output of the target current and one of the first preset currents. The present invention also provides a charging chip and an electronic device. The present invention can control the power in the constant power mode to remain consistent and ensure the switching accuracy from the constant power mode to the constant current mode.

Description

Technical Field

[0001] The present invention relates to a control circuit, and in particular to a switching control circuit at least used for switching control between a constant power mode and a constant current mode, a charging chip having the switching control circuit, and an electronic device having the switching control circuit. Background Art

[0002] At present, the charging technology of mobile phones, tablet computers and other terminals is developing rapidly, and fast charging technology has become the standard configuration of current terminals. Generally speaking, the current fast charging technology includes three stages / modes in the charging process: constant voltage, constant power and constant current.

[0003] In the initial constant voltage mode, when the output current is small, the output power is less than the set power, and a constant voltage (CV) output is used; as the output current gradually increases, after the power reaches the set power value, the output voltage begins to decrease while the current increases, maintaining a constant power (CP) output; when the output current increases to the set maximum current value, the constant current (CC) mode is entered, the output current remains unchanged, and the voltage continues to decrease. Generally speaking, in the constant power mode, the power is required to remain consistent in real time; in the constant current mode, the CC current switching from the constant power mode to the constant current mode must be accurate. However, in the prior art, it is often impossible to ensure that the power in the constant power mode remains consistent, or when switching from the constant power mode to the constant current mode, there will be an overlapping interval, resulting in an inaccurate switching point. This existing situation often leads to reduced charging efficiency or damage to the charging equipment after a long time.

[0004] Therefore, how to control the power in constant power mode to remain consistent and ensure the switching accuracy from constant power mode to constant current mode has become an issue that needs to be considered in fast charging technology. Summary of the invention

[0005] The object of the present invention is to provide a switching control circuit, a charging chip and an electronic device, which can control the power in a constant power mode to remain consistent and ensure the switching accuracy from the constant power mode to the constant current mode.

[0006] On the one hand, a switching control circuit is provided, the switching control circuit comprising an oscillator circuit, a delay calibration and timing circuit, a target current acquisition circuit and a current switching circuit. The oscillator circuit is used to generate a clock signal. The delay calibration and timing circuit is used to perform delay calibration on the clock signal to output at least one control signal. The target current acquisition circuit is used to respond to the at least one control signal to obtain a target current, and the target current is used to reflect the target constant power current in the constant power mode. The current switching circuit comprises a first input terminal, a second input terminal and a current output terminal, the first input terminal is used to receive the target current, the second input terminal is used to receive a first preset current, and the first preset current is used to reflect the target constant current in the constant current mode; the current switching circuit is used to control the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal, wherein when the target current is less than the first preset current, the output current is the target current, so as to realize the current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize the current control in the constant current mode.

[0007] On the other hand, a charging chip is provided, the charging chip includes a switching control circuit, the switching control circuit includes an oscillator circuit, a delay calibration and timing circuit, a target current acquisition circuit and a current switching circuit. The oscillator circuit is used to generate a clock signal. The delay calibration and timing circuit is used to perform delay calibration on the clock signal to output at least one control signal. The target current acquisition circuit is used to respond to the at least one control signal to obtain a target current, and the target current is used to reflect the target constant power current in the constant power mode. The current switching circuit includes a first input terminal, a second input terminal and a current output terminal, the first input terminal is used to receive the target current, the second input terminal is used to receive a first preset current, and the first preset current is used to reflect the target constant current in the constant current mode; the current switching circuit is used to control the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal, wherein when the target current is less than the first preset current, the output current is the target current, so as to realize the current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize the current control in the constant current mode.

[0008] On the other hand, an electronic device is provided, the electronic device includes a switching control circuit, the switching control circuit includes an oscillator circuit, a delay calibration and timing circuit, a target current acquisition circuit and a current switching circuit. The oscillator circuit is used to generate a clock signal. The delay calibration and timing circuit is used to perform delay calibration on the clock signal to output at least one control signal. The target current acquisition circuit is used to respond to the at least one control signal to obtain a target current, and the target current is used to reflect the target constant power current in the constant power mode. The current switching circuit includes a first input terminal, a second input terminal and a current output terminal, the first input terminal is used to receive the target current, the second input terminal is used to receive a first preset current, and the first preset current is used to reflect the target constant current in the constant current mode; the current switching circuit is used to control the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal, wherein when the target current is less than the first preset current, the output current is the target current, so as to realize the current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize the current control in the constant current mode.

[0009] The switching control circuit, charging chip and electronic device of the present application, when the current target current is less than the first preset current, that is, when it is still in the constant power mode, the current control in the constant power mode is performed by outputting the target current, so that the output current is the target constant power current; and when the current target current reaches the first preset current, that is, the switching point between the current constant power mode and the constant current mode, at this time, the output current is made to be the target constant current by outputting the first preset current, and accurately switches to the constant current mode. The switching accuracy from the constant power mode to the constant current mode is achieved. In addition, since the present application uses delay calibration and timing circuits for delay calibration, the output power can be guaranteed to be constant and will not change with changes in the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings required for use in the implementation mode will be briefly introduced below. Obviously, the drawings described below are some implementation modes of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 Schematic diagram of the voltage-current curve during the charging process.

[0012] Figure 2is a circuit block diagram of a switching control circuit in an embodiment of the present application.

[0013] Figure 3 is a specific circuit diagram of a switching control circuit in an embodiment of the present application.

[0014] Figure 4 Schematic diagram of the timing of a clock signal and a plurality of control signals in one embodiment of the present application.

[0015] Figure 5 4 is a circuit block diagram of a current switching circuit in a switching control circuit in one embodiment of the present application.

[0016] Figure 6 Detailed circuit diagram of a current switching circuit in one embodiment of the present application.

[0017] Figure 7 is a structural block diagram of an electronic device in an embodiment of the present application.

[0018] Figure 8 Flow chart of a switching control method in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that the terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0021] The method for adjusting the capacitive button signal threshold range according to the embodiment of the present invention can be applied to any terminal device having a capacitive button.

[0022] See also Figure 1 Figure 2 is a schematic diagram of the voltage-current curve during the charging process. Figure 1As shown, in general, the charging process includes three stages / modes: constant voltage, constant power and constant current. In the initial constant voltage mode, when the output current is small, the output power is less than the set power P0, and a constant voltage (CV) is output; as the output current gradually increases, after the power reaches the set power value P0, it enters the constant power mode. In the constant power mode, as the current increases, the output voltage begins to decrease, maintaining a constant power (CP) output, that is, the output power is maintained at the set power value P0; when the output current increases to the set current value Icc, it enters the constant current (CC) mode, the output current remains unchanged, that is, maintained at the set current value Icc, and the voltage continues to decrease. Therefore, during the charging process, the voltage keeps decreasing from the constant power mode to the constant current mode, while the current keeps increasing from the constant voltage mode to the constant power mode until it remains unchanged in the constant current mode. Among them, Figure 1 Schematic diagram of the voltage-current curve under ideal conditions.

[0023] See also Figure 2 , is a circuit block diagram of a switching control circuit 100 in an embodiment of the present application. The switching control circuit 100 is used for switching control between a constant power mode and a constant current mode and controlling the power in the constant power mode to be constant. Figure 1 As shown, the switching control circuit 100 includes an oscillator circuit 1 , a delay calibration and timing circuit 2 , a target current acquisition circuit 3 and a current switching circuit 4 .

[0024] Wherein, the oscillator circuit 1 is used to generate a clock signal; the delay calibration and timing circuit 2 is used to perform delay calibration on the clock signal to output at least one control signal; the target current acquisition circuit 3 is used to respond to the plurality of control signals to obtain a target current, and the target current is used to reflect the target constant power current in the constant power mode; the current switching circuit 4 includes a first input terminal 41, a second input terminal 42 and a current output terminal 43, the first input terminal 41 is used to receive the target current, the second input terminal 42 is used to receive a first preset current, and the first preset current is used to reflect the target constant current in the constant current mode; the current switching circuit 4 is used to control the current output terminal 43 to output an output current according to the target current received by the first input terminal 41 and the first preset current received by the second input terminal 42, wherein when the current target current is less than the first preset current, the output current is the target current, which is used to realize the current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, which is used to switch to the constant current mode and realize the current control in the constant current mode.

[0025] Thus, in the present application, since the target current reflects the target constant power current in the constant power mode, and the first preset current reflects the target constant current in the constant current mode, when the current target current is less than the first preset current, it means that it is still in the constant power mode. At this time, the current control in the constant power mode is performed by outputting the target current, so that the output current is the target constant power current; and when the current target current reaches the first preset current, it means that the switching point between the current constant power mode and the constant current mode has been reached. At this time, the output current is made to be the target constant current by outputting the first preset current, and the constant current mode is accurately switched. The switching accuracy from the constant power mode to the constant current mode is achieved. In addition, since the present application uses delay calibration and timing circuit 2 for delay calibration, the output power can be guaranteed to be constant and will not change with the change of the output voltage.

[0026] The target constant power current in this application refers to the current that should be output in the constant power mode, that is, the current that can maintain constant power corresponding to the current output voltage in the constant power mode. The target constant current refers to the set current value Icc output in the constant current mode.

[0027] Among them, the target current in the present application is used to reflect the target constant power current in the constant power mode, which means that the target current is equal to or in a certain proportional relationship with the target constant power current in the constant power mode, and the first preset current reflects the target constant current in the constant current mode, which means that the first preset current is equal to or in a certain proportional relationship with the target constant current in the constant current mode. Among them, when it is a certain proportional relationship, the proportional relationship between the target current and the target constant power current in the constant power mode is the same as the proportional relationship between the first preset current and the target constant current in the constant current mode, for example, it can be reduced by the same proportional coefficient.

[0028] Further, such as Figure 2 As shown, the switching control circuit 100 also includes a feedback comparison circuit 5, which is used to receive the output current output by the current switching circuit 4 and a feedback current reflecting the current actual output current, and compare the output current and the feedback current, and generate an adjustment signal when the output current is inconsistent with the feedback current, until the feedback current is consistent with the output current, so that the actual current in the constant power mode is consistent with the target constant power current to achieve current control in the constant power mode, or the actual current in the constant current mode is consistent with the target constant current current, and switch to the constant current mode and achieve current control in the constant current mode.

[0029] That is, specifically, in order to further realize, through the feedback comparison circuit 5, that the actual output current is equal to the current that should be output in the current constant power mode, thereby ensuring constant power, and to realize that when switching to the constant current mode, the actual output current is equal to the set current value Icc that should be output in the current constant current mode, thereby ensuring precise switching of constant power and constant current.

[0030] In some embodiments, the oscillator circuit 1 is used to receive an associated current related to a current output voltage and the first preset current, and to generate the clock signal according to the output current and the first preset current.

[0031] That is, in some embodiments, the clock signal generated by the oscillator circuit 1 is specifically generated according to the output current related to the current output voltage and the first preset current.

[0032] The associated current associated with the current output voltage may refer to a current converted from the current output voltage, for example, obtained by dividing the output voltage by the resistance value of a specific resistor. In some embodiments, the specific resistor, for example, a resistor of 200 ohms, may be connected to the output end of the switching control circuit 100, and the associated current is generated in the specific resistor. Since the current output voltage is constantly changing, the associated current is actually constantly changing.

[0033] Please also read Figure 3 , is a specific circuit diagram of the switching control circuit 100 in an embodiment of the present application. Figure 3As shown, the oscillator circuit 1 includes a comparator 11, a first capacitor C1, a first resistor R1 and an NMOS tube M0. The comparator 11 includes a first positive input terminal 111, a first negative input terminal 112 and a first output terminal 113. The first positive input terminal 111 is used to receive the associated current Ivout, and the first positive input terminal 111 is also grounded through the first capacitor C1. The first negative input terminal 112 is used to receive the first preset current, and the first negative input terminal 112 is also grounded through the first resistor R1. The NMOS tube M0 and the first capacitor C1 are connected in parallel between the first positive input terminal 111 and the ground, and the first output terminal 113 is connected to the gate of the NMOS tube M0. The first preset current flows through the first resistor R1, and a preset reference voltage Vr is generated at the first inverting input terminal 112. The first preset current is used to charge the first capacitor C1, so that the voltage Vc at one end of the first capacitor C1 connected to the first positive input terminal 111 increases, that is, the voltage Vc at the first positive input terminal 111 increases. When the voltage Vc at the first positive input terminal increases to reach the preset reference voltage Vr, the comparator 11 outputs a high-level signal to the gate of the NMOS tube M0 through the first output terminal 113, and controls the NMOS tube M0 to be turned on, so that the first capacitor C1 is discharged through the turned-on NMOS tube M0, and the voltage at the first positive input terminal 111 drops to less than the preset reference voltage Vr, so that the comparator outputs a low-level signal through the first output terminal 113, thereby causing the oscillator circuit 1 to output a periodically changing clock signal, wherein the low-level duration in each cycle of the clock signal is equal to the charging duration T for the first capacitor to be charged to reach the preset reference voltage.

[0034] like Figure 3 As shown, the delay calibration and timing circuit 2 includes a signal input terminal 20, a first signal output terminal 21, a second signal output terminal 22 and a third signal output terminal 23. The signal input terminal 20 of the delay calibration and timing circuit 2 is connected to the first output terminal 113 of the comparator 11 for receiving the clock signal. The delay calibration and timing circuit 2 is used to perform delay calibration on the clock signal to output the first control signal S1, the second control signal S2 and the third control signal S3 through the first signal output terminal 21, the second signal output terminal 22 and the third signal output terminal 23 respectively.

[0035] Please also read Figure 4 , is a timing diagram of a clock signal and a plurality of control signals. The low level duration in each cycle of the clock signal CK output by the oscillator circuit 1 is equal to the charging duration T for the first capacitor to charge to the preset reference voltage. Figure 4 As shown, the first control signal S1 is a signal obtained by extending the high level duration of the clock signal CK and then inverting it, wherein the high level duration of the first control signal S1 is equal to the charging duration T of the first capacitor C1 to reach the preset reference voltage, that is, equal to the low level duration of the clock signal CK. The second control signal S1 is equal to the clock signal CK, that is, the second control signal S1 can be the clock signal CK. The third control signal S3 is a signal obtained by delaying the high level of the clock signal CK, that is, delaying it to a high level, the high level period of the third control signal S3 is staggered with the high level period of the second control signal S2, and the high level periods of the second control signal S2 and the third control signal S3 are both located in the low level period of the first control signal S1.

[0036] Thus, the delay calibration and timing circuit 2 performs delay calibration on the clock signal, and outputs the first control signal S1, the second control signal S2 and the third control signal S3 through the first signal output terminal 21, the second signal output terminal 22 and the third signal output terminal 23 respectively, for controlling subsequent circuits to achieve constant power output.

[0037] Among them, although the associated current Ivout changes with the current output voltage, it is well known that charging generally takes more than one hour. Therefore, the charging time T for the first capacitor to charge to the preset reference voltage is much shorter than the time of the constant power mode. Therefore, in a shorter time, the cycles of the clock signal and the multiple control signals can be regarded as unchanged. Therefore, Figure 4 The clock signal and the plurality of control signals shown remain substantially the same in each cycle over a period of several cycles.

[0038] Specifically, Figure 3 As shown, the target current acquisition circuit 3 includes a first switch K1, a second switch K2, a third switch K3, a second capacitor C2, a third capacitor C3, a first operational amplifier 31 and a second resistor R2, one end of the first switch K1 is used to connect a second preset current, and the second preset current is related to the target output voltage when the constant power mode is switched to the constant current mode, the other end of the first switch K2 is grounded through the third switch K3, the second switch K3 is connected between the connection node N1 of the first switch K1 and the third switch K3 and the second positive input terminal 311 of the first operational amplifier 31, the connection node N1 of the first switch K1 and the third switch K3 is also grounded through the second capacitor C2, the second positive input terminal 311 is also grounded through the third capacitor C3, and the second inverting input terminal 312 of the first operational amplifier 31 is also grounded through the second resistor R2.

[0039] Please refer to Figure 1 The ideal current corresponding to the conversion / switching time point from the constant power mode to the constant current mode is the set current value Icc in the constant current mode, and the corresponding switching point output voltage is Vsp. The power of the constant power is equal to the power at the conversion time point, that is, equal to the product of the target output voltage Vsp and the constant current Icc.

[0040] Among them, the second preset current is related to the switching point output voltage when the constant power mode is switched to the constant current mode, which may mean that the second preset current is a current converted by the switching point output voltage Vsp, for example, obtained by dividing the switching point output voltage by the resistance value of a specific resistor, for example, divided by 200 ohms.

[0041] Since the target output voltage is generally a fixed value after the switching control circuit 100 is applied to the terminal, for example, since the current corresponding to the target output voltage is theoretically a constant current, and the power at this time is also the set power in the constant power mode, the target output voltage is a value that can be uniquely obtained according to the set current value Icc in the constant current mode and the set power in the constant power mode. Therefore, the second preset current can be directly generated by a constant current source (referred to as a constant current source) after being calculated in advance according to the output voltage of the switching point and the resistance value of the specific resistor.

[0042] The aforementioned first preset current may also be generated by a constant current source (hereinafter referred to as a constant current source).

[0043] like Figure 3 As shown, the first inverting input terminal 112 of the comparator 11 is specifically connected to a first constant current source Y1, and the first constant current source Y1 is used to generate a first preset current. The first inverting input terminal 112 of the comparator 11 receives the first preset current generated by the first constant current source Y1. The second input terminal 42 of the current switching circuit 4 is connected to a second constant current source Y2, and the second constant current source Y2 is also used to provide the first preset current. The first preset current generated by the second constant current source Y2 received by the second input terminal 42 of the current switching circuit 4. The first switch K1 is used to access the second preset current. One end is connected to a third constant current source Y3, and the third constant current source Y3 is used to generate the second preset current. Among them, "XX receives the current generated by the constant current source" in this application means that the direction of the current generated by the constant current source is to flow in the direction of XX. For example, the first preset current generated by the second constant current source Y2 received by the second input terminal 42 of the current switching circuit 4 means that the first preset current generated by the second constant current source Y2 flows into the second input terminal 42 of the current switching circuit 4.

[0044] like Figure 3 As shown, the first signal output terminal 21 is connected to the first switch K1, and is used to output the first control signal S1 to the first switch K1 to control the conduction or cut-off of the first switch K1. The second signal output terminal 22 is connected to the second switch K2, and is used to output the second control signal to the second switch K2 to control the conduction or cut-off of the second switch K2. The third signal output terminal 23 is connected to the third switch K3, and is used to output the third control signal S3 to the third switch K3 to control the conduction or cut-off of the third switch K3.

[0045] The first switch K1, the second switch K2 and the third switch K3 are all high-level conductive switches. During a first duration when the first control signal S1 is at a high level, i.e., time T, the second control signal S2 and the third control signal S3 are continuously at a low level, the first switch K1 is continuously turned on, the second switch K2 and the third switch K3 are turned off, and the second preset current continuously charges the second capacitor C2 through the turned-on first switch K1 during the first duration. During a second duration when the first control signal S1 is at a low level, the second control signal S2 first becomes a high level, at which time the first control signal S1 and the third control signal S3 are both at a low level, at which time the second switch K2 is turned on, the first switch K1 and the third switch K3 are turned off, and the second capacitor C2 and the third capacitor C3 share charge through the turned-on second switch K2, i.e., the second capacitor C2 charges the third capacitor C3. When the third control signal S3 changes to a high level, the first control signal S1 and the second control signal S2 are both low levels, the third switch K3 is turned on, the first switch K1 and the second switch K2 are turned off, and the second capacitor C2 is connected to the ground through the turned-on third switch K3 to discharge. Through the above-mentioned periodic process, under the control of the first control signal S1, the second control signal S2 and the third control signal S3 in several cycles, the voltage of the third capacitor C3 is equal to the cut-off voltage Vs when the charging of the second capacitor C2 is cut off, the second non-inverting input terminal 311 of the first operational amplifier 31 and the second inverting input terminal 312 are virtually shorted, and the voltage of the second inverting input terminal 312 is also the cut-off voltage Vs, the cut-off voltage Vs is applied to the second resistor R0, and the current flowing through the second resistor R0 is the target current Iconv.

[0046] That is, through the above structure, the target current acquisition circuit 3 can obtain the target current Iconv reflecting the target constant power current in the constant power mode.

[0047] Specifically, as mentioned above, the ideal current corresponding to the conversion / switching time point when switching from the constant power mode to the constant current mode is the set current value Icc in the constant current mode, and the corresponding switching point output voltage is Vsp. Since the conversion time point is still in the constant power mode, the power at the conversion time point is still equal to the power in the constant power mode, that is, equal to the product of the switching point output voltage Vsp and the constant current Icc.

[0048] In some embodiments, the target current Iconv is set equal to the target constant power current in the constant power mode, and the current output voltage is set to Vout. Therefore, the target current Iconv and the current output voltage Vout are actually the power in the constant power mode, which is equal to the switching point output voltage Vsp*constant current Icc.

[0049] That is, we can get formula 1:

[0050] Vout*Iconv=Vsp*Icc.

[0051] As mentioned above, when the oscillator circuit 1 generates the clock signal CK, the associated current Ivout charges the first capacitor C1, so that the charging time for the end of the first capacitor C1 connected to the first positive input terminal 111 to reach the preset reference voltage Vr is T. Assuming that the capacitance of the first capacitor C1 is C1, according to the charge calculation formula, Ivout*T=Vr*C1, assuming that the first preset current is Icc1, and the resistance value of the first resistor R1 is R1, since the preset reference voltage Vr=Icc1*R1, and as mentioned above, Ivout=Vout / R, therefore, Formula 2 is obtained:

[0052] Ivout*T=Icc1*R1*C1.

[0053] Further, we can obtain formula 3: T = Icc1*R1*C1 / Ivout;

[0054] In the target current acquisition circuit 3, as mentioned above, the conduction time of the first switch K1 is equal to the charging time T for the end of the first capacitor C1 connected to the first positive input terminal 111 to reach the preset reference voltage Vr, and the charging time of the second preset current Ivsp to the second capacitor C2 is also equal to T. Therefore, assuming that the capacitance of the second capacitor C2 is C2, according to the charge calculation formula, Ivsp*T=cut-off voltage Vs*C2, therefore, Formula 4 can be obtained: Cut-off voltage Vs=Ivsp*T / C2, and the aforementioned Formula 3: T=Icc1*R1*C1 / Ivout is substituted into Formula 4 to obtain Formula 5:

[0055] Vs=Ivsp*Icc1*R1*C1 / (C2*Ivout);

[0056] Assume that the associated current Ivout is generated by applying the current output voltage Vout to a specific resistor R with a resistance value R, then Ivout = Vout / R. Assume that the second preset current is Ivsp, which is generated by applying the switching point output voltage Vsp to a specific resistor R with a resistance value R, that is, Ivsp = Vsp / R.

[0057] Therefore, since Iconv=cutoff voltage Vs / R2, Ivsp=Vsp / R, Ivout=Vout / R, we can get formula 6:

[0058] Iconv*R2=Vsp*Icc1*R1*C1*R / (R*C2*Vout), assuming the resistance value R1=R2, the capacitance value C1=C2, then formula 6 can be simplified to:

[0059] Iconv*R2=Vsp*Icc1*R1 / Vout, that is, it meets the aforementioned formula 1: Iconv*Vout=Vsp*Icc1. That is, in this application, through the design of the above switching control circuit, the target current Iconv is a current that meets the constant power mode corresponding to the current output voltage Vout.

[0060] like Figure 2-Figure 3 As shown, in some embodiments, the switching control circuit 100 further includes a current mirror circuit 6, and the current mirror circuit 6 is used to mirror the target current Iconv to the first input terminal 41 of the current switching circuit 4. Figure 3 As shown, the current mirror circuit 6 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3. The sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to each other, the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, the drain of the first MOS transistor M1 is connected to the source of the third MOS transistor M3, the drain of the second MOS transistor M2 is connected to the first input terminal 41 of the current switching circuit 4, the drain of the third MOS transistor M3 is connected to the end of the second resistor R2 away from the ground, the gate of the third MOS transistor M3 is connected to the second output terminal 312 of the first operational amplifier 31, the current flowing through the third MOS transistor M3 is equal to the target current flowing through the second resistor R2, the first MOS transistor M1 and the second MOS transistor M2 form a current mirror, and the target current Iconv flowing through the third MOS transistor M3 is mirrored to the drain of the second MOS transistor M2, so that the first input terminal 41 of the current switching circuit 4 receives the target current Iconv.

[0061] Among them, Figure 3As shown, the sources of the first MOS transistor M1 and the second MOS transistor M2 are also connected to a voltage source VDD.

[0062] like Figure 3 As shown, as also described above, the second input terminal 32 of the current switching circuit 3 is connected to the second constant current source Y2 to receive the first preset current generated by the second constant current source Y2.

[0063] The current switching circuit 3 can output the target current Iconv when the current target current is less than the first preset current to achieve current control in the constant power mode; when the target current reaches the first preset current, the current switching circuit 3 can output the first preset current Icc1 to switch to the constant current mode and achieve current control in the constant current mode.

[0064] See also Figure 5 , is a circuit block diagram of a current switching circuit 4 in an embodiment of the present application. The current switching circuit 4 further includes an adding circuit 401, a subtracting circuit 402, a first current mirror 403 and a second current mirror 404, the adding circuit 401 is connected to the first input terminal 41 and the second input terminal 42 of the current switching circuit 4, and is used to add the first preset current and the target current to output a summed current of the first preset current Icc1 and the target current Iconv, wherein when the target current Iconv is less than the first preset current Icc1, the summed current is equal to the sum of the first preset current Icc1 and the target current Iconv, and when the target current Iconv is not less than the first preset current Icc1, the summed current is equal to twice the first preset current Icc1. The first current mirror 403 is used to mirror the summed current to the subtraction circuit 402, and the subtraction circuit 402 is used to subtract the summed current from the first preset current Icc1 to obtain a subtracted current difference. The second current mirror 404 is connected between the subtraction circuit 402 and the current output terminal 43 of the current switching circuit 4, and is used to mirror the current difference to the current output terminal 43 to obtain an output current output from the current output terminal 43.

[0065] Among them, since the target current Iconv is less than the first preset current Icc1, the total current is equal to the sum of the first preset current Icc1 and the target current Iconv, and when the target current Iconv is not less than the first preset current Icc1, the total current is equal to twice the first preset current Icc1, and since the target current Iconv is less than the first preset current Icc1, it is still in constant power mode at this time, and when the target current is not less than the first preset current, it enters constant current mode at this time. Therefore, in constant power mode, the total current is equal to the sum of the first preset current Icc1 and the target current Iconv, and after subtracting the first preset current Icc1, the target current Iconv is obtained; and in constant current mode, the total current is equal to twice the first preset current Icc1, and after subtracting the first preset current Icc1, the first preset current Icc1 is obtained.

[0066] Therefore, through the above circuit structure, the current switching circuit 4 can output the target current Iconv when the current target current is less than the first preset current Icc1 to achieve current control in the constant power mode; when the target current Iconv reaches the first preset current Icc1, the first preset current Icc1 is output.

[0067] See also Figure 6 , is a specific circuit diagram of the current switching circuit 4 in one embodiment of the present application. Figure 6 As shown, the adding circuit 401 includes a fourth MOS tube M4 and a fifth MOS tube M4, the drain of the fourth MOS tube M4 is connected to the second input terminal 42 of the current switching circuit 4, and is used to receive the first preset current Icc1, the drain of the fifth MOS tube M4 is connected to the first input terminal 41 of the current switching circuit 4, and is used to receive the target current Iconv, the gate of the fourth MOS tube M4 is connected to the gate of the fifth MOS tube M5, the source of the fourth MOS tube M4 is connected to the source of the fifth MOS tube M5, the fourth MOS tube M4 and the fifth MOS tube constitute the adding circuit 401, and the total current is output through the source connected between the fourth MOS tube M4 and the fifth MOS tube M5.

[0068] As mentioned above, when the target current is less than the first preset current, the total current is equal to the sum of the first preset current and the target current, and when the target current is not less than the first preset current, the source output current of the fifth MOS tube M5 is limited to the first preset current, therefore, the total current is equal to twice the first preset current.

[0069] The first current mirror 403 includes a sixth MOS tube M6 and a seventh MOS tube M7, the drain of the sixth MOS tube M6 is connected to the source of the fourth MOS tube M4 and the source of the fifth MOS tube M5, the source of the sixth MOS tube M6 is grounded, the gate of the sixth MOS tube M6 is connected to the gate of the seventh MOS tube M7, the source of the seventh MOS tube M7 is grounded, the summed current is mirrored to the seventh MOS tube M7, so that the current flowing through the seventh MOS tube M7 is the summed current.

[0070] The subtraction circuit 402 includes a first branch L1, a second branch L2 and a third branch L3, wherein the first ends of the first branch L1, the second branch L2 and the third branch L3 are connected to the same node N2, the second end of the first branch L1 is used to input the first preset current Icc1, the second end of the second branch L2 is connected to the drain of the seventh MOS tube M7, and the current flowing through is the summed current. The second current mirror 404 includes an eighth MOS tube M8 and a ninth MOS tube M9, wherein the drain of the eighth MOS tube M8 is connected to the second end of the third branch L3, wherein the current of the third branch L3 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current Icc1 flowing through the first branch L1. That is, as Figure 6 As shown, the current of the first branch L1 flows into the node N2, the current of the third branch L3 also flows into the node N2, and the direction of the summed current flowing through the second branch L2 is from the node N2 to the seventh MOS transistor M7, therefore, in fact, the summed current flowing through the second branch L2 is equal to the sum of the current of the third branch L3 and the first preset current Icc1 flowing through the first branch L1. Therefore, the current of the third branch L3 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current Icc1 flowing through the first branch L1.

[0071] The gate of the eighth MOS tube M8 is connected to the gate of the ninth MOS tube M9, the drain of the eighth MOS tube M8 is connected to the second end of the third branch L3, the current flowing through the drain of the eighth MOS tube M8 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current flowing through the first branch L1, the source of the eighth MOS tube M8 is connected to the source of the ninth MOS tube M9, the drain of the ninth MOS tube M9 is connected to the current output terminal 43 of the current switching circuit 4, the current of the drain of the eighth MOS tube M8 is mirrored to the drain of the ninth MOS tube M9, so that the output current output by the current output terminal 43 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current flowing through the first branch L1. Thus, when the current target current Iconv is less than the first preset current Icc1, the output current is the target current Iconv, and when the target current Iconv reaches the first preset current Icc1, the output current is the first preset current Icc1.

[0072] Among them, Figure 6 The second end of the first branch L2 is connected to the fourth constant current source Y4, the fourth constant current source Y4 generates the first preset current Icc1, and the second end of the first branch L2 receives the first preset current Icc1 generated by the fourth constant current source Y4.

[0073] The source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are also connected to the voltage source VDD.

[0074] Please refer back to Figure 3 , wherein the feedback comparison circuit 5 specifically includes a second operational amplifier 51, the second operational amplifier includes a third positive phase input terminal 511, a third negative phase input terminal 512 and a third output terminal 513, the third positive phase input terminal 511 is used to receive the feedback current Ics reflecting the current actual output current, and the third positive phase input terminal 511 is also grounded through a third resistor R3. The third negative phase input terminal 512 is connected to the current output terminal 43 of the current switching circuit 4, and the third negative phase input terminal 512 is also grounded through a fourth resistor R4.

[0075] The feedback current Ics flows through the third resistor R3 so that the third positive phase input terminal 511 has a corresponding voltage, the output current output by the current output terminal 43 of the current switching circuit 4 flows through the fourth resistor R4 so that the third negative phase input terminal 512 has a corresponding voltage, and the second operational amplifier 51 compares the voltages of the third positive phase input terminal 511 and the third negative phase input terminal 512, and generates an adjustment signal when the voltages of the third positive phase input terminal 511 and the third negative phase input terminal 512 are not equal. Specifically, when the voltage of the third positive phase input terminal 511 is greater than the voltage of the third negative phase input terminal 512, a high-level adjustment signal is output, and when the voltage of the third positive phase input terminal 511 is less than the voltage of the third negative phase input terminal 512, a low-level adjustment signal is output.

[0076] The resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4. The voltage of the third positive phase input terminal 511 is equal to Ics*R3. Assuming that the output current output by the current output terminal 43 is Icp, the voltage of the third negative phase input terminal 512 is equal to Icp*R4. Since the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4, the magnitude relationship between the voltage of the third positive phase input terminal 511 and the voltage of the third negative phase input terminal 512 is the relationship between the feedback current Ics and the output current Icp.

[0077] The adjustment signal can be provided to a subsequent processing circuit, and the subsequent processing circuit can control the actual output current to be lowered when receiving a high-level adjustment signal, and control the actual output current to be increased when receiving a low-level adjustment signal, so that the actual output current, that is, the feedback current Ics, is equal to the output current Icp. For another example, further, there is a switch in the output path, and the processing circuit can control the change of the duty cycle of the switch on and off to change the size of the actual output current.

[0078] The third output terminal 513 is also connected to components such as capacitors and resistors for filtering.

[0079] Therefore, through the switching control circuit 100 of the present application, the power in the constant power mode can be controlled to remain consistent and the switching accuracy from the constant power mode to the constant current mode can be ensured.

[0080] In some embodiments, the switching control circuit 100 can be integrated into a chip, such as a charging chip, to achieve power consistency in the constant power mode during charging and ensure switching accuracy from the constant power mode to the constant current mode. Furthermore, the charging chip can be a fast charging chip that supports fast charging.

[0081] See also Figure 7 , is a structural block diagram of an electronic device 200 in an embodiment of the present application. The electronic device 200 includes the aforementioned switching control circuit 100 .

[0082] The electronic device 100 may be a terminal such as a mobile phone or a tablet computer, and the electronic device 100 may also be a charging adapter or the like.

[0083] The electronic device 100 further includes other components, which are irrelevant to the improvement of the present invention and are therefore not described in detail.

[0084] See also Figure 8 , is a flow chart of a switching control method in an embodiment of the present application. The switching control method is applied to the switching control circuit 100. Figure 8 As shown, the switching control method includes:

[0085] 801: Generate a clock signal through an oscillator circuit.

[0086] 802: Perform delay calibration on the clock signal through a delay calibration and timing circuit to output a plurality of control signals.

[0087] 803: Responding to the plurality of control signals through a target current acquisition circuit to obtain a target current, where the target current is used to reflect a target constant power current in a constant power mode.

[0088] 804: Receive the target current through a first input terminal of the current switching circuit, and receive a first preset current through a second input terminal of the current switching circuit, where the first preset current is used to reflect a target constant current in a constant current mode.

[0089] 805: The current switching circuit controls the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal; wherein, when the current target current is less than the first preset current, the output current is the target current, so as to realize current control in the constant power mode; and when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize current control in the constant current mode.

[0090] Among them, the switching control method may also include other steps, and may also include steps corresponding to the operations performed by the aforementioned switching control circuit 100, for example: the "when the current target current is less than the first preset current, the output current is the target current, so as to realize current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize current control in the constant current mode" includes: receiving the output current output by the current switching circuit and a feedback current reflecting the current actual output current through a feedback comparison circuit, and comparing the output current and the feedback current, and generating an adjustment signal when the output current is inconsistent with the feedback current, until the feedback current is consistent with the output current, so that the actual current in the constant power mode is consistent with the target constant power current to realize current control in the constant power mode, or the actual current in the constant current mode is consistent with the target constant current current, and switching to the constant current mode and realizing current control in the constant current mode.

[0091] Specifically, other steps included in the switching control method may refer to the related description of the aforementioned switching control circuit 100 .

[0092] This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, various operating steps and components for performing operating steps may be deleted, modified, or incorporated into other steps.

[0093] The above is an implementation of the embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the embodiment of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A switching control method, characterized in that: Applied to a switching control circuit, the switching control circuit includes a delay calibration and timing circuit, a target current acquisition circuit and a current switching circuit; the switching control method includes: outputting a plurality of control signals through the delay calibration and timing circuit for delay calibration of a clock signal; A target current is obtained by a target current acquisition circuit in response to the control signals, wherein the target current is used to reflect a target constant power current in a constant power mode; The target current is received through a first input terminal of the current switching circuit, and a first preset current is received through a second input terminal of the current switching circuit, wherein the first preset current is used to reflect a target constant current in a constant current mode; The current switching circuit controls the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal; when the target current is less than the first preset current, the output current is the target current to achieve current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current to switch to the constant current mode and achieve current control in the constant current mode; The switching control circuit further includes an oscillator circuit for generating a clock signal; the oscillator circuit is used to receive an associated current related to a current output voltage and the first preset current, and generate the clock signal according to the associated current and the first preset current, wherein the delay calibration and timing circuit outputs at least one control signal by calibrating the clock signal; Wherein, the delay calibration and timing circuit includes a first signal output terminal, a second signal output terminal and a third signal output terminal, and the delay calibration and timing circuit is used to perform delay calibration on the clock signal to output a first control signal, a second control signal and a third control signal through the first signal output terminal, the second signal output terminal and the third signal output terminal respectively, wherein the first control signal is a signal obtained by extending the high level duration in the clock signal and then inverting it, the high level duration in the first control signal is equal to the charging duration T for the first capacitor in the oscillator circuit to charge to a preset reference voltage, and the associated current is used to charge the first capacitor; the second control signal is equal to the clock signal, and the third control signal is a signal obtained by delaying the high level of the clock signal, the high level period of the third control signal is staggered with the high level period of the second control signal, and the high level periods of the second control signal and the third control signal are both located in the low level period of the first control signal.

2. A switching control circuit, characterized in that: The switching control circuit comprises: a delay calibration and timing circuit for delay calibration of a clock signal, and for outputting at least one control signal; The target current acquisition circuit is used to obtain a target current in response to the at least one control signal, and the target current is used to reflect a target constant power current in a constant power mode; A current switching circuit comprises a first input terminal, a second input terminal and a current output terminal, wherein the first input terminal is used to receive the target current, the second input terminal is used to receive a first preset current, and the first preset current is used to reflect the target constant current in the constant current mode; the current switching circuit is used to control the current output terminal to output an output current according to the target current received by the first input terminal and the first preset current received by the second input terminal, Wherein, when the target current is less than the first preset current, the output current is the target current, so as to realize the current control in the constant power mode; when the target current reaches the first preset current, the output current is the first preset current, so as to switch to the constant current mode and realize the current control in the constant current mode; The switching control circuit further includes an oscillator circuit for generating a clock signal; the oscillator circuit is used to receive an associated current related to a current output voltage and the first preset current, and generate the clock signal according to the associated current and the first preset current, wherein the delay calibration and timing circuit outputs at least one control signal by calibrating the clock signal; Wherein, the delay calibration and timing circuit includes a first signal output terminal, a second signal output terminal and a third signal output terminal, and the delay calibration and timing circuit is used to perform delay calibration on the clock signal to output a first control signal, a second control signal and a third control signal through the first signal output terminal, the second signal output terminal and the third signal output terminal respectively, wherein the first control signal is a signal obtained by extending the high level duration in the clock signal and then inverting it, the high level duration in the first control signal is equal to the charging duration T for the first capacitor in the oscillator circuit to charge to a preset reference voltage, and the associated current is used to charge the first capacitor; the second control signal is equal to the clock signal, and the third control signal is a signal obtained by delaying the high level of the clock signal, the high level period of the third control signal is staggered with the high level period of the second control signal, and the high level periods of the second control signal and the third control signal are both located in the low level period of the first control signal.

3. The switching control circuit according to claim 2, characterized in that: The switching control circuit also includes a feedback comparison circuit, which is used to receive an output current output by the current switching circuit and a feedback current reflecting the current actual output current, and compare the output current and the feedback current, and generate an adjustment signal when the output current is inconsistent with the feedback current, until the feedback current is consistent with the output current, so that the actual current in the constant power mode is consistent with the target constant power current to achieve current control in the constant power mode, or the actual current in the constant current mode is consistent with the target constant current current, and the current is switched to the constant current mode and current control in the constant current mode is achieved.

4. The switching control circuit according to claim 3, characterized in that: The oscillator circuit includes a comparator, a first capacitor, a first resistor and an NMOS tube. The comparator includes a first positive input terminal, a first negative input terminal and a first output terminal. The first positive input terminal is used to receive the associated current, and the first positive input terminal is also grounded through the first capacitor. The first negative input terminal is used to receive the first preset current, and the first negative input terminal is also grounded through the first resistor. The NMOS tube and the first capacitor are connected in parallel between the first positive input terminal and the ground, and the first output terminal is connected to the gate of the NMOS tube; wherein the first preset current flows through the first resistor and generates a preset reference voltage at the first negative input terminal. The associated current is used to generate a preset reference voltage at the first negative input terminal. The first capacitor is charged, so that the voltage of the first non-inverting input terminal rises. When the voltage of the first non-inverting input terminal rises to reach the preset reference voltage, the comparator outputs a high-level signal to the gate of the NMOS tube through the first output terminal, and controls the NMOS tube to be turned on, so that the first capacitor is discharged through the turned-on NMOS tube, and the voltage of the first non-inverting input terminal drops to less than the preset reference voltage, so that the comparator outputs a low-level signal through the first output terminal, thereby causing the oscillator circuit to output a periodically changing clock signal, wherein the low-level duration in each cycle of the clock signal is equal to the charging duration T for the first capacitor to charge to reach the preset reference voltage.

5. The switching control circuit according to any one of claims 2 to 4, characterized in that: The target current acquisition circuit includes a first switch, a second switch, a third switch, a second capacitor, a third capacitor, a first operational amplifier and a second resistor. One end of the first switch is used to connect to a second preset current, and the second preset current is related to the output voltage when the constant power mode is switched to the constant current mode. The other end of the first switch is grounded through the third switch. The second switch is connected between a connection node between the first switch and the third switch and a second non-inverting input terminal of the first operational amplifier. The connection node between the first switch and the third switch is also grounded through a second capacitor. The second non-inverting input terminal is also grounded through the third capacitor. The second inverting input terminal of the first operational amplifier is also grounded through the second resistor.

6. The switching control circuit according to claim 5, characterized in that: The first signal output terminal is connected to the first switch, and is used to output the first control signal to the first switch to control the first switch to be turned on or off. The second signal output terminal is connected to the second switch, and is used to output the second control signal to the second switch to control the second switch to be turned on or off. The third signal output terminal is connected to the third switch, and is used to output the third control signal to the third switch to control the third switch to be turned on or off. The first switch, the second switch, and the third switch are all high-level conduction switches. During a first duration when the first control signal is at a high level, the second control signal and the third control signal are continuously at a low level, the first switch is continuously turned on, and the second switch and the third switch are turned off. During the first duration, the second preset current continuously charges the second capacitor through the turned-on first switch. During a second duration when the first control signal is at a low level, the The second control signal first changes to a high level, at which time the first control signal and the third control signal are both low levels, at which time the second switch is turned on, the first switch and the third switch are turned off, and the second capacitor and the third capacitor share charge through the turned-on second switch. When the third control signal changes to a high level, at which time the first control signal and the second control signal are both low levels, at which time the third switch is turned on, the first switch and the second switch are turned off, and the second capacitor is connected to the ground through the turned-on third switch to discharge; under the control of the first control signal, the second control signal and the third control signal for several cycles, the voltage of the third capacitor is equal to the cut-off voltage when the charging of the second capacitor is cut off, the second non-inverting input terminal of the first operational amplifier is virtually shorted with the second inverting input terminal, and the voltage of the second inverting input terminal is also the cut-off voltage, the cut-off voltage is applied to the second resistor, and the current flowing through the second resistor is the target current.

7. A charging chip, characterized in that: The charging chip includes the switching control circuit as described in any one of claims 2-6.

8. An electronic device, characterized in that: The electronic device comprises the switching control circuit as claimed in any one of claims 2 to 6.

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