Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate, a bit line structure located on the substrate, and capacitor contact holes located on opposite sides of the bit line structure; an isolation sidewall, wherein the isolation sidewall is located between the bit line structure and the capacitor contact hole, and a void isolation layer is provided between the isolation sidewalls located on opposite sides of the bit line structure, wherein the void isolation layer is located on the bit line structure, wherein the void isolation layer has a first void, and wherein a second void is provided between the isolation sidewall and the void isolation layer. The present invention is conducive to reducing the parasitic capacitance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the feature size of semiconductor integrated circuits continues to decrease, higher requirements are placed on the manufacturing process of dynamic random access memory (DRAM).

[0003] Specifically, as the feature size continues to shrink, the spacing between adjacent conductors becomes smaller and smaller, and the thickness of the dielectric layer separating adjacent conductors becomes thinner and thinner. When the dielectric constant of the dielectric layer remains unchanged, the thinner the thickness of the dielectric layer, the more serious the parasitic capacitance problem between adjacent conductors. Summary of the invention

[0004] The embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are beneficial to reducing the parasitic capacitance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, a bit line structure located on the substrate, and capacitor contact holes located on opposite sides of the bit line structure; an isolation side wall, wherein the isolation side wall is located between the bit line structure and the capacitor contact hole, and a gap isolation layer is provided between the isolation side walls located on opposite sides of the bit line structure, the gap isolation layer is located on the bit line structure, a first gap is provided in the gap isolation layer, and a second gap is provided between the isolation side wall and the gap isolation layer.

[0006] In addition, the second gap is also located between the isolation spacer and the bit line structure.

[0007] In addition, the semiconductor structure further includes: a sacrificial sidewall, the sacrificial sidewall is located between the isolation sidewall and the bit line structure, the sacrificial sidewall covers the conductive layer sidewall of the bit line structure, and the second gap exposes the top surface of the sacrificial sidewall.

[0008] In addition, the top surface of the void isolation layer is lower than the top surface of the isolation sidewall.

[0009] In addition, the first gap and the second gap extend in parallel with an extending direction of the bit line structure.

[0010] In addition, in a direction perpendicular to the surface of the substrate, the thickness of the first gap is less than or equal to 100 nm.

[0011] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate and a bit line structure located on the substrate, the bit line structure including a top dielectric layer, and the bit line structure having capacitor contact holes on two opposite sides; forming a sacrificial sidewall covering the sidewall of the top dielectric layer; removing at least a portion of the top dielectric layer to form a first gap; performing a deposition process to form a gap isolation layer having the first gap; forming an isolation sidewall covering the sacrificial sidewall, and removing at least a portion of the sacrificial sidewall to form a second gap located between the isolation sidewall and the gap isolation layer.

[0012] In addition, the process steps for forming the gap isolation layer include: forming an enveloping layer covering the top surface of the top dielectric layer and the side walls of the sacrificial sidewall, wherein the first gap is formed in the enveloping layer; forming a first sealing layer for blocking the top opening of the first gap, wherein the first sealing layer and the enveloping layer constitute the gap isolation layer.

[0013] In addition, the deposition rate of forming the first sealing layer is greater than the deposition rate of forming the surrounding layer.

[0014] In addition, removing at least a portion of the sacrificial spacer includes: removing a portion of the sacrificial spacer, and the remaining sacrificial spacer covers the conductive layer sidewall of the bit line structure.

[0015] In addition, the top surface of the void isolation layer is lower than the top surface of the isolation side wall; after the second void is formed, a second sealing layer is formed to block the top opening of the second void, and the second sealing layer covers the top surface of the void isolation layer.

[0016] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0017] In the above technical solution, a new semiconductor structure is provided, in which a first gap is provided in the gap isolation layer, and a second gap is provided between the gap isolation layer and the isolation side wall. The setting of the first gap and the second gap is beneficial to reducing the dielectric constant of the dielectric layer between the relative capacitor contact windows, thereby reducing the parasitic capacitance between the capacitor contact windows.

[0018] In addition, the sacrificial sidewall covers the sidewall of the conductive layer of the bit line structure, which can protect the conductive layer to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0020] Figures 1 to 18A schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0022] Figures 1 to 18 A schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0023] refer to Figure 1 , providing a substrate 10, a bottom dielectric film 101, a first conductive film 111a, a second conductive film 112a, a top dielectric film 113a, a first mask layer 121, a second mask layer 122 and a third mask layer 123 stacked in sequence on the substrate 10.

[0024] The bottom dielectric film 101 is used to isolate the first conductive film 111a from the active area (not shown) in the substrate 10, and the material of the bottom dielectric film 101 includes silicon nitride; a portion of the first conductive film 111a contacts the active area to serve as a bit line contact, and the material of the first conductive film 111a includes polysilicon; the material of the second conductive film 112a includes tungsten; the top dielectric film 113a acts as a dielectric layer and protects the second conductive film 112a, and the material of the top dielectric film 113a includes silicon nitride.

[0025] In this embodiment, the mask layer includes a first mask layer 121 and a second mask layer 122. The hardness of the first mask layer 121 is greater than that of the second mask layer 122 to improve the etching accuracy of the subsequent etching process. In other embodiments, an anti-reflective coating is also provided between the first mask layer and the first sacrificial film to reduce problems such as reflection and standing waves.

[0026] The material of the first mask layer 121 may include silicon nitride, the material of the second mask layer 122 may include polysilicon, and the anti-reflective coating is generally a carbon coating.

[0027] In this embodiment, the third mask layer 123 is used to define the position of the bit line structure to be formed subsequently.

[0028] refer to Figure 2, forming a fourth mask layer 124 covering the top surface and sidewalls of the third mask layer 123 and the top surface of the second mask layer 122 , wherein the fourth mask layer 124 is used to limit the width of the subsequently formed bit line structure in a direction parallel to the substrate 10 .

[0029] refer to Figure 3 , the second mask layer 122 is etched by using the self-aligned double patterning (SADP) technique, and the width of the remaining second mask layer 122 is the same as that of the third mask layer 123 (refer to Figure 2 ) sidewall of the fourth mask layer 124 (reference Figure 2 The remaining second mask layer 122 is used as a mask for etching to form a bit line structure, and the width of the remaining second mask layer 122 is equal to the width of the bit line structure to be formed subsequently.

[0030] refer to Figure 4 The remaining second mask layer 122 is used to form a top dielectric film 113a, a second conductive film 112a, a first conductive film 111a and a bottom dielectric film 101 (reference Figure 3 ) is etched to form a bit line structure 11.

[0031] In this embodiment, the bit line structure 11 includes a bottom dielectric layer (not shown), a conductive layer and a top dielectric layer 113, and the conductive layer includes a first conductive layer 111 and a second conductive layer 112; in other embodiments, the conductive layer may include a single layer or more than two conductive layers.

[0032] refer to Figure 5 , using a deposition process to form a first sacrificial film 131a covering the sidewalls and top surface of the bit line structure 11 and the surface of the substrate 10; Figure 6 The first sacrificial film 131a covering the surface of the substrate 10 and the top surface of the bit line structure 11 is removed by a maskless dry etching process (refer to Figure 5 ), the remaining first sacrificial film 131a serves as a sacrificial sidewall 131.

[0033] In this embodiment, the material of the sacrificial spacer 131 is different from the material of the top dielectric layer 113 , and the material of the sacrificial spacer 131 includes silicon dioxide.

[0034] Reference Figure 7 Before etching the top dielectric layer 113 , a first sacrificial layer 141 is formed to fill between adjacent bit line structures 11 , and the first sacrificial layer 141 exposes the top dielectric layer 113 .

[0035] The material of the first sacrificial layer 141 is different from that of the top dielectric layer 113, which helps to prevent the etching process for the top dielectric layer 113 from damaging the substrate 10. Specifically, the material of the first sacrificial layer 141 includes exposed photoresist.

[0036] refer to Figure 8 , the top dielectric layer 113 is etched to form a first gap 132 between the opposite sacrificial sidewalls 131 .

[0037] In this embodiment, only a portion of the top dielectric layer 113 is etched to retain a portion of the top dielectric layer 113 , and the remaining top dielectric layer 113 is used to protect the second conductive layer 112 of the bit line structure 11 .

[0038] In this embodiment, the process steps of forming the gap isolation layer include: Fig. 9 , a single deposition process is performed to form a gap isolation film 133a that blocks the first gap 132; Fig.10 , for the gap isolation film 133a (reference Fig. 9 ) is subjected to a planarization process so that the top surface of the gap isolation film 133a is flush with the top surface of the sacrificial sidewall 131, and the remaining gap isolation film 133a serves as the sacrificial isolation layer 133.

[0039] In other embodiments, the process steps for forming the void isolation layer include: first performing a first deposition process with a slower deposition rate to form an enclosing layer covering the top surface of the top dielectric layer and the side walls of the sacrificial side walls, wherein the enclosing layer has a first void; and then performing a second deposition process with a faster deposition rate to achieve rapid sealing, i.e., forming a first sealing layer that blocks the top opening of the first void, wherein the first sealing layer and the enclosing layer constitute a void isolation layer.

[0040] After forming the gap isolation layer 133, the first sacrificial layer 141 is removed (refer to Fig. 9 ) to expose the sidewall of the sacrificial spacer 131 away from the bit line structure 11.

[0041] refer to Fig.11 , a deposition process is used to form a first isolation film 134 .

[0042] In this embodiment, the first isolation film 134 includes a top isolation layer 134 b covering the top surface of the sacrificial spacer 131 and the top surface of the gap isolation layer 133 , an isolation spacer 134 a covering the sidewall of the sacrificial spacer 131 , and a bottom isolation layer 134 c covering the surface of the substrate 10 .

[0043] In this embodiment, reference Fig.12Before etching away the top isolation layer 134b, a second sacrificial layer 142 is formed to fill between adjacent bit line structures 11 to prevent the etching process for the top isolation layer 134b from penetrating the bottom isolation layer 134c and causing damage to the substrate 10; in other embodiments, the second sacrificial layer is not formed after etching away the top isolation layer.

[0044] In this embodiment, the material of the second sacrificial layer 142 includes exposed photoresist.

[0045] refer to Fig.13 , remove the top isolation layer 134b (reference Fig.12 ), and removing at least a portion of the sacrificial spacer 131 to form a second gap 135.

[0046] In this embodiment, only a portion of the sacrificial sidewall 131 is removed, and the remaining sacrificial sidewall 131 covers the sidewalls of the first conductive layer 111 and the second conductive layer 112. In this way, it is not only beneficial to avoid the removal process of the sacrificial sidewall 131 from damaging the first conductive layer 111 and the second conductive layer 112, but also beneficial to protect the first conductive layer 111 and the second conductive layer 112, avoid signal transmission interruption caused by the conductive layer being damaged by the partially collapsed material, and ensure that the semiconductor structure as a whole has good signal transmission performance.

[0047] refer to Fig.14 , forming a second sealing layer 136 to block the top opening of the second gap 135.

[0048] In this embodiment, the top surface of the second sealing layer 136 is flush with the top surface of the second sacrificial layer 142 , that is, the second sealing layer 136 is formed by a planarization process.

[0049] It should be noted that when forming a sealing layer to block the top opening of a certain gap, if the width of the top opening of the gap is relatively large, in order to prevent the sealing layer from collapsing due to being unable to bear its own weight, and to ensure rapid sealing to increase the size of the remaining gap, usually only a thin sealing layer is formed. However, although this type of sealing layer can bear its own weight, when other structures covering the sealing layer are too heavy, it will also cause the sealing layer to collapse.

[0050] In this embodiment, before forming the second sealing layer 136, the height difference between the top surface of the void isolation layer 133 and the top surface of the isolation sidewall 134a is adjusted so that the top surface of the void isolation layer 133 is lower than the preset height of the top surface of the isolation sidewall 134a. In this way, when the second sealing layer is subsequently deposited, the void isolation layer 133 can be used as a support to form a thicker second sealing layer 136, which is conducive to preventing the second sealing layer 136 from collapsing due to its own weight or the weight of the covering material exceeding the pressure limit, thereby ensuring that the semiconductor structure has good structural stability.

[0051] refer to Fig.15 and Fig.16 , forming a fifth mask layer 143 , and performing a dry etching process through the fifth mask layer 143 .

[0052] In this embodiment, in the extension direction parallel to the bit line structure 11, the substrate 10 can be divided into a first area A and a second area B arranged at intervals. The first area A between adjacent bit line structures 11 is used to form capacitor contact holes and fill capacitor contact windows, and the second area B between adjacent bit line structures 11 is used to form an isolation layer, which is used to divide the capacitor contact holes and isolate adjacent capacitor contact windows.

[0053] In this embodiment, the fifth mask layer 143 covers the top surface of the second sacrificial layer 142 in the first region A and exposes the top surface of the second sacrificial layer 142 in the second region B. Accordingly, the dry etching process is performed through the fifth mask layer 143, including: removing the second sacrificial layer 142 in the second region B.

[0054] In other embodiments, before forming the fifth mask layer, the material of the second sacrificial layer is replaced, for example, the photoresist material is replaced with a silicon dioxide material.

[0055] refer to Fig.17 , performing deposition process and planarization process.

[0056] In this embodiment, the fifth mask layer 143 (see Fig.15 ) to avoid the need for the grinding device to contact with at least three materials (the material of the fifth mask layer 143, the material of the second sacrificial layer 142, and the material deposited by the deposition process) during the subsequent planarization process, thereby avoiding the impact of the concave-convex structure formed by the large difference in removal rates of different materials on the grinding device, thereby ensuring that the grinding device has a long service life, or there is no need to replace the grinding liquid or mask components midway to avoid excessive differences in removal rates, thereby improving process efficiency.

[0057] In other embodiments, the fifth mask layer is retained during the deposition process, and the fifth mask layer and other film layers are removed simultaneously by a planarization process, which is beneficial to reducing process steps and shortening process cycle.

[0058] In this embodiment, the deposition process is used to deposit the isolation material, and the isolation material is used to form the contact isolation layer 15, and the contact isolation layer 15 is used to isolate and define adjacent capacitor contact holes. Specifically, a contact isolation film having a top surface higher than the top surface of the second sealing layer 136 can be formed first, and then the contact isolation film and the second sacrificial layer 142 are planarized to form the contact isolation layer 15 and the second sacrificial layer 142 having a top surface flush with the top surface of the second sealing layer 136.

[0059] refer to Fig.18 , for the second sacrificial layer 142 in the remaining first region A (refer to Fig.17 ) and the bottom isolation layer 134c located between the second sacrificial layer 142 and the substrate 10 are etched to form a capacitor contact hole (not shown); the capacitor contact hole is filled to form a capacitor contact window 16.

[0060] In this embodiment, the capacitor contact window 16 includes a first capacitor contact window 161 located at the top and a second capacitor contact window 162 located at the bottom, and the contact resistance between the second capacitor contact window 162 and the substrate 10 is smaller than the contact resistance between the first capacitor contact window 161 and the substrate 10. This is beneficial to improving signal transmission performance.

[0061] The material of the first capacitor contact window 161 includes tungsten, and the material of the second capacitor contact window 162 includes polysilicon.

[0062] In the present embodiment, a method for manufacturing a semiconductor structure is provided, which can reduce the dielectric constant between capacitor contact windows located on opposite sides of a bit line structure, thereby reducing the parasitic capacitance between the opposite capacitor contact windows.

[0063] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which can be manufactured using the above-mentioned method for manufacturing the semiconductor structure.

[0064] refer to Fig.18 The semiconductor structure includes: a substrate 10, a bit line structure 11 located on the substrate 10, and capacitor contact holes (not marked) located on opposite sides of the bit line structure 11; an isolation sidewall 134a, the isolation sidewall 134a is located between the bit line structure 11 and the capacitor contact hole, and a gap isolation layer 133 is provided between the isolation sidewalls 134a located on opposite sides of the bit line structure 11, the gap isolation layer 133 is located on the bit line structure 11, the gap isolation layer 11 has a first gap 132, and a second gap 135 is provided between the isolation sidewall 134a and the gap isolation layer 133.

[0065] In this embodiment, the second gap 135 is also located between the isolation spacer 134 a and the bit line structure 11 .

[0066] In this embodiment, the semiconductor structure further includes: a sacrificial sidewall 131 , which is located between the isolation sidewall 134 a and the bit line structure 11 , and covers the conductive layer sidewall of the bit line structure 11 . The second gap 135 exposes the top surface of the sacrificial sidewall 131 .

[0067] In this embodiment, the top surface of the void isolation layer 133 is lower than the top surface of the isolation sidewall 134 a .

[0068] In this embodiment, the first gap 132 and the second gap 135 extend in a direction parallel to the extension direction of the bit line structure 11 .

[0069] In this embodiment, in the direction perpendicular to the substrate 10, the thickness of the first gap 132 is less than or equal to 100 nm, for example, 85 nm, 90 nm or 95 nm. This helps to avoid structural collapse due to the gap being unable to provide support, and ensures that the semiconductor structure has good structural stability.

[0070] In this embodiment, a new semiconductor structure is provided, wherein a first gap is provided in the gap isolation layer, and a second gap is provided between the gap isolation layer and the isolation sidewall. The arrangement of the first gap and the second gap is conducive to reducing the parasitic capacitance between relative capacitor contact windows.

[0071] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, a bit line structure located on the substrate, and capacitor contact holes located on opposite sides of the bit line structure; An isolation side wall, wherein the isolation side wall is located between the bit line structure and the capacitor contact hole, and a gap isolation layer is provided between the isolation side walls located on opposite sides of the bit line structure, the gap isolation layer is located on the bit line structure, a first gap is provided in the gap isolation layer, a second gap is provided between the isolation side wall and the gap isolation layer, and a top surface of the gap isolation layer is lower than a top surface of the isolation side wall.

2. The semiconductor structure according to claim 1, characterized in that: The second gap is also located between the isolation spacer and the bit line structure.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A sacrificial sidewall spacer is located between the isolation sidewall spacer and the bit line structure, the sacrificial sidewall spacer covers the conductive layer sidewall of the bit line structure, and the second gap exposes the top surface of the sacrificial sidewall spacer.

4. The semiconductor structure according to claim 1, characterized in that The first gap and the second gap extend in parallel with an extension direction of the bit line structure.

5. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the surface of the substrate, the thickness of the first gap is less than or equal to 100 nm.

6. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and a bit line structure located on the substrate, wherein the bit line structure comprises a top dielectric layer and has capacitor contact holes on two opposite sides of the bit line structure; forming a sacrificial sidewall covering the sidewall of the top dielectric layer; removing at least a portion of the top dielectric layer to form a first gap; Performing a deposition process to form a void isolation layer having the first void; An isolation spacer covering the sacrificial spacer is formed, and at least a portion of the sacrificial spacer is removed to form a second gap between the isolation spacer and the gap isolation layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The process steps for forming the void isolation layer include: forming an enveloping layer covering the top surface of the top dielectric layer and the sidewalls of the sacrificial sidewall, wherein the enveloping layer has the first void; forming a first sealing layer for blocking the top opening of the first void, wherein the first sealing layer and the enveloping layer constitute the void isolation layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The deposition rate of forming the first sealing layer is greater than the deposition rate of forming the surrounding layer.

9. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The removing at least a portion of the sacrificial spacer includes: removing a portion of the sacrificial spacer, and the remaining sacrificial spacer covers the conductive layer sidewall of the bit line structure.

10. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The top surface of the void isolation layer is lower than the top surface of the isolation side wall; after the second void is formed, a second sealing layer is formed to block the top opening of the second void, and the second sealing layer covers the top surface of the void isolation layer.

11. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: Providing a bit line structure on the substrate includes: Providing a bottom dielectric film, a first conductive film, a second conductive film, a top dielectric film, a first mask layer, a second mask layer and a third mask layer stacked in sequence on the substrate; etching the second mask layer; and The top dielectric film, the second conductive film, the first conductive film and the bottom dielectric film are etched through the remaining second mask layer to form the bit line structure.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The hardness of the first mask layer is greater than the hardness of the second mask layer.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The third mask layer is used to define the position of the bit line structure.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: Providing a bit line structure on the substrate further includes: A fourth mask layer is formed to cover the top surface and sidewalls of the third mask layer and the top surface of the second mask layer to limit the width of the bit line structure in a direction parallel to the substrate.

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