Circuit boards and server motherboards

Abstract

The present application relates to a circuit board and a server motherboard. The circuit board includes: a surface layer, the surface layer includes a first pad, a second pad, a first via and a second via, the first pad and the first via are connected through the surface layer portion of a first signal line, the second pad and the second via are connected through the surface layer portion of a second signal line, the arrangement direction of the first via and the second via are parallel to the outlet direction of the first signal line and the second signal line, the arrangement direction of the first pad and the second pad is perpendicular to the outlet direction, and the first center line of the first via and the second via intersects with the second center line of the first pad and the second pad. It can solve the problem in the prior art that the routing of the signal line occupies too much space and the risk of signal crosstalk is high.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a circuit board and a server mainboard. Background Art

[0002] Server motherboards have increasing requirements for high-speed signal frequencies, and the quality of signal transmission is related to the stability of motherboard operation. In some high-performance boards, some switching chips have up to 256 pairs of high-speed differential signal lines, and some even have more. Based on the characteristics of high-speed differential signal lines that transmit signals in pairs, the corresponding pads and vias are also in pairs.

[0003] In the case where the outgoing direction of the high-speed differential signal line pair is perpendicular to the center line connecting the two pads, in the prior art, the arrangement of the surface vias and the pads of the circuit board is: the two vias are located on the same side of the center line connecting the two pads. In this arrangement, in order to reduce signal interference, the routing of the high-speed differential signal line cannot pass through the paired vias. Therefore, the routing of the high-speed differential signal line will take up too much space, increasing the risk of signal crosstalk. Summary of the invention

[0004] Based on this, it is necessary to provide a circuit board and a server motherboard to address the above technical issues, which can solve the problems in the prior art that the routing of signal lines occupies too much space and has a high risk of signal crosstalk.

[0005] In a first aspect, the present application provides a circuit board, comprising: a surface layer, the surface layer comprising a first solder pad, a second solder pad, a first via and a second via, the first solder pad and the first via being connected via a surface portion of a first signal line, the second solder pad and the second via being connected via a surface portion of a second signal line, an arrangement direction of the first via and the second via being parallel to an outlet direction of the first signal line and the second signal line, an arrangement direction of the first solder pad and the second solder pad being perpendicular to the outlet direction, and a first center line connecting the first via and the second via intersecting with a second center line connecting the first solder pad and the second solder pad.

[0006] The above-mentioned circuit board is arranged in such a way that the arrangement direction of the first via and the second via included in the surface layer is parallel to the outlet direction of the first signal line and the second signal line, the arrangement direction of the first pad and the second pad is perpendicular to the outlet direction, and the first center line of the first via and the second via intersects with the second center line of the first pad and the second pad. Compared with the prior art, the present application reduces the routing length of the signal line pair in the BGA area, can effectively avoid the problem of interpenetration of the signal line pair, thereby reducing the risk of signal crosstalk, and at the same time helps to reduce the overall link loss of the signal line pair. In addition, it can also reduce the routing space occupied by the signal line pair, so that more signal line pairs can be accommodated in the same size BGA area.

[0007] In one embodiment, the circuit board also includes an adjacent layer to the surface layer, the adjacent layer to the surface layer includes a first anti-pad, and the outer contour of the first anti-pad includes a vertical projection surface of the first pad on the adjacent layer, a vertical projection surface of the second pad on the adjacent layer, a vertical projection surface of the first via on the adjacent layer, and a vertical projection surface of the second via on the adjacent layer.

[0008] In the present embodiment, by providing anti-pads at adjacent layers of the surface layer of the circuit board, the outer contour of which includes the vertical projection surface of the first pad on the adjacent layer, the vertical projection surface of the second pad on the adjacent layer, the vertical projection surface of the first via on the adjacent layer, and the vertical projection surface of the second via on the adjacent layer, the signal delay problem caused by inconsistent reference of the signal line pairs on the surface layer is avoided, thereby ensuring the signal transmission quality of the signal line pairs.

[0009] In one embodiment, the first anti-pad is in a plum blossom shape.

[0010] In the present embodiment, the anti-pads in the adjacent layers of the surface layer are determined to be plum blossom-shaped, which avoids the signal delay problem caused by inconsistent references of the signal line pairs on the surface layer and ensures the signal transmission quality of the signal line pairs. At the same time, the area occupied by the anti-pads in the adjacent layers of the surface layer is saved to provide more deployment space for other lines in the layer.

[0011] In one embodiment, the circuit board also includes at least one first inner layer, the first inner layer is located between two adjacent layers corresponding to the surface layers, and the first inner layer includes a second anti-pad; the outer contour of the second anti-pad includes a vertical projection surface of the first via on the first inner layer and a vertical projection surface of the second via on the first inner layer.

[0012] In this embodiment, by providing an anti-pad in the first inner layer 3, whose outer contour includes the vertical projection surface of the first via 12a and the vertical projection surface of the second via 12b on the inner layer, the signal delay problem caused by inconsistent reference of the signal line pair is avoided, thereby ensuring the signal transmission quality of the signal line pair.

[0013] In one embodiment, the second anti-pad is elliptical in shape.

[0014] In the present application, the shape of the second anti-pad is set to an ellipse, which can ensure that the reference layer of the inner layer part of the first signal line is consistent with the reference layer of the inner layer part of the second signal line, thereby reducing the signal delay of the signal line pair during the signal transmission process.

[0015] In one embodiment, the circuit board also includes a second inner layer, which is located between the adjacent layers corresponding to the two surface layers, and the second inner layer includes the inner layer portion of the first signal line and the inner layer portion b2 of the second signal line b; the inner layer portion of the first signal line is connected to the first via, and the inner layer portion b2 of the second signal line b is connected to the second via.

[0016] In one embodiment, the first center connecting line is equal to the second center connecting line in length.

[0017] In this embodiment, the method of making the first center connection line and the second center connection line equal in length can be used to make the circuit board easier to manufacture and reduce the complexity of the manufacturing process.

[0018] In one embodiment, a wiring length of the second signal line on the circuit board is equal to a wiring length of the first signal line on the circuit board.

[0019] In this embodiment, considering that the lengths of the signal line pairs are not equal, resulting in unequal delays of different signal lines, and thus timing problems caused by the unequal delays, the wiring length of the second signal line on the circuit board is set equal to the wiring length of the first signal line on the circuit board to ensure the transmission quality of high-speed signals.

[0020] In one embodiment, the wiring length of the second signal line in the surface layer is equal to the wiring length of the first signal line in the surface layer.

[0021] In this embodiment, by making the wiring length of the second signal line in the inner layer equal to the wiring length of the first signal line in the inner layer, the consistency of the signal delay can be improved to a certain extent; at the same time, compared with the manufacturing process of making the wiring length of the second signal line on the circuit board equal to the wiring length of the first signal line on the circuit board, the process complexity of the circuit board during manufacturing is reduced.

[0022] In a second aspect, a server mainboard is provided, comprising the circuit board described in the first aspect.

[0023] It can be understood that the server mainboard provided above includes the circuit board described in the first aspect. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the circuit board described in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a conventional fanout method of BGA in the prior art;

[0025] Figure 2 It is a schematic diagram of the structure of via-in-pad in the prior art;

[0026] Figure 3 is a schematic diagram of the structure of the surface layer of a circuit board in one embodiment;

[0027] Figure 4 A diagram comparing the effects of the surface layer and the internal wiring layer in a circuit board in one embodiment;

[0028] Figure 5 A schematic diagram of the structure of adjacent layers of a surface layer in a circuit board in one embodiment;

[0029] Figure 6 is a schematic structural diagram of a first anti-pad in an embodiment;

[0030] Figure 7 A comparison diagram of the effects of the first anti-pad in one embodiment;

[0031] Figure 8 is a schematic structural diagram of the first inner layer in one embodiment;

[0032] Fig. 9 A comparison diagram of the effect of the second anti-pad in one embodiment;

[0033] Fig.10 is a schematic structural diagram of the second inner layer in one embodiment;

[0034] Fig.11 A comparison diagram of differential mode return loss simulation effects in one embodiment;

[0035] Fig.12 A comparison diagram of differential mode insertion loss simulation effects in one embodiment;

[0036] Fig.13 A comparison diagram of the effects of the power layer in a circuit board in one embodiment. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0043] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] In addition, the use of “based on” or “according to” is meant to be open and inclusive, because the process, step, calculation or other action “based on” or “according to” one or more stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond the stated ones.

[0045] Before explaining the embodiments of the present application in detail, some terms involved in the embodiments of the present application are first explained.

[0046] 1. BGA

[0047] Ball grid array (BGA) technology is a surface mount packaging technology used in integrated circuits. This technology is often used to permanently fix devices such as microprocessors. BGA packaging can provide more pins than other packages such as dual in-line packages or quad flat packages. The entire bottom surface of the device can be used as pins instead of only the periphery. It can also have a shorter average wire length than periphery-limited package types, so as to have better high-speed performance.

[0048] 2. Fanout

[0049] PCB fan-out refers to a process where a component pin is extended a short distance and then a via is drilled to end the process. This via is usually connected to other layers of the PCB.

[0050] 3. Neck mode

[0051] Neck mode specifically refers to a routing method that uses a smaller line width than the normal line width. Neck mode (where Neck means neck (thinner than the head and body), refers to the narrower section of the routing path) will be much thinner than the line width required by the stackup.

[0052] Due to the restrictions of the server motherboard on the number of circuit board layers, space, line length, power supply, etc., for the ball grid array package BGA, high-speed differential signal lines basically use two methods: fan-out and via-in-pad. Among them, Fanout specifically refers to fan-out drilling, that is, drilling short lines from the pad. At present, a common conventional Fanout method for ball grid array package BGA is to determine the center point of the BGA, and leave two wider channels in the middle of the BGA that intersect vertically at the center point for laying out multiple traces coming out from the inside. The BGA is divided into four quadrants by two wider channels that intersect vertically. The Fanout drilling direction of each quadrant can be referred to Figure 1 For the via-in-pad drilling method, please refer to Figure 2 As shown, the process cost of this drilling method increases by about 10%.

[0053] In the fan-out drilling method, for the situation where the outlet direction of the high-speed differential signal line is perpendicular to the center line connecting the two pads, based on Figure 1 From the Fanout punching direction shown in FIG, it can be seen that the arrangement of the vias and pads on the surface layer 1 of the circuit board is as follows: the two vias are located on the same side of the center line of the two pads. In this arrangement, in order to reduce signal interference, the routing of high-speed differential signal lines cannot pass through the pairs of vias. Therefore, the routing of high-speed differential signal lines will occupy too much space, increasing the risk of signal crosstalk and loss.

[0054] Based on the above technical background and the problems existing in the prior art, Figure 3 An embodiment of the present application provides a circuit board, which includes: a surface layer 1, the surface layer 1 includes a first pad 11a, a second pad 11b, a first via 12a and a second via 12b, the first pad 11a and the first via 12a are connected through a surface portion a1 of a first signal line a, the second pad 11b and the second via 12b are connected through a surface portion b1 of a second signal line b, the arrangement direction of the first via 12a and the second via 12b is parallel to the outlet direction of the first signal line a and the second signal line b, the arrangement direction of the first pad 11a and the second pad 11b is perpendicular to the outlet direction of the first signal line a and the second signal line b, and the first center line 12ab of the first via 12a and the second via 12b intersects with the second center line 11ab of the first pad 11a and the second pad 11b.

[0055] Optionally, the first signal line a and the second signal line b are a signal line pair, which is used to transmit a group of signals. Further, the first signal line a and the second signal line b are a high-speed differential signal line pair.

[0056] In a possible implementation, there is a BGA region in the surface layer 1, and the area of ​​the BGA region in the surface layer 1 is less than or equal to the area of ​​the surface layer 1. The first pad 11a, the second pad 11b, the first via 12a, the second via 12b, the first signal line a, the first signal line a, and the second signal line b are all deployed in the BGA region.

[0057] For example, refer to Figure 4 , provides a comparison effect diagram; among them, Figure 4 (a) shows the arrangement of vias and pads in the BGA area of ​​the circuit board surface layer 1 of the embodiment of the present application. Figure 4 (b) shows the arrangement of vias and pads in the BGA area of ​​the circuit board surface layer 1 in the prior art. Figure 4 (c) shows that Figure 4 Based on the arrangement shown in (a), the arrangement of signal line pairs in the BGA area of ​​any routing layer of the circuit board, Figure 4 (d) shows that Figure 4 Based on the arrangement shown in (b), the arrangement of signal line pairs of any routing layer in the BGA area of ​​the circuit board in the prior art. Figure 4 (c) and Figure 4 By comparison with (b), it can be seen that in the same BGA area, the arrangement of vias and pads in the BGA area of ​​the circuit board surface layer 1 of the embodiment of the present application allows more signal line pairs to be accommodated in any routing layer, and the neck mode routing of each pair of signal lines is shorter. Neck mode refers to a routing method in which the routing line width is smaller than the normal line width.

[0058] In one embodiment, the first center line 12ab and the second center line 11ab are equal in length.

[0059] In practical applications, the first center line 12ab and the second center line 11ab are equal in length, which can be understood as the center of the first pad 11a, the center of the second pad 11b, the center of the first via 12a, and the center of the second via 12b are located at the four corners of the square. This is easier to achieve during the production of the circuit board and reduces the complexity of the production process.

[0060] In this embodiment, the outlet direction of the first signal line a and the second signal line b can be understood as the line direction of the first signal line a and the second signal line b at the boundary of the BGA area. Furthermore, the outlet position of the first signal line a and the second signal line b is not limited to the surface layer 1 of the circuit board, and can be in other routing layers. In the case where the outlet position of the first signal line a and the second signal line b is located in other routing layers, the appearance direction of the first signal line a and the second signal line b can be understood as the line direction of the BGA area at the boundary of the vertical projection surface of other routing layers.

[0061] In the BGA area routing layout, the signal line is divided into two types of outlets: left and right outlets and top and bottom outlets. Since the outlet directions of left and right outlets and top and bottom outlets are different, in the embodiment of the present application, for both left and right outlets and top and bottom outlets, their outlet directions are perpendicular to the arrangement direction of the pads to which they are connected.

[0062] In the above-mentioned circuit board, the arrangement direction of the first via 12a and the second via 12b included in the surface layer 1 is parallel to the outlet direction of the first signal line a and the second signal line b, and the arrangement direction of the first pad 11a and the second pad 11b is perpendicular to the outlet direction, and the first center line 12ab of the first via 12a and the second via 12b intersects with the second center line 11ab of the first pad 11a and the second pad 11b. Compared with the prior art, the present application reduces the routing length of the signal line pair in the BGA area, can effectively avoid the problem of interpenetration of the signal line pair, thereby reducing the risk of signal crosstalk, and at the same time helps to reduce the overall link loss of the signal line pair. In addition, it can also reduce the routing space occupied by the signal line pair, so that more signal line pairs can be accommodated in the same size BGA area.

[0063] In one embodiment, in order to ensure the consistency of the reference surface of the surface layer portion a1 of the first signal line a and the surface layer portion b1 of the second signal line b, the reference Figure 5 The circuit board also includes an adjacent layer 2 of the surface layer 1, and the adjacent layer 2 of the surface layer 1 includes a first anti-pad 21. The outer contour of the first anti-pad 21 includes a vertical projection surface of the first pad 11a on the adjacent layer 2, a vertical projection surface of the second pad 11b on the adjacent layer 2, a vertical projection surface of the first via 12a on the adjacent layer 2, and a vertical projection surface of the second via 12b on the adjacent layer 2.

[0064] Exemplarily, the shape of the first anti-pad 21 can be determined by connecting the outer contour of the vertical projection surface of the first pad 11a on the adjacent layer 2, the outer contour of the vertical projection surface of the second pad 11b on the adjacent layer 2, the outer contour of the vertical projection surface of the first via 12a on the adjacent layer 2, and the outer contour of the vertical projection surface of the second via 12b on the adjacent layer 2 through an arc. For example, the shape of the first anti-pad 21 can be a circle.

[0065] In the present embodiment, by setting an anti-pad at the adjacent layer 2 of the surface layer 1 of the circuit board, the outer contour of which includes the vertical projection surface of the first solder pad 11a on the adjacent layer 2, the vertical projection surface of the second solder pad 11b on the adjacent layer 2, the vertical projection surface of the first via 12a on the adjacent layer 2, and the vertical projection surface of the second via 12b on the adjacent layer 2, the signal delay problem caused by inconsistent reference of the signal line pair of the surface layer 1 is avoided, thereby ensuring the signal transmission quality of the signal line pair.

[0066] In one embodiment, referring to Figure 6 , the shape of the first anti-pad 21 is a plum blossom shape.

[0067] It should be noted that the shape of the first anti-pad 21 is not limited to the plum blossom shape, but can also be a circle as mentioned above, or a rectangle, etc. No matter what shape the first anti-pad 21 is determined to be, its outer contour includes the vertical projection surface of the first pad 11a on the adjacent layer 2, the vertical projection surface of the second pad 11b on the adjacent layer 2, the vertical projection surface of the first via 12a on the adjacent layer 2, and the vertical projection surface of the second via 12b on the adjacent layer 2. The shape of the anti-pad can be adjusted according to actual application requirements, and the embodiments of the present application do not impose any limitations on this.

[0068] For example, refer to Figure 7 , is a comparison diagram of the effects of the first anti-pad 21 in the same area. Figure 7 (a) shows that Figure 4 (a) shows an arrangement of vias and pads in the BGA region of the circuit board surface layer 1, and the shape of the first anti-pad 21 is a plum blossom effect diagram; Figure 7 (b) shows the Figure 4 (b) shows an arrangement of vias and pads in the BGA region of the circuit board surface layer 1, and the shape of the first anti-pad 21 is a horizontal elliptical effect diagram. Figure 7 (a) and Figure 7 From the comparison with (b), it can be seen that the first anti-pad 21 provided in the embodiment of the present application can ensure that the reference layer of the surface part a1 of the first signal line a and the surface part b1 of the second signal line b remain consistent after being hollowed out, thereby reducing the consistency of the signal delay of the signal line pair during the signal transmission process.

[0069] In this embodiment, the anti-pad in the adjacent layer 2 of the surface layer 1 is determined to be a plum blossom shape, which avoids the signal delay problem of the signal line pair in the surface layer 1 due to inconsistent references and ensures the signal transmission quality of the signal line pair. At the same time, the area occupied by the anti-pad in the adjacent layer 2 of the surface layer 1 is saved to provide more deployment space for other lines in the layer.

[0070] In one embodiment, referring to Figure 8 The circuit board also includes at least one first inner layer 3, the first inner layer 3 is located between the adjacent layers 2 corresponding to the two surface layers 1, and the first inner layer 3 includes a second anti-pad 31; the outer contour of the second anti-pad 31 includes a vertical projection surface of the first via 12a on the first inner layer 3 and a vertical projection surface of the second via 12b on the first inner layer 3.

[0071] It should be noted that the first inner layer 3 specifically refers to a layer of the inner layers of the circuit board other than the adjacent layer 2 of the surface layer 1, which has no signal line pair connected to the first via 12a and the second via 12b.

[0072] In one implementation, the shape of the second anti-pad 31 can be determined by connecting the vertical projection surface of the first via 12a on the inner layer and the vertical projection surface of the second via 12b on the inner layer by an arc line. For example, the shape of the first anti-pad 21 is a gourd shape, and the upper and lower areas of the gourd shape are the same size.

[0073] In this embodiment, by providing an anti-pad in the first inner layer 3, whose outer contour includes the vertical projection surface of the first via 12a and the vertical projection surface of the second via 12b on the inner layer, the signal delay problem caused by inconsistent reference of the signal line pair is avoided, thereby ensuring the signal transmission quality of the signal line pair.

[0074] In a preferred embodiment, referring to Figure 8 , the shape of the second anti-pad 31 is elliptical.

[0075] It should be noted that the shape of the second anti-pad 31 is not limited to an ellipse, but can also be a circle as mentioned above, or a rectangle, etc. No matter what shape the second anti-pad 31 is determined to be, its outer contour includes the vertical projection surface of the first via 12a on the inner layer and the vertical projection surface of the second via 12b on the inner layer. Its shape can be adjusted according to actual application requirements, and the embodiments of the present application do not impose any limitations on this.

[0076] For example, refer to Fig. 9 , is a comparison diagram of the effects of the second anti-pad 31 in the same area. Fig. 9 (a) shows that Figure 4 (a) shows an arrangement of vias and pads in the BGA region of the circuit board surface layer 1, and the shape of the second anti-pad 31 is a longitudinal elliptical effect diagram; Fig. 9 (b) shows the Figure 4 (b) shows an arrangement of vias and pads in the BGA region of the circuit board surface layer 1, and the shape of the first anti-pad 21 is a horizontal elliptical effect diagram. Fig. 9 (a) and Fig. 9 By comparison with (b), it can be seen that the shape of the second anti-pad 31 provided in the embodiment of the present application is set to an elliptical shape, which can ensure that the reference layer of the inner layer part a2 of the first signal line a is consistent with the inner layer part of the second signal line b, thereby reducing the signal delay of the signal line pair during the signal transmission process.

[0077] In one embodiment, referring to Fig.10 The circuit board also includes a second inner layer 4, which is located between the adjacent layers 2 corresponding to the two surface layers 1. The second inner layer 4 includes the inner layer portion a2 of the first signal line a and the inner layer portion b2 of the second signal line b; the inner layer portion a2 of the first signal line a is connected to the first via 12a, and the inner layer portion b2 of the second signal line b is connected to the second via 12b.

[0078] Combination Figure 4 As shown in the comparison effect diagram, the second inner layer 4 included in the circuit board of the embodiment of the present application can accommodate more signal line pairs, and the neck mode routing of each pair of signal lines is shorter. Among them, the neck mode refers to a routing method in which the routing line width is smaller than the normal line width.

[0079] The embodiment of the present application takes into account that the lengths of the signal line pairs are unequal, resulting in unequal delays of different signal lines, and thus timing problems caused by the unequal delays. Therefore, in order to ensure the transmission quality of high-speed signals, the wiring length of the second signal line b on the circuit board in the embodiment of the present application is equal to the wiring length of the first signal line a on the circuit board.

[0080] In one implementation, it is difficult to realize a manufacturing process that makes the lengths of signal lines in the circuit board equal. Preferably, the wiring length of the second signal line b in the embodiment of the present application is equal to the wiring length of the first signal line a in the surface layer 1. This can reduce the process complexity of the circuit board during manufacturing and improve the consistency of signal delay to a certain extent.

[0081] In another implementation, considering that the wiring length of the second signal line b on the surface layer 1 is generally shorter than the wiring length of the first signal line a on the surface layer 1, in order to further reduce the unequal delay caused by the inconsistent wiring lengths of the first signal line a and the second signal line b, and the timing problems caused by the unequal delays. Preferably, the wiring length of the second signal line b in the inner layer of the embodiment of the present application is equal to the wiring length of the first signal line a in the inner layer. It can reduce the process complexity of the circuit board during the manufacturing process, and at the same time improve the consistency of the signal delay to a certain extent.

[0082] In one implementation, referring to Table 1, the present application embodiment provides a layer structure description of a circuit board, taking a 14-layer symmetrical stacking structure as an example, as follows:

[0083] Table 1

[0084]

[0085]

[0086] It should be noted that oz means the thickness of copper foil; plating means electroplating; Signal means signal; Plane means negative. PP refers to the semi-sintered sheet, which is placed between the upper and lower layers of adjacent copper foils, acting as a barrier and bonding the two copper layers; CORE is the substrate, which is usually in the inner layer.

[0087] Reference Fig.11 , provides a comparison diagram of differential mode return loss simulation effects, where the horizontal axis represents frequency and the vertical axis represents differential mode return loss; Fig.10 The curve Fanout1 in the figure corresponds to the differential mode return loss simulation curve of the circuit board provided by the prior art when transmitting high-speed signals; the curve Fanout2 corresponds to the differential mode return loss simulation effect curve of the circuit board provided by the embodiment of the present application when transmitting high-speed signals. By comparing the curve Fanout1 and the curve Fanout2, it can be seen that the circuit board provided by the embodiment of the present application can optimize the differential mode return loss from -16dB of the prior art to below -20dB at a frequency of 16GHz. Numerically speaking, the reflected signal energy is reduced from about 14% to 10%, which improves the differential mode return loss, which is a significant improvement.

[0088] Reference Fig.12 , provides a comparison diagram of differential mode insertion loss simulation effects, where the horizontal axis represents frequency and the vertical axis represents differential mode insertion loss; Fig.11 The curve Fanout1 in the figure corresponds to the differential mode insertion loss simulation curve of the circuit board provided by the prior art when transmitting high-speed signals; the curve Fanout2 corresponds to the differential mode insertion loss simulation effect curve of the circuit board provided by the embodiment of the present application when transmitting high-speed signals. By comparing the curve Fanout1 and the curve Fanout2, it can be seen that the circuit board provided by the embodiment of the present application better meets the signal integrity requirements and can effectively enhance the signal transmission capability.

[0089] In addition, refer to Fig.13 , is a comparison chart of the effects of the power layer in a circuit board. Specifically, Fig.13 (a) is a power region 131 in a power layer of a circuit board provided in an embodiment of the present application; Fig.13(b) is a power supply area 141 in a power supply layer of a circuit board in the prior art. Fig.13 (a) and Fig.13 The gray areas in (b) are all copper-covered areas of the power layer. In practical applications, for the same copper width, Fig.13 The effective width of (b) is 40.2mil, Fig.13 The effective width of (a) is 53.6 mil. If 40 mil can be used to carry a current of 1A, then Fig.13 The circuit in (a) can carry a current of 1.34A.

[0090] In one embodiment, the present application also provides a server mainboard, including the above-mentioned circuit board.

[0091] It should be noted that the specific limitations on the server motherboard can be found in the above limitations on the circuit board, which will not be repeated here.

[0092] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0094] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A circuit board, characterized in that: include: A surface layer, wherein the surface layer includes a first pad, a second pad, a first via hole, and a second via hole, the first pad and the first via hole are connected via a surface layer portion of a first signal line, the second pad and the second via hole are connected via a surface layer portion of a second signal line, the first via hole and the second via hole are arranged in a direction parallel to an outlet direction of the first signal line and the second signal line, the first pad and the second pad are arranged in a direction perpendicular to the outlet direction, and a first center line connecting the first via hole and the second via hole intersects a second center line connecting the first pad and the second pad; The first center line and the second center line are of equal length; the surface layer further includes a ball grid array BGA area, the area of ​​the BGA area is smaller than the area of ​​the surface layer, and the first pad, the second pad, the first via, the second via, the first signal line, and the second signal line are all deployed in the BGA area; The first signal line and the second signal line are a signal line pair for transmitting a group of signals. The outlet direction of the first signal line and the second signal line is the line direction of the first signal line and the second signal line at the boundary of the BGA area. The outlet modes of the first signal line and the second signal line are divided into two outlet modes: left-right outlet and top-bottom outlet. The outlet positions of the first signal line and the second signal line are not limited to the surface layer of the circuit board, but also include other routing layers. The wiring length of the second signal line on the surface layer is equal to the wiring length of the first signal line on the surface layer. The wiring length of the second signal line on the inner layer is equal to the wiring length of the first signal line on the inner layer. The circuit board also includes an adjacent layer to the surface layer, and the adjacent layer to the surface layer includes a first anti-pad, and the outer contour of the first anti-pad includes a vertical projection surface of the first pad on the adjacent layer, a vertical projection surface of the second pad on the adjacent layer, a vertical projection surface of the first via on the adjacent layer, and a vertical projection surface of the second via on the adjacent layer. The shape of the first anti-pad is determined by transitionally connecting the outer contour of the vertical projection surface of the first pad on the adjacent layer, the outer contour of the vertical projection surface of the second pad on the adjacent layer, the outer contour of the vertical projection surface of the first via on the adjacent layer, and the outer contour of the vertical projection surface of the second via on the adjacent layer through an arc line.

2. The circuit board according to claim 1, characterized in that: The first anti-pad is in a plum blossom shape.

3. The circuit board according to claim 1, characterized in that: The first anti-pad is in a gourd shape, and the upper and lower areas of the gourd shape are the same.

4. The circuit board according to claim 1, characterized in that: The circuit board also includes at least one first inner layer, the first inner layer is located between adjacent layers corresponding to the two surface layers, and the first inner layer includes a second anti-pad; the outer contour of the second anti-pad includes a vertical projection surface of the first via on the first inner layer and a vertical projection surface of the second via on the first inner layer.

5. The circuit board according to claim 4, characterized in that: The second anti-pad is in an elliptical shape.

6. The circuit board according to claim 4, characterized in that: The second anti-pad is circular in shape.

7. The circuit board according to claim 4, characterized in that: The first inner layer is a layer of other inner layers of the circuit board except the adjacent layers of the surface layer, which has no signal line pair connected to the first via hole and the second via hole.

8. The circuit board according to claim 1, characterized in that: The circuit board also includes a second inner layer, which is located between the adjacent layers corresponding to the two surface layers, and the second inner layer includes the inner layer portion of the first signal line and the inner layer portion of the second signal line; the inner layer portion of the first signal line is connected to the first via, and the inner layer portion of the second signal line is connected to the second via.

9. The circuit board according to any one of claims 1 to 8, characterized in that: A wiring length of the second signal line on the circuit board is equal to a wiring length of the first signal line on the circuit board.

10. A server motherboard, characterized in that: Comprising a circuit board as described in any one of claims 1-9.

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