3D storage device and reading method thereof

Abstract

Disclosed are a 3D memory device and a reading method thereof. The 3D memory device includes a plurality of memory cell strings, each memory cell string includes a plurality of memory cells, the topmost memory cell of each memory cell string is connected to a top selection tube, the top selection tube is connected to a bit line, and the bottommost memory cell of the memory cell string is connected to a bottom selection tube. The reading method includes: programming a plurality of memory cells of a memory cell string in sequence according to a programming sequence; when performing a reading operation on a memory cell, applying different bit line voltages to the memory cell string according to the programming sequence of the memory cell. The present application adjusts the application of different bit line voltages to the memory cell string according to the programming sequence of the memory cell, and the memory cell programmed first adopts a larger bit line voltage when reading, increasing the current on the memory cell string, thereby reducing the Vt forward drift and widening caused by the BPD effect to increase the read window margin and reduce the influence of read interference.

Description

[0001] This application is a divisional application of the Chinese patent application with the application date of January 6, 2021, application number 202110013950.8, and invention name “3D storage device and its reading method”. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional storage device and a reading method thereof. Background Art

[0003] In recent years, the development of flash memory devices has been particularly rapid. The main feature of flash memory devices is that they can maintain stored information for a long time without power supply, and have the advantages of high integration, fast access speed, easy erasure and rewrite, etc. Therefore, they have been widely used in many fields such as microcomputers and automatic control. In order to further improve the bit density of flash memory devices and reduce the bit cost, three-dimensional flash memory device (3D NAND) technology has been rapidly developed. Figure 1a A circuit diagram showing a memory cell string of a 3D memory device, Figure 1b A schematic diagram showing the operating state of each memory cell during the programming process of a memory cell string. The memory cell string includes a plurality of memory cells (MC1-MCn), where n is an integer greater than or equal to 2. The topmost memory cell of each memory cell string is connected to a top selection tube TSG, which is connected to a bit line, and the bottommost memory cell of the memory cell string is connected to a bottom selection tube BSG.

[0004] For the programming process of a 3D memory device, the general programming sequence is to start programming from the memory cell closest to the bottom selection tube and end from bottom to top to the memory cell closest to the top selection tube. This programming sequence can be called a typical programming sequence or a forward programming sequence.

[0005] See also Figure 1b, before programming the memory cell string, all memory cells are set to the erased state E. The memory cell MCn closest to the bottom selection tube is programmed first, at which time the other memory cells are in the erased state E, and the memory cell MCn is set to the programmed state P after being programmed. After all the memory cells on the memory cell string are programmed in sequence, the memory cells MC1-MCn are all set to the programmed state P. Due to the background pattern dependency (BPD) effect and the interference effect, the memory cells MC1-MCn may have slightly different threshold voltages (Vt). This will cause the distribution of the memory cell threshold voltage (i.e., the threshold voltage difference) to be widened. Increasing the threshold voltage difference between memory cells can reduce the read margin in a single-level cell or a multi-level cell, and can also have an adverse effect on the margin in-cycling and retention characteristics.

[0006] Figure 2 The threshold voltage distribution of the memory cell due to BPD is shown. The solid line represents the threshold voltage distribution of the memory cell MCn after it is first programmed, and the dotted line represents the threshold voltage distribution of the memory cell MCn after all the memory cells are forward programmed. When verifying and reading the memory cell programmed first, the change in the drain resistance causes a positive shift in the threshold voltage of the memory cell. The earlier the memory cell is programmed, the greater the threshold voltage shift caused by the BPD effect.

[0007] See also Figure 3a and Figure 3b In the reading process after the programming of the memory cell string is completed, when the selected memory cell is read, a read voltage Vread is applied to the word line connected to the selected memory cell, and a pass voltage Vread_pass is applied to the word line connected to other unselected memory cells. The BPD effect can be improved by increasing the pass voltage (Vread_pass) applied to the word line connected to other unselected memory cells, that is, applying an increased pass voltage (Vread_pass+△Vpass) to the word line connected to other unselected memory cells. Although the threshold voltage shift caused by the BPD effect is reduced (such as Figure 3b As shown in the figure), it will inevitably cause read disturb and increase the impact of read disturb. Summary of the invention

[0008] In view of the above problems, an object of the present invention is to provide a 3D memory device and a reading method thereof, which changes the bit line voltage when reading the memory cell according to the programming sequence of the memory cell to improve the threshold voltage shift caused by the BPD effect.

[0009] According to one aspect of the present invention, a method for reading a 3D memory device is provided, wherein the 3D memory device comprises a plurality of memory cell strings, each memory cell string comprises a plurality of memory cells, the topmost memory cell of each memory cell string is connected to a top selection tube, the top selection tube is connected to a bit line, and the bottommost memory cell of the memory cell string is connected to a bottom selection tube, comprising:

[0010] sequentially programming a plurality of memory cells of a memory cell string according to a programming order;

[0011] When a memory cell is read, different bit line voltages are applied to the memory cell string according to the programming sequence of the memory cell.

[0012] Preferably, the earlier the memory cell is in the programming sequence, the greater the bit line voltage applied to the memory cell string during the reading operation.

[0013] Preferably, the reading method also includes: dividing multiple memory cells of a memory cell string into a first memory group, a second memory group and a third memory group according to a programming order, wherein the first memory group is programmed first, the second memory group is programmed in the middle, and the third memory group is programmed last; when the memory cell selected by the reading operation is located in the first memory group, a first bit line voltage is applied to the memory cell string; when the memory cell selected by the reading operation is located in the second memory group, a second bit line voltage is applied to the memory cell string; when the memory cell selected by the reading operation is located in the third memory group, a third bit line voltage is applied to the memory cell string; the amplitudes of the first bit line voltage, the second bit line voltage and the third bit line voltage are different.

[0014] Preferably, the first bit line voltage is greater than the second bit line voltage, and the second bit line voltage is greater than the third bit line voltage.

[0015] Preferably, when the programming sequence is a forward programming sequence, the programming is performed sequentially from the memory cells adjacent to the bottom selection tube to the memory cells adjacent to the top selection tube.

[0016] Preferably, the closer the memory cell selected by the reading operation is to the bottom selection tube, the greater the bit line voltage applied to the memory cell string.

[0017] Preferably, when the programming sequence is a reverse programming sequence, the programming is performed sequentially from the memory cells adjacent to the top selection tube to the memory cells adjacent to the bottom selection tube.

[0018] Preferably, the closer the memory cell selected by the reading operation is to the top selection transistor, the greater the bit line voltage applied to the memory cell string.

[0019] According to another aspect of the present invention, a 3D memory device is provided, comprising: a memory cell array, comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells, the topmost memory cell of each memory cell string being connected to a top selection tube, the top selection tube being connected to a bit line, and the bottommost memory cell of the memory cell string being connected to a bottom selection tube; a controller, electrically connected to the memory cell array, and used to sequentially program a plurality of memory cells of a memory cell string according to a programming order; when a read operation is performed on a memory cell, different bit line voltages are applied to the memory cell string according to the programming order of the memory cell.

[0020] Preferably, the earlier the memory cell is in the programming sequence, the greater the bit line voltage applied to the memory cell string by the controller when performing a read operation on the memory cell.

[0021] Preferably, the controller is further used for:

[0022] According to the programming order of multiple memory cells in a memory cell string, the multiple memory cells are divided into a first memory group, a second memory group and a third memory group, wherein the first memory group is programmed first, the second memory group is programmed in the middle, and the third memory group is programmed last; when the memory cell selected by the read operation is located in the first memory group, a first bit line voltage is applied to the memory cell string;

[0023] When the memory cell selected by the read operation is located in the second memory group, applying a second bit line voltage to the memory cell string;

[0024] When the memory cell selected by the read operation is located in the third memory group, applying a third bit line voltage to the memory cell string;

[0025] The first bit line voltage, the second bit line voltage, and the third bit line voltage have different amplitudes.

[0026] Preferably, the first bit line voltage is greater than the second bit line voltage, and the second bit line voltage is greater than the third bit line voltage.

[0027] Preferably, when the programming sequence is a forward programming sequence, the controller programs sequentially from the storage cells adjacent to the bottom selection tube to the storage cells adjacent to the top selection tube.

[0028] Preferably, the closer the memory cell selected by the reading operation is to the bottom selection tube, the greater the bit line voltage applied by the controller to the memory cell string.

[0029] Preferably, when the programming sequence is a reverse programming sequence, the controller programs sequentially from the storage unit adjacent to the top selection tube to the storage unit adjacent to the bottom selection tube.

[0030] Preferably, the closer the memory cell selected by the reading operation is to the top selection tube, the greater the bit line voltage applied by the controller to the memory cell string.

[0031] The 3D memory device and the reading method thereof provided by the present invention, when performing a reading operation on a memory cell, apply different bit line voltages to the memory cell string according to the programming order of the memory cell. The earlier the programming order of the memory cell, the larger the bit line voltage is applied to the memory cell string when performing a reading operation on the memory cell, increasing the current on the memory cell string, thereby reducing the Vt forward drift and widening caused by the BPD effect to increase the read window margin and reduce the influence of read disturb. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1a and Figure 1b A circuit diagram of a memory cell string of a 3D memory device and a schematic diagram showing an operation state of each memory cell during a programming process of the memory cell string are respectively shown;

[0034] Figure 2 shows the threshold voltage distribution of memory cells due to BPD;

[0035] Figure 3a and 3b A schematic diagram of a memory cell string read operation and a threshold voltage distribution of a memory cell are shown respectively;

[0036] Figure 4 A flow chart showing a method for reading a 3D memory device according to an embodiment of the present invention is shown;

[0037] Figure 5 Show Figure 4 The flowchart of step S20 shown;

[0038] Figure 6a and Figure 6b Schematic diagrams showing forward programming and reverse programming and post-reading operations of a memory cell string according to an embodiment of the present invention respectively;

[0039] Figure 7 A schematic diagram showing a characteristic curve of a 3D memory device under a read operation;

[0040] Figure 8 A schematic structural diagram of a 3D memory device provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0042] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0043] The term “above” as used in the present invention refers to being above the plane of the substrate, and may refer to direct contact between materials or to a spaced arrangement.

[0044] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the present invention, such as the structure, materials, dimensions, processing techniques and technologies of the device are described below to facilitate a clearer understanding of the present invention. However, as can be appreciated by those skilled in the art, the present invention may be implemented without following these specific details.

[0045] The present invention may be embodied in various forms, some examples of which will be described below.

[0046] In a specific application, the memory cell array is composed of memory cell strings arranged in an array, wherein the memory cells in each row in each layer are connected to the same word line (WL), and the memory cell strings in each column are connected to the same bit line (BL). By selecting the corresponding word line and bit line in the memory cell array, the corresponding memory cell can be selected.

[0047] Figure 4 FIG. 2 is a flow chart showing a method for reading a 3D memory device according to an embodiment of the present invention. Figure 4 As shown, the reading method includes the following steps.

[0048] In step S10 , a plurality of memory cells of a memory cell string are programmed sequentially according to a programming order.

[0049] In this embodiment, the forward programming sequence is to start programming from the storage cell closest to the bottom selection tube BSG and end from bottom to top to the storage cell closest to the top selection tube TSG, that is, to program from the storage cell adjacent to the bottom selection tube BSG to the storage cell adjacent to the top selection tube TSG in sequence. The reverse programming sequence is to start programming from the storage cell closest to the top selection tube TSG and end from top to bottom to the storage cell closest to the bottom selection tube BSG, that is, to program from the storage cell adjacent to the top selection tube TSG to the storage cell adjacent to the bottom selection tube BSG in sequence.

[0050] In step S20, when a read operation is performed on a memory cell, different bit line voltages are applied to the memory cell string according to the programming sequence of the memory cell.

[0051] In this embodiment, the earlier the memory cell is in the programming sequence, the greater the bit line voltage applied to the memory cell string during the read operation. When performing a read operation on a selected memory cell, a read voltage Vread is applied to the word line connected to the selected memory cell, and a pass voltage Vread_pass is applied to the word lines connected to other unselected memory cells.

[0052] In a preferred embodiment, step S20 includes steps S21 to S24, see Figure 5 .

[0053] In step S21, multiple memory cells of a memory cell string are divided into a first memory group, a second memory group and a third memory group according to a programming order, the first memory group is programmed first, the third memory group is programmed last, and the second memory group is programmed between the first and third memory groups.

[0054] In this embodiment, when the programming sequence is a forward programming sequence, the first storage group is close to the bottom selection tube BSG, and the third storage group is close to the top selection tube TSG. The closer the storage cell selected by the read operation is to the bottom selection tube BSG, the greater the bit line voltage applied to the storage cell string. Figure 6a As shown in the example, the first storage group includes the n-1th storage cell MC(n-1) and the nth storage cell MCn; the second storage group includes the third storage cell MC3-n-2th storage cell MC(n-2); and the third storage group includes the first storage cell MC1 and the second storage cell MC2.

[0055] When the programming sequence is the reverse programming sequence, the first storage group is close to the top selection tube TSG, and the third storage group is close to the bottom selection tube BSG. The closer the memory cell selected by the read operation is to the TSG top selection tube, the greater the bit line voltage applied to the memory cell string. Figure 6b As shown in the example, the first storage group includes the first storage cell MC1 and the second storage cell MC2; the second storage group includes the third storage cell MC3 to the n-2th storage cell MC(n-2); and the third storage group includes the n-1th storage cell MC(n-1) and the nth storage cell MCn.

[0056] In step S22, when the memory cell selected by the read operation is located in the first memory group, a first bit line voltage is applied to the memory cell string.

[0057] In step S23, when the memory cell selected by the read operation is located in the second memory group, a second bit line voltage is applied to the memory cell string.

[0058] In step S24, when the memory cell selected by the read operation is located in the third memory group, a third bit line voltage is applied to the memory cell string.

[0059] In this embodiment, the first bit line voltage VBL1, the second bit line voltage VBL2 and the third bit line voltage VBL3 have different amplitudes. Since the first storage group is programmed first and the third storage group is programmed last, the first bit line voltage VBL1 is greater than the second bit line voltage VBL2, and the second bit line voltage VBL2 is greater than the third bit line voltage VBL3, that is, VBL1>VBL2>VBL3.

[0060] In a preferred embodiment, the third bit line voltage VBL3 is the same as the bit line voltage VBL during program verification.

[0061] The reading method of the 3D memory device provided by the embodiment of the present invention applies different bit line voltages to the memory cell string according to the programming order of the memory cell when performing a reading operation on a memory cell. The earlier the programming order of the memory cell, the larger the bit line voltage is applied to the memory cell string when performing a reading operation on the memory cell, increasing the current on the memory cell string, thereby reducing the Vt forward drift and widening caused by the BPD effect to increase the read window margin and reduce the influence of read disturb.

[0062] Figure 8 The 3D memory device provided by an embodiment of the present invention includes a memory cell array 110 and a controller 120 , wherein the controller 120 is used to execute the above reading method.

[0063] Among them, the memory cell array 110 includes multiple memory cell strings, each memory cell string includes multiple memory cells MC1-MCn, the top memory cell of each memory cell string is connected to the top selection tube TSG, the top selection tube is connected to the bit line BL, and the bottom memory cell of the memory cell string is connected to the bottom selection tube.

[0064] The controller 120 is electrically connected to the memory cell array 110 and is used to program multiple memory cells of a memory cell string in sequence according to a programming order; when a memory cell is read, different bit line voltages are applied to the memory cell string according to the programming order of the memory cell.

[0065] In this embodiment, the forward programming sequence is to start programming from the storage cell closest to the bottom selection tube BSG and end from bottom to top to the storage cell closest to the top selection tube TSG, that is, to program from the storage cell adjacent to the bottom selection tube BSG to the storage cell adjacent to the top selection tube TSG in sequence. The reverse programming sequence is to start programming from the storage cell closest to the top selection tube TSG and end from top to bottom to the storage cell closest to the bottom selection tube BSG, that is, to program from the storage cell adjacent to the top selection tube TSG to the storage cell adjacent to the bottom selection tube BSG in sequence.

[0066] In this embodiment, the earlier the programming order of the memory cell is, the greater the bit line voltage applied to the memory cell string by the controller 120 when performing a read operation on the memory cell. When performing a read operation on a selected memory cell, a read voltage Vread is applied to the word line connected to the selected memory cell, and a pass voltage Vread_pass is applied to the word lines connected to other unselected memory cells.

[0067] In a preferred embodiment, the controller 120 is also used to divide multiple memory cells into a first storage group, a second storage group and a third storage group according to the programming order of multiple memory cells in a memory cell string, wherein the first storage group is programmed first, the second storage group is programmed in the middle, and the third storage group is programmed last; when the memory cell selected by the read operation is located in the first storage group, a first bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the second storage group, a second bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the third storage group, a third bit line voltage is applied to the memory cell string; the amplitudes of the first bit line voltage, the second bit line voltage and the third bit line voltage are different.

[0068] In this embodiment, when the programming sequence is a forward programming sequence, the first storage group is close to the bottom selection tube BSG, and the third storage group is close to the top selection tube TSG. The closer the storage cell selected by the read operation is to the bottom selection tube BSG, the greater the bit line voltage applied to the storage cell string. Figure 6a As shown in the example, the first storage group includes the n-1th storage cell MC(n-1) and the nth storage cell MCn; the second storage group includes the third storage cell MC3-n-2th storage cell MC(n-2); and the third storage group includes the first storage cell MC1 and the second storage cell MC2.

[0069] When the programming sequence is the reverse programming sequence, the first storage group is close to the top selection tube TSG, and the third storage group is close to the bottom selection tube BSG. The closer the memory cell selected by the read operation is to the TSG top selection tube, the greater the bit line voltage applied to the memory cell string. Figure 6bAs shown in the example, the first storage group includes the first storage cell MC1 and the second storage cell MC2; the second storage group includes the third storage cell MC3 to the n-2th storage cell MC(n-2); and the third storage group includes the n-1th storage cell MC(n-1) and the nth storage cell MCn.

[0070] In this embodiment, the first bit line voltage VBL1, the second bit line voltage VBL2 and the third bit line voltage VBL3 have different amplitudes. Since the first storage group is programmed first and the third storage group is programmed last, the first bit line voltage VBL1 is greater than the second bit line voltage VBL2, and the second bit line voltage VBL2 is greater than the third bit line voltage VBL3, that is, VBL1>VBL2>VBL3.

[0071] In a preferred embodiment, the third bit line voltage VBL3 is the same as the bit line voltage VBL during program verification.

[0072] The 3D memory device provided by the embodiment of the present invention applies different bit line voltages to the memory cell string according to the programming order of the memory cell when performing a read operation on a memory cell. The earlier the programming order of the memory cell, the larger the bit line voltage is applied to the memory cell string when performing a read operation on the memory cell, increasing the current on the memory cell string, thereby reducing the Vt forward drift and widening caused by the BPD effect to increase the read window margin and reduce the influence of read disturbance.

[0073] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, it should be understood by those skilled in the art that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0074] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for reading a 3D memory device, wherein the 3D memory device comprises a plurality of memory cell strings, each memory cell string comprises a plurality of memory cells, the top memory cell of each memory cell string is connected to a top selection tube, the top selection tube is connected to a bit line, and the bottom memory cell of the memory cell string is connected to a bottom selection tube, wherein: include: sequentially programming a plurality of memory cells of a memory cell string according to a programming order; Dividing a plurality of memory cells of a memory cell string into a plurality of memory groups according to a programming sequence; the number of the memory groups is less than or equal to the number of memory cells in a memory cell string; When a memory cell in a memory cell string is read, different bit line voltages are applied to the memory cell string according to a programming sequence of a memory group to which the memory cell belongs; The earlier the programming sequence of the storage group to which the storage cell belongs is, the greater the bit line voltage applied to the storage cell string during the reading operation.

2. The reading method according to claim 1, characterized in that: The method of dividing a plurality of memory cells of a memory cell string into a plurality of memory groups according to a programming order comprises: According to the programming order of multiple memory cells in a memory cell string, the multiple memory cells are divided into a first memory group, a second memory group and a third memory group, wherein the first memory group is programmed first, the second memory group is programmed in the middle, and the third memory group is programmed last; when the memory cell selected by the read operation is located in the first memory group, a first bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the second memory group, a second bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the third memory group, a third bit line voltage is applied to the memory cell string.

3. The reading method according to claim 2, characterized in that: The third bit line voltage is the same as the bit line voltage during program verification.

4. The reading method according to claim 1, characterized in that: The programming sequence is a forward programming sequence, and the plurality of memory cells of a memory cell string are programmed sequentially according to the programming sequence, including: Programming is performed sequentially from a memory cell adjacent to a bottom selection tube of a memory cell string to a memory cell adjacent to a top selection tube; When a read operation is performed on a memory cell in a memory cell string, the closer the memory group to which the memory cell selected by the read operation belongs is to the bottom selection tube, the greater the bit line voltage applied to the memory cell string.

5. The reading method according to claim 1, characterized in that: The programming sequence is a reverse programming sequence, and the plurality of memory cells of a memory cell string are programmed sequentially according to the programming sequence, including: Programming is performed sequentially from a memory cell adjacent to a top selection tube to a memory cell adjacent to a bottom selection tube in a memory cell string; When a read operation is performed on a memory cell in a memory cell string, the closer the memory group to which the memory cell selected by the read operation belongs is to the top selection tube, the greater the bit line voltage applied to the memory cell string.

6. A 3D memory device, characterized in that: include: A memory cell array, comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells, the top memory cell of each memory cell string being connected to a top selection tube, the top selection tube being connected to a bit line, and the bottom memory cell of the memory cell string being connected to a bottom selection tube; A controller, electrically connected to the memory cell array, for sequentially programming a plurality of memory cells of a memory cell string according to a programming sequence; Dividing a plurality of memory cells of a memory cell string into a plurality of memory groups according to a programming sequence; the number of the memory groups is less than or equal to the number of memory cells in a memory cell string; when performing a reading operation on a memory cell in a memory cell string, applying different bit line voltages to the memory cell string according to the programming sequence of the memory group to which the memory cell belongs; The earlier the programming order of the storage group to which the storage cell belongs is, the greater the bit line voltage applied to the storage cell string by the controller when performing a read operation on the storage cell.

7. The 3D memory device according to claim 6, characterized in that: The controller is also used for: According to the programming order of multiple memory cells in a memory cell string, the multiple memory cells are divided into a first memory group, a second memory group and a third memory group, wherein the first memory group is programmed first, the second memory group is programmed in the middle, and the third memory group is programmed last; when the memory cell selected by the read operation is located in the first memory group, a first bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the second memory group, a second bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the third memory group, a third bit line voltage is applied to the memory cell string.

8. The 3D memory device according to claim 7, characterized in that: The third bit line voltage is the same as the bit line voltage during program verification.

9. The 3D memory device according to claim 6, characterized in that: The programming sequence is a forward programming sequence, and the plurality of memory cells of a memory cell string are programmed sequentially according to the programming sequence, including: The controller programs sequentially from the memory cells adjacent to the bottom selection tube in a memory cell string to the memory cells adjacent to the top selection tube; when a read operation is performed on a memory cell in a memory cell string, the closer the memory group to which the memory cell selected by the read operation belongs is to the bottom selection tube, the greater the bit line voltage applied by the controller to the memory cell string.

10. The 3D memory device according to claim 6, characterized in that: The programming sequence is a reverse programming sequence, and the plurality of memory cells of a memory cell string are programmed sequentially according to the programming sequence, including: The controller programs sequentially from the memory cells adjacent to the top selection tube in a memory cell string to the memory cells adjacent to the bottom selection tube; when a read operation is performed on a memory cell in a memory cell string, the closer the memory group to which the memory cell selected by the read operation belongs is to the top selection tube, the greater the bit line voltage applied by the controller to the memory cell string.

Images