Semiconductor circuits

Abstract

A semiconductor circuit (1) comprises: an analog circuit (101) which inputs a measured signal; and a digital circuit (102) which outputs a digital output signal; the analog circuit (101) comprises: a correction element group (10) which includes a correction element for correcting an offset, the offset being an amount of deviation generated in a path for transmitting the measured signal due to a characteristic deviation of the analog circuit; and an inspection element group (20) which includes an inspection element for inspecting the correction element; and the digital circuit (102) inspects the correction element group (10) using the inspection element group (20).

Description

Technical Field

[0001] The present invention relates to a semiconductor circuit, and more particularly to a test / diagnosis circuit capable of testing / diagnosing a correction element inside a data converter. Background Art

[0002] In various applications, a data converter (hereinafter referred to as a data converter) such as an AD converter (ADC, analog-to-digital converter) or a TD converter (TDC, time-to-digital converter) is used to measure a physical quantity.

[0003] As an example, there can be cited a successive AD converter built into a microcomputer, a high-precision AD converter used in a sensor AFE (analog front end), an AD converter for detecting the remaining battery level, a wideband AD converter for implementing software wireless, a high-precision TD converter for performing picosecond time measurement in ToF (Time-Of-Flight) applications, a TD converter used as an element of an all-digital ADPLL (ALL-Digital-PLL) used in wireless applications, etc.

[0004] In the field of data converters, there is a demand for higher performance and lower cost, such as higher speed, higher precision, lower power consumption, and less area.

[0005] For example, in the case of a general-purpose successive approximation AD converter (hereinafter referred to as SAR-ADC), the limit of resolution is about 10 to 12 bits due to the limit of device accuracy.

[0006] In response to this, in recent years, technologies for actively correcting the deviation of various components within analog circuits using digital circuits have been disclosed, and the digitization of circuits is advancing.

[0007] Examples of correction techniques disclosed in patent documents and non-patent documents are shown below.

[0008] The ADC disclosed in Patent Document 1 includes a capacitor array for correction in order to correct an offset and upper capacitance of an internal DAC, and the capacitance value is set so as to compensate for nonlinearity.

[0009] Patent Document 2 describes an offset compensation circuit for a comparator which is an element of an ADC.

[0010] In the offset compensation circuit of the comparator, an offset voltage compensation circuit is provided at the output of the differential preamplifier circuit, and a variable capacitor is provided at each differential output.

[0011] The offset of the comparator is made zero by adjusting the balance of the capacitance values ​​connected to the positive and negative sides of the differential output so that it cancels out the circuit offset.

[0012] The offset correction technique of the comparator is related to the linearity (accuracy) of the ADC.

[0013] As shown in Patent Documents 1 and 2, correction elements are provided inside analog circuits. By using digital circuits to perform corrections to offset element variations caused by manufacturing variations, the size of the elements can be reduced, the circuit area can be reduced, and high precision can be achieved.

[0014] Examples of inspection techniques disclosed in patent documents and non-patent documents are shown below.

[0015] Patent Documents 3 and 4 disclose technologies for inspecting DAC capacitance inside an AD.

[0016] In the inspection method disclosed in Patent Document 3, a plurality of inspection capacitors are provided, and the accuracy of the capacitors is determined by comparing the potential of an internal capacitance DAC with the potential of the inspection capacitors.

[0017] In the inspection method disclosed in Patent Document 4, inspection MOS transistors are arranged in an array at nodes of an internal capacitor DAC to form AND and OR logics, thereby detecting failures of individual capacitor DACs (main elements).

[0018] In the method described in Patent Document 3, if a plurality of inspection capacitors themselves fail or have poor accuracy, there is a concern that inspection accuracy may be reduced, so it is necessary to ensure the accuracy of the inspection capacitors.

[0019] Furthermore, in the method described in Patent Document 4, since the gate of the MOS transistor added to the analog node of the capacitor DAC is suspended, the settling time of the capacitor DAC is slowed down, and there is a concern that the conversion speed may be reduced.

[0020] As described above, the inspection method is generally a method of inspecting the components of the DAC such as capacitors that mainly contribute to AD conversion (hereinafter referred to as main components), not a method of inspecting the correction components, and there is no method of inspecting the correction components themselves.

[0021] In contrast to the analog inspection approaches of Patent Documents 3 and 4, Non-Patent Documents 2 and 5 disclose digital methods for diagnosing faults using digital values ​​reflecting analog errors.

[0022] As described in Non-Patent Document 2, during inspection, the value of the self-calibration memory can be actively read and used for testing.

[0023] That is, since the register value indicates the correction amount for the error amount, if the register value is too large, it is indirectly determined that the error inside the simulation is too large, and it can be rejected as a failure.

[0024] However, such a digital method is an indirect method and cannot distinguish whether the main element has degraded / failed, the correction element has degraded / failed, or the driver circuit that drives the correction element has degraded / failed, making it difficult to determine the actual fault location.

[0025] Furthermore, Patent Document 6 discloses a TD converter (TDC, time-to-digital converter) as a data converter.

[0026] Non-patent document 3 discloses an open-loop integrating amplifier for achieving lower power consumption.

[0027] Prior art literature

[0028] Patent Literature

[0029] Patent Document 1: U.S. Patent No. 8638248

[0030] Patent Document 2: Japanese Patent No. 5412369

[0031] Patent Document 3: Japanese Patent Application Publication No. 2015-128203

[0032] Patent Document 4: U.S. Patent No. 5,175,547

[0033] Patent Document 5: Japanese Patent Application Publication No. 2017-38200

[0034] Patent Document 6: Japanese Patent Application Publication No. 2010-273118

[0035] Non-patent literature

[0036] Non-patent literature 1: Bob Verbruggen, “A 2.1mW 11b 410MS / s Dynamic Pipelined SARADC with Background Calibration in 28nm Digital CMOS,” VLSI Symposium 2013

[0037] Non-patent document 2: Digitally assisted / analog test technology, Haruo Kobayashi, Japan Institute of Electronics, Information and Communications Technology, July 22, 2010

[0038] Non-patent literature 3: Badr Malki, “A complementary dynamic residue amplifier fora 67dB SNDR 1.36mW170 MS / s pipelined SAR ADC”, ESSCIRC 2014 Fig.31 Gain correction function in Summary of the invention

[0039] Problems to be solved by the invention

[0040] In order to achieve high precision, high speed and low power consumption, in data converters with internal correction elements, in cases where the correction amount may change during normal use after manufacturing such as background correction, in order to ensure all correction conditions, a pre-manufacturing inspection method and a post-manufacturing self-diagnosis function are required.

[0041] The present invention provides a semiconductor circuit for detecting a correction function of a data converter in a semiconductor circuit having a converter.

[0042] Means used to solve problems

[0043] In the present disclosure, as means for solving the problems, the present invention is roughly configured as follows.

[0044] In the following configuration, the numbers and symbols in parentheses () indicate the numbers and symbols of the corresponding parts in the disclosed embodiment, and are only used to make the corresponding relationship clear, and do not limit the present invention.

[0045] A semiconductor device according to a technical solution of the present invention is a semiconductor circuit (1) including a data converter (100) that outputs a digital output signal corresponding to a measured signal, and comprises: an analog circuit (101) that inputs the measured signal; and a digital circuit (102) that outputs the digital output signal; the analog circuit (101) has: a correction element group (10) that includes a correction element for correcting nonlinearity occurring during the conversion process from the measured signal to the digital output signal in the analog circuit; and an inspection element group (20) that includes an inspection element for inspecting the correction element; the digital circuit (102) inspects the correction element group using the inspection element group (20).

[0046] Effects of the Invention

[0047] According to the present invention, it is possible to perform a correction function test in a semiconductor circuit having a data converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1This is a block diagram showing a configuration example of a semiconductor circuit including a data converter according to the first embodiment.

[0049] Figure 2 It is a diagram showing a configuration example of a correction circuit according to the first embodiment.

[0050] Figure 3 This is a block diagram showing a configuration example of a semiconductor circuit including a data converter according to the second embodiment.

[0051] Figure 4 Yes means Figure 3 A circuit diagram of an example of a comparator in FIG.

[0052] Figure 5 2 is a diagram showing a convenient definition of the comparator offset sign.

[0053] Figure 6 This is a diagram showing an example of an output waveform of a comparator.

[0054] Figure 7 This is a diagram showing an example of a waveform influenced by the offset correction capacitance of the comparator.

[0055] Figure 8 is a diagram showing a convenient redefinition of the comparator offset sign including correction.

[0056] Fig. 9 1 is a diagram showing an example of a first correspondence table between comparator offset correction control codes and offset correction amounts.

[0057] Fig.10 : is a diagram showing an example of a second correspondence table between comparator offset correction control codes and offset correction amounts.

[0058] Fig.11 This is a diagram showing the relationship between the correction control code and the offset correction amount.

[0059] Fig.12 This is a diagram showing the influence of comparator noise.

[0060] Fig.13 3 is a diagram showing the influence of the nonlinearity of the comparator.

[0061] Fig.14 A circuit diagram showing an offset control unit in the second embodiment.

[0062] Fig.15A It is a diagram showing the procedure of checking / diagnosing each weight of the offset correction element of the comparator in the second embodiment.

[0063] Fig. 15B yes Fig.15A The following is a diagram showing the order of inspection / diagnosis of each weight of the offset correction element of the comparator.

[0064] Fig.16 This is a diagram showing an example of a digital unit for testing and diagnosing an offset correction element of a comparator in the second embodiment.

[0065] Fig.17 This is a table showing the correction offset amount when the first fixed code is set in the second embodiment.

[0066] Fig.18 This is a table showing the correction offset amount when the second fixed code is set in the second embodiment.

[0067] Fig.19 1 is a schematic diagram showing generation of a first fixed code and execution of a binary search in the second embodiment.

[0068] Fig. 20 It is a schematic diagram showing CDF determination in the second embodiment.

[0069] Fig.21 It is a schematic diagram showing generation of the second fixed code and weight determination based on CDF comparison in the second embodiment.

[0070] Fig. 22 It is a schematic diagram showing weight determination using check bits in the second embodiment.

[0071] Fig.23A It is a diagram showing a procedure of checking and diagnosing the correction width of the offset correction element of the comparator in the third embodiment.

[0072] Fig. 23B yes Fig.23A Continuing from the above, this is a diagram showing the procedure for checking / diagnosing the correction amplitude of the offset correction element of the comparator.

[0073] Fig.24 This is a diagram showing an example of a digital unit for testing and diagnosing an offset correction element of a comparator in the third embodiment.

[0074] Fig.25 It is a schematic diagram showing the amplitude determination in the third embodiment.

[0075] Fig.26 It is a diagram showing a procedure for checking and diagnosing the correction function of the offset correction element of the comparator in the fourth embodiment.

[0076] Fig. 27 This is a diagram showing an example of a digital unit for testing and diagnosing an offset correction element of a comparator in the fourth embodiment.

[0077] Fig.28 It is a schematic diagram showing a toggle check in the fourth embodiment.

[0078] Fig.29 This is a diagram showing an example of the inspection / diagnosis procedure in the fourth embodiment.

[0079] Fig.30 This is a block diagram showing a correction mechanism of the residual amplifier in the fifth embodiment.

[0080] Fig.31 : is a circuit diagram showing an example of a residual amplifier with a gain correction function in the fifth embodiment.

[0081] Fig.32 This is a circuit diagram showing an example of an amplification time adjustment unit in the fifth embodiment.

[0082] Fig.33 This is a circuit diagram showing an example of an amplification time adjustment unit in the sixth embodiment.

[0083] Fig.34 : is a circuit diagram showing a signal amplifier section of a residual amplifier in the seventh embodiment.

[0084] Fig.35 : is a circuit diagram showing an offset control unit of a residual amplifier in the seventh embodiment.

[0085] Fig.36 It is a block diagram showing a correction mechanism for the MSB capacitance of the DAC in the eighth embodiment.

[0086] Fig.37 This is a circuit diagram showing an example of a capacitance correction unit in the eighth embodiment.

[0087] Fig.38 This is a block diagram showing a correction mechanism for ADC gain in the ninth embodiment.

[0088] Fig.39 : is a circuit diagram showing an example of a capacitance correction unit in the ninth embodiment.

[0089] Fig.40 This is a block diagram showing a correction mechanism of a TDC converter (time-to-digital converter) in the tenth embodiment.

[0090] Fig.41 This is a circuit diagram showing an example of a delay circuit in the tenth embodiment.

[0091] Fig.42 This is a circuit diagram showing an example of a reference voltage circuit in the eleventh embodiment.

[0092] Fig.43A This is a diagram showing an example of the case where inspection elements of opposite polarities are controlled in the twelfth embodiment.

[0093] Fig.43B yes Fig.43A Continuing from , this is a diagram showing an example of a case where inspection elements of opposite polarities are controlled.

[0094] Fig.44A This is a diagram showing an example of the case where inspection elements of opposite polarities are controlled in the twelfth embodiment.

[0095] Fig.44B yes Fig.44A Continuing from , this is a diagram showing an example of a case where inspection elements of opposite polarities are controlled.

[0096] Fig.45 An example of an offset control unit of a comparator in the thirteenth embodiment is shown.

[0097] Fig.46 This is a diagram showing an example of correction of the AD converter.

[0098] Fig.47 This is a diagram showing an example of correction of the AD converter.

[0099] Fig.48 A circuit diagram of a conventional offset control unit is shown.

[0100] Fig.49 This is a diagram showing the difference in correction resolution due to the weight of the correction element. DETAILED DESCRIPTION

[0101] (Knowledge that is the basis of the present invention)

[0102] The inventors of the present invention have discovered that the following problems may occur regarding the data converter described in the "Background Art" column.

[0103] Specifically, in the case where the correction amount may vary during normal use after factory shipment, a pre-shipment inspection method and a post-shipment self-diagnosis function are required to ensure all correction states.

[0104] In particular, the inventors of the present invention have found that when using the device as an in-vehicle component, internal controllability such as simulating internal fault detection and identification of a fault location is a necessary condition, and inspection of the correction element itself is required.

[0105] When an analog circuit is added for inspection and diagnosis, there is a problem that the conversion speed of AD conversion itself decreases.

[0106] Furthermore, when a digital method of reading a register value of a memory indicating a correction amount is adopted for inspection and diagnosis, there is a problem that it is difficult to identify a fault location because it is an indirect method.

[0107] Furthermore, as described above, the prior art is an inspection method that focuses on the main elements (DAC, comparator, amplifier, etc.) that mainly contribute to the data converter, or the value or state of the main element and the correction element added together. However, there is a problem that the correction element itself cannot be comprehensively inspected / diagnosed.

[0108] Furthermore, as described later in this specification, when there are correction elements on both the positive and negative sides of a differential circuit, there is a problem that it is difficult to identify which element on either the positive or negative side has failed and which location of the failure in the differential circuit has failed.

[0109] Furthermore, in the inspection / diagnosis of the offset compensation circuit of the comparator, since the input-output function of the comparator is nonlinear, there is a problem that all weights of the offset correction element used for the comparator cannot be inspected, which will be described later in this specification.

[0110] On the other hand, in order to perform correction, it is necessary to perform control different from normal operation.

[0111] As a control method for correction, there are trimming performed before manufacturing and foreground correction performed during a period when normal operation is stopped. However, there is a problem that these methods are weak against environmental changes such as temperature, voltage, and aging.

[0112] The ADC disclosed in Non-Patent Document 1 discloses a background correction technique for performing correction of elements in parallel with normal operation.

[0113] In Non-Patent Document 1, the offset of a comparator and the gain of a residual amplifier of a pipeline ADC are corrected in parallel with normal operation.

[0114] Since characteristic degradation caused by environmental changes (temperature, voltage, aging, etc.) that cannot be addressed by adaptation and foreground correction can be corrected in parallel with normal operations, the robustness of the system can be maintained.

[0115] On the other hand, since the selection state of the correction element changes in order to perform correction according to environmental changes, there are problems in the pre-manufacturing inspection for ensuring all correction states and the diagnosis method when a failure occurs during normal use.

[0116] In the above, methods such as providing correction elements in analog circuits for correction and performing adaptation, foreground correction, and background correction according to the timing of correction are shown.

[0117] In such a correction circuit, special control for correction is performed to detect an error in an analog circuit, and feedback is given to components of a data converter to perform correction.

[0118] There are generally two ways of applying feedback.

[0119] As a first example, Fig.46 In the AD converter (500) shown, a quantizer output signal is output from an analog circuit (501) which converts analog information into digital information.

[0120] Furthermore, in a digital circuit (502) to which the quantizer output signal is input, an error detection circuit (504) inside the digital circuit detects an error in the analog circuit and outputs an error signal, and a correction operation corresponding to the error signal is performed on the quantizer output signal in an encoding unit (502) inside the digital circuit to which the error signal is input.

[0121] This method is one of the correction methods that feedback from digital to digital.

[0122] As a second example, Fig.47 In the AD converter (510) shown, a quantizer output signal is output from an analog circuit (511).

[0123] Furthermore, in the digital circuit (512) to which the quantizer output signal is input, the error of the analog circuit is detected in the error detection circuit (514) inside the digital circuit and an error signal is output, and the control code for correcting the elements inside the analog circuit is output in the correction code generation circuit (515) inside the digital circuit to which the error signal is input, and in the analog circuit to which the control code is input, the constant of the element is corrected and the quantizer output in the corrected state is output, and the digital operation of assigning weights as usual is performed in the encoding unit (513) inside the digital circuit.

[0124] This method is one of the correction methods for feedback from digital to analog.

[0125] exist Fig.46 The correction method of feedback from digital to digital shown above has the disadvantage that it cannot be completely corrected by digital operation alone when the elements inside the analog circuit have excessive deviations, that is, when there is an error of 1LSB or more equivalent to an AD converter.

[0126] On the other hand, Fig.47In the correction method of feedback from digital to analog shown above, even if the elements inside the analog circuit vary excessively, correction can be made as long as a correction element for correcting the excessive variation is provided, thereby maintaining a small circuit area and high precision.

[0127] On the other hand, since a plurality of buses are provided for feeding back the control code from digital to analog, there is a disadvantage in that the complexity of the circuit increases.

[0128] As described above, from the perspective of characteristics and robustness, it is best to perform feedback correction from digital to analog and background correction, but inspection and diagnosis before shipment are required.

[0129] In order to explain the specifications required for the correction element, the relationship between the weight of the correction element and the resolution is supplementally explained.

[0130] exist Fig.49 (a) to (c) show the difference in correction resolution due to the weight of the correction element.

[0131] exist Fig.49 In FIG. 1 , the horizontal axis represents the correction code (the value of the control code), and the vertical axis represents the offset correction voltage.

[0132] exist Fig.49 In the example of , the weight of the offset correction element is changed to calculate the offset correction amount.

[0133] That is, in Fig.49 In (a), the weight between adjacent correction elements is set to "2", the LSB is set to 1, and the weight from LSB to MSB is set to "1:2:4:8".

[0134] exist Fig.49 In (b), the weight between adjacent correction elements is set to "1.8", and the weight from LSB to MSB is set to "1.0:1.8:(1.8 squared):(1.8 cubed)".

[0135] exist Fig.49 In (c), the weight between adjacent correction elements is set to "2.2", and the weight from LSB to MSB is set to "1: (2.2): (2.2 squared): (2.2 cubed)".

[0136] The correction resolution is determined by the maximum value of the step voltage between adjacent codes.

[0137] exist Fig.49 In (a), since all values ​​are 1 mV, the correction resolution is 1 mV.

[0138] exist Fig.49In the case of (b), since the difference between "Code=0" and "Code=1" corresponds to 1 mV, and the difference between "Code=7" and "Code=8" corresponds to 0.208 mV, the correction resolution is 1 mV.

[0139] exist Fig.49 In (c), since the difference between "Code=7" and "Code=8" is the largest, which is equivalent to 2.608mV, the correction resolution is 2.608mV.

[0140] As in Fig.49 As supplemented in the example, as the inspection specification required for the correction element, it is not necessary to ensure the linearity of the main elements such as the DAC capacitor, but it is necessary to check the resolution (maximum value of the step voltage), and regarding the weight requirement between adjacent elements, it is necessary to check the situation of being "less than 2 (≦2)".

[0141] In order to solve the above-mentioned problems, a semiconductor device of a technical solution of the present invention is a semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, and comprises: an analog circuit that quantizes the input measured signal; and a digital circuit that outputs the digital output signal; the analog circuit has: a correction element group, including a correction element, which is used to correct the nonlinearity occurring in the process of converting the measured signal to the digital output signal in the analog circuit; and an inspection element group, including an inspection element, which is used to inspect the correction element; the digital circuit uses the inspection element group to inspect the correction element group.

[0142] This enables inspection and diagnosis of the functions and weights of the correction elements, and thus enables inspection of the correction element group.

[0143] For example, the digital circuit may include: a self-diagnostic code generating circuit for generating a self-diagnostic code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; an error detecting circuit for detecting a difference between a quantized output signal of the analog circuit output in accordance with the self-diagnostic code and a predetermined threshold value as an error signal; and a self-diagnostic circuit for generating a self-diagnostic signal representing a diagnosis result of the correction element group based on the error signal.

[0144] Thus, the control code generated by the self-diagnosis code generation circuit can be supplied to the correction element inside the data converter, and the function and weight of the correction element can be checked / diagnosed by the self-diagnosis circuit. In other words, it is easy to check each correction element included in the correction element group.

[0145] For example, the self-diagnosis code may include a first fixed code and an optimal value code; the first fixed code is a code for enabling a correction element selected as an inspection object from the correction element group and disabling other correction elements and inspection elements; the optimal value code is a code for minimizing the error signal with respect to the first fixed code, and is generated by a binary search method; the self-diagnosis circuit calculates a cumulative value of the error signal corresponding to a combination of the first fixed code and the optimal value code, determines whether the cumulative value is within a prescribed range, and determines that the correction element group has a malfunction if the cumulative value is not within the prescribed range.

[0146] Therefore, when the error cannot be minimized within a predetermined range, it is determined that the correction element group has a defect, that is, a certain correction element has a defect.

[0147] For example, the self-diagnosis code may include a first fixed code, a second fixed code and an optimal value code; the first fixed code is a code for enabling a correction element selected as an inspection object from the correction element group and disabling other correction elements and inspection elements; the optimal value code is a code for minimizing the error signal with respect to the first fixed code, and is generated by a binary search method; the measured signal is a differential signal including a first polarity signal and a second polarity signal; the correction element group includes: a first element group connected to a transmission path of the first polarity signal; and a second element group connected to a transmission path of the second polarity signal; the first fixed code corresponds to the first element group and disables the second element group; the second fixed code The code is a code that sets a correction element selected as the inspection object in the above-mentioned first element group to be disabled, sets a correction element with a smaller weight than the correction element in other correction elements to be enabled, and sets the inspection element to be enabled; the above-mentioned optimal value code corresponds to the second element group, and sets the first element group to be disabled; the above-mentioned self-diagnosis circuit calculates the first cumulative value obtained by accumulating the above-mentioned error signal corresponding to the combination of the above-mentioned first fixed code and the above-mentioned optimal value code, calculates the second cumulative value obtained by accumulating the above-mentioned error signal corresponding to the combination of the above-mentioned second fixed code and the above-mentioned optimal value code, determines the size relationship between the above-mentioned first cumulative value and the above-mentioned second cumulative value, and determines that the correction element of the inspection object has a defect when the size relationship does not meet the specified conditions.

[0148] Thus, the operating point used for self-diagnosis can be set to the operating point that minimizes the above-mentioned error by using the optimal value code. That is, no matter which correction element is the inspection object, the operating point that minimizes the above-mentioned error can be used, and self-diagnosis of the correction element of the inspection object can be easily performed. In other words, it is easy to inspect each correction element.

[0149] For example, the self-diagnostic circuit may sequentially select one correction element from the correction element group as an inspection target.

[0150] Thus, when the error cannot be minimized within a predetermined range even though the measured signal is a differential signal, it can be determined that the correction element group has a malfunction, that is, a certain correction element has a malfunction.

[0151] For example, one or more correction elements in the correction element group may also be used as the inspection element.

[0152] Thus, even if the measured signal is a differential signal, self-diagnosis of each correction element can be easily performed.

[0153] A semiconductor device according to a technical solution of the present invention, wherein a data converter for outputting a digital output signal corresponding to a measured signal comprises an analog circuit (101) and a digital control circuit (102); the analog circuit (101) comprises at least: a main element group (114), each having a reference weight for quantizing the measured signal; a correction element group (140), each having an adjustment weight for correcting various analog quantities; a check element group (141), each having a check weight for checking the weight of the correction element group; a quantizer, which converts information of the measured signal into a digital signal; and an analog control unit (117), which performs control within the analog circuit; the digital circuit (102) comprises at least: an encoding unit (103), which converts the quantizer output signal of the quantizer into a digital signal; The signal is converted into a digital output signal assigned with a specified weight and outputted; an error detection circuit (104, 119), referring to one or more inspection weights of the inspection element group (141), compares the accumulated result of the digital output signal accumulated a specified number of times with a specified threshold value in order to detect the error of an adjustment weight in the correction element group (140), and outputs an error signal; a self-diagnosis code generation circuit (107, 122), controls the correction element group (140), and outputs a control code including a plurality of bit signals for diagnosing each correction element; and a self-diagnosis circuit (120), receives the error signal and outputs a self-diagnosis output signal; the self-diagnosis circuit performs self-diagnosis on each correction element of the correction element group (140).

[0154] The quantizer as one embodiment of the present invention may be one or more than one quantizer.

[0155] Furthermore, the output result of the comparator used in the inspection / diagnosis may be one or more than one.

[0156] A structure in which the weight can be inspected / diagnosed can be adopted by setting the size of the inspection element group (141) as one embodiment of the present invention to be the same as or smaller than the size of the LSB of the inspection element (140).

[0157] In one embodiment of the present invention, the correction element group (140) and the inspection element group (141) can be capacitors (400, 401), MOS transistors (372, 373, 374, 375), or resistors (456, 457).

[0158] A self-diagnosis code generating circuit (170) as one embodiment of the present invention comprises: an optimal correction code output mode, receiving the error output signal, and outputting an optimal correction code (292, 288, 289) to minimize the quantization error of the quantizer; and a logic inversion code output mode, outputting a logic inversion code (301A, 301B) in which a first bit signal in the optimal correction signal for controlling a correction element to be inspected is logically inverted; during inspection / self-diagnosis, the circuit comprises: a first step (261, 262, 263), setting the optimal correction code output mode, supplying the optimal correction code to the analog circuit, and obtaining the output of the error detection circuit as a first error signal; a second step (265, 266), setting the logic inversion code output mode, supplying the logic inversion code to the analog circuit, and obtaining the output of the error detection circuit as a second error signal; and a third step (267, 268, 269), comparing the magnitude relationship between the first error signal and the second error signal, and performing fault diagnosis on the correction element to be inspected.

[0159] In addition, as another embodiment, the self-diagnostic code generating circuit comprises: a first weight check code output mode (182, 185), in which a first bit signal for controlling a first correction element of a check object is set to 1 or 0, a second correction bit signal group for controlling a correction element having an adjustment weight smaller than that of the first correction element is set to the inversion logic of the first bit signal, a check bit signal for controlling the check element is set to the inversion logic of the first bit signal, and bit signals other than these are set to specified fixed signals for output; and a second weight check code output mode (184, 187, 188, 189), in which the first bit signal is set to the inversion logic of the bit signal when the first weight check code output mode is set, and the second bit signal group is set to the inversion logic of the bit signal when the first weight check code output mode is set, The check bit for controlling the check element is set to the inversion logic of the bit signal when the first weight check code output mode is set, and the bit signals other than this are set to the specified fixed signals for output; during inspection / self-diagnosis, it comprises: a first step (152, 153), which is set to the first weight check code output mode, and the specified multiple bit signals are supplied to the analog circuit to obtain the output of the error detection circuit as the first error signal; a second step (156, 157), which is set to the second weight check code output mode, and the specified multiple bit signals are supplied to the analog circuit to obtain the output of the error detection circuit as the second error signal; and a third step (158, 159, 160), which calculates the difference between the first error signal and the second error signal to perform weight diagnosis of the correction element group.

[0160] In addition, as another embodiment, when inspecting / diagnosing a correction element group of a circuit (114, 130) using a differential structure (or having two sets), in the above-mentioned first step (152, 153), a correction element group with a polarity on the non-inspection object side is used to obtain an optimal correction code (184, 187, 188, 189) to minimize the quantization error, thereby maintaining the CDF near 0.5, making inspection / diagnosis easy to perform.

[0161] In addition, as another embodiment, the following steps may be performed: a first step (217, 218), inputting a first reference signal (252), and obtaining the above-mentioned optimal correction code as a first optimal correction code; a second step (219, 220), inputting a second reference signal, and obtaining the above-mentioned optimal correction code as a second optimal correction code; and a third step (221, 222, 224), calculating the difference between the above-mentioned first optimal correction code and the above-mentioned second optimal correction code, and performing amplitude diagnosis of the correction element group.

[0162] In addition, as another embodiment, when inspecting a correction element group of a circuit (114, 130) using a differential structure (or having two sets), as a selection of an inspection element group serving as an inspection reference, either an inspection element group (355) having a polarity on the inspection object side (or a set on the inspection object side) or an inspection element group (357) having a polarity on the opposite side (or a set on the non-inspection object side) can be used.

[0163] In addition, as another embodiment, the data converter may be an analog-to-digital converter (ADC, 110) or a time-to-digital converter (TDC, 440).

[0164] Furthermore, as another embodiment, the inspection element group (471) can also be used as the correction element group (470).

[0165] However, in the case of this embodiment, the LSB cannot be checked.

[0166] Hereinafter, embodiments will be described with reference to the drawings.

[0167] In order to avoid the following description from being unnecessarily lengthy and to facilitate understanding by those skilled in the art, repeated descriptions may be omitted.

[0168] In addition, the following description and detailed description based on the drawings do not limit the subject matter described in the claims.

[0169] <First Embodiment>

[0170] Hereinafter, the circuit configuration and function of the first embodiment will be described using the drawings.

[0171] In the first embodiment, basic functions of a semiconductor circuit having a data converter according to the present invention are described.

[0172] Figure 1 1 is a block diagram showing a configuration example of a semiconductor circuit 1 including an AD converter 100 as a data converter according to the first embodiment. Figure 2 It is a diagram showing a configuration example of the correction circuit 109 according to the first embodiment.

[0173] Figure 1 The semiconductor circuit 1 is a circuit formed in a semiconductor device such as an LSI. The semiconductor circuit 1 in the figure includes an AD converter (ADC, analog-to-digital converter) as an example of a data converter. In addition, the data converter is not limited to the AD converter 100. The data converter may also include a TD converter (TDC, time-to-digital converter) in addition to the AD converter.

[0174] The AD converter 100 includes an analog circuit 101 and a digital circuit 102. The analog circuit 101 includes a correction circuit 109. The correction circuit 109 is Figure 2 In the example of FIG. 1 , a correction element group 10 , an inspection element group 20 , and drivers 15 to 18 , 20 are provided.

[0175] The correction element group 10 corrects the nonlinearity generated in the process of converting the measured signal into the digital output signal in the analog circuit 101. The nonlinearity mentioned here includes, for example, offset (deviation generated in the signal), gain (deviation of the magnification), capacitance value (relative deviation between the reference element arrays in), etc. The following describes the offset as a specific example of the nonlinearity to be corrected by the correction element group 10. Path0 in the figure represents the path for transmitting the measured signal as an external analog signal. It is assumed that an offset as the deviation occurs in the path path0 due to the characteristic deviation of the analog circuit. The offset is caused by the characteristic deviation of the circuit elements during manufacturing, the characteristic deviation caused by environmental changes, and aging. The control code in the figure includes a correction code for controlling the correction element group 10 during normal operation, and a spontaneous correction code for controlling the inspection element group 20 and the correction element group 10 during self-diagnosis.

[0176] The correction element group 10 includes correction elements 11 to 14. The correction elements 11 to 14 are given weights of, for example, 1, 2, 4, or 8 times. The correction elements 11 to 14 are controlled by corresponding drivers to be enabled or disabled, respectively. The correction element controlled to be enabled adds a correction amount corresponding to the weight to the path path0. The correction element controlled to be disabled does not add a correction amount to the path path0. Here, the correction amount is a physical quantity such as voltage or current. The correction elements 11 to 14 are composed of, for example, a voltage source, a current source, a capacitive element, or a resistive element for generating the correction amount.

[0177] The drivers 15 to 16 drive the corresponding correction elements according to the corresponding bits in the control code, that is, enable or disable them. The drivers 15 to 16 are composed of, for example, gate circuits or switch circuits that output binary signals corresponding to the bits of the control code.

[0178] Furthermore, the correction amount is not limited to voltage or current, and may be a physical amount such as delay time, heating amount, or pressurization amount.

[0179] The inspection element group 20 includes at least one inspection element 21 . Figure 2 The inspection element 21 is the same element with the same weight as the correction element 11. That is, the inspection element 21 has the same structure as the correction element with the smallest weight among the correction elements included in the correction element group 10.

[0180] The test element group 20 may include other test elements having the same weight as the test element 21, or may include other test elements having a weight different from that of the test element 21. Furthermore, the test element 21 may have a smaller weight than the correction element with the smallest weight.

[0181] exist Figure 1 In the embodiment, the digital circuit 102 includes at least a coding unit 103 , an error detection circuit 104 , a self-diagnosis circuit 105 , a correction code generation circuit 106 , a self-diagnosis code generation circuit 107 , and a selector 108 .

[0182] An external analog signal is input as an input signal to the AD converter 100 .

[0183] The analog circuit 101 has a reference voltage source (not shown) for generating a reference voltage inside, and can perform AD conversion on either an external analog signal or an internal reference voltage.

[0184] During normal operation, information of an external analog signal is quantized in the analog circuit 101 to which the external analog signal is input, and becomes a digital signal, which is output as a quantizer output signal.

[0185] The quantizer output signal is input to the encoding unit 103 .

[0186] The coding unit 103 assigns predetermined weights to one or more quantizer output signals, performs digital operations, and outputs digital output signals.

[0187] When inspecting and diagnosing a correction element (not shown) inside the analog circuit 101 , an internal reference voltage is AD-converted.

[0188] After being AD-converted, the quantizer output signal is input to the error detection circuit 104 .

[0189] In the error detection circuit 104, the result is compared with a predetermined threshold value (for example, an expected value), and an error signal is output.

[0190] The error signal indicates error information used for checking / diagnosing the correction signal, and may be either the sign of the error information (positive error or negative error) or quantitative information of the error information.

[0191] Furthermore, in order to remove these noises, the signal may be integrated once or more.

[0192] The error signal is input to the self-diagnostic circuit 105 , the correction code generation circuit 106 , and the self-diagnostic code generation circuit 107 .

[0193] The correction code generating circuit 106 to which the error signal is input outputs a correction code.

[0194] The self-diagnostic code generating circuit 107 to which the error signal is input outputs a self-diagnostic code.

[0195] The correction code is a digital signal having a plurality of bits and is used to control the state of a correction element that corrects analog characteristics within the analog circuit 101 .

[0196] The self-diagnosis code is a digital signal having a plurality of bits and is used to check and diagnose the control function and weight of each correction element.

[0197] The self-diagnosis circuit 105 to which the error signal is input holds, compares, and calculates error information for checking the state of the correction element, and outputs a self-diagnosis signal.

[0198] The self-diagnosis circuit 105 may set a threshold value based on the error signal to perform a diagnosis and determination, or may store error information in two different states to perform a diagnosis and determination of the weight in order to determine the relative weight of the correction element.

[0199] The self-diagnosis signal to be output may output position information such as which element of the correction element has failed, or may output a signal indicating the weight of one of the correction elements to be inspected / diagnosed.

[0200] The correction code and the self-diagnosis code are input to the selector 108 .

[0201] The selector 108 outputs a control code having a plurality of bits for controlling the state of the correction element of the analog circuit 101 .

[0202] In order to control the selector 108, an action mode signal is input, and according to the action mode signal, switching is performed to set it to a correction mode for correcting the characteristics of the analog circuit 101 and outputting a correction code, or to set it to a self-diagnosis mode for inspecting / diagnosing each correction element in the correction element group of the analog circuit 101 and outputting a self-diagnosis code.

[0203] When the control code is a correction code, the analog circuit 101 to which the control code is input outputs a quantizer output signal in a state in which each analog characteristic of the analog circuit 101 is corrected.

[0204] Furthermore, when the control code is a self-diagnosis code, a quantizer output signal indicating the weight state of the correction element inside the analog circuit 101 is output.

[0205] Thus, the AD converter 100 of the first embodiment is a semiconductor circuit 1 including a data converter 100 that outputs a digital output signal corresponding to a measured signal, and has an analog circuit 101 that quantizes the input measured signal and a digital circuit 102 that outputs the digital output signal. The analog circuit 101 has a correction element group 10 including a correction element for correcting the nonlinearity generated in the process of converting the measured signal into the digital output signal in the analog circuit, and an inspection element group 20 including an inspection element for inspecting the correction element. The digital circuit 102 inspects the correction element group 10 using the inspection element group 20.

[0206] This enables inspection and diagnosis of the functions and weights of the correction elements, and thus enables inspection of the correction element group.

[0207] Here, the digital circuit 102 may include: a self-diagnostic code generation circuit 107 for generating a self-diagnostic code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; an error detection circuit 104 for detecting a difference between a quantized output signal of an analog circuit output corresponding to the self-diagnostic code and a prescribed threshold value as an error signal; and a self-diagnostic circuit 105 for generating a self-diagnostic signal representing a diagnosis result of the correction element group based on the error signal.

[0208] Thus, the control code generated by the self-diagnosis code generation circuit can be provided to the correction element inside the data converter, and the function and weight of the correction element can be checked / diagnosed by the self-diagnosis circuit. In other words, it is easy to check each correction element included in the correction element group.

[0209] Therefore, in the case of the first embodiment, not only is there a correction code generation circuit for correcting the analog circuit 101, but there is also a self-diagnosis code generation circuit for checking the function and weight of each correction element. Since self-diagnosis codes corresponding to each correction element are generated and comprehensive inspection / diagnosis is performed, it is possible to inspect / diagnose all correction elements.

[0210] That is, in the prior art, linear and partial faults in the state of the main element or the state in which the main element and the correction element are added are checked, and normality can be ensured only in a limited correction state. In contrast, in the present embodiment, the effect of ensuring the normality of each correction element can be achieved by ensuring the normality of all correction states.

[0211] As described above, the semiconductor circuit of the first embodiment is a semiconductor circuit 1 including a data converter 100 that outputs a digital output signal corresponding to a measured signal, and has an analog circuit 101 that quantizes the input measured signal and a digital circuit 102 that outputs a digital output signal; the analog circuit 101 has: a correction element group 10, including a correction element for correcting the nonlinearity generated during the conversion process from the measured signal to the digital output signal in the analog circuit; and an inspection element group 20, including an inspection element for inspecting the correction element; the digital circuit 102 uses the inspection element group 20 to inspect the correction element group 10.

[0212] Here, the digital circuit 102 may include: a self-diagnostic code generation circuit 107 for generating a self-diagnostic code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; an error detection circuit 104 for detecting a difference between a quantized output signal of an analog circuit output corresponding to the self-diagnostic code and a prescribed threshold value as an error signal; and a self-diagnostic circuit 105 for generating a self-diagnostic signal representing a diagnosis result of the correction element group based on the error signal.

[0213] Here, the analog circuit 101 may include a quantizer for quantizing a measured signal or a reference signal corrected by a correction element group and converting it into a quantizer output signal; the digital circuit may include: an encoding unit for converting the quantizer output signal into a digital output signal assigned with a specified weight and outputting it; an error detection circuit for outputting a cumulative result of accumulating the difference between the quantizer output signal and a specified threshold value multiple times as an error signal; a self-diagnostic code generation circuit for outputting a self-diagnostic code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; and a self-diagnostic circuit for receiving the error signal and outputting a self-diagnostic output signal indicating whether the correction element group is qualified or not; and the self-diagnostic circuit performs self-diagnosis of each correction element in the correction element group.

[0214] <Second Embodiment>

[0215] Hereinafter, the circuit configuration and operation of the second embodiment will be described with reference to the drawings.

[0216] In the second embodiment, in order to show a more specific configuration example, a successive AD converter ( Figure 2 ) as an example, an example of a configuration in which each correction element of a correction element group for comparator offset correction is taken as an inspection / diagnosis object is described.

[0217] In addition, regarding the components appearing in the second to thirteenth embodiments, components having the same names as those in the first or other embodiments are examples in which the same components are more specifically described even if they are marked differently.

[0218] Figure 3 FIG. 1 is a block diagram showing a configuration example of a semiconductor circuit including a data converter according to the second embodiment. Figure 3 , a successive approximation type successive AD converter 110 is shown as an example of a data converter.

[0219] Figure 3 The successive AD converter 110 is Figure 1 The specific example of the AD converter 100 of the present invention is an example of using a differential circuit structure. The AD converter 100 of the present invention is not limited to this, and can also be applied to a single-ended circuit structure.

[0220] The constituent elements are shown below.

[0221] The successive AD converter 110 includes an analog circuit 111 and a digital circuit 112, and is input with an external analog signal (VINP, VINM, VINP is on the positive side, and VINM is on the negative side). After the analog signal is time-discretized and amplitude-quantized, the quantizer output signal is output, and a digital operation is performed by an encoder circuit (not shown) to output a digital signal as a result of the AD conversion.

[0222] The analog circuit 111 includes an analog element section to be corrected and an element control section.

[0223] As an analog element unit, a sample-and-hold circuit 113 , a DAC (digital-to-analog converter) 114 , a comparator 116 , and a driver circuit 115 are provided.

[0224] As an element control unit, a DAC control unit 117 is provided.

[0225] The digital circuit includes an element portion for controlling the DAC and an element portion for controlling a correction object.

[0226] As the element unit for controlling the DAC, a SAR control unit 118 , a DAC direct control mode memory unit 124 , and a selector 125 are provided.

[0227] As the element unit for controlling the correction object, an error detection circuit 119 , a self-diagnosis circuit 120 , a correction code generation circuit 121 , a self-diagnosis code generation circuit 122 , and a selector 123 are provided.

[0228] The connection relationship between the components is shown below.

[0229] An external analog signal (VINP, VINM) is input to the sample-and-hold circuit.

[0230] In the sample-and-hold circuit 113 , during normal operation, an input signal is sampled and time-discretized, an analog information signal is output, and a voltage is held at the top plate voltage nodes (topPlateP, topPlateN) of the DAC 114 .

[0231] Furthermore, the sample-and-hold circuit 113 is also provided with a mechanism for setting the output to the midpoint reference voltage VCM during correction.

[0232] A driver circuit 115 is connected to the bottom plate side of the DAC 114 , and a DAC control unit 117 determines whether to set the high potential side reference voltage VRH or the low potential side reference voltage VRL.

[0233] In addition, DAC114 is composed of a capacitor array of a plurality of main elements to which weights are assigned. Figure 2 The (8C, 4C, 2C, 1C) in the figure respectively represent that the weights are (8, 4, 2, 1) based on 1LSB of the DAC.

[0234] The top plate voltage nodes (topPlateP, topPlateN) are input to the comparator 116 to be corrected.

[0235] The analog information is quantized into digital information in the comparator 116 and output as a quantizer output signal.

[0236] The quantizer output signal is output to the SAR control unit 118 and the error detection circuit 119 .

[0237] The SAR control unit 118 outputs a control signal for controlling the DAC 114 to the selector 125 based on the quantizer output signal.

[0238] On the other hand, the selector 125 outputs a control signal, which is a basis of the DAC control code, to the DAC control unit 117 in accordance with the output signal of the SAR control unit 118 and the DAC control mode signal input from the DAC direct control mode memory unit 124 .

[0239] The error detection circuit 119 compares and calculates a predetermined threshold value (expected value, standard value, reference value, etc.) based on the quantizer output signal, and outputs an error signal.

[0240] The error signal is output to the correction code generation circuit 121 and the self-diagnosis code generation circuit 122 .

[0241] The correction code generation circuit 121 determines a correction code based on the error signal and outputs the correction code.

[0242] The self-diagnostic code generation circuit 122 determines a correction code based on the error signal and outputs the correction code.

[0243] The correction code and the self-diagnosis code are input to the selector 123 .

[0244] The selector 123 outputs either a correction code or a self-diagnosis code as a control code to a correction target based on the input operation mode signal.

[0245] The self-diagnosis circuit 120 receives the error signal, the self-diagnosis code, and the correction code, and outputs a self-diagnosis output signal.

[0246] The following describes the operations of the components.

[0247] The operation modes include (1) a normal operation mode, (2) a correction mode, and (3) an inspection / self-diagnosis mode.

[0248] In (1) the normal operation mode, the external analog signal (VINP, VINM) is sampled (time discretized) at the DAC top plate voltage nodes (topPlateP, topPlateN) via the sample-and-hold circuit 113 .

[0249] The difference (referred to as a residual voltage) between the sampled voltage and the reference voltage generated by charge redistribution of the capacitance of the DAC 114 controlled by the DAC control unit 117 and the driver circuit 115 is input to the comparator 116 .

[0250] The comparator 116 compares the positive side voltage (topPlateP) and the negative side voltage (topPlateN) of the residual voltage, and outputs "1" if the positive side is larger, and outputs "0" if the negative side is larger.

[0251] In the normal operation mode, the output of the SAR control unit 118 is selected as the output signal of the selector 125 according to the DAC control mode signal.

[0252] The SAR control unit 118 outputs a control signal, which will become the basis of the DAC control code, to the DAC control unit 117 based on the quantizer output signal, and successively compares the difference (residual voltage) between the analog signal and the voltage signal generated by the DAC 114, and performs quantization processing in a manner that makes the residual voltage close to zero.

[0253] In addition, although the number of comparison cycles is shown as 4 bits in this embodiment, it is not limited to this.

[0254] Furthermore, one comparator 116 may perform processing of a plurality of successive comparison cycles, or a plurality of comparators may perform processing of each cycle.

[0255] In addition, regarding the quantizer output signal, it is assumed that a value of each cycle is held by a circuit not shown in the figure, and in the present embodiment, four quantizer output signals are output with a 4-bit structure.

[0256] The quantizer output from the comparator 116 is fed back to both the SAR control unit 118 and the error detection circuit 119. However, when background correction is performed, the offset state of the comparator is detected by the error detection circuit, and the correction code is updated at any time by the correction code generation circuit 121 and reflected in the offset control code (CCp, CCn), so that AD conversion is performed in the state of correcting the offset.

[0257] Next, (2) the correction mode will be described.

[0258] (2) In the correction mode, there are two types: foreground correction and background correction.

[0259] During foreground correction, the AD conversion operation is stopped, and the internal midpoint reference voltage (VCM) is sampled (time discretized) at the DAC top plate voltage nodes (topPlateP, topPlateN) via the sample-and-hold circuit 113 .

[0260] By performing AD conversion on the internal midpoint reference voltage (VCM), the input state of the comparator is set to a specified state (for example, a differential voltage zero state) so that the offset of the comparator 116 is corrected in a manner that makes the probability of occurrence of "1" and "0" in the comparator output (quantizer output signal) close to 50%.

[0261] During foreground correction, on the basis of stopping the AD conversion action, the output of the correction code generation circuit is selected from the output of the selector 123 and the optimal value of the correction code is approached, and the output code representing the specific code maintained by the DAC direct control mode memory unit 124 is selected from the output of the selector 125 to control the DAC114.

[0262] During background correction, the output of the correction code generation circuit is selected from the output of the selector 123 while the AD conversion operation is continued, the correction code changes to an optimal value in response to environmental changes, and the output of the SAR control unit 118 is selected from the output of the selector 125 to perform the same DAC control operation as in the normal operation mode.

[0263] Since the main purpose of the present invention is to inspect and diagnose the correction element, the details of (2) the correction mode will be omitted.

[0264] Next, (3) the inspection / self-diagnosis mode will be described.

[0265] The inspection / self-diagnosis object of this embodiment is the correction element itself for correcting the offset of the comparator, so before describing the related invention, a comparator with an offset correction mechanism will be described.

[0266] Figure 4 Yes means Figure 3 A circuit diagram of an example of a comparator in FIG. Figure 4 The comparator 130 is Figure 3 The comparator 116 is an example of a device including an offset control unit 132 as an offset correction mechanism. The offset control unit 132 is also Figure 1 An example of the correction circuit 109 is shown.

[0267] exist Figure 4 In the embodiment, the comparator 130 is composed of a differential amplifier 131 , an offset control unit 132 , and a differential latch circuit 133 .

[0268] In the offset control section 132 , CapP and CapN are provided as variable capacitors for correction in the positive and negative sides of the differential, respectively, and one end of each is connected to the positive and negative output nodes Vgp and Vgn of the differential amplifier section.

[0269] The correction elements (CapP, CapN) can make the capacitance values ​​variable according to the offset correction amount capacitance control codes (CCp, CCn) supplied from the digital circuit.

[0270] The following describes the offset correction function of the comparator and its problems.

[0271] An offset control unit 132 is included in the figure.

[0272] The correction control code bus (CC3p, CC2p, CC1p, CC0p, CC3n, CC2n, CC1n, CC0n) supplied from the digital circuit is supplied to the correction element driver circuit 136, and the correction element driver circuit 136 supplies VDD (power supply voltage) or VSS (GND voltage) to the correction element group.

[0273] The correction element group is composed of MOS transistors, and has a capacitance value between a node that short-circuits a drain and a source and a node of a gate driven by the correction element driver circuit 136 .

[0274] In the case of an NMOS transistor, if a driver circuit supplies VDD, a channel is formed in the MOS and the capacitance value increases.

[0275] On the other hand, if VSS is supplied, no channel is formed, and the capacitance value becomes a parasitic capacitance with respect to GND, and the capacitance value becomes small.

[0276] The comparator 130 to be corrected has a random offset Voff mainly due to manufacturing variations of the differential pair of the differential amplifier section 131 .

[0277] In the description of the present invention, since the sign of the offset needs to be defined in advance for convenience, Figure 5 A convenient definition of the offset sign is set in .

[0278] The same explanation can be given even with opposite signs, so they are just signs for convenience.

[0279] When the comparator offset 137 is zero, the comparator 130 has a positive input VINCP, a negative input VINCM, a positive output VOUTCP, and a negative output VOUTCM. When the value of the differential input (VINCP-VINCM) is greater than 0, VOUTCP outputs "1", and in the opposite case, VOUTCP outputs "0", and VOUTCM outputs the inverted logic of VOUTCP.

[0280] When the offset Voff is caused by manufacturing variation, the substantial differential input of the comparator 130 is (VINCP-Voff-VINCM). When the value of the substantial differential input is greater than 0, VOUTCP outputs "1", and otherwise outputs "0".

[0281] exist Figure 6 An example of a comparator output waveform is shown in FIG.

[0282] When the input clock CLKC of the comparator is “Low”, the comparator is reset, the internal nodes (Vgp, Vgn) become the power supply potential (VDD), and the output nodes (Voutp, Voutn) become the GND potential (VSS).

[0283] When the comparator input clock CLKC changes to "High", the comparator is set to the amplification state, the differential input signal (VINCP, VINCM) is amplified by the differential amplifier 131, the internal nodes (Vgp, Vgn) approach VSS, and the signal corresponding to the input is turned on.

[0284] Corresponding to the turning on of the signal of the internal node (Vgp, Vgn), the differential latch circuit performs a regeneration action and changes to the comparator output state, and the logic of the output voltage (VOUTCP, VOUTCM) is determined.

[0285] exist Figure 5 In the example of , it is shown that the voltage of the input signal VINCP is determined to be larger than the input signal VINCM, VOUTCP outputs "1" and VOUTCM outputs "0".

[0286] Figure 7 A diagram showing a waveform example representing the effect of the offset correction capacitor.

[0287] When the variable correction capacitor CapP is increased by a control signal, since the approaching operation of the Vgp node towards GND during amplification becomes slower, it changes in the direction of turning on with Vgp > Vgn.

[0288] Therefore, the output VOUTCP at this time is "0".

[0289] On the other hand, when the variable correction capacitor CapN is increased by a control signal, since the approaching operation of the Vgn node towards GND during amplification becomes slower, it changes in the direction of turning on with Vgp < Vgn.

[0290] Therefore, the output signal VOUTCP at this time is "1".

[0291] In this way, the offset is adjusted by adjusting the load balance of the differential circuit.

[0292] Due to considering the signs of the above-mentioned offset correction effects based on CapP and CapN, Figure 5 the definition is redefined.

[0293] In Figure 8 a redefinition showing the convenience of including the corrected comparator offset sign is presented.

[0294] Let the offset correction amount 138 when CapP is increased be Vcalp, let the offset correction amount 139 when CapN is increased be Vcaln, let the comparator offset 137 be the offset Voff, let the differential input (VINCP - VINCM) be Vin, and let the comparator output be VOUTCP.

[0295] At this time, the substantial differential input VinCP of the comparator 130 is ((VINCP - Voff - Vcalp) - (VINCM - Vcalm)).

[0296] That is, it is (Vin - Voff - (Vcalp - Vcalm)).

[0297] From this, the effects of CapP and CapN on the offset become a relationship of "opposite signs".

[0298] Furthermore, since 4-bit correction capacitors are arranged on the positive side and 4-bit correction capacitors are arranged on the negative side, it has a correction effect equivalent to 5 bits.

[0299] In Fig. 9and Fig.10 An example of specifically calculating the offset correction control code and the offset correction amount is shown in FIG.

[0300] exist Fig. 9 and Fig.10 In , the weight of the correction amount is set to (1.8 to the cube, 1.8 to the square, 1.8 to the first power, 1).

[0301] Furthermore, the offset action amount of each weight is set to (5.832, 3.24, 1.8, 1) [mV].

[0302] like Fig. 9 and Fig.10 As shown, since both CapP and CapN function as offset correction capacitors, a plurality of control codes can be allocated to achieve one offset correction amount, and there is no one-to-one relationship, so correction can be achieved using any control code correspondence table.

[0303] In short, the sum of (Vcalp-Vcalm) functions as the offset correction amount.

[0304] exist Fig.11 : The relationship between the correction control code and the offset correction amount is shown in .

[0305] Based on the first correspondence table <mapping1>And the second correspondence table <mapping2>The same correction amplitude can be achieved with any correction amount.

[0306] As can be seen from the figure, since the weight is less than 2 (1.8), there is a point where the correction amount decreases with an increase in the control code.

[0307] That is, the following situation is shown: although the resolution can be maintained due to the presence of redundancy, a plurality of correction control codes may be matched (a plurality of solutions) in order to realize one offset correction amount depending on the situation.

[0308] Therefore, due to the redundancy of the correction capacitor, the offset correction amount and the control code may not have a one-to-one relationship.

[0309] From the viewpoint of inspection and diagnosis of the correction element itself, redundancy that does not form a one-to-one relationship as described above becomes a problem.

[0310] When a partial failure of the correction element or a partial failure of the output of the driver circuit of the correction element is assumed, it is assumed that a signal indicating the offset correction amount of the comparator can be known by some direct or indirect method during inspection / diagnosis.

[0311] At this time, when the output of the indicated correction amount is a normal value, it is normal only due to redundancy, and it cannot be asserted that all correction elements are normal (however, there is also an advantage that even if one fails, other solutions can be found to recover due to redundancy).

[0312] Furthermore, when the diagnostic output is an abnormal value, as described in the example of the control code correspondence table of the differential circuit, the correction amount and the control code state are not 1-to-1, so there is a problem of difficulty in determining the location of the faulty element, such as which of the positive and negative sides is faulty, and which correction element is faulty (hereinafter referred to as "the problem of concealment of internal defects due to redundancy").

[0313] In addition, the problem of comparator noise is described.

[0314] As analog circuits such as data converters continue to be miniaturized and their voltages continue to decrease, comparator noise has become a problem in AD conversion, correction, inspection, and diagnosis.

[0315] exist Fig.12 The influence of comparator noise is shown in .

[0316] exist Fig.12 In the graph, the horizontal axis is the comparator input voltage, and the vertical axis represents the CDF (Cumulative Distribution Function), which is the probability that the comparator outputs "1" corresponding to the input.

[0317] When the input voltage is zero, the CDF is approximately 0.5, the probability of outputting "1" is 50%, and the probability of outputting "0" is 50%.

[0318] Fig.12 (a) Fig.12 (b) is a simulation result when the comparator output result is repeatedly measured in order to remove the influence of noise.

[0319] Fig.12 (a) is the result of 64 measurements. Fig.12 (b) is the result of 4096 measurements.

[0320] As shown in the figure, Fig.12 (a) Since the number of comparison outputs is small, erroneous judgment may occur due to noise.

[0321] The influence of the noise of the comparator is one of the main causes of the degradation of the accuracy of the AD conversion result, and it becomes a problem as a result of misjudgment in correction or inspection / diagnosis (hereinafter, this problem is referred to as "misjudgment problem caused by noise").

[0322] In addition, the problem of nonlinearity of the comparator will be described.

[0323] exist Fig.13 A diagram illustrating the influence of the nonlinearity of the comparator is shown in FIG.

[0324] The horizontal axis represents the actual differential input VinCP of the comparator, and the vertical axis represents CDF.

[0325] An example is shown in which several correction control codes are selected and CDFs are measured in order to inspect / diagnose the correction control codes.

[0326] When two adjacent control codes near the black circle comparator transition point (0.5) are selected, they are measured as "0.4" and "0.6" respectively, and normal / abnormal determination is easy.

[0327] On the other hand, at the non-comparator transition point portion of the white circle, if two control codes are selected, both output "0.0".

[0328] Therefore, when the CDF is not near "0.5", it becomes difficult to determine whether the control code for correction functions normally and whether the magnitude relationship between the correction elements is as expected.

[0329] Thus, there is a problem that only a part of the correction control code can be correctly checked / diagnosed due to nonlinearity (hereinafter, this problem is referred to as "the problem of state estimation caused by nonlinearity of the comparator").

[0330] The purpose of the present invention is to inspect / diagnose a correction element, so the analog circuit structure is not limited, but as an example, Figure 3 The comparator is described below.

[0331] As Figure 3 The structure of the comparator offset control unit 132 is used in the present invention Fig.14 The circuit diagram shown.

[0332] Compared with previous Fig.48 The offset control unit shown in the figure, the offset control unit of the present invention is Fig.14 It is shown in FIG. 1 that, compared with the conventional structure, an inspection element group 141 is added.

[0333] The inspection element group 141 is used when inspecting the weight of the correction element group 140, is controlled by the control signals CCdp and CCdn, and has the same capacitance value as the LSB (1C) of the correction element group.

[0334] However, the size is not limited to this, and the same effect can be obtained by setting the size of the inspection element group to a value less than the LSB (1C) of the correction element group.

[0335] The following is based on Fig.15A and Fig. 15B Flow chart, see Figure 2 and Fig.16 The circuit structure uses Figures 17 to 21 The table and schematic diagram illustrate the order of weight checking of the present invention.

[0336] exist Fig.15A and Fig. 15B 1 shows the procedure (flow chart) for checking / diagnosing each weight of the offset correction element of the comparator.

[0337] exist Fig.16 An example of the structure of the digital part is shown in .

[0338] exist Fig.17 , Fig.18 Indicates the correction offset during inspection / diagnosis.

[0339] exist Fig.19 , Fig. 20 , Fig.21 Calculation examples of the correction offset and CDF during inspection / diagnosis are shown in FIG.

[0340] exist Fig. 22 A schematic diagram showing weight determination using check bits is shown in FIG.

[0341] In sequence 150, a check / diagnosis of the weights of the comparator correction elements is initiated.

[0342] exist Figure 2 In the circuit structure, a predetermined operation mode signal is provided, the correction code generation circuit 121 is disabled, and the self-diagnosis code generation circuit 122 is enabled to start the operation.

[0343] In sequence 151, an operation of selecting a correction component to be inspected is performed.

[0344] Since the correction elements are disposed on both the positive side (P side) and the negative side (N side), they are individually selected for inspection / diagnosis.

[0345] Furthermore, which bit of the correction element (which correction element) is to be checked is selected.

[0346] This is a sequence that is programmed, selected sequentially, or it can be a sequence selected by information held in a register.

[0347] In this embodiment, the test bit selection unit 190 receives the test object bit designation signal TestBit output from the state control 173 and outputs information that serves as a basis for the control code used for the test to the first fixed code generation unit and the second fixed code generation unit 183 .

[0348] Since the correction element is an array set to a value with a weight of 2 or less, the above-mentioned "problem of concealment of internal defects due to redundancy" can be solved by performing individual inspections / diagnoses directed to the correction elements one by one.

[0349] In the sequence 152 and 153 , the first fixed code is generated and the binary search is performed.

[0350] The present invention assumes a case where the same operation is performed on all correction bits to check all bits. As an example, a case where the MSB of the P-side correction element is checked will be described.

[0351] The self-diagnostic code output from the first fixed code generating unit 182 is set to a fixed value of (1, 0, 0, 0) (0) as a value output to (CC3p, CC2p, CC1p, CC0p) (CCdp) of the P-side control code.

[0352] This fixed value is stored in the first fixed code register 185 and maintained.

[0353] On the other hand, the N-side control code is searched for the optimal code with the minimum quantization error (CDF is around 0.5) by the binary search control unit 184.

[0354] The code in the middle of the search is saved in the search code register 187, and each time the code with a CDF close to 0.5 is saved in the optimal code register 188, the error with 0.5 as the center of the CDF is saved in the minimum error register 189 for updating.

[0355] In addition, during the control of the binary search, the control signal (CCdn) of the N-side inspection element is fixed to (0).

[0356] exist Fig.19 In the binary search state, Fig.17 ] represents the correction offset when the first fixed code is set.

[0357] In this embodiment, taking the offset Voff as 4.05 mV as an example, the correction amount Vcalm on the N side is determined so that the sum of the correction amount Vcalp relative to the offset Voff and the first fixed code setting (1000)(0) on the P side and the quantization error is minimized (CDF≈0.5), thereby determining the control code on the N side.

[0358] The quantizer output signal is input to the subtractor 199 together with the cumulative expected value register 191, and the subtraction result is stored in the accumulator 192 (accumulator).

[0359] By repeatedly measuring using the integrator, the above-mentioned "problem of erroneous determination due to noise" can be solved.

[0360] The output of the accumulator 192 is supplied to the binary search control unit 184 as an error signal, and is also supplied to the demultiplexer 181 .

[0361] When the binary search is completed and the optimal code is determined, the first fixed code is supplied as a control signal to the correction element on the positive side via the selector 180C and the selector 180A.

[0362] Furthermore, the optimal code register 188 outputs the determined optimal code, and supplies it to the correction element on the N side as a control signal via the selector 180D and the selector 180B.

[0363] As the result at this time is maintained, the process is switched to STEP 2 in the demultiplexer 181 , and the error signal is stored in the first accumulation result 193 .

[0364] The first integration result is input to the CDF determination unit 197 and compared with the upper limit value / lower limit value stored in the CDF standard value register 195 .

[0365] exist Fig. 20 The figure below shows a schematic diagram of specification value determination based on CDF.

[0366] The figure is an example. When 0.2≦CDF≦0.8 (sequence 154), it is considered to be a normal determination and the process moves to the next step (155).

[0367] If it is not within the range (sequence 156), the resolution is considered to be insufficient and is determined to be abnormal.

[0368] Furthermore, when the CDF determines that the offset resolution is abnormal, a malfunction has occurred in one of the P-side correction element group and the N-side correction element group, but it is difficult to determine the fault location. However, which one has the malfunction is not a problem in this sequence stage.

[0369] That is, the main purpose is to maintain the CDF near 0.5 so that a check of a specific bit can be performed in the next step.

[0370] In the next step, the P side is reconstructed, the N side is maintained fixed at the optimal value, and the sign of the CDF is observed to which sign it deviates from 0.5. Being able to keep the CDF near 0.5 for inspection is important for implementing the present invention.

[0371] Through this series of sequences, the offset is moved to Fig.13 The position shown in FIG. 1 is capable of performing internal state inference, thereby being able to solve the above-mentioned "problem of state inference caused by comparator nonlinearity".

[0372] In sequence 156, selectors 180C, 180D, and demultiplexer 181 are switched to STEP2.

[0373] The self-diagnostic code output from the second fixed code generation unit 183 is set to a fixed value of (0, 1, 1, 1) (1) which is (CC3n, CC2n, CC1n, CC0n)(CCdn).

[0374] This fixed value is stored in the second fixed code register 186 and maintained.

[0375] On the other hand, the N-side control code is maintained fixed to the optimal code output by the optimal code register 188 (in this embodiment, (0, 0, 1, 0) (0).

[0376] The second fixed code is supplied to the P-side correction element via the selectors 180C and 180A.

[0377] The optimum code is supplied to the N-side correction element via selectors 180D and 180B.

[0378] In this example, in this series of operations, it is important that the N-side control code remains unchanged. Since the P-side control code is reconstructed and the change in the CDF result relative to near 0.5 is determined, when a fault is determined, the fault location can be determined to be the P side. Since each bit is checked, it is also possible to check / diagnose which bit has a fault.

[0379] The sequences 157 to 160 are described.

[0380] The error signal (order 157 ) output from the accumulator 192 is supplied to the second accumulation result register 194 .

[0381] The difference between the first integrated result and the second integrated result is calculated by the subtractor 200 and supplied to the weight determination unit 198, which determines which CDF is larger (procedure 158), and performs a self-diagnosis output (procedures 159 and 160).

[0382] In the example of this embodiment, since it is the MSB of the P-side correction element, if CDF2≦CDF1, it is determined to be normal, and otherwise, it is considered that the weight of the MSB correction element is 2 or more and it is determined to be abnormal.

[0383] exist Fig.21 A schematic diagram showing a series of operations is provided as a supplement.

[0384] Furthermore, as a supplement, Fig. 22 A schematic diagram showing weight determination using check bits is shown in FIG.

[0385] The correction amount Vcalm on the N side can be controlled, but the offset Voff corresponding to the manufacturing variation cannot be controlled (it varies randomly within a certain range).

[0386] Furthermore, in order to check a specific bit on the P side, the check object bit needs to be fixed to "1" or "0".

[0387] Based on these constraints, in this embodiment, the P side is fixed (1000 or 0111), the offset Voff is set to the offset caused by manufacturing variation, and the problem is solved by controlling the CDF to be close to 0.5 through binary search control on the N side outside the inspection object.

[0388] This can be considered as a preparatory operation for inspection / diagnosis in which the correction amount Vcalm on the N side is adjusted by binary search for the sum of the fixed value Vcalp on the P side (fixed for inspection) and the manufacturing variation offset Voff so as to keep the CDF near 0.5.

[0389] By basing Fig.15A and Fig. 15B The order of the flowchart is performed on both the P side and the N side, and all bits are checked / diagnosed, which can ensure that the weights of all correction elements are less than 2 based on the inspection element.

[0390] As described above, there is an effect that the "problem of erroneous determination due to noise" can be solved by integrating the quantizer output results by the accumulator in the error detection circuit.

[0391] Furthermore, by using a correction element on the polarity side that is not the object of inspection to move the CDF to near 0.5, the magnitude relationship between the two relative integration results can be determined, thereby having the effect of solving the "problem of state estimation caused by nonlinearity of the comparator".

[0392] Furthermore, since the weights of the P side and the N side are individually inspected / diagnosed based on the inspection element, the defective condition can be determined by individually inspecting each correction element, which has the effect of solving the "problem of hidden internal defects caused by redundancy".

[0393] As described above, in the semiconductor circuit of the second embodiment, the self-diagnosis code includes a first fixed code and an optimal value code; the first fixed code is a code that enables a correction element selected as an inspection object from the correction element group and disables other correction elements and inspection elements; the optimal value code is a code that minimizes the error signal relative to the first fixed code and is generated by a binary search method; the self-diagnosis circuit 105 calculates the cumulative value of the error signal corresponding to the combination of the first fixed code and the optimal value code, and determines whether the cumulative value is within a specified range. When it is not within the specified range, it is determined that the correction element group has a malfunction.

[0394] Here, the self-diagnosis code may include a first fixed code, a second fixed code, and an optimal value code; the first fixed code is a code that enables a correction element selected as an inspection object from the correction element group and disables other correction elements and inspection elements; the optimal value code is a code that minimizes the error signal relative to the first fixed code and is generated by a binary search method; the measured signal is a differential signal including a first polarity signal and a second polarity signal; the correction element group includes a first element group connected to a transmission path of the first polarity signal and a second element group connected to a transmission path of the second polarity signal; the first fixed code corresponds to the first element group and disables the second element group; the second fixed code corresponds to the second element group and disables the second element group; The fixed code is a code that disables a correction element selected as the inspection object in the first element group, enables the correction element with a smaller weight than the correction element among other correction elements, and enables the inspection element; the optimal value code corresponds to the second element group, and disables the first element group; the self-diagnosis circuit 105 calculates a first cumulative value obtained by accumulating error signals corresponding to the combination of the first fixed code and the optimal value code, calculates a second cumulative value obtained by accumulating error signals corresponding to the combination of the second fixed code and the optimal value code, determines the size relationship between the first cumulative value and the second cumulative value, and determines that the correction element of the inspection object has a defect when the size relationship does not meet the specified conditions.

[0395] Here, the self-diagnostic circuit may sequentially select one correction element from the correction element group as an inspection object.

[0396] Here, one or more correction elements in the correction element group may also be used as inspection elements.

[0397] Here, the quantizer may include one or more comparators, and the error detection circuit may generate an error signal by integrating the results of digital operations on the output results of one comparator or the output results of two or more comparators with predetermined weights as the quantizer output signal.

[0398] Here, the correction element group may include a plurality of correction elements to which weights are assigned; and the inspection element may have a weight that is the same as or smaller than a correction element corresponding to the smallest weight in the correction element group.

[0399] Here, it can also be that the self-diagnosis code generation circuit has a first weight check code output mode and a second weight check code output mode; in the first weight check code output mode, the first bit signal for controlling the first correction element of the inspection object is set to 1 or 0, the second correction bit signal group for controlling the correction element whose adjustment weight is smaller than the first correction element is set to the inverted logic value of the first bit signal, the check bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than it are set to a specified fixed signal for output; in the second weight check code output mode, the first bit signal is set to the inverted logic value when the first weight check code output mode is set, the second bit signal group is set to the inverted logic value of the first bit signal, the check bit for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than it are set to a specified fixed signal for output; when the digital circuit is inspected, it is set to the first weight check code output mode to generate a first error signal based on the error signal from the error detection circuit, and is set to the second weight check code output mode to generate a second error signal based on the error signal from the error detection circuit, and the difference between the first error signal and the second error signal is calculated to perform weight diagnosis of the correction element group.

[0400] Here, it can also be that the analog circuit is composed of a differential circuit, and has a first element group including a correction element and a test element connected to the positive side input path of the differential circuit, and a second element group including a correction element and a test element connected to the negative side input path of the differential circuit; the first element group and the second element group constitute a correction element group and a test element group; the self-diagnostic code generation circuit has a first group of inspection modes for inspecting the first element group and a second group of inspection modes for inspecting the second element group, and performs inspections on the first element group and the second element group, respectively.

[0401] Here, it may also be that the analog circuit has a redundant structure including a first element group including a correction element group and an inspection element group, and a second element group with the same weight as the first element group, which belongs to one node; and the self-diagnostic code generation circuit has a first group of inspection modes for inspecting the first element group and a second group of inspection modes for inspecting the second element group, and inspects the first element group and the second element group respectively.

[0402] Here, it can also be that, in the first group of inspection modes, for the first element group, the self-diagnosis code generation circuit sets the first bit signal for controlling the correction element of the inspection object to 1 or 0, sets the second correction bit signal group for controlling the correction element whose adjustment weight is smaller than the first correction element to the inverted logic value of the first bit signal, sets the inspection bit signal for controlling the inspection element to the inverted logic value of the first bit signal, sets the bit signals other than the inverted logic value to a specified fixed signal, and outputs it, and for the second element group, outputs the optimal correction code to minimize the quantization error of the quantizer; in the first group of inspection modes, the digital circuit generates the first error signal based on the error signal of the error detection circuit, and regarding the control code of the first element group, sets the first A one-bit signal is set to the inverted logic value of the bit signal in the first step, a second bit signal group is set to the inverted logic value of the bit signal in the first step, a check bit for controlling the check element is set to the inverted logic value of the bit signal in the first step, and the other bit signals are set to specified fixed signals for output. Moreover, for the second element group, the output optimal correction code is maintained, and a second error signal is generated as the output of the error detection circuit. At the transition point of the quantizer where the quantization error is minimized, the magnitude of the first error signal and the second error signal is determined, thereby checking whether the weight is below the specified value. In the second group of inspection modes, the relationship between the first element group and the second element group in the first group of inspection modes is replaced and the same processing is performed.

[0403] Here, the data converter may also be an analog-to-digital converter.

[0404] Here, the analog-to-digital converter may include one or more comparators, and the comparator may be composed of a differential circuit. In order to correct the offset of the comparator, a correction element group and an inspection element group are respectively provided in the positive transmission path and the negative transmission path within the differential circuit. The correction elements included in the correction element groups of the positive transmission path and the negative transmission path are respectively inspected based on the inspection element groups.

[0405] <Third Embodiment>

[0406] Hereinafter, the circuit configuration and operation of the third embodiment will be described with reference to the drawings.

[0407] The inspection and diagnosis of the offset correction element of the comparator is described.

[0408] The structure is described below.

[0409] In the third embodiment, similarly to the second embodiment, a successive AD converter ( Figure 2 ) as an example, a structural example in which the correction amplitude of the correction element group for comparator offset correction is taken as the inspection / diagnosis object is described.

[0410] The structure is the same as that of the second embodiment, and only the digital part is different.

[0411] As a problem of the second embodiment, by comparing the weights between adjacent spaces (for example, between control codes (1000) and (0111)) based on the inspection element, the relative accuracy between the correction elements can be confirmed. However, when the inspection element itself fails, it is divided into a case where the amplitude is reduced and a case where it is excessive.

[0412] In the second embodiment, for example, when the inspection element is larger than the correction element by 1 LSB and the inspection / diagnosis is passed (normal determination), the width becomes large and the resolution becomes coarser than the design assumption.

[0413] Furthermore, when the inspection element passes inspection / diagnosis because the inspection element is 1 LSB smaller than the correction element, the resolution is fine enough but the width is smaller than the design assumption, and the width is too narrow to correct the deviation caused by manufacturing variation.

[0414] The purpose of the present invention is to inspect / diagnose a correction element, so the analog circuit structure is not limited. As an example, Figure 3 The comparator is described below.

[0415] As Figure 3 The structure of the comparator offset control unit 132 is used in the present invention Fig.14 The circuit diagram shown.

[0416] The following is based on Fig.23A and Fig. 23B Flow chart, see Figure 2 and Fig.24 The circuit structure uses Fig.25 The schematic diagram of the present invention is used to illustrate the order of amplitude checking of the present invention.

[0417] First, an overview is given. The main idea is to use the internal DAC of the successive comparator ADC to generate two voltages (±Δ), control the correction element in the comparator to correct the voltage, and store the two control codes in a register and compare them to perform an inspection / diagnosis of the absolute amount of correction, such as how much code is equivalent to the generated voltage.

[0418] In sequence 211, it is determined whether to inspect the P-side correction element or the N-side correction element.

[0419] In this embodiment, the amplitude inspection / diagnosis on the P side will be described as an example.

[0420] In sequences 212 and 213, for the P-side correction element control code CCp_TEST, the fixed code ((1000)(0), (mmmm)(n), m is the bit signal of each correction element, and n is the bit signal for the inspection element) output from the MSB fixed code register 235 is output via selectors 234C and 234A.

[0421] On the other hand, for the N-side correction element control code CCn_TEST, the binary search control unit 247 that receives the error signal updates the output of the search code register 238 to minimize the quantization error (makes the CDF close to 0.5), saves the optimal code in the optimal code register 244, and saves the minimum value of the error signal in the minimum error register 241.

[0422] The procedures 214, 215, and 216 are the same as those in the embodiment, and are the procedures for determining whether the CDF is close to 0.5 and determining whether the resolution is normal or abnormal. They can be omitted. Fig.24 This part is omitted for simplicity of explanation.

[0423] In sequences 217 and 218 , as an example, a control code for applying (+Δ) corresponding to +3.0 mV to the comparator inputs (topPlateP, topPlateN) is selected from the DAC direct control mode memory unit and output via selectors 254 and 255 .

[0424] The P-side control code is controlled using the binary search control unit 245 and the search code register 236 so as to cancel out the voltage.

[0425] The P-side control code with the smallest quantization error (CDF is around 0.5) is held by the optimal code register 242 and stored in the first code result register 248 .

[0426] At this time, regarding the N-side control code, the output of the optimum code register 244 is output via the selectors 234D and 235B.

[0427] In sequences 219 and 220 , as an example, a control code for applying (−Δ) corresponding to −3.0 mV to the comparator inputs (topPlateP, topPlateN) is selected from the DAC direct control mode memory unit and output via selectors 254 and 255 .

[0428] The binary search control unit 246 and the search code register 237 are used to control the P-side control code so as to cancel out the voltage.

[0429] The P-side control code with the smallest quantization error (CDF is around 0.5) is held by the optimal code register 243 and stored in the first code result register 249 .

[0430] At this time, regarding the N-side control code, the output of the optimum code register 244 is output via the selectors 234D and 235B.

[0431] In sequence 221 , the control code difference between the first code result and the second code result is calculated, and the amplitude determination unit 251 determines whether the difference is between the allowable minimum value RMIN and the allowable maximum value RMAX held by the amplitude specification value register 250 .

[0432] When the amplitude is normal, it moves to the order 222 or 223.

[0433] If the amplitude is defective, the process proceeds to sequence 224, and an amplitude error signal is output as a self-diagnosis output signal.

[0434] exist Fig.25 A schematic diagram of this embodiment is shown in FIG.

[0435] When the test voltage +Δ is applied, the P-side control code is ((1011)(0)).

[0436] On the other hand, when the test voltage -Δ is applied, the P-side control code is ((0011)(0)).

[0437] At this time, the code difference is equivalent to (1000), which is a normal determination.

[0438] In this example, a voltage equivalent to half the MSB of the correction amplitude is generated by the DAC, and control codes equivalent to MSB±(MSB / 2) are calculated by binary search to obtain the code difference, thereby achieving the correspondence between the applied voltage and the control code, so that the absolute amount of the control code can be checked / diagnosed.

[0439] Therefore, by combining the inspection / diagnosis of relative accuracy in the second embodiment and the inspection / diagnosis of absolute value in the third embodiment, it is possible to inspect / diagnose both the resolution and the width of the correction element.

[0440] As described above, in the semiconductor circuit of the third embodiment, the data converter has an input switching unit for switching whether the signal input to the data converter is used as a measured signal or as a reference signal; the self-diagnostic code generation circuit has an optimal correction code output mode for outputting an optimal correction code with a minimum quantization error; during inspection, the digital circuit is set to the optimal correction code output mode, and the first reference signal is selected through the input switching unit, and the optimal correction code is obtained as the first optimal correction code, and the optimal correction code is set to the optimal correction code output mode, and the second reference signal is selected through the input switching unit, and the optimal correction code is obtained as the second optimal correction code, and the difference between the first optimal correction code and the second optimal correction code is calculated to perform correction amplitude diagnosis of the correction element group.

[0441] <Fourth Embodiment>

[0442] Hereinafter, the circuit configuration and operation of the fourth embodiment will be described with reference to the drawings.

[0443] The inspection and diagnosis of the offset correction element of the comparator is described.

[0444] The structure is described below.

[0445] In the fourth embodiment, similarly to the second and third embodiments, a successive AD converter ( Figure 2 ) as an example, the following describes a structural example in which the function of the correction element group for comparator offset correction is the object of inspection / diagnosis, assuming that only the digital part is different.

[0446] The method of inspecting the weight of the correction element described in the second embodiment has a problem that it takes a long time to increase the number of repeated measurements in order to remove noise in order to inspect the accuracy of the correction element.

[0447] On the other hand, in the third embodiment, a method of eliminating the obvious initial failure in the simplest way is provided.

[0448] The purpose of the present invention is to inspect / diagnose the correction element, so the analog circuit structure is not limited. As an example, Figure 3 The comparator is described below.

[0449] As Figure 3 The structure of the comparator offset control unit 132 is used in the present invention Fig.14 The circuit diagram shown.

[0450] The following is based on Fig.26 Flow chart, see Figure 2 and Fig. 27 The circuit structure uses Fig.28 The schematic diagram of the present invention is used to illustrate the order of functional inspection of the present invention.

[0451] First, let me give you an overview. The gist is that there is a comparator decision point near the minimum quantization error (CDF near 0.5) where the internal state can be inferred by binary search. If the bits of the control code (correction code) at that point in time are inverted, the CDF deviates from 0.5 by a certain amount. However, since the sign and direction of the deviation are known, it is possible to detect driver circuit failures and device failures (non-response, offset correction does not change to the expected sign, etc.) inside the analog circuit (in Fig.28 Schematic diagram is shown in ).

[0452] In the sequence 261, 262, 263, the selectors 284C, 284D, and the demultiplexer 295 are switched to STEP1.

[0453] In this embodiment, a code mapping table combining the P side and the N side is used.

[0454] As an example, use Fig.10 The mapping table.

[0455] Since there are 4 bits on the P side and 1 bit on the N side, management can be performed using a control signal equivalent to 5 bits.

[0456] A code mapping unit (290A, 290B) is provided for converting the signal corresponding to 5 bits into a signal corresponding to positive and negative 4 bits.

[0457] The binary search control unit 293 and the search code register 291 which receive the error signal, the above-mentioned code mapping units 290A and 290B, and the positive side search code register 286 and the negative side search code register 287 which hold the positive and negative search codes respectively, perform the binary search and hold the result, and determine the control code to correct the manufacturing deviation Voff (this order is the same as the correction execution block in the correction code generation unit, so the functional blocks can be shared).

[0458] In addition, the error signal is stored in the first accumulation result register 297 as the first CDF result (CDF1).

[0459] In the sequence 264, one is selected as to which bit (from MSB to LSB and check element) of which polarity (P side, N side) is to be checked / diagnosed.

[0460] The bit information selected as the inspection target is output from the inspection bit selection unit 285 to the bit inversion units 301A and 301B as a bit inversion signal.

[0461] In the sequences 265 and 266, the selectors 284C and 285B and the demultiplexer 295 are switched to STEP 2, and the CDF in the state where the bit to be inspected is inverted is measured.

[0462] At this time, the output from the optimal code register 292 storing the optimal code obtained by the binary search is supplied to the positive optimal code register 288 and the negative optimal code register 289 via the code mapping unit 290B, and supplied to the control code of the comparator via the selectors 284C and 284D.

[0463] The CDF result is stored in the second accumulation result register 298 via the demultiplexer 295 as the second CDF result (CDF2).

[0464] In sequences 267, 268, and 269, self-diagnosis is performed.

[0465] The output of the first accumulation result register 297 and the second accumulation result register 298 are output to the subtractor 296 , and the subtraction result is supplied to the jump determination unit 300 .

[0466] The jump determination unit 300 receives the output of the jump specification value register 299 and determines whether the sign relationship between CDF1 and CDF2 is in an appropriate direction.

[0467] Supplementary explanation on the sign relationship between CDF1 and CDF2.

[0468] In the present embodiment, Vin is 0, Vcalp and Vcalm are correction amounts, and Voff is a manufacturing offset, so the actual comparator input VinCP is (-Voff-Vcalp+Vcalm).

[0469] Here, the functions of Vcalp and Vcalm are "opposite sign relationship".

[0470] That is, if a correction bit on the P side is changed from 0 to 1, VinCP decreases, so CDF2 should decrease by a specified amount (should be lower than 0.5); if it is changed from 1 to 0, VinCP increases, so CDF2 should increase by a specified amount (should be higher than 0.5).

[0471] On the other hand, if a correction bit on the N side is changed from 0 to 1, VinCP increases, so CDF2 should increase by a specified amount (should be higher than 0.5). If it is changed from 1 to 0, VinCP decreases, so CDF2 should decrease by a specified amount (should be lower than 0.5).

[0472] As can be seen from this, by inputting information (PosNegFlag) on ​​which polarity of the comparator is checked to the jump determination unit, it is possible to determine an abnormality.

[0473] Regarding the jump specification value, a value with a predetermined amount of offset (threshold) set from 0.5 in the expected sign direction is set. By observing the change in CDF2, it can be determined whether the driver circuit and the correction capacitor element that drive the correction capacitor are functioning normally.

[0474] In this embodiment, two values ​​that are different by a predetermined amount are compared and determined. Therefore, unlike the second embodiment, accuracy determination is not performed, and the number of repeated measurements can be reduced. By performing this inspection first, inspection time can be shortened.

[0475] Fig.29 This shows an example of the inspection / diagnosis sequence.

[0476] In sequence 311, the jump check / diagnosis described in the fourth embodiment is performed ( Fig.26 , Fig. 27 ).

[0477] Compared with the weight inspection, the measurement time can be shortened, and defective products in the order 311 can be removed as defective products.

[0478] Order 312( Fig.15A and Fig. 15B , Fig.16 ) is a weight check of each correction element described in the second embodiment, and the sequence 313 ( Fig.23A and Fig. 23B , Fig.24 ) is the check of the correction range described in the fourth embodiment.

[0479] Through this series of inspections, the functionality and accuracy of each correction component can be guaranteed.

[0480] As described above, in the semiconductor circuit of the fourth embodiment, the self-diagnostic code generating circuit has an optimal correction code output mode for receiving an error signal and outputting an optimal correction code so as to minimize the quantization error of the quantizer, and a logic inversion code output mode for outputting a logic inversion code in which the first bit signal in the optimal correction code for controlling the correction element to be inspected is logically inverted. During inspection, the digital circuit is set to the optimal correction code output mode, the optimal correction code is supplied to the analog circuit, and a first error signal is generated based on the error signal from the error detection circuit. The circuit is set to the logic inversion code output mode, the logic inversion code is supplied to the analog circuit, and a second error signal is generated based on the error signal from the error detection circuit. The magnitude relationship between the first error signal and the second error signal is compared, and fault diagnosis of the correction element to be inspected is performed.

[0481] <Fifth Embodiment>

[0482] Hereinafter, the circuit configuration and operation of the fifth embodiment will be described with reference to the drawings.

[0483] The inspection and diagnosis of the gain correction element of the residual amplifier will be described.

[0484] In the fifth embodiment, a pipeline AD converter 320 is taken as an example to describe a configuration example in which a gain correction element of a residual amplifier is an object of inspection and diagnosis.

[0485] The structure is described below.

[0486] exist Fig.30 In the example, the analog part is composed of a sample-and-hold circuit 323 , a first sub-ADC 324 , a residual amplifier 325 , and a second sub-ADC 326 .

[0487] The sample-and-hold circuit 323 samples the differential signal (VINP, VINM) during normal operation, and samples the midpoint reference voltage VCM (equivalent to the differential signal zero) during correction, inspection, or diagnosis.

[0488] The first sub-ADC 324 is taken as an example by Figure 2 The successive approximation ADC structure shown in the figure quantizes the sampled voltage (VINP, VINM) and maintains the residual voltage during normal operation. During correction / inspection / diagnosis, for the differential signal zero, the internal DAC voltage is controlled according to the code maintained in the DAC direct control mode memory unit 332 to generate a specified voltage, which is maintained as a residual.

[0489] The residual amplifier 325 amplifies the residual voltage held by the first sub-ADC 324 at a predetermined magnification after the AD conversion of the first sub-ADC is completed.

[0490] The second sub-ADC 326 is constituted by a successive approximation ADC as an example, and quantizes the voltage obtained by outputting the residual amplifier.

[0491] In a pipeline ADC, a high-power amplifier is required to maintain the magnification (gain) accuracy of the residual amplifier. However, with the development of low voltage and correction technology, low power consumption is being achieved by using open-loop integrating amplifiers such as those shown in Non-Patent Document 3.

[0492] Among them, the open-loop integrating amplifier has large gain variations due to manufacturing variations, but consumes low power.

[0493] Therefore, a correction technology based on a digital circuit is applied to the gain deviation of the residual amplifier to achieve both low power consumption and high accuracy.

[0494] As a representative example of the correction technology, there is a gain estimation method based on dither described in Non-Patent Document 1.

[0495] The internal DAC of the first sub-ADC is directly controlled to add a predetermined random voltage to the residual voltage, and an amount corresponding to the predetermined random voltage is subtracted from the voltage amplified by the residual amplifier using the internal DAC of the second sub-ADC.

[0496] Through this operation, the gain error remains in the residual voltage held by the second sub-ADC, and the information of the gain error mixed in the conversion result of the second sub-ADC is processed to estimate and correct the gain error of the residual amplifier.

[0497] Fig.31 2 is a circuit diagram showing an example of the residual amplifier 325 with a gain correction function.

[0498] The residual amplifier 325 includes a signal amplifying section 350 and an amplification time adjusting section 351 .

[0499] In the case of an open-loop integrating amplifier, the gain can be increased as the amplification time is longer, so the gain is adjusted by adjusting the amplification time.

[0500] exist Fig.32 An example of the amplification time adjustment unit 351 used in the present invention is shown in FIG.

[0501] The amplification time adjustment unit 351 includes a correction element group 354 and a test element group 355 .

[0502] The correction element group 354 is composed of MOS capacitor elements having a weight of 2 or less (≦2), and as an example, the inspection element group 355 is composed of MOS capacitor elements having the same weight as the LSB of the correction element group.

[0503] In the present invention, the size of the inspection element group is not limited to the above-mentioned size, and the same effect can be obtained as long as it is less than 1LSB of the correction element group.

[0504] The correction component group is controlled by the control code (CG3p, CG2p, CG1p, CG0p), and the inspection component group is controlled by the control code (CGdp).

[0505] In the following, it is assumed that when the bit signal of the control code is “1”, the capacitive element is enabled and the gain is increased, and when the bit signal of the control code is “0”, the capacitive element is disabled and the gain is decreased.

[0506] As a method of recording the control code, assume that (CG3p, CG2p, CG1p, CG0p)(CGdp) adopts the recording method of (xxxx)(y).

[0507] The following describes the operation.

[0508] For the weight of each correction element in the correction element group, use the same Fig.15A and Fig. 15B The weights of the comparator correction elements shown in the figure are checked / diagnosed in the same order.

[0509] That is, the sampling voltage is set to VCM. As an example of MSB correction element inspection, in the first sequence, the self-diagnostic code generation circuit 337 sets (CG3p, CG2p, CG1p, CG0p)(CGdp) to (1, 0, 0, 0)(0), and the gain error measurement method same as the above-mentioned dithering method is used to obtain the AD conversion result (multiple bits of quantizer output result) of the second sub-ADC326, which is accumulated and set as the first accumulated result.

[0510] Furthermore, in the second sequence, the self-diagnostic code generation circuit 337 sets (CG3p, CG2p, CG1p, CG0p)(CGdp) to (0, 1, 1, 1)(1), and uses the same gain measurement method as the above-mentioned dithering method to obtain the AD conversion result of the second sub-ADC326, which is accumulated and set as the second accumulated result.

[0511] The first integrated result is compared with the second integrated result, and the weight error of the gain correction element is measured, and a judgment is made by a self-diagnosis circuit.

[0512] The same method can be used to diagnose / check weights below MSB.

[0513] Here, attention is not paid to inspection / diagnosis near the optimum gain setting (gain setting where the first sub-ADC and the second sub-ADC are connected while maintaining linearity), so the CDF of the subsequent comparator is not limited to near 0.5, and AD conversion is required for error measurement for inspection / diagnosis.

[0514] That is, the residual voltage mixed with the gain error may be larger than 1 LSB of the second sub-ADC in some cases, and AD conversion (quantization) using a plurality of comparators is required for weight measurement.

[0515] In the case of the offset correction element weight check of the comparator, only one quantizer output result (the circuit of the corrected comparator itself) is used. In contrast, in the weight check of the gain correction element of the amplifier in this embodiment, inspection / diagnosis is performed based on the cumulative result of multiple quantizer output results of the second sub-ADC.

[0516] The weight determination order of the comparator ( Fig.15A The order of 153 and Fig. 15B In the case of residual amplifier gain error measurement, by saving and replacing the accumulated value of the AD conversion result (multiple quantizer output results) of the second sub-ADC into a register, it is possible to Fig.15A and Fig. 15B In the same order, the gain correction element of the residual amplifier is checked / diagnosed.

[0517] As described above, in addition to the gain correction element of the residual amplifier, there is also a check element, which has the following effect: by using the input code generation for inspection / diagnosis based on the self-diagnostic code generation circuit and the accumulated value of the AD conversion result of the sub-ADC in the later stage of the pipeline, the weight of each gain correction element can be checked / diagnosed.

[0518] As described above, in the semiconductor circuit of the fifth embodiment, the self-diagnosis code generating circuit has a first weight check code output mode and a second weight check code output mode; in the first weight check code output mode, the first bit signal for controlling the first correction element of the inspection object is set to 1 or 0, the second correction bit signal group for controlling the correction element whose adjustment weight is less than the first correction element is set to the inverted logic value of the first bit signal, the check bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than these are set to specified fixed signals for output, and in the second weight check code output mode, the first The bit signal is set to the inverted logic value when the first weight check code output mode is set, the second bit signal group is set to the inverted logic value of the first bit signal, the check bit for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than this are set to specified fixed signals for output. During inspection, the digital circuit is set to the first weight check code output mode, and a first error signal is generated based on the error signal from the error detection circuit. It is set to the second weight check code output mode, and a second error signal is generated based on the error signal from the error detection circuit. The difference between the first error signal and the second error signal is calculated to perform weight diagnosis of the correction element group.

[0519] <Sixth Implementation Method>

[0520] Hereinafter, the circuit configuration and operation of the sixth embodiment will be described with reference to the drawings.

[0521] The inspection and diagnosis of the gain correction element of the residual amplifier will be described.

[0522] The structure is described below.

[0523] As a circuit structure, the block diagram of the fifth embodiment ( Fig.30 ) and the residual amplifier structure ( Fig.31 ), as the amplification time adjustment unit, using Fig.33 The zoom time adjustment section.

[0524] The amplification time adjustment unit 351 is composed of a first set element group 358 and a second set element group 359, which respectively include a correction element group (354, 356) and a test element group (355, 357).

[0525] The first set component group 358 is controlled by the control code (CG3p, CG2p, CG1p, CG0p) (CGdp), and the second set component group 359 is controlled by the control code (CG3n, CG2n, CG1n, CG0n) (CGdn).

[0526] The following describes the operation.

[0527] For the weight of each correction element in the correction element group, use the same Fig.15A and Fig. 15B The weights of the comparator correction elements shown in the figure are checked / diagnosed in the same order.

[0528] In the present embodiment, since there are two sets of the first set element group 358 and the second set element group 359 , it is possible to perform inspection and diagnosis by setting the optimum gain.

[0529] For example, when checking the MSB of the first set of element groups, as the first order, the control code (CG3p, CG2p, CG1p, CG0p)(CGdp) is set to (1, 0, 0, 0)(0), and the control code (CG3n, CG2n, CG1n, CG0n)(CGdn) is set to the code (y, y, y, y)(0) for which the optimal value (optimal gain setting) is found by binary search.

[0530] As the second order, the control code (CG3p, CG2p, CG1p, CG0p)(CGdp) is set to (1, 0, 0, 0)(0), and the control code (CG3n, CG2n, CG1n, CG0n)(CGdn) is set to (y, y, y, y)(0), and the initial quantizer output result of the second sub-ADC326 is accumulated as the first accumulated result.

[0531] As the third order, the control code (CG3p, CG2p, CG1p, CG0p)(CGdp) is set to (0, 1, 1, 1)(1), and the control code (CG3n, CG2n, CG1n, CG0n)(CGdn) is set to (y, y, y, y)(0), and the initial quantizer output result of the second sub-ADC326 is accumulated as the second accumulated result.

[0532] By comparing the first integration result with the second integration result, the weight of the correction element of the amplifier gain element can be checked.

[0533] Compared with the fifth embodiment, the sixth embodiment can measure weights near the optimum gain, so only one quantizer output (processing of 1 bit) is required, so the scale of the inspection / diagnosis circuit can be reduced.

[0534] As described above, in the semiconductor circuit of the sixth embodiment, the self-diagnosis code generating circuit has a first weight check code output mode and a second weight check code output mode. In the first weight check code output mode, the first bit signal for controlling the first correction element of the inspection object is set to 1 or 0, the second correction bit signal group for controlling the correction element whose adjustment weight is less than the first correction element is set to the inverted logic value of the first bit signal, the check bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than these are set to specified fixed signals for output. In the second weight check code output mode, the first The bit signal is set to the inverted logic value when the first weight check code output mode is set, the second bit signal group is set to the inverted logic value of the first bit signal, the check bit for controlling the inspection element is set to the inverted logic value of the first bit signal, and the bit signals other than this are set to specified fixed signals for output. During inspection, the digital circuit is set to the first weight check code output mode, and a first error signal is generated based on the error signal from the error detection circuit. It is set to the second weight check code output mode, and a second error signal is generated based on the error signal from the error detection circuit. The difference between the first error signal and the second error signal is calculated to perform weight diagnosis of the correction element group.

[0535] Here, it is also possible that the analog circuit is composed of a differential circuit, and has a first element group including a correction element and a test element connected to the positive side input path of the differential circuit, and a second element group including a correction element and a test element connected to the negative side input path of the differential circuit, the first element group and the second element group constitute a correction element group and a test element group, and the self-diagnostic code generation circuit has a first group of inspection modes for inspecting the first element group and a second group of inspection modes for inspecting the second element group, and the first element group and the second element group are inspected separately.

[0536] <Seventh Embodiment>

[0537] Hereinafter, the circuit configuration and operation of the seventh embodiment will be described with reference to the drawings.

[0538] Inspection and diagnosis of the offset correction element of the residual amplifier will be described.

[0539] As the circuit structure, use the block diagram ( Fig.30 ), and the residual amplifier structure ( Fig.31 ) after the signal amplifier is deformed Fig.34 The signal amplifier shown in Fig.35 The offset control section of the residual amplifier is shown.

[0540] exist Fig.34 In the signal amplifier shown, the NMOS transistor is variably controlled for offset correction.

[0541] That is, there is a differential pair 371 with an offset adjustment function.

[0542] exist Fig.35 In the offset control unit shown, switching between the inspection element groups 374 and 375 and the correction element groups 372 and 373 is selected by a driver signal (not shown).

[0543] By adjusting the positive and negative balance of the differential pair size, the offset is corrected and controlled.

[0544] In this circuit, since the inspection element groups 374 and 375 are provided, the weight of each correction element can be inspected and diagnosed by using the same procedure as in the second embodiment and the integrated value of the conversion result of the second sub-ADC 326 .

[0545] In addition to adjusting the offset Fig.34 , Fig.35 In addition to the method of balancing the MOS of the differential pair used as shown, it is also possible to Fig.34 The offset can be adjusted by adding a variable capacitor to the differential pair output, or by adjusting the back gate of the MOS. Regardless of which offset adjustment method is adopted, the inspection / diagnosis circuit of this embodiment can inspect the weight of the correction element.

[0546] As described above, in the semiconductor circuit of the seventh embodiment, the analog / digital converter is a pipeline analog / digital converter, which has a residual amplifier and one or more comparators. The residual amplifier is composed of an open-loop integrating amplifier. As a circuit structure for adjusting the offset of the residual amplifier, a correction element group is provided on the positive side and the negative side of the output inside the differential circuit respectively. As a circuit structure for adjusting the offset by balancing the positive and negative, the correction element group is checked using the accumulated result of the comparator.

[0547] <Eighth Implementation Method>

[0548] Hereinafter, the circuit configuration and operation of the eighth embodiment will be described with reference to the drawings.

[0549] The inspection and diagnosis of the correction element of the DAC capacitor for correcting the linearity of the DAC will be described.

[0550] As a circuit structure, using Fig.36 As the correction part, use Fig.37 circuit.

[0551] The analog circuit block configuration is the same as that of the second embodiment, but the DAC portion is different.

[0552] The MSB capacitance (397A, 397B) of the DAC is set to a value (8C-Δ) obtained by subtracting Δ from a capacitance value as a desired value, and a correction capacitance (398A, 398B) capable of switching in conjunction with the MSB capacitance is provided.

[0553] Correction capacitor (398A, 398B) uses Fig.37 In the structure shown, the correction capacitor is switched in conjunction with normal DAC operation by obtaining the signal supplied from the DAC control unit and the NAND logic of the control code (CD3p, CD2p, CD1p, CD0p) (CDdp), (CD3n, CD2n, CD1n, CD0n) (CDdn).

[0554] If more correction capacitors (398A, 398B) are selected, the apparent MSB capacitance increases, the MSB step voltage increases, and the linearity can be adjusted.

[0555] This correction method is also applicable to the MSB and below of the DAC.

[0556] As a method of inspection / diagnosis, the weight inspection / diagnosis can be performed in the same order as the weight inspection / diagnosis method of the comparator in the second embodiment and the weight inspection / diagnosis method of the amplifier gain in the fifth embodiment.

[0557] Specifically, when inspecting the MSB of the P-side correction element, (CD3p, CD2p, CD1p, CD0p)(CDdp) is set to (1, 0, 0, 0)(0), and (CD3n, CD2n, CD1n, CD0n)(CDdn) is set to the optimal value determined by binary search (the transition point where the quantization error of the comparator is the smallest) to obtain a first cumulative result, and (CD3p, CD2p, CD1p, CD0p)(CDdp) is set to (0, 1, 1, 1)(1), and (CD3n, CD2n, CD1n, CD0n)(CDdn) is set to the optimal value to obtain a second cumulative result. By comparing the first cumulative result with the second cumulative result, relative weight inspection / diagnosis between the correction elements based on the inspection element can be performed.

[0558] As described above, in the semiconductor circuit of the eighth embodiment, the analog / digital converter is a successive approximation type analog / digital converter, and includes an internal digital / analog converter having a differential circuit structure with a plurality of capacitors (M) in each of the positive-side transmission path and the negative-side transmission path, and one or more comparators. It includes a correction element group and an inspection element group that respectively correct the linearity of N (N < M) of the plurality of capacitors, and uses the cumulative result of the comparator to respectively inspect the correction elements for the internal digital / analog converter in the positive-side correction element group and the negative-side correction element group.

[0559] <Ninth Embodiment>

[0560] Hereinafter, the circuit structure and operation of the ninth embodiment will be described with reference to the drawings.

[0561] Describe the inspection / diagnosis of the DAC gain correction element for correcting the ADC gain.

[0562] As the circuit structure, use Fig.38 of the block diagram, and as the correction unit, use Fig.39 of the circuit.

[0563] The analog circuit block structure is the same as that of the second embodiment, but the DAC part is different.

[0564] For the binary capacitor arrays (427A, 428A, 429A, 427B, 428B, 429B) of the DAC, correction capacitors (430A, 430B) for adjusting the DAC gain are provided.

[0565] The correction capacitors (430A, 430B) adopt Fig.39 the structure shown, and are controlled by the signals supplied from the DAC control unit and the control codes (CE3p, CE2p, CE1p, CE0p) (CEdp), (CE3n, CE2n, CE1n, CE0n) (CEdn).

[0566] In the normal DAC operation, since this correction capacitor is a capacitor stably connected to the VCM potential, the more correction capacitors connected, the lower the output voltage of the DAC and the higher the ADC gain.

[0567] As a method of inspection / diagnosis, the weight inspection / diagnosis can be performed in the same order as the weight inspection / diagnosis of the comparator in the second embodiment and the weight inspection / diagnosis method of the amplifier gain in the fifth embodiment.

[0568] As described above, in the semiconductor circuit of the ninth embodiment, the analog / digital converter is a successive approximation type analog / digital converter, and includes an internal digital / analog converter having a differential circuit structure with a plurality of capacitors (M capacitors) provided in a positive-side transmission path and a negative-side transmission path, and one or more comparators. The correction element group is used for gain correction for N (N < M) of the plurality of capacitors, and checks the correction elements for the internal digital / analog converter for the positive-side transmission path and the negative-side transmission path respectively using the cumulative result of the comparator.

[0569] <Tenth Embodiment>

[0570] Hereinafter, the circuit structure and operation of the tenth embodiment will be described with reference to the drawings.

[0571] Describe the inspection / diagnosis of correction elements used for delay control in a TD converter (time-to-digital converter).

[0572] Describe the following: The present invention can be applied not only to an AD converter that compares an analog signal with a specified voltage and quantifies it, but also to the inspection / diagnosis of correction elements in a TD converter that compares an input clock with a reference clock and performs time quantization.

[0573] As a circuit structure, an example in which the TD converter shown in Patent Document 6 is modified is shown.

[0574] The basic operation and function are the same as those in Patent Document 6, but the functional blocks for inspection / diagnosis are different.

[0575] In Fig.40 the circuit block of the present invention is shown, and in Fig.41 the variable delay control unit is shown.

[0576] In the present invention, an inspection element group 451 is added to the variable delay control unit (DL0, DL1, DL2, DL3), and a block for correction / inspection / diagnosis having a selector 441, a correction code generation circuit 442, a self-diagnosis code generation circuit 443, an error detection circuit 444, and a self-diagnosis circuit 445 is added.

[0577] As Fig.41 shown, the variable delay control unit includes a correction element group 450 and an inspection element group 451, and adjusts the bias current amount by control codes (CT3, CT2, CT1, CT0) (CTd) to control the delay amount.

[0578] A bias current source is provided by MOS transistors.

[0579] As a method of inspection / diagnosis, the weight inspection / diagnosis can be performed in the same order as the weight inspection / diagnosis method of the comparator in the second embodiment and the weight inspection / diagnosis method of the amplifier gain in the fifth embodiment.

[0580] Specifically, when inspecting the MSB of the correction element, (CT3, CT2, CT1, CT0) (CTd) is set to (1, 0, 0, 0) (0), and the quantization information obtained from the trigger circuit (FF0, FF1, FF2, FF3) is accumulated to obtain a first accumulation result. (CT3, CT2, CT1, CT0) (CTd) is set to (0, 1, 1, 1) (1), and the quantization information obtained from the trigger circuit (FF0, FF1, FF2, FF3) is accumulated to obtain a second accumulation result. By comparing the first accumulation result with the second accumulation result, relative weight inspection / diagnosis between the correction elements based on the inspection element can be performed.

[0581] As described above, in the semiconductor circuit of the tenth embodiment, the measured signal is set to a pulse signal that takes 1 or 0, the data converter is a time / digital converter that compares the phase difference between the pulse signal and the reference clock signal and converts it into a digital signal, and the correction element group corrects the transition timing of 1 and 0 of the pulse signal.

[0582] Here, it can also be that the time / digital converter has: a multi-stage delay circuit whose delay amount can be controlled; a correction element group that corrects the delay amount of the delay circuit; an inspection element group that inspects the correction element group; a trigger group that takes in the logic of each output of the delay circuit corresponding to the edge timing of the above-mentioned pulse signal, thereby performing a comparison operation between the pulse signal and the delay stage output; a counter that obtains a cumulative result of accumulating the digital output signals of the trigger group; and an encoder that takes in the digital output signals of the trigger group and encodes them; the time / digital converter performs self-diagnosis of the correction element group based on the cumulative result.

[0583] <Eleventh Embodiment>

[0584] In the second embodiment, a case where a MOS variable capacitance capacitor is a correction element is shown. Fig.14 ), in the seventh embodiment, a case where the MOS differential pair array is a correction element is shown ( Fig.35 ), in the eighth embodiment, the capacitor array is shown as a correction element ( Fig.37 ), in the tenth embodiment, a current source array (actually an array of MOS transistors) is shown ( Fig.41 ).

[0585] As described above, various devices are applied to the correction element.

[0586] Hereinafter, an example of a correction element using a resistor will be described as an eleventh embodiment.

[0587] Fig.42 This is a circuit showing an example of a reference voltage circuit in the eleventh embodiment of the present invention.

[0588] The structure is described below.

[0589] The input resistor 458 (RI-Δ) and the feedback resistor 459 (RF) are connected in series, and their common connection point is connected to the inverting input terminal of the amplifier 455. The non-inverting input terminal of the amplifier 455 is connected to the reference voltage VCM, and the other end of the feedback resistor 459 is connected to the output of the amplifier 455.

[0590] The reference voltage VR is input to the input of the input resistor 458 .

[0591] In this way, an inverting amplifier structure is adopted to amplify the voltage level.

[0592] A correction element group 456 for fine adjustment and a correction element group 457 for inspecting the correction element group are connected in parallel to the input resistor 458 (RI-Δ). Whether the inputs of the correction element group and the inspection element group are set to VR or VCM is controlled by a control signal not shown, and the voltage level is corrected.

[0593] The weight inspection of the resistance of the correction element group 456 is performed by setting the input of 457 to be switchable between VR and VCM only during inspection and setting the input of 457 to VCM except during inspection.

[0594] The output voltage VREFOUT can be used to correct the characteristics of each analog block, for example, when used as a reference voltage of an AD converter to adjust a DAC gain or as a voltage for adjusting a bias current.

[0595] As a method of inspection / diagnosis, the weight inspection / diagnosis can be performed in the same procedure as the weight inspection / diagnosis method of the comparator in the second embodiment or the weight inspection / diagnosis method of the amplifier gain in the fifth embodiment.

[0596] The correction element group is inspected / diagnosed using the comparator and sub-ADC conversion results inside the AD converter that receives VREFOUT as a reference voltage.

[0597] In this way, the weight of the resistor used as the correction element can also be inspected and diagnosed by the method of the present invention.

[0598] As described above, in the semiconductor circuit of the eleventh embodiment, the correction element and the inspection element are constituted by at least one of a capacitor, a resistor, and a MOS transistor, and are used for correction of analog voltage or correction of time.

[0599] <Twelfth Implementation Method>

[0600] In the second embodiment, which targets the offset of the comparator, when inspecting the P-side correction element ( Fig.14 ) Using the inspection element on the N side, the same inspection / diagnosis can be performed based on the inspection element on the opposite polarity side.

[0601] exist Fig.43A and Fig.43B An example in which control is performed on the test elements of opposite polarity is shown in FIG.

[0602] exist Fig.43A and Fig.43B , an example of performing the MSB check on the P side is shown, but codes can also be generated for other bits using the same principle.

[0603] exist Fig.43A 2 shows the second embodiment, but the P-side inspection element is used as a reference for inspecting the P-side correction element.

[0604] On the other hand, Fig.43B A twelfth embodiment is shown in FIG. 1 , but an N-side correction element is used.

[0605] In order to make the correction amount Vcalp on the P side and the correction amount Vcalm on the N side "act with opposite signs" in the offset of the comparator, "1" is set to the check bit on the N side in the first fixed code.

[0606] This is equivalent to the effect of the code on the P side on the decimal number 8 minus the decimal number 1.

[0607] Next, in the second fixed code, "0" is set to the check bit on the N side.

[0608] This is equivalent to the code on the P side subtracting the decimal number 0 from the decimal number 7 (doing nothing).

[0609] Thus, by comparing the first integration result and the second integration result obtained by the first fixed code and the second fixed code, the weight of the MSB of the P-side correction element can be checked and diagnosed.

[0610] A circuit ( Fig.39 ) in the same manner, the same inspection / diagnosis can also be performed based on the inspection element on the opposite polarity side.

[0611] exist Fig.44A and Fig.44B An example of a case where the inspection element of the opposite polarity is controlled is shown in FIG.

[0612] exist Fig.44A and Fig.44B , an example of performing the MSB check on the P side is shown, but codes can also be generated for other bits using the same principle.

[0613] exist Fig.44A , a ninth embodiment is shown, but a P-side inspection element is used as a reference for inspecting the P-side correction element.

[0614] On the other hand, Fig.44B A twelfth embodiment is shown in FIG. 1 , but an N-side correction element is used.

[0615] When correction capacitors are provided on the positive and negative sides of the differential, such as a DAC gain correction element, the respective correction amounts "act with the same sign".

[0616] That is, no matter which polarity of the correction capacitor is increased, the DAC gain decreases.

[0617] Therefore, when a method is adopted in which the test element on the opposite polarity side is controlled, "0" is set to the test bit on the N side in the first fixed code.

[0618] This is equivalent to what the code on the P side does to the decimal number 8 plus the decimal number 0 (do nothing).

[0619] Next, in the second fixed code, "1" is set for the check bit on the N side.

[0620] This is equivalent to the code on the P side adding the decimal number 1 to the decimal number 7.

[0621] Thus, by comparing the first integration result and the second integration result obtained by the first fixed code and the second fixed code, the weight of the MSB of the P-side correction element can be checked and diagnosed.

[0622] As described above, when there are correction elements and test elements on both sides of the differential circuit, either polarity may be used as the test element, and a combination thereof may be used of course.

[0623] As described above, in the semiconductor circuit of the twelfth embodiment, the analog / digital converter is a pipeline analog / digital converter, which has a residual amplifier and one or more comparators, and the residual amplifier is composed of an open-loop integrating amplifier. As a circuit structure for adjusting the gain of the residual amplifier, it is set to have a circuit structure with a correction element group in each of the positive side transmission path and the negative side transmission path inside the comparator, or a circuit structure with a correction element group for adjusting the delay amount of the amplification time of the residual amplifier, and the digital circuit uses the accumulated result of the comparator to check the correction element group.

[0624] <Thirteenth Embodiment>

[0625] Hereinafter, the circuit configuration and operation of the thirteenth embodiment will be described with reference to the drawings.

[0626] The offset correction element of the comparator of the second embodiment is used as the inspection / diagnosis object. Fig.45 An example of an offset control unit of a comparator shown.

[0627] exist Fig.45 In this case, 1LSB of the correction element group is also used as the inspection element group.

[0628] In the case shown in the figure, although there is no means to inspect 2C of (LSB+1), it is possible to inspect / diagnose the capacitance weights of (LSB+2) or more (ie, (MSB-1) or more).

[0629] However, the ratio relationship of (6C, 3C, 2C, 1C) in the figure is equivalent to (3C, 1.5C, 1C, 0.5C), so it can be regarded as a correction capacitor array with a weight of less than 1.5 and the inspection element set to 0.5C.

[0630] On the other hand, since the inspection element is equivalent to 0.5C, there is a disadvantage that the correction range for the number of bits is reduced.

[0631] The embodiments of the present invention have been described above.

[0632] In addition, the present invention is not limited to the configuration of the above-described embodiment, and naturally includes various variations and modifications that can be made by those skilled in the art within the scope of the present invention.

[0633] As described above, in the semiconductor circuit according to the thirteenth embodiment, one or more correction elements in the correction element group are used also as test elements.

[0634] The semiconductor circuit of one or more forms of the present invention is described above based on the embodiment, but the present invention is not limited to the embodiment. As long as it does not deviate from the main purpose of the present invention, various forms after the present embodiment is applied to the embodiment that can be thought of by a person skilled in the art, or forms constructed by combining constituent elements of different embodiments can also be included in the scope of one or more forms of the present invention.

[0635] Industrial Applicability

[0636] The semiconductor circuit of the present invention can be used for a data converter such as an analog / digital converter, a time / digital converter, etc.

[0637] Marking Description

[0638] 100, 500, 510AD converter

[0639] 101, 111, 321, 381, 411, 501, 511 analog circuits

[0640] 102, 112, 322, 382, ​​412, 502, 512 digital circuits

[0641] 103, 447, 503, 513 encoder parts

[0642] 104, 119, 172, 231, 283, 334, 395, 425, 444, 504, 514 Error detection circuit

[0643] 105, 120, 171, 233, 282, 335, 396, 426, 445 self-diagnosis circuit

[0644] 106, 121, 336, 393, 423, 442, 515 Correction Code Generation Circuit

[0645] 107, 122, 170, 232, 281, 337, 394, 424, 443 self-diagnosis code generation circuit

[0646] 108, 123, 125, 180A, 180B, 180C, 180D, 234A, 234B, 234C, 234D, 254, 255, 284C, 284D, 333, 338, 389, 390, 419, 420, 441, 472 selector

[0647] 110, 380, 410 successive AD converters

[0648] 113, 323, 383, 413 sample and hold circuits

[0649] 114, 328, 385, 415DAC (digital / analog converter)

[0650] 115, 329, 386, 416 driver circuits

[0651] 116, 130, 327, 384, 414 comparators

[0652] 117, 340, 387, 417DAC control unit

[0653] 118, 253, 331, 339, 391, 421SAR Control Department

[0654] 124, 252, 332, 392, 422DAC direct control mode memory unit

[0655] 131 Differential amplifier

[0656] 132 Deviation control unit

[0657] 133 Differential latch circuit

[0658] 134 Correction capacitor control unit

[0659] 135, 140, 352, 354, 356, 372, 373, 400, 402, 435, 437, 456, 470 Correction component group

[0660] 136, 353 Correction element driver circuit

[0661] 137 Comparator Offset

[0662] 138, 139 Correction

[0663] 141, 355, 357, 374, 375, 401, 403, 436, 438, 457, 471 inspection component group

[0664] 150~163、210~226、260~271、310~314 Examination / diagnosis order

[0665] 173, 230, 280 status control unit

[0666] 181, 295 demultiplexer

[0667] 182 1st fixed code generation unit

[0668] 183 2nd fixed code generation unit

[0669] 184, 245, 246, 247, 293 binary search control unit

[0670] 185 1st fixed code register

[0671] 186 2nd fixed code register

[0672] 187, 236, 237, 238, 291 search code register

[0673] 188, 242, 243, 244, 292 optimal code registers

[0674] 189, 239, 240, 241, 294 minimum error register

[0675] 190, 285 Check bit selection unit

[0676] 191 Cumulative expected value register

[0677] 192 Totalizer

[0678] 193 1st cumulative result register

[0679] 194 2nd cumulative result register

[0680] 195CDF Specification Value Register

[0681] 196 Weight specification value register

[0682] 197CDF Judgment Department

[0683] 198 Weight Determination Department

[0684] 199, 200, 256, 296 subtractors

[0685] 235MSB fixed code register

[0686] 248 First code result register

[0687] 249 Second code result register

[0688] 250 Amplitude specification value register

[0689] 251 Amplitude determination unit

[0690] 286 Positive side search code register

[0691] 287 Negative side search code register

[0692] 288 Positive side optimal code register

[0693] 289 Negative side optimal code register

[0694] 290A, 290B code mapping unit

[0695] 297 1st cumulative result register

[0696] 298 2nd cumulative result register

[0697] 299 Jump specification value register

[0698] 300 Jump determination unit

[0699] 301A, 301B bit inversion unit

[0700] 320 pipeline AD converter

[0701] 324 First Sub ADC

[0702] 325 residual amplifier

[0703] 326 Second sub-ADC

[0704] 330 Pipeline Control Department

[0705] 350 Signal Amplifier

[0706] 351 Amplification Time Adjustment Department

[0707] 358 The first set of components

[0708] 359 Second set of components

[0709] 370 Signal Amplifier

[0710] 371 Differential Pair with Offset Adjustment

[0711] MSB Capacitors for 397A and 397B DACs

[0712] Correction capacitor section of 398A, 398B, 430A, 430B DAC

[0713] Binary Capacitance for 427A, 428A, 429A, 427B, 428B, 429B DACs

[0714] 440TD Converter (Time / Digital Converter)

[0715] 446 Edge Detection / Counter Circuit

[0716] 455 Amplifier

[0717] 458 Input resistance

[0718] 459 Feedback resistor

[0719] Comparator input voltage on the positive side of topPlateP

[0720] Comparator input voltage on the negative side of topPlateN

[0721] VRH High potential side reference voltage

[0722] VRL Low potential side reference voltage

[0723] VCM midpoint reference voltage

[0724] Control code for comparator offset correction capacitor on CCp positive side

[0725] Control code for comparator offset correction capacitor on the negative side of CCn

[0726] Positive side output of the differential amplifier of the Vgp comparator

[0727] The negative output of the differential amplifier of the Vgn comparator

[0728] CapP is the correction capacitor on the positive side of the comparator

[0729] CapN is the correction capacitor on the negative side of the comparator

Claims

1. A semiconductor circuit comprising a data converter for outputting a digital output signal corresponding to a measured signal, characterized in that: have: an analog circuit for quantizing the input signal to be measured; and A digital circuit outputs the above digital output signal; The above analog circuit has: A correction element group, including a correction element, the correction element is used to correct the nonlinearity occurring in the conversion process from the measured signal to the digital output signal in the analog circuit; as well as An inspection element group, including an inspection element, the inspection element is used to inspect the correction element; The digital circuit uses the inspection element group to inspect the correction element group; The digital circuit has: a self-diagnosis code generating circuit for generating a self-diagnosis code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; an error detection circuit for detecting a difference between a quantized output signal of the analog circuit output in accordance with the self-diagnosis code and a predetermined threshold value as an error signal; as well as A self-diagnosis circuit, based on the error signal, generates a self-diagnosis signal indicating a diagnosis result of the correction element group; The self-diagnosis code includes the first fixed code and the optimal value code; The first fixed code is a code for enabling one correction element selected as an inspection object from the correction element group and disabling the other correction elements and the inspection element; The optimal value code is a code that minimizes the error signal with respect to the first fixed code, and is generated by a binary search method; The self-diagnosis circuit calculates the integrated value of the error signal corresponding to the combination of the first fixed code and the optimal value code, determines whether the integrated value is within a specified range, and determines that the correction element group has a malfunction if it is not within the specified range.

2. A semiconductor circuit comprising a data converter for outputting a digital output signal corresponding to a measured signal, characterized in that: have: an analog circuit for quantizing the input signal to be measured; and A digital circuit outputs the above digital output signal; The above analog circuit has: A correction element group, including a correction element, the correction element is used to correct the nonlinearity occurring in the conversion process from the measured signal to the digital output signal in the analog circuit; as well as An inspection element group, including an inspection element, the inspection element is used to inspect the correction element; The digital circuit uses the inspection element group to inspect the correction element group; The digital circuit has: a self-diagnosis code generating circuit for generating a self-diagnosis code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; an error detection circuit for detecting a difference between a quantized output signal of the analog circuit output in accordance with the self-diagnosis code and a predetermined threshold value as an error signal; as well as A self-diagnosis circuit, based on the error signal, generates a self-diagnosis signal indicating a diagnosis result of the correction element group; The self-diagnosis code includes the first fixed code, the second fixed code and the optimal value code; The first fixed code is a code for enabling one correction element selected as an inspection object from the correction element group and disabling the other correction elements and the inspection element; The optimal value code is a code that minimizes the error signal with respect to the first fixed code, and is generated by a binary search method; The measured signal is a differential signal including a first polarity signal and a second polarity signal; The above correction element group includes: a first element group connected to a transmission path of the first polarity signal; and A second component group connected to the transmission path of the second polarity signal; The first fixed code corresponds to the first component group, and sets the second component group to be disabled; The second fixed code is a code for disabling one correction element selected as the inspection object in the first element group, enabling correction elements with a smaller weight than the correction element among other correction elements, and enabling the inspection element; The above optimal value code corresponds to the second component group, and the first component group is set to be disabled; The self-diagnostic circuit calculates a first cumulative value obtained by accumulating the error signal corresponding to the combination of the first fixed code and the optimal value code, calculates a second cumulative value obtained by accumulating the error signal corresponding to the combination of the second fixed code and the optimal value code, determines the size relationship between the first cumulative value and the second cumulative value, and determines that the correction element of the inspection object has a defect when the size relationship does not satisfy a specified condition.

3. The semiconductor circuit according to claim 1 or 2, characterized in that: The self-diagnostic circuit sequentially selects one correction element from the correction element group as an inspection object.

4. The semiconductor circuit according to claim 1 or 2, characterized in that: One or more correction elements in the correction element group also serve as the inspection element.

5. A semiconductor circuit comprising a data converter for outputting a digital output signal corresponding to a measured signal, characterized in that: have: an analog circuit for quantizing the input signal to be measured; and A digital circuit outputs the above digital output signal; The above analog circuit has: A correction element group, including a correction element, the correction element is used to correct the nonlinearity occurring in the conversion process from the measured signal to the digital output signal in the analog circuit; as well as An inspection element group, including an inspection element, the inspection element is used to inspect the correction element; The digital circuit uses the inspection element group to inspect the correction element group; The analog circuit includes a quantizer for quantizing the measured signal or the reference signal corrected by the correction element group and converting it into a quantizer output signal; The digital circuit has: An encoding unit converts the quantizer output signal into a digital output signal to which a predetermined weight is assigned and outputs the digital output signal; The error detection circuit outputs the accumulated result obtained by accumulating the difference between the output signal of the quantizer and the predetermined threshold value for multiple times as an error signal; a self-diagnosis code generating circuit for outputting a self-diagnosis code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; as well as A self-diagnosis circuit receives the error signal and outputs a self-diagnosis output signal indicating whether the correction element group is good or not; The self-diagnosis circuit performs self-diagnosis on each correction element of the correction element group; The self-diagnosis code generation circuit has: an optimal correction code output mode, receiving the error signal and outputting an optimal correction code to minimize the quantization error of the quantizer; and a logic inversion code output mode for outputting a logic inversion code in which a first bit signal for controlling a correction element to be inspected in the optimal correction code is logically inverted; The above digital circuit, During the inspection, the optimal correction code output mode is set, the optimal correction code is supplied to the analog circuit, and a first error signal is generated based on the error signal from the error detection circuit; Setting the logic inversion code output mode, supplying the logic inversion code to the analog circuit, and generating a second error signal based on the error signal from the error detection circuit; The magnitude relationship between the first error signal and the second error signal is compared to perform a fault diagnosis of the correction element to be inspected.

6. A semiconductor circuit comprising a data converter for outputting a digital output signal corresponding to a measured signal, characterized in that: have: an analog circuit for quantizing the input signal to be measured; and A digital circuit outputs the above digital output signal; The above analog circuit has: A correction element group, including a correction element, the correction element is used to correct the nonlinearity occurring in the conversion process from the measured signal to the digital output signal in the analog circuit; as well as An inspection element group, including an inspection element, the inspection element is used to inspect the correction element; The digital circuit uses the inspection element group to inspect the correction element group; The analog circuit includes a quantizer for quantizing the measured signal or the reference signal corrected by the correction element group and converting it into a quantizer output signal; The digital circuit has: An encoding unit converts the quantizer output signal into a digital output signal to which a predetermined weight is assigned and outputs the digital output signal; The error detection circuit outputs the accumulated result obtained by accumulating the difference between the output signal of the quantizer and the predetermined threshold value for multiple times as an error signal; a self-diagnosis code generating circuit for outputting a self-diagnosis code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; as well as A self-diagnosis circuit receives the error signal and outputs a self-diagnosis output signal indicating whether the correction element group is good or not; The self-diagnosis circuit performs self-diagnosis on each correction element of the correction element group; The self-diagnosis code generation circuit has a first weight check code output mode and a second weight check code output mode; In the first weight check code output mode, The first bit signal for controlling the first correction element to be inspected is set to 1 or 0, the second correction bit signal group for controlling the correction element having an adjustment weight smaller than that of the first correction element is set to the inverted logic value of the first bit signal, the inspection bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the other bit signals are set to predetermined fixed signals and output; In the second weight check code output mode, the first bit signal is set to the inverted logic value when the first weight check code output mode is set, the second bit signal group is set to the inverted logic value of the first bit signal, the check bit for controlling the check element is set to the inverted logic value of the first bit signal, and the bit signals other than this are set to a specified fixed signal for output; The above digital circuit, During the inspection, the first weighted check code output mode is set to generate a first error signal based on the error signal from the error detection circuit; Setting the second weight check code output mode to generate a second error signal based on the error signal from the error detection circuit; A difference between the first error signal and the second error signal is calculated to perform a weight diagnosis of the correction element group.

7. A semiconductor circuit comprising a data converter for outputting a digital output signal corresponding to a measured signal, characterized in that: have: an analog circuit for quantizing the input signal to be measured; and A digital circuit outputs the above digital output signal; The above analog circuit has: A correction element group, including a correction element, the correction element is used to correct the nonlinearity occurring in the conversion process from the measured signal to the digital output signal in the analog circuit; as well as An inspection element group, including an inspection element, the inspection element is used to inspect the correction element; The digital circuit uses the inspection element group to inspect the correction element group; The analog circuit includes a quantizer for quantizing the measured signal or the reference signal corrected by the correction element group and converting it into a quantizer output signal; The digital circuit has: An encoding unit converts the quantizer output signal into a digital output signal to which a predetermined weight is assigned and outputs the digital output signal; The error detection circuit outputs the accumulated result obtained by accumulating the difference between the output signal of the quantizer and the predetermined threshold value for multiple times as an error signal; a self-diagnosis code generating circuit for outputting a self-diagnosis code for enabling or disabling each correction element included in the correction element group and enabling or disabling each inspection element included in the inspection element group; as well as A self-diagnosis circuit receives the error signal and outputs a self-diagnosis output signal indicating whether the correction element group is good or not; The self-diagnosis circuit performs self-diagnosis on each correction element of the correction element group; The data converter includes an input switching unit that switches whether the signal input to the data converter is to be the measured signal or the reference signal. The self-diagnostic code generation circuit has an optimal correction code output mode for outputting an optimal correction code with the smallest quantization error of the quantizer; The above digital circuit, During the inspection, the optimal correction code output mode is set, and the first reference signal is selected by the input switching unit to obtain the optimal correction code as the first optimal correction code; The optimal correction code output mode is set, and the second reference signal is selected by the input switching unit to obtain the optimal correction code as the second optimal correction code; A difference between the first optimum correction code and the second optimum correction code is calculated to perform a correction range diagnosis of the correction element group.

8. The semiconductor circuit according to any one of claims 5 to 7, wherein: The quantizer has more than one comparator; The error detection circuit generates the error signal by integrating the output result of one comparator or the result of digitally calculating the output results of two or more comparators with predetermined weights as the quantizer output signal.

9. The semiconductor circuit according to any one of claims 5 to 7, wherein: One or more correction elements in the correction element group also serve as the inspection element.

10. The semiconductor circuit according to any one of claims 5 to 7, wherein: The correction element group comprises a plurality of correction elements to which weights are assigned; The inspection element has a weight that is equal to or smaller than a correction element corresponding to a minimum weight in the correction element group.

11. The semiconductor circuit according to any one of claims 5 to 7, wherein: The correction element and the inspection element are composed of at least one of a capacitor, a resistor, and a MOS transistor, and are used for correction of analog voltage or correction of time.

12. The semiconductor circuit according to any one of claims 5 to 7, wherein: The above analog circuit is composed of a differential circuit and has: A first element group includes a correction element and a test element connected to the positive input path of the differential circuit; as well as A second element group includes a correction element and a test element connected to the negative input path of the differential circuit; The first component group and the second component group constitute the correction component group and the inspection component group; The self-diagnosis code generation circuit has: A first inspection mode is used to inspect the first component group; as well as A second inspection mode is used to inspect the second component group; The first component group and the second component group are inspected separately.

13. The semiconductor circuit according to any one of claims 5 to 7, wherein: The above analog circuit has a redundant structure, including: a first component group, belonging to one node, including the correction component group and the inspection component group; and a second component group having the same weights and structure as the first component group; The self-diagnosis code generation circuit has: A first inspection mode for inspecting the first component group; and A second inspection mode is used to inspect the second component group; The first component group and the second component group are inspected separately.

14. The semiconductor circuit according to claim 12, wherein: The self-diagnosis code generating circuit, in the first group inspection mode, For the first element group, a first bit signal for controlling the correction element to be inspected is set to 1 or 0, a second correction bit signal group for controlling the correction element having an adjustment weight smaller than that of the first correction element is set to the inverted logic value of the first bit signal, a check bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the other bit signals are output as predetermined fixed signals; For the second element group, outputting an optimal correction code to minimize the quantization error of the quantizer; The above digital circuit, In the first set of inspection modes, a first error signal is generated based on the error signal of the error detection circuit; For the control code of the first element group, the first bit signal is set to the inverted logic value of the bit signal at the first step, the second bit signal group is set to the inverted logic value of the bit signal at the first step, the check bit for controlling the check element is set to the inverted logic value of the bit signal at the first step, and the other bit signals are set to specified fixed signals for output, and for the second element group, the optimal correction code is maintained for output, A second error signal is generated as an output of the error detection circuit, At a transition point of the quantizer where the quantization error is the minimum, determining the magnitude of the first error signal and the second error signal, thereby checking whether the weight is below a specified value; In the second set of inspection modes mentioned above, The relationship between the first component group and the second component group in the first inspection pattern is changed and the same processing is performed.

15. The semiconductor circuit according to claim 13, wherein: The self-diagnosis code generating circuit, in the first group inspection mode, For the first element group, a first bit signal for controlling the correction element to be inspected is set to 1 or 0, a second correction bit signal group for controlling the correction element having an adjustment weight smaller than that of the first correction element is set to the inverted logic value of the first bit signal, a check bit signal for controlling the inspection element is set to the inverted logic value of the first bit signal, and the other bit signals are output as predetermined fixed signals; For the second element group, outputting an optimal correction code to minimize the quantization error of the quantizer; The above digital circuit, In the first set of inspection modes, a first error signal is generated based on the error signal of the error detection circuit; For the control code of the first element group, the first bit signal is set to the inverted logic value of the bit signal at the first step, the second bit signal group is set to the inverted logic value of the bit signal at the first step, the check bit for controlling the check element is set to the inverted logic value of the bit signal at the first step, and the other bit signals are set to specified fixed signals for output, and for the second element group, the optimal correction code is maintained for output, A second error signal is generated as an output of the error detection circuit, At a transition point of the quantizer where the quantization error is the minimum, determining the magnitude of the first error signal and the second error signal, thereby checking whether the weight is below a specified value; In the second set of inspection modes mentioned above, The relationship between the first component group and the second component group in the first inspection pattern is changed and the same processing is performed.

16. The semiconductor circuit according to claim 12, wherein: When inspecting the correction element included in the first element group, the inspection element included in the second element group is used; When inspecting the correction element included in the second element group, the inspection element included in the first element group is used.

17. The semiconductor circuit according to claim 13, wherein: When inspecting the correction element included in the first element group, the inspection element included in the second element group is used; When inspecting the correction element included in the second element group, the inspection element included in the first element group is used.

18. The semiconductor circuit according to any one of claims 5 to 7, wherein: The above-mentioned data converter is an analog-to-digital converter.

19. The semiconductor circuit according to claim 18, wherein: The analog-to-digital converter includes one or more comparators; The above comparator is composed of a differential circuit; In order to correct the offset of the comparator, a correction element group and a check element group are respectively provided in the positive side transmission path and the negative side transmission path in the differential circuit; The correction elements included in the correction element group of the positive side transport path and the negative side transport path are respectively inspected based on the inspection element group.

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