Method of operating a memory device

Abstract

A method for operating a memory device is disclosed, including: preparing to program a target word line; determining whether at least one memory cell of an adjacent word line is to be programmed to a first target state; and deciding to program the adjacent word line first or the target word line first according to whether the at least one memory cell of the adjacent word line is to be programmed to the first target state.

Description

Technical Field

[0001] The present invention relates to an operation method of a memory device. Background Art

[0002] In a memory device, a programming operation of an adjacent word line (such as WL(N + 1)) will increase the threshold voltage of this word line (WLN), which is called word line interference. The main factor causing word line interference is that the overdrive voltage of the adjacent word line is insufficient. The overdrive voltage VOV is defined as the difference between the gate-source voltage (VGS) and the threshold voltage (VTH) of a transistor, and can be expressed as follows: VOV = VGS - VTH.

[0003] Figure 1 Show the situation of the threshold voltage increase caused by word line interference. Figure 1 The figure shows the threshold voltage distribution of triple-level cells (TLC), where ERS represents the erased state. The solid line represents the threshold voltage distribution of word line WLN after programming the word line WLN, and the dashed line represents the threshold voltage distribution of word line WLN after programming the word line WL(N + 1), which is caused by word line interference. After comparing the solid line and the dashed line, it can be known that word line interference will indeed increase the threshold voltage. A wider threshold voltage distribution will make it difficult to correctly judge the read data.

[0004] Therefore, how to reduce word line interference to improve the performance of the memory device is one of the efforts. Summary of the Invention

[0005] According to an example of the present invention, an operation method of a memory device is proposed, including: preparing to program a target word line; judging whether at least one memory cell of an adjacent word line is to be programmed to a first target state; and according to whether the at least one memory cell of the adjacent word line is to be programmed to the first target state, deciding to program the adjacent word line first or the target word line first.

[0006] According to another example of the present invention, an operation method of a memory device is proposed, including: preparing to read a target word line; judging whether at least one of the multiple memory cells of the target word line has been programmed to a target state; and according to whether at least one of the memory cells of the target word line has been programmed to the target state, applying an original pass voltage or an increased pass voltage to the adjacent word line.

[0007] In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows: Brief Description of the Drawings

[0008] Figure 1 Show the situation where the threshold voltage increases caused by word line interference.

[0009] Figure 2 Show a flowchart of a programming operation method of a memory device according to an embodiment of the present invention.

[0010] Figure 3 Illustrate the threshold voltage distribution diagram of a three-bit cell according to an embodiment of the present invention.

[0011] Figure 4 Show a flowchart of a read operation method of a memory device according to another embodiment of the present invention.

[0012] Figure 5 Illustrate the threshold voltage distribution diagram of a three-bit cell according to an embodiment of the present invention.

[0013] Figure 6 Illustrate a functional block diagram of a memory device according to an embodiment of the present invention.

[0014]

Symbol Description

[0015] 210~260, 405~435: Steps

[0016] L31, L51, L52: Threshold voltage distribution curves

[0017] 600: Memory device

[0018] 610: Memory array

[0019] 620: Controller Detailed Description of the Invention

[0020] The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the explanations of these terms shall be based on the explanations or definitions in this specification. Each embodiment of the present invention has one or more technical features. On the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0021] Figure 2The flowchart shows a programming operation method of a memory device according to an embodiment of the present invention. In step 210, a plurality of memory cells of a programming word line WLN (which may also be referred to as a target word line) are prepared. In step 220, it is determined whether at least one memory cell among the plurality of memory cells of the adjacent word line WL(N + 1) is to be programmed to the highest state (i.e., the target state). In an embodiment of the present invention, the memory cells are multi-level cells (MLC), triple-level cells (TLC), or quad-level cells (QLC). Taking triple-level cells as an example, the cell can be programmed into 8 states, namely the erased state, state A, state B, state C, state D, state E, state F, and state G. Therefore, the highest state is state G, which has the highest threshold voltage.

[0022] If step 220 is affirmative, then in step 230, these memory cells of the word line WL(N + 1) are programmed to the highest state.

[0023] If step 220 is negative, then in step 240, these memory cells of the word line WLN are programmed (here, these memory cells of the word line WLN are respectively programmed to one of state A to state F).

[0024] In step 250, it is determined whether the programming of all word lines has been completed. If step 250 is affirmative, the process ends. If step 250 is negative, the process continues to step 260 to update N (N = N + 1) for programming the next word line.

[0025] That is, according to whether at least one memory cell among the plurality of memory cells of the adjacent word line WL(N + 1) is to be programmed to the highest state, it is determined whether to program the plurality of memory cells of the adjacent word line WL(N + 1) first or the plurality of memory cells of the word line WLN first.

[0026] In an embodiment of the present invention, when preparing to program a target word line, first check whether at least one memory cell among the memory cells of adjacent word lines is to be programmed to a first target state (highest state). When at least one memory cell among the memory cells of adjacent word lines is to be programmed to the first target state, first program the memory cells of the adjacent word lines, and then program the memory cells of the target word line. The reason for this is that in the known art, when at least one memory cell among the memory cells of adjacent word lines is to be programmed to the first target state, word line interference will be caused to the target word line. Therefore, in the embodiment of the present invention, when at least one memory cell among the memory cells of adjacent word lines is to be programmed to the first target state, first program the adjacent word lines, and then program the target word line. In this way, the word line interference to the target word line can be effectively reduced.

[0027] Please refer to Figure 3 , which shows the threshold voltage distribution diagram of a three-bit cell according to an embodiment of the present invention. Figure 3 The upper part represents the threshold voltage distribution of the known art, where the increase in the threshold voltage from state A to state F due to word line interference is represented by curve L31. As is known, if the threshold voltage is increased, it will be more difficult to correctly interpret. Figure 3 The lower part represents the threshold voltage distribution diagram of the multi-bit cell in the embodiment of the present invention. Comparing Figure 3 the upper part and the lower part, it can be found that the embodiment of the present invention can effectively solve the increase in the threshold voltage from state A to state F caused by word line interference. And the narrower threshold voltage distribution helps to correctly judge the read data.

[0028] Figure 4 shows a flowchart of a read operation method of a memory device according to another embodiment of the present invention. In step 405, prepare to read word line WLN. In step 410, determine whether at least one memory cell of word line WLN is programmed to a second target state. Here, the second target state is, for example, state A. Since the programming states of all cells of each word line have been recorded in advance, it can be used to determine whether at least one memory cell of word line WLN is programmed to the second target state.

[0029] If step 410 is yes, then in step 415, apply a higher pass voltage (Vpass) to the adjacent word line WL(N + 1); if step 410 is no (that is, any memory cell of word line WLN is not programmed to the second target state), then in step 420, apply an original pass voltage to the adjacent word line WL(N + 1).

[0030] In an embodiment of the present invention, during a read operation, when at least one of the memory cells of the word line WLN is programmed to a second target state, a higher pass voltage is applied to an adjacent word line WL(N + 1) to increase the overdrive voltage of the word line WL(N + 1). This is because, if the overdrive voltage of the word line WL(N + 1) is insufficient, the word line interference for the erased state cells of the word line WLN will be more obvious. Therefore, by increasing the overdrive voltage of the word line WL(N + 1), the word line interference for the erased state cells of the word line WLN can be reduced / improved.

[0031] In an embodiment of the present invention, during a read operation, when none of the memory cells of the word line WLN is programmed to a second target state, an original pass voltage is applied to an adjacent word line WL(N + 1) to avoid read disturbance.

[0032] In step 425, the word line WLN is read. In step 430, it is determined whether all word lines have been read. If step 430 is yes, the process ends. If step 430 is no, the process continues to step 435. In step 435, the value of N is updated (N = N + 1), and the process returns to step 405 to prepare to read the next word line.

[0033] That is, in an embodiment of the present invention, during a read operation, according to whether at least one of the memory cells of the word line WLN has been programmed to a second target state (state A), the pass voltage applied to the adjacent word line WL(N + 1) is adjusted. When at least one of the memory cells of the word line WLN has been programmed to a second target state (state A), the pass voltage applied to the word line WL(N + 1) is increased. When none of the memory cells of the word line WLN has been programmed to a second target state (state A), an original pass voltage is applied to the adjacent word line WL(N + 1).

[0034] Please refer to Figure 5 , which shows a threshold voltage distribution diagram of a three-bit cell according to an embodiment of the present invention. Figure 5 The upper half represents the threshold voltage distribution of the prior art, where the threshold voltage distribution of the erased state cells (caused by word line interference) is represented by curve L51. Figure 5 The lower half represents the threshold voltage distribution diagram of the multi-bit cell of the embodiment of the present invention, where the threshold voltage distribution of the erased state cells (caused by word line interference) is represented by curve L52. Comparing Figure 5 the upper half and the lower half, it can be found that the embodiment of the present invention can effectively improve the word line interference of the erased state cells. Therefore, when reading the memory cells, it is easier to determine whether the memory cells are in the erased state or the second target state (state A).

[0035] In an embodiment of the present invention, Figure 4 The read flowchart of can be applied to a normal read operation or a program-verify operation. This is within the protection scope of the present invention.

[0036] In an embodiment of the present invention, Figure 2 The programming process of and Figure 4 The read process of can be implemented in combination. That is, the programming operation is implemented with Figure 2 The programming process of ; and the normal read operation and / or the program-verify operation are implemented with Figure 4 The read process of.

[0037] In other possible embodiments of the present invention, Figure 2 The programming process of and Figure 4 The read process of can be implemented independently. This is also within the protection scope of the present invention.

[0038] Please refer to Figure 6 , which shows a functional block diagram of a memory device according to an embodiment of the present invention. The memory device 600 includes: a memory array 610 including a plurality of memory cells and a plurality of word lines; and a controller 620 coupled to the memory array 610. The controller 620 can execute the above operation method of the above embodiment, so the details are omitted here.

[0039] In summary, the above embodiments of the present invention can effectively suppress word line interference to help correctly interpret the read data.

[0040] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for operating a memory device, wherein, comprising: Preparing to program a target word line; Determining whether at least one memory cell of an adjacent word line is to be programmed to a first target state; and Deciding to program the adjacent word line first or the target word line first according to whether the at least one memory cell of the adjacent word line is to be programmed to the first target state; wherein, the first target state is the highest state, and when at least one memory cell of the adjacent word line is to be programmed to the highest state, the memory cells of the adjacent word line are programmed first, and then the memory cells of the target word line are programmed.

2. The operating method according to claim 1, wherein, When any memory cell of the adjacent word line is not to be programmed to the first target state, the target word line is programmed first.

3. The operating method according to claim 1, wherein, further comprising: Preparing to read the target word line; Determining whether at least one of the multiple memory cells of the target word line has been programmed to a second target state; and Applying an original pass voltage or an increased pass voltage to the adjacent word line according to whether at least one of the memory cells of the target word line has been programmed to the second target state.

4. The operating method according to claim 3, wherein, When at least one of the memory cells of the target word line has been programmed to the second target state, the increased pass voltage is applied to the adjacent word line; and When none of the memory cells of the target word line has been programmed to the second target state, the original pass voltage is applied to the adjacent word line.

5. The operating method according to claim 3, wherein, This operating method is applied to a normal read operation or a program-verify operation.

6. A method for operating a memory device, wherein, comprising: Preparing to read a target word line; Determining whether at least one of the multiple memory cells of the target word line has been programmed to a target state; and Applying an original pass voltage or an increased pass voltage to the adjacent word line of the target word line according to whether at least one of the memory cells of the target word line has been programmed to the target state, and the target state and the erased state of the corresponding memory cell are adjacent states.

7. The operating method according to claim 6, wherein, further comprising: When at least one of the memory cells of the target word line has been programmed to the target state, the increased pass voltage is applied to the adjacent word line.

8. The operating method according to claim 6, wherein, further comprising: When none of the memory cells of the target word line has been programmed to the target state, the original pass voltage is applied to the adjacent word line.

9. The operating method according to claim 6, wherein, This operating method is applied to a normal read operation or a program-verify operation.

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