A one-bit binary adder circuit based on memristor

Abstract

The present application provides a one-bit binary adder circuit based on memristor, comprising: a plurality of AND gates, OR gates and complementary metal oxide semiconductor inverters, wherein the plurality of AND gates and OR gates are based on memristor, and by connecting the corresponding complementary metal oxide semiconductor inverters with the corresponding AND gates, OR gates and input and output terminals of the circuit, the speed of the linear memristor device is increased, the size is reduced, the power consumption is reduced, the logic density is increased, and stronger computing power can be provided for processors and other computing circuits.

Description

Technical Field

[0001] The present application relates to the technical field of digital-analog circuits, and in particular to a one-bit binary adder circuit based on memristor. Background Art

[0002] A full adder is generally composed of two half adders, and a half adder can be composed of an XOR gate and an AND gate. Based on the basic AND gate, OR gate, and XOR gate, we can use them to realize the circuit design of the adder.

[0003] Usually the standard cell is a NAND (or NOT) logic gate. In a stable state, no current flows out of the output node because the output node of the AND (or) logic gate is connected to the metal oxide semiconductor gate. In this method, each standard cell needs to have two connections between the complementary metal oxide semiconductor layer and the memristor layer, one for the intermediate level conversion and one for the output. However, studies have found that the MRL gate based on nonlinear memristor devices in the circuit is slow, occupies a large volume, and consumes too much power. However, with the development of technology, such an adder circuit based on traditional nonlinear memristor design can no longer meet application requirements. Therefore, designing an adder circuit with small size, low power consumption and fast MRL gate speed has become an urgent problem to be solved. Summary of the invention

[0004] The present application provides a memristor-based one-bit binary adder circuit to solve the problems of slow gate speed, large size and high power consumption of nonlinear memristor devices (MRL).

[0005] A memristor-based one-bit binary adder circuit comprises: a plurality of AND gates, OR gates and complementary metal oxide semiconductor inverters, wherein the plurality of AND gates and OR gates are based on memristors;

[0006] The complementary metal oxide semiconductor inverter includes a first complementary metal oxide semiconductor inverter, a second complementary metal oxide semiconductor inverter, a third complementary metal oxide semiconductor inverter, and a fourth complementary metal oxide semiconductor inverter;

[0007] The AND gates include a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate, and the OR gates include a first OR gate, a second OR gate and a third OR gate;

[0008] The input end of the first complementary metal oxide semiconductor inverter is connected to the addend input end, the input end of the second complementary metal oxide semiconductor inverter is connected to the augend input end, the first input end of the first AND gate is connected to the output end of the first complementary metal oxide semiconductor inverter, the second input end of the first AND gate is connected to the input end of the second complementary metal oxide semiconductor inverter, the first input end of the second AND gate is connected to the input end of the first complementary metal oxide semiconductor inverter, the second input end of the second AND gate is connected to the output end of the second complementary metal oxide semiconductor inverter, the first input end of the first OR gate is connected to the output end of the first AND gate, and the second input end of the first OR gate is connected to the output end of the second AND gate;

[0009] The input end of the third complementary metal oxide semiconductor inverter is connected to the output end of the first OR gate, the input end of the fourth complementary metal oxide semiconductor inverter is connected to the carry input end, the first input end of the third AND gate is connected to the output end of the third complementary metal oxide semiconductor inverter, the second input end of the third AND gate is connected to the carry input end, the first input end of the fourth AND gate is connected to the input end of the third complementary metal oxide semiconductor inverter, the second input end of the fourth AND gate is connected to the output end of the fourth complementary metal oxide semiconductor inverter, the first input end of the second OR gate is connected to the output end of the third AND gate, and the second input end of the second OR gate is connected to the output end of the fourth AND gate;

[0010] The first input end of the fifth AND gate is connected to the output end of the first OR gate, the second input end of the fifth AND gate is connected to the carry input end, the first input end of the sixth AND gate is connected to the first input end connected to the input end of the first complementary metal oxide semiconductor inverter, and the second input end of the sixth AND gate is connected to the input end of the second complementary metal oxide semiconductor inverter.

[0011] Preferably, the first AND gate, the second AND gate, the third AND gate, the fourth AND gate, the fifth AND gate and the sixth AND gate each include an AND operation module, the AND operation module includes two positively connected memristors in parallel, and the output node of each of the AND operation modules is the same node as the output node of the memristor in the AND operation module.

[0012] Preferably, the first OR gate, the second OR gate and the third OR gate each include an OR operation module, the OR operation module includes two negative-connected memristors in parallel, and the output node of each of the OR operation modules is the same node as the output node of the memristor within the OR operation module.

[0013] Preferably, the output signal of the second OR gate is a carry S, and the output signal of the third OR gate is a sum C. out.

[0014] It can be seen from the above technical solution that the present application provides a one-bit binary adder circuit based on memristor, including: multiple AND gates, OR gates and complementary metal oxide semiconductor inverters, multiple of the AND gates and OR gates are based on memristors, and by connecting the corresponding complementary metal oxide semiconductor inverters with the corresponding AND gates, OR gates and the input and output terminals of the circuit, the speed of the linear memristor device can be improved, the size can be reduced, the power consumption can be reduced, and the logic density can be improved, which can provide processors and other computing circuits with stronger computing power. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 The circuit schematic diagram is a one-bit binary adder circuit based on memristor;

[0017] Figure 2 is the voltage versus time curve of node 1;

[0018] Figure 3 It is the curve of voltage outputted from S port and time;

[0019] Figure 4 C OUT The voltage and time curve of the port output. DETAILED DESCRIPTION

[0020] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0021] The technical solution provided in this application provides a one-bit binary adder circuit based on memristor, see Figure 1, including: multiple AND gates, OR gates and complementary metal oxide semiconductor inverters, multiple AND gates and OR gates are based on memristors, the complementary metal oxide semiconductor inverters include a first complementary metal oxide semiconductor inverter U1, a second complementary metal oxide semiconductor inverter U2, a third complementary metal oxide semiconductor inverter U3, and a fourth complementary metal oxide semiconductor inverter U4, the AND gates include a first AND gate Y1, a second AND gate Y2, a third AND gate Y3, a fourth AND gate Y4, a fifth AND gate Y5 and a sixth AND gate Y6, and the OR gates include a first OR gate H1, a second OR gate H2 and a third OR gate H3.

[0022] The input end of the first complementary metal oxide semiconductor inverter U1 is connected to the addend input end, the input end of the second complementary metal oxide semiconductor inverter U2 is connected to the augend input end, the first input end of the first AND gate Y1 is connected to the output end of the first complementary metal oxide semiconductor inverter U1, the second input end of the first AND gate Y1 is connected to the input end of the second complementary metal oxide semiconductor inverter U2, the first input end of the second AND gate Y2 is connected to the input end of the first complementary metal oxide semiconductor inverter U1, the second input end of the second AND gate Y2 is connected to the output end of the second complementary metal oxide semiconductor inverter U2, the first input end of the first OR gate H1 is connected to the output end of the first AND gate Y1, and the second input end of the first OR gate H1 is connected to the output end of the second AND gate Y2.

[0023] The input end of the third complementary metal oxide semiconductor inverter U3 is connected to the output end of the first OR gate H1, the input end of the fourth complementary metal oxide semiconductor inverter U4 is connected to the carry input end, the first input end of the third AND gate Y3 is connected to the output end of the third complementary metal oxide semiconductor inverter U3, the second input end of the third AND gate Y3 is connected to the carry input end, the first input end of the fourth AND gate Y4 is connected to the input end of the third complementary metal oxide semiconductor inverter U3, the second input end of the fourth AND gate Y4 is connected to the output end of the fourth complementary metal oxide semiconductor inverter U4, the first input end of the second OR gate H2 is connected to the output end of the third AND gate Y3, and the second input end of the second OR gate H2 is connected to the output end of the fourth AND gate Y4.

[0024] The first input end of the fifth AND gate Y5 is connected to the output end of the first OR gate H1, the second input end of the fifth AND gate Y5 is connected to the carry input end, the first input end of the sixth AND gate Y6 is connected to the first input end connected to the input end of the first complementary metal oxide semiconductor inverter U1, and the second input end of the sixth AND gate Y6 is connected to the input end of the second complementary metal oxide semiconductor inverter U2.

[0025] Furthermore, the first AND gate Y1, the second AND gate Y2, the third AND gate Y3, the fourth AND gate Y4, the fifth AND gate Y5 and the sixth AND gate Y6 each include an AND operation module, the AND operation module includes two positively connected memristors in parallel, and the output node of each of the AND operation modules is the same node as the output node of the memristor in the AND operation module.

[0026] Furthermore, the first OR gate H1, the second OR gate H2 and the third OR gate H3 each include an OR operation module, the OR operation module includes two negative-connected memristors in parallel, and the output node of each OR operation module is the same node as the output node of the memristor in the OR operation module.

[0027] Furthermore, the output terminal number of the first OR gate H1 is M1, the output signal of the second OR gate H2 is carry S, and the output signal of the third OR gate H3 is sum C. out .

[0028] In practical applications, Hspice software can be used to build a circuit for simulation. In some embodiments, the following formula can be used as the calculation formula of the adder:

[0029] S=A⊕B⊕C IN (1)

[0030] C OUT =A·B+A⊕B·C IN (2)

[0031] In the formula, A represents the addend, B represents the augend, and C IN Indicates low-order carry, S indicates carry, C OUT Represents sum.

[0032] In the technical solution provided in this application, a 4V voltage (high level, i.e. 1) is applied to port A, and a 0V voltage (low level, i.e. 0) is applied to port B. The voltage and time curve of node 1 after the first XOR gate can be seen in Figure 2 It can be seen that after a 4V voltage is applied to port A and a low level is applied to port B, the voltage and time curve of node 1 after the first XOR gate is basically consistent with the curve of the XOR gate output voltage when a high level and a low level are input in the above text.

[0033] C IN When a 3V voltage (high level, i.e. 1) is applied to the port, the voltage output at port S and the time curve are shown in Figure 3It can be seen that the output voltage of the S port decreases continuously from 0.2ns to 1.2ns, and the fastest rate of effect is at 0.7s. During this period of time, it can be roughly considered that a 2V high-level pulse voltage is input from node 1, and C IN When a 3V voltage is applied to the port, the output voltage variation characteristic curve of the S port is basically consistent with the XOR gate output voltage curve when two high levels are input above. When 1.72V is taken as the threshold voltage, the output voltage is equal to 1.72V, which is regarded as the output low level (0).

[0034] C IN When a 3V voltage (high level, i.e. 1) is applied to the port, C OUT For the voltage and time curve of the port output, please refer to Figure 4 It can be seen that 2.11VC is taken during 0.2ns to 1.2ns OUT The port output voltage remains stable at about 2.11V. Here, it can be seen that one AND gate inputs a 2V high level and a 3V high level, and the other AND gate inputs a 4V high level and a low level. The output voltages of the two AND gates can be seen as high level (1) and low level (0), respectively. The curve obtained after passing through an OR gate. When 2.11V is taken as the threshold voltage, the output voltage is equal to 2.11V, which is regarded as the output high level (1).

[0035] It can be seen that when cascaded memristor-based MRL gates are connected, current can flow from the output node into the input of the next logic gate. In this case, the currents flowing through the two memristor devices of a gate are not equal, and the smaller current may drop below the current threshold of the memristor device, causing the logic gate to partially switch. This phenomenon reduces the output voltage and can cause the logic to malfunction after a single logic level.

[0036] One way to eliminate possible logic failures is to increase the voltage of the high logic state to ensure that all currents in the circuit are greater than the current threshold of the device. The increase in voltage is limited by the complementary metal oxide semiconductor process because high voltage may cause the complementary metal oxide semiconductor transistor to break down and also consume more power. Another way to eliminate logic failures is to amplify the signal with CMOS logic gates, prevent steady-state current leakage and perform signal recovery.

[0037] In the technical solution provided in the present application, the voltage is increased and the signal recovery is achieved through a complementary metal oxide semiconductor inverter. These signal degradation problems are circuit-related, that is, the degree of signal degradation depends on the logic circuit structure and the parameters of the memristor device. Memristor ratio logic is a hybrid complementary metal oxide semiconductor memory logic family. Compared with CMOS logic, this logic family uses less chip area. The design workload of MRL circuits can be reduced by using standard library cells consisting only of "NOR" and "NAND" logic gates. However, standard cells limit the flexibility of the design process and limit the opportunities for area savings. Other optimization criteria, such as increasing the operating voltage and minimizing the number of connections between the CMOS and memristor layers, are also possible.

[0038] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A one-bit binary adder circuit based on memristor, characterized in that: include: A plurality of AND gates, OR gates and complementary metal oxide semiconductor inverters, wherein a plurality of the AND gates and OR gates are memristor-based; The complementary metal oxide semiconductor inverter includes a first complementary metal oxide semiconductor inverter U1, a second complementary metal oxide semiconductor inverter U2, a third complementary metal oxide semiconductor inverter U3, and a fourth complementary metal oxide semiconductor inverter U4; The AND gates include a first AND gate Y1, a second AND gate Y2, a third AND gate Y3, a fourth AND gate Y4, a fifth AND gate Y5 and a sixth AND gate Y6, and the OR gates include a first OR gate H1, a second OR gate H2 and a third OR gate H3; The input end of the first complementary metal oxide semiconductor inverter U1 is connected to the addend input end, the input end of the second complementary metal oxide semiconductor inverter U2 is connected to the augend input end, the first input end of the first AND gate Y1 is connected to the output end of the first complementary metal oxide semiconductor inverter U1, the second input end of the first AND gate Y1 is connected to the input end of the second complementary metal oxide semiconductor inverter U2, the first input end of the second AND gate Y2 is connected to the input end of the first complementary metal oxide semiconductor inverter U1, the second input end of the second AND gate Y2 is connected to the output end of the second complementary metal oxide semiconductor inverter U2, the first input end of the first OR gate H1 is connected to the output end of the first AND gate Y1, and the second input end of the first OR gate H1 is connected to the output end of the second AND gate Y2; The input end of the third complementary metal oxide semiconductor inverter U3 is connected to the output end of the first OR gate H1, the input end of the fourth complementary metal oxide semiconductor inverter U4 is connected to the carry input end, the first input end of the third AND gate Y3 is connected to the output end of the third complementary metal oxide semiconductor inverter U3, the second input end of the third AND gate Y3 is connected to the carry input end, the first input end of the fourth AND gate Y4 is connected to the input end of the third complementary metal oxide semiconductor inverter U3, the second input end of the fourth AND gate Y4 is connected to the output end of the fourth complementary metal oxide semiconductor inverter U4, the first input end of the second OR gate H2 is connected to the output end of the third AND gate Y3, and the second input end of the second OR gate H2 is connected to the output end of the fourth AND gate Y4; The first input end of the fifth AND gate Y5 is connected to the output end of the first OR gate H1, the second input end of the fifth AND gate Y5 is connected to the carry input end, the first input end of the sixth AND gate Y6 is connected to the first input end connected to the input end of the first complementary metal oxide semiconductor inverter U1, and the second input end of the sixth AND gate Y6 is connected to the input end of the second complementary metal oxide semiconductor inverter U2.

2. A memristor-based one-bit binary adder circuit according to claim 1, characterized in that: The first AND gate Y1, the second AND gate Y2, the third AND gate Y3, the fourth AND gate Y4, the fifth AND gate Y5 and the sixth AND gate Y6 all include an AND operation module, the AND operation module includes two positively connected memristors in parallel, and the output node of each of the AND operation modules is the same node as the output node of the memristor in the AND operation module.

3. A memristor-based one-bit binary adder circuit according to claim 1, characterized in that: The first OR gate H1, the second OR gate H2 and the third OR gate H3 each include an OR operation module, the OR operation module includes two negative parallel connected memristors, and the output node of each OR operation module is the same node as the output node of the memristor in the OR operation module.

4. The memristor-based one-bit binary adder circuit according to claim 1, characterized in that: The output signal of the second OR gate H2 is a carry S, and the output signal of the third OR gate H3 is a sum C. out .

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