Reconfigurable finfet-based artificial neuron and synapse device

Abstract

A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device and a plurality of gates formed around the plurality of fins to form a plurality of fin field effect transistors (FinFETs). The plurality of FinFETs can form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses can include two or more of the plurality of gates. Each of the one or more artificial neurons includes one of the plurality of gates.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. non-provisional patent application No. 16 / 530,714, filed August 2, 2019, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This application generally describes circuit structures that can be used to form artificial neurons and synaptic structures. More specifically, this application describes methods and structures for connecting the gates of FinFETs to configure artificial neurons and synaptic structures at the same technology node. Background Technology

[0004] Modern electronic neural networks comprise digital and / or analog circuit systems inspired by and attempting to approximate the biological neural networks used in neurological systems found in nature. Like their natural counterparts, electronic neural networks attempt to learn and perform various tasks and recognize input stimuli without being pre-programmed with task-specific rules. This learning process can be accomplished using a set of connected nodes representing artificial neurons that operationally approximate the behavior of neurons in biological systems. The connections between neurons can approximate the behavior of biological synapses to transmit signals between one or more artificial neurons. Multiple successive layers of neuronal and synaptic connections can be linked together to break down complex tasks into multiple incremental stages. Therefore, electronic neural networks can be taught to perform new tasks in the same way that biological neural networks learn and grow over time. Summary of the Invention

[0005] In some embodiments, a semiconductor device that implements artificial neurons and synapses together on a semiconductor device may include: a plurality of fins formed on the semiconductor device; and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons includes one of the plurality of gates.

[0006] In some implementations, a method of implementing artificial neurons and synapses together on a semiconductor device can include forming a plurality of fins on the semiconductor device. The method can also include forming a plurality of gates around the plurality of fins to form a plurality of fin field effect transistors (FinFETs). The plurality of FinFETs can form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses can include two or more of the plurality of gates, and each of the one or more artificial neurons can include one of the plurality of gates.

[0007] In any implementation, any and / or all of the following features can be incorporated in any combination and without limitation. The device can also include one or more connections between the plurality of gates, where the one or more connections can form a network of one or more artificial synapses and one or more artificial neurons. The one or more connections between the plurality of gates can be implemented directly after gate deposition. The one or more connections between the plurality of gates can be implemented in a metal layer of the semiconductor device. The plurality of fins can include a first fin, the plurality of gates can include a first plurality of gates, and the first plurality of gates can be formed on the first fin to form a single artificial synapse of the plurality of artificial synapses. The plurality of fins can include a first plurality of fins, the plurality of gates can include a first gate, and the first gate can be formed on the first plurality of fins to form at least a portion of one of the plurality of artificial synapses. The semiconductor device can include a silicon substrate, and each of the plurality of fins can be formed as a vertical ridge in the silicon substrate. The plurality of FinFETs can include a plurality of ferroelectric FinFETs. The plurality of fins can be formed in a uniform pattern on the semiconductor device such that each of the plurality of fins can be used for an artificial neuron or an artificial synapse. Each of the plurality of fins can be formed to have a uniform width. The one or more connections can be established in a system level after the semiconductor device is manufactured. The one or more connections can be established in a software level after the semiconductor device is manufactured. Each of the one or more artificial neurons can be configured to receive a plurality of signal pulses before switching between conductance states. Each of the one or more artificial synapses can be configured to receive a plurality of signal pulses, each of the plurality of signal pulses causing a respective domain to switch between conductance states. Each of the plurality of fins can be about 10 nm wide. The plurality of fins and the plurality of gates can be formed as neurons in a plurality of discrete regions, and a plurality of discrete regions of the plurality of discrete regions can be connected to form a synapse. The plurality of fins and the plurality of gates can be formed in a same technology node. One or more complementary metal-oxide-semiconductor (CMOS) circuits can be formed on the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0008] A further understanding of the nature and advantages of various implementations can be realized by reference to the remaining portions of the specification and the drawings, wherein like reference numerals are used throughout. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When referring to a reference numeral, unless the context clearly dictates otherwise, the reference numeral is being used to identify one or more components that are associated with the reference numeral throughout the specification and drawings. In some instances, multiple reference numerals can be used to identify different components that are associated with a particular component.

[0009] Figure 1 A diagram of a portion of a neural network in accordance with some embodiments is depicted.

[0010] Figure 2 A circuit network implementing a neural network in accordance with some embodiments is depicted.

[0011] Figure 3 A switching cycle of a ferroelectric field effect transistor (FeFET) as a function of transistor area in accordance with some embodiments is depicted.

[0012] Figure 4 A ferroelectric fin field effect transistor (FinFET) that can be used to implement artificial neurons and synapses in accordance with some embodiments is depicted.

[0013] Figure 5 A view of a ferroelectric FinFET structure with multiple gate structures in accordance with some embodiments is depicted.

[0014] Figure 6 A view of the same ferroelectric FinFET structure with multiple gate structures used to implement artificial synapses in accordance with some embodiments is depicted.

[0015] Figure 7 A ferroelectric FinFET structure with multiple fins in accordance with some embodiments is depicted.

[0016] Figure 8 A ferroelectric FinFET structure with multiple fins and multiple gates in accordance with some embodiments is depicted.

[0017] Figure 9 A FinFET structure including multiple fins and multiple gates implemented in the same technology node in accordance with some embodiments is depicted.

[0018] Figure 10 How a connection can be established over a gate deposition layer between gates in a FinFET structure 900 in accordance with some embodiments is depicted.

[0019] Figure 11 A flowchart of a method for implementing a network of artificial neurons and synapses together on a semiconductor device in accordance with some embodiments is depicted. DETAILED DESCRIPTION

[0020] Embodiments are described herein for implementing artificial neurons and artificial synapses together on a single technology node in a semiconductor device. Multiple rows of ferroelectric FinFETs can be fabricated on a silicon substrate. Gates can be connected together to form multi-domain FinFETs that approximate synaptic behavior by gradually transitioning the conductivity of the FinFET channel in response to received signal pulses. Neuron behavior can be approximated using single gates by receiving multiple signal pulses before switching their single conductivity state. Because the same structure can be used as the basis for artificial neurons and artificial synapses, a neural network can be formed on a single technology node and can be configured at the gate deposition layer or metal deposition layer at the time of fabrication. Alternatively, the neural network can be configured and / or reconfigured at the system level layer after fabrication using configurable connections.

[0021] Figure 1 A diagram illustrating a portion of a neural network 100 in accordance with some embodiments is depicted. The neural network 100 includes a plurality of inputs 102. These inputs can correspond to inputs in a biological system, such as elongated projections of axons or neurons representing nerve fibers that conduct electrical impulses and act as transmission lines in the nervous system. For example, the plurality of inputs 102 can represent axons associated with respective photoreceptors that are used to encode and transmit electrical signals representing received light in the surrounding environment. The electrical signals can be scaled to represent the size or intensity of the received signal. For example, the plurality of inputs 102 can generate electrical signals that are proportional to the intensity of the received light signal. It should be noted that the use of photoreceptors and image recognition is provided by way of example only and is not meant to be limiting. Other types of biological and electrical neural networks can be used to receive and process any type of input.

[0022] After receiving input signals at the plurality of inputs 102, each of the plurality of inputs 102 can transmit a pulse 106 to one or more neurons 104. The neural network 100 illustrates these paths between inputs 102 and neurons 104 as a plurality of synapses 110. In a biological nervous system, a synapse is a structure that allows a neuron or nerve cell to transmit an electrical or chemical signal to another neuron. In the neural network 100, synapses 110 can be used to model biological synapses that transmit a weighted signal between inputs 102 and neurons 104 that represents the magnitude of the signal received by the input 102. Synapses 110 can also be weighted. For example, a single input of the plurality of inputs 102 can receive an input signal that is differentially weighted by a synapse as it is sent to different neurons 104. The weighting of synapses 110 allows the neural network to "learn" to recognize specific input patterns and perform specific output tasks. In modeling synapses 110 in a neural network, the synapses can be represented by a semiconductor device that can receive a plurality of successive input pulses and produce a corresponding output. For example, each input pulse can cause the synapse output to gradually increase between a logic 0 level and a logic 1 level.

[0023] Synapses 110 can connect inputs 102 to one or more neurons 104. The connections between inputs 102 and neurons 104 can be made with a one-to-many topology. Neurons 104 in a neural network can mimic biological neurons, which are electrically excitable cells that communicate with other cells through connecting synapses. After receiving a sufficient number of input pulses, a neuron 104 can "fire" or transition to an excited state. This state can be associated with a sensory response (e.g., touch, sound, light, etc.) and / or motor control from the brain. To approximate the behavior of biological neurons, neurons 102 in a neural network 100 can be implemented using any device that can receive a plurality of input pulses from one or more synapses 110 and cause the output 108 of the neuron 104 to switch between a logic 0 state and a logic 1 state after receiving a threshold number of input pulses.

[0024] Figure 1A greatly simplified view of a neural network 100 is illustrated to clearly depict various network components. In practice, the neural network 100 can also include one or more hidden layer neurons and synapses between the input 102 and the output 108. These hidden layers or intermediate layers allow the task of producing the final output 108 to be broken down into sub-steps, each of which can be represented by a corresponding hidden layer of synapses and neurons. For example, the neural network 100 can be configured to distinguish between two different types of images, causing the output 108a to fire when a first type of image is recognized and the output 108b to fire when a second type of image is recognized. A first hidden layer of neurons and synapses can recognize edges within the image. A second hidden layer of neurons and synapses can recognize shapes that are facilitated by the edges within the image. Finally, the neuron 104 in the output stage can combine the recognized shapes to distinguish between the first image type and the second image type. Thus, the neural network 100 can be much more complex than what is apparent from the electrical components and connections. Figure 1 As complex modern neural networks can be accompanied by size, complexity, speed requirements, and / or routing difficulties, there is a great need for circuit elements that can represent biological neurons and synapses in a way that can still allow many devices to be efficiently laid out and manufactured on a single technology node.

[0025] Figure 2 A circuit network 200 implementing a neural network is illustrated in accordance with some embodiments. The neural network represented by the circuit network 200 can be similar to the neural network 100 in Figure 1 . As in Figure 1 , the circuit network 200 is a greatly simplified view of a simple neural network, with many connections and / or hidden layers omitted for clarity in depicting various circuit components that can be used to represent neurons and synapses. Figure 2 The circuit network 200 includes a plurality of inputs 206 that can correspond to the input 102 of Figure 1 . These inputs can be connected to a plurality of devices representing neurons 204 by devices representing synapses. The devices representing synapses can include transistors 202 that connect the inputs of the neurons 204 to the circuit inputs 206. For simplicity, many additional circuit elements (such as access transistors) have been omitted from Figure 2 The access transistors can prevent interference with the gates connected to the inputs, while the outputs are connected to the gates of the FeFETs. This access transistor, along with the memory transistor / element, constitutes one synapse element of a pseudo-crossbar synapse array.

[0026] Many different devices can be used to represent synapses in a circuit network. In this circuit network 200, the transistors 202 can be implemented using semiconductor devices that can be in the V GOnline receive multiple input pulses and provide a proportional output to neurons 204 (extremely scaled) that are also FeFET transistors. Thus, these transistors 202 can be used to model the input and output neurons 204. The transistors 202 that represent the synapses can be configured to receive multiple pulses from the neurons 204 and fire after receiving a threshold number of pulses. A hidden layer of transistors representing the neurons and synapses of a hidden layer as described above can be used to augment this basic network of transistor connections between input and output neurons 204. Thus, when implementing the circuit network 202, it can be beneficial to use semiconductor devices that can implement the analog behavior of the synapses and the digital behavior of the neurons in a single process. G Online receive multiple input pulses and provide a proportional output to neurons 204 (extremely scaled) that are also FeFET transistors. Thus, these transistors 202 can be used to model the input and output neurons 204. The transistors 202 that represent the synapses can be configured to receive multiple pulses from the neurons 204 and fire after receiving a threshold number of pulses. A hidden layer of transistors representing the neurons and synapses of a hidden layer as described above can be used to augment this basic network of transistor connections between input and output neurons 204. Thus, when implementing the circuit network 202, it can be beneficial to use semiconductor devices that can implement the analog behavior of the synapses and the digital behavior of the neurons in a single process.

[0027] In various implementations, many different types of transistors can be used to implement the basic components of a neural network. However, some implementations described herein can use a particular type of transistor known as a ferroelectric field effect transistor (FeFET). FeFETs are logic / memory transistors that can maintain their logic / memory state even when power is removed. FeFETs are similar to traditional metal-oxide-silicate (MOS) transistors, except that the logic gate dielectric is replaced with a ferroelectric material, which is a dielectric that "remembers" or stores the electric field to which it has been exposed. In a FeFET, a persistent dipole (or so-called "domain") can be formed within the gate dielectric itself, thereby splitting the threshold voltage of the FeFET into two stable states that can represent binary logic states. Because these stable states are persistent, the operation of a FeFET can store state information just like in a traditional charge-based flash memory cell. FeFETs also use a relatively small amount of power and can be scaled with traditional CMOS technology intrinsically. When used as memory devices, the read / write times and write / erase amplitudes of FeFET cells are also significantly faster and lower, respectively, compared to memory such as flash NAND memory.

[0028] Figure 3 A switching cycle of a FeFET in accordance with some implementations is illustrated. Ferroelectric materials are materials that can change state after an external stimulus is applied, such as an applied voltage. Ferroelectric materials can include multiple physical domains that can switch between two stable states. Ferroelectrics can be integrated into the gate of a FeFET to be used as a memory device. Figure 3 One of the features of a FeFET that makes it particularly useful for modeling neurons and synapses in a neural network is illustrated. Figure 3Each of the left side FeFET states 302, 304, 306, 308 represents various states of the FeFET as it gradually transitions between a logical 0 state and a logical 1 state. Because of this gradual transition, a synapse can be modeled using the FeFET in Figure 3 Recall that synapse behavior gradually transitions between logical states in response to repeated input pulses on the gate electrode. The FeFET can gradually switch conductance over time as it receives pulses from an input or other similar neuron device in a neural network, rather than switching the device's conductance in response to a single event.

[0029] To model synapse behavior, the FeFET can be designed to be relatively larger than a similar neuron device, such that the gate electrode can be represented as multiple domains or physical regions that can be independently switched between logical states in the gate electrode. Figure 3 Each of these domains is represented in the gate electrode of the FeFET in various states 302, 304, 306, 308 using vertical arrows. The direction of these vertical arrows changes to represent the switching behavior of the corresponding domain in the gate. Changing one of the domains in the FeFET can correspond to a change in the structure of the ferroelectric lattice material in the FeFET. Because the lattice itself changes its configuration, the state of the FeFET can persist between input pulses that cause the domain to switch. And, each domain can be represented with its own hysteresis plot 310 that switches between stable states. Thus, upon receiving a single pulse at the gate of the FeFET, one of the domains can switch between stable states, such as transitioning from a logical 0 to a logical 1.

[0030] From Figure 3The upper FeFET state 302 begins with the FeFET starting at a logic 0. In this example, the FeFET can be designed to include three distinct domains, however in practice, the device can include fewer or more domains than three. Each of the three upward pointing vertical arrows indicates that each of the three domains is currently in a stable logic 0 state. After receiving a first input pulse of opposite polarity than that required to be in a logic 0 state, the FeFET can enter state 304. In state 304, the first domain of the FeFET has switched from a logic 0 to a logic 1. This is also indicated in the hysteresis plot 310. The received input pulse was sufficient to change a single domain while leaving the other domains in a stable logic 0 state. Note that some transitions can require multiple pulses to switch a single domain. Next, the FeFET can receive a second input pulse causing the second domain of the FeFET to transition to a logic 1 state. This is represented by the second downward pointing arrow in the FeFET's gate in the diagram of state 306. Finally, the FeFET can receive a third input pulse causing the last domain to transition to a logic 1 state.

[0031] This gradual transition of domains within a FeFET having multiple domains can provide an analog-like transition between states, which can be useful when modeling synaptic behavior. State 302 represents a full logic 0 state of the FeFET before receiving any input pulses. Conversely, state 308 represents a full logic 1 state of the FeFET after receiving a sufficient amount of input pulses, such as at least three pulses. Because each of the domains independently switches, the conductance of the channel in the FeFET can gradually change between a non-conductive state and a fully conductive state in a corresponding manner. This change in conductance can cause the output of the synapse to also gradually increase / decrease as positive / negative input pulses are received to switch the corresponding domains.

[0032] Figure 3Graph 312 in FIG. 3 represents the switching behavior of a FeFET with a varying number of domains. Signal 314 represents a multi-domain FeFET gradually receiving pulses over time. The number of pulses received is represented by the horizontal axis, while the generated conductance of the channel of the FeFET is represented by the vertical axis. For a multi-domain FeFET, each received pulse or set of pulses causes a step increase in the conductance of the channel as the individual domains switch. The FeFET represented by signal 314 can include at least six domains. Curve 318 represents an ideal response, which can be approximated by increasing the number of domains in the FeFET. For example, as the number of domains in the FeFET increases, the step size of signal 314 can become smaller, and the overall shape of signal 314 can begin to approximate the shape of curve 318. Graph 312 thus illustrates how a multi-domain FeFET can be used to model the analog output of a synapse that responds proportionally to received input pulses.

[0033] In contrast to the synapse behavior illustrated by the multi-domain FeFET in Figure 3 The neuron behavior in a neural network can also be represented using simpler, smaller FeFET devices in contrast to the synapse behavior illustrated by the multi-domain FeFET in Figure 3 While not explicitly shown in FIG. 3, a FeFET with only a single domain will only have a single switching event. Signal 316 of graph 312 shows how a single-domain FeFET can respond to multiple received pulses. A similar neuron FeFET with only a single domain can exhibit a single switching event between stable logic states, rather than switching individual domains upon receiving a pulse. For example, a smaller FeFET representing a neuron can "fire" or transition between stable states upon receiving a sufficient number of pulses from a larger FeFET representing a synapse. Thus, FeFETs are useful not only for representing synapse behavior, but by limiting the number of domains in a device, FeFETs can also be used to represent neuron behavior.

[0034] Figure 4 A ferroelectric fin field effect transistor (FinFET) 400 that can be used to implement artificial neurons and synapses in accordance with some embodiments is illustrated. FinFET 400 is a multi-gate device that includes MOSFETs built onto a substrate 408. Instead of implementing the source and drain of a transistor as doped wells in the substrate 408, a fin 401 is fabricated on top of the substrate 408 to form the channel, source 406, and drain 404 of the transistor. A gate 402 can be wrapped around the channel formed by the fin 401 to provide greater control over the channel when turning the transistor on / off. FinFET devices have significantly faster switching times and higher current densities compared to mainstream CMOS technology.

[0035] Throughout the remainder of this disclosure, a FeFET can be usedFigure 4 A simplified diagram of various FinFET devices is shown in the lower left corner. However, Figure 4 A detailed diagram 420 in the upper right corner depicts one embodiment of various layers that can be deposited around the channel of a FinFET 400. For these embodiments, a ferroelectric material can be added (or exchanged with an existing high-k material) to the gate of the FinFET 400 to act as a neuron or synapse as described above. For example, the channel can include an undoped silicon fin 401 surrounded by a gate oxide 412 and a ferroelectric material 414. This ferroelectric structure can then be fabricated with a conductive gate material 408 to create the electric field needed to polarize the ferroelectric material 414.

[0036] The ferroelectric FinFET 400 can be fabricated using similar methods to standard logic FinFETs using a self-aligned double patterning technique, where spacers are formed by deposition or reaction of a film layer deposited on a substrate. An etch process can then remove all of the fill material on the horizontal surfaces, leaving material only on the sidewalls. After the pattern features are removed, only the spacers remain. This spacer technique can be used to define narrow fins on a substrate in a line. However, unlike standard FinFET fabrication processes, the ferroelectric FinFET 400 can also include a ferroelectric high-K deposition step and a cap anneal to stabilize the ferroelectric phase. Some embodiments can use a solid solution mixed with different ratios of silicon, aluminum, lanthanum, zirconium, and / or HfO-ZrOx constituents. Some embodiments can also use an additional anneal process to stabilize the ferroelectric phase within a high-K value. When fabricating ferroelectric FinFETs to implement artificial synapses, connections between multiple gates can be used as described below in the "Back End of Line (BEoL)" portion of the fabrication process.

[0037] For the embodiments described herein, the ferroelectric FinFET 400 can be particularly well suited to implement artificial neurons and synapses. When compared to flat devices, the domains described above in the fin 401 can be implemented in the ferroelectric material 414 to provide significant improvements when implementing large numbers of devices at scale. Furthermore, the shape of the gate 402 can create more domains while also reducing the size of these domains. This can result in increased variability of the ferroelectric FinFET devices when compared to other devices. It can also be relatively easy to add additional gates to the device to model synapses, which provides improved ability to tune the device and can allow a designer to choose between implementing neurons with a single gate and synapses with multiple gates on the same silicon structure.

[0038] Figure 4The ferroelectric FinFET 400 illustrated in FIG. 4 can be used to implement artificial neurons. A single gate 402 can be designed to include a single domain that switches after the gate 402 receives a number of pulses. For example, the ferroelectric FinFET 400 can be used to implement one of the artificial neurons 204 in FIG. 2. Figure 2

[0039] Figure 5 A view of a ferroelectric FinFET structure 500 with multiple gate structures is illustrated in accordance with some embodiments. This ferroelectric FinFET structure 500 can include a raised fin 501 as illustrated in FIG. 4. However, the single fin 501 can have multiple gates 502, 504, 506, 508 deposited on the fin 501. To implement an artificial neuron, a single gate (e.g., gate 502) can be selected from the multiple gates 502, 504, 506, 508 and connected to an input from an artificial synapse. The source and drain regions on either side of the single gate can then be connected to an output of the neuron. Figure 4

[0040] Figure 6 A view of the same ferroelectric FinFET structure 500 with multiple gate structures used to implement an artificial synapse is illustrated in accordance with some embodiments. Rather than using only a single gate 502 on the ferroelectric FinFET structure 500, the multiple gates 502, 504, 506, 508 can be electrically connected together using electrical connections 510. The multiple gates 502, 504, 506, 508 can be selected from the multiple gates 502, 504, 506, 508 to form a ferroelectric FinFET that includes multiple domains as described above to simulate synapse behavior. Figure 6 The electrical connections 510 illustrated in FIG. 5 can be formed in the same deposition layer as the gates 502, 504, 506, 508. As will be described below, this electrical connection 510 can also be fabricated in a metal layer above the deposition layer of the gates 502, 504, 506, 508. This electrical connection 510 can also be fabricated using a configurable connection network or through a configurable process at the system level.

[0041] By connecting the multiple gates 502, 504, 506, 508 together using the electrical connections 510, a ferroelectric FinFET can be formed that includes multiple domains as described above to simulate synapse behavior. In particular, the multiple gates can form multiple domains, each of which can independently switch in response to an input pulse received from an upstream artificial neuron.

[0042] Figure 5 and Figure 6 ​​The ferroelectric FinFET illustrated in FIG. 5 can use the same fin structure to implement neurons and synapses. Thus, a single fin 501 can have multiple gates 502, 504, 506, 508, and the connections between these gates 502, 504, 506, 508 can define whether the fin 501 is part of an artificial neuron or part of an artificial synapse.

[0043] Figure 7 A ferroelectric FinFET structure 700 with multiple fins is illustrated in accordance with some embodiments. Multiple fins 701, 702, 703 can be formed on a semiconductor device or substrate 705. Multiple gates 710, 712, 714 can be formed around the multiple fins 701, 702, 703 to form multiple potential FinFETs based on varying connections that can be made between the multiple gates 710, 712, 714. In this example, an artificial neuron can be implemented using gate 710 on fin 701 that is not connected to multiple other gates (e.g., gates 712, 714). Thus, in this example, three fins 701, 702, 703 and three gates 710, 712, 714 can form three separate artificial neurons.

[0044] Figure 8 A ferroelectric FinFET structure 800 with multiple fins and multiple gates is illustrated in accordance with some embodiments. This ferroelectric FinFET structure 800 is similar to structure 700 of Figure 7 except that each of the multiple gates 810, 812, 814 can be electrically connected together to form an artificial synapse. Recall that Figure 6 the artificial synapse formed in FIG. 5 uses a single fin 501 to form multiple domains of the artificial synapse, with multiple gates 502, 504, 506, 508 attached to the single fin 501. In contrast, Figure 8 the artificial synapse formed in FIG. 8 uses multiple gates 810, 812, 814 that are each coupled to multiple fins 801, 802, 803. Figure 6 The use of a multi-gate FinFET to implement a synapse, as opposed to Figure 8 the use of a multi-channel FinFET to implement a synapse. Again, these connections can be made directly through gate deposition using BEoL processes in a metal layer or using configurable system-level processes. Figure 8 The multi-channel configuration of FIG. 8 can be advantageous because it is efficient and does not cause a scalable signal for neurons, as opposed to the multi-gate, single fin configuration of FIG. 7. Figure 6

[0045] Figure 9 ​A FinFET structure 900 according to some embodiments is illustrated, which includes multiple fins and multiple gates implemented in the same technology node. The term "technology node" can also be referred to as "process node," "process technology," or simply "node." This term can refer to a particular semiconductor manufacturing process having certain design rules, circuit generation, and architecture. The FinFET structure 900 can include fins fabricated in multiple rows, with one or more gate structures over each of the fins. Figure 9 Examples include fins with four gates on each fin. However, this illustrates only one example of a possible arrangement of the FinFET structure 900. Other structures can include varying numbers of gates on each fin, ranging from a single gate to five gates, seven gates, ten gates, fifteen gates, and / or any range therein. For example, some fins can be implemented with only a single gate, while other fins can be implemented with three gates, five gates, and so on, such that varying gate configurations can be obtained in the same technology node.

[0046] One of the advantages of using ferroelectric FinFET structures is that artificial synapses and artificial neurons can be implemented in the same leading technology node that can follow logic scaling. As mentioned above, artificial neurons are relatively small in size compared to artificial synapses, which are relatively large in size. Recall that artificial synapses can require multiple physical domains, which correspond to the larger physical size of the gate / channel regions of the devices. When using technologies other than FinFET devices, because of the different sizes of artificial neurons and artificial synapses, artificial neurons and artificial synapses must be implemented on different technology nodes. However, the multi-gate FinFET technology described herein allows artificial neurons and artificial synapses to be implemented on the same technology node. Some embodiments can also use technologies including FDSOI or standard bulk high-K metal technologies.

[0047] The FinFET structure 900 can be fabricated first by depositing an SOI layer on top of a silicon substrate. Next, linear rows of a sacrificial layer (e.g., SiGe) can be deposited on top of the SOI to the gaps between where pairs of fins are to be. A masking layer (Si3N4 on SiO2) can be deposited on top of the sacrificial layer and the SOI, and the masking layer can be etched back to form spacers along the edges of the sacrificial layer. Finally, the sacrificial layer can be removed, and the SOI can be etched away such that only the portion under the masking layer remains. This portion can form pairs of fins on top of the silicon substrate. Next, the various materials described above including the conductive layer and the ferroelectric layer can be patterned deposited on top of the fins to form multiple unconnected and / or connected gates.

[0048] Figure 9The FinFET structure 900 illustrated represents a set of primitive ferroelectric FinFET transistors. Depending on how the gates are connected together, these primitive ferroelectric FinFET transistors can be configured into networks of neurons and synapses. The fabrication of this set of FinFETs is cost-effective during manufacturing because the entire structure can be built using the same technology node. This structure can also be combined with other CMOS circuits and scaled down as needed for each specific application.

[0049] Connecting multiple gates together can form an artificial synapse, while using a single gate on a fin can form an artificial neuron. Synapses can be multi-channel (multiple gates on multiple fins) and / or multi-gate (multiple gates on a single fin). Some implementations can connect various gates together to form a network of neurons and synapses by performing direct gate deposition. For example, the same step of depositing conductive material for gates on the fins in a FinFET structure 900 can also be used to deposit conductive traces connecting various gates together to form artificial synapses. Direct gate deposition can also be used to connect artificial synapses and artificial neurons together to form a neural network.

[0050] Figure 10 The illustration shows how connections can be established between gates over a gate deposition layer in a FinFET structure 900 according to some embodiments. Some embodiments may add connections (e.g., metal layers) between gates in a BEoL process to form synapses and neural networks. Figure 10 In an example, metal layer 1010 can be used to route connections between various gates. For instance, connections 1002 in metal layer 1010 can be used to connect three gates 1012, 1014, and 1016 on a single fin 1018 to form a synapse. Gates 1012, 1014, and 1016 can be connected to metal layer 1010 vias 1020, 1022, and 1024. The synapse formed by the three connected gates 1012, 1014, and 1016 can represent a multi-gate single-fin artificial synapse as described above.

[0051] The same process can also be used to form multichannel synapses using multiple fins. For example, multiple gates 1044, 1046 on different fins 1040, 1042 can be connected together using the connection 1006 and a pair of vias 1048, 1050 in the metal layer 1010. This can form a multichannel synapse, which may be preferred in some embodiments. Furthermore, neurons can be formed by connecting a single gate 1060 to the connection 1004 in the metal layer 1010. Although Figure 10Additional connections can also be made in metal layer 1010 between artificial synapses and artificial neurons, although not explicitly shown. In addition, the source / drain regions of the FinFETs can be connected to the metal layer 1010 through vias to complete the neural network.

[0052] In some embodiments, the connections shown in metal layer 1010 can instead be made in a system-level layer, so that the FinFET structure 900 can be configured and / or reconfigured after the manufacturing process is complete. For example, Figure 9 and Each of the gates on the FinFET structure 900 in Figure 10 may have a via connection to a system-level layer. In some embodiments, the system-level layer can include a configurable network of connections, such as a configurable network found in a field-programmable gate array (FPGA) or other configurable logic device. This option allows the neural network to be configured and reconfigured multiple times by controlling the connections in the system-level layer. Some embodiments can also connect the via coupled to each of the gates to an input of a programmable processor, such as a microcontroller or microprocessor. These embodiments allow the connections in the neural network to be configured and reconfigured at run-time.

[0053] Figure 11 A flowchart 1100 of a method for implementing a network of artificial neurons and synapses together on a semiconductor device in accordance with some embodiments is shown. The method can include forming a plurality of fins on a semiconductor device (1102). The fins can be formed using the processes described above. The fins can be formed on a single silicon substrate in a single technology node. Some embodiments can form the fins so that they have a uniform width and / or a uniform spacing. The semiconductor device can include a silicon substrate, where each of the plurality of fins is formed as a vertical ridge on the silicon substrate as shown above. The fins can be any width, such as 10 nm wide.

[0054] The method can also include forming a plurality of gates around the plurality of fins to form a plurality of FinFET devices (1104). The FinFET devices can also include a layer of ferroelectric material to form a ferroelectric FinFET. As shown in Figure 10 The plurality of gates can be formed so that multiple gates are formed on a single fin, and so that a single gate is formed on a single fin, as shown in

[0055] The method can also include connecting together gates in the plurality of gates to form artificial neurons and / or artificial synapses (1106). For example, artificial synapses can be formed by connecting together multiple gates on a single fin. Artificial synapses can also be formed by connecting together multiple gates on multiple fins. Connections between artificial neurons and artificial synapses and connections used to form artificial synapses can be formed in the gate deposition layer, metal layer, or system level layer as described above. These connections can also include connections between neurons and synapses to form a neural network. When a neural network is formed, artificial neurons can be configured to receive multiple signal pulses before switching between conductive states as described above. Similarly, artificial synapses can be configured to receive multiple signal pulses that successively switch individual domains within the synapse between conductive states.

[0056] It is to be understood that Figure 11 The specific steps illustrated in FIG. 10 provide a particular method of implementing artificial neurons and artificial synapses according to various embodiments. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments can perform the steps outlined above in a different order. Moreover, Figure 11 Individual steps illustrated in FIG. 10 can include multiple sub-steps that can be performed in various sequences as appropriate for the individual step. Also, additional steps can be added or removed depending on the particular applications. One of ordinary skill in the art will recognize many modifications, variations, and alternatives.

[0057] In the foregoing specification, numerous specific details have been set forth for purposes of providing a thorough understanding of the various embodiments. However, it will be apparent to those skilled in the art that embodiments can be practiced without some or all of these specific details. In other instances, well known structures and devices are shown in block diagram form.

[0058] The foregoing description of the exemplary embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the

[0059] In the foregoing specification, specific details are given to provide a thorough understanding of implementations. However, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the implementations. Implementations can be practiced without these specific details. For example, circuits, systems, networks, processes, and other components can be shown as components in block diagram form in order not to obscure the implementations in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques have not been shown in detail in order to avoid obscuring the implementations.

[0060] Also, it is noted that individual implementations can be described as a process that is depicted as a flowchart, data flow diagram, structure diagram, or block diagram. Although a flowchart can describe operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations can be rearranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process can correspond in part to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0061] In the foregoing specification, aspects of various implementations are described with reference to specific implementations. Those skilled in the art will recognize that implementations are not limited to these specific implementations. Various features and aspects of the implementations can be used individually or jointly. Further, implementations can be utilized in any number of environments and applications beyond the specific examples described herein. Therefore, the specification and drawings are to be regarded as illustrative rather than a restrictive.

Claims

1. A semiconductor device on which an artificial neuron and a synapse are implemented together, the semiconductor device comprising: Multiple fins are formed on the semiconductor device; Multiple gates are formed around the multiple fins to form multiple ferroelectric fin field-effect transistors (FinFETs), wherein: The plurality of FinFETs include one or more artificial synapses and one or more artificial neurons; Each of the one or more artificial synapses includes two or more of the plurality of gates, the two or more of the plurality of gates being electrically connected together by an electrical connection; and Each of the one or more artificial neurons includes a single gate among the plurality of gates.

2. The semiconductor device of claim 1, further comprising one or more connections between the plurality of gates, wherein the one or more connections form a network of the one or more artificial synapses and the one or more artificial neurons, wherein the one or more connections between the plurality of gates are implemented directly after gate deposition.

3. The semiconductor device of claim 1, further comprising one or more connections between the plurality of gates, wherein the one or more connections form a network of the one or more artificial synapses and the one or more artificial neurons, wherein the one or more connections between the plurality of gates are implemented in a metal layer of the semiconductor device.

4. The semiconductor device of claim 1, wherein: The plurality of fins includes a first fin; The plurality of gates includes a first plurality of gates; and The first plurality of gates are formed on the first fin to form a single artificial synapse in one or more artificial synapses.

5. The semiconductor device of claim 1, wherein: The plurality of fins includes a first plurality of fins; The plurality of gates includes a first gate; and The first gate is formed on the first plurality of fins to form at least a portion of one or more of the artificial synapses.

6. The semiconductor device of claim 1, wherein the semiconductor device comprises a silicon substrate, and each of the plurality of fins is formed as a vertical ridge in the silicon substrate.

7. The semiconductor device of claim 1, wherein two or more of the plurality of gates form two or more ferroelectric domains, the two or more ferroelectric domains switching independently in response to pulses received by respective artificial synapses.

8. The semiconductor device of claim 1, wherein the plurality of fins are formed in a uniform pattern on the semiconductor device such that each of the plurality of fins is available for use with one or more artificial neurons or one or more artificial synapses, and wherein each of the plurality of fins is formed to have a uniform width.

9. A method for simultaneously implementing an artificial neuron and a synapse on a semiconductor device, the method comprising: Multiple fins are formed on the semiconductor device; Multiple gates are formed around the plurality of fins to form multiple ferroelectric fin field-effect transistors (FinFETs), wherein: The plurality of FinFETs include one or more artificial synapses and one or more artificial neurons; Each of the one or more artificial synapses includes two or more of the plurality of gates, the two or more of the plurality of gates being electrically connected together by an electrical connection; and Each of the one or more artificial neurons includes a single gate among the plurality of gates.

10. The method of claim 9, further comprising establishing one or more connections between the plurality of gates, wherein the one or more connections form a network of the one or more artificial synapses and the one or more artificial neurons, wherein the one or more connections are established at the system level after the semiconductor device is manufactured.

11. The method of claim 9, further comprising establishing one or more connections between the plurality of gates, wherein the one or more connections form a network of the one or more artificial synapses and the one or more artificial neurons, and wherein the one or more connections are established at the software level after the semiconductor device is manufactured.

12. The method of claim 9, wherein: Each of the one or more artificial neurons is configured to receive multiple signal pulses before switching between conductivity states; and Each of the one or more artificial synapses is configured to receive a plurality of signal pulses, each of which causes a corresponding domain to switch between conductivity states.

13. The method of claim 9, wherein the plurality of fins and the plurality of gates are formed as neurons in a plurality of discrete regions, and the plurality of discrete regions are connected to form synapses.

14. The method of claim 9, wherein the plurality of fins and the plurality of gates are formed in the same technology node or in the same process technology.

15. The method of claim 9, further comprising forming one or more complementary metal-oxide-semiconductor (CMOS) circuits on the semiconductor device.

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