A modeling method for high voltage diode plasma extraction transition oscillation analysis

Abstract

The present invention discloses a modeling method for high-voltage diode plasma extraction transition oscillation analysis, which specifically includes the following steps: S1: Determine the internal parameters of the device according to the diode data manual, and obtain the operation law of the internal carriers and space charge regions in the reverse recovery stage from the operating conditions. S2: Extract the internal distributed parasitic parameters according to the module packaging structure. S3: Establish a device equivalent lumped circuit model based on the carrier movement law in the reverse recovery stage using the voltage-current relationship of each part, and obtain the dynamic change law of each parameter in the model. S4: Establish a loop lumped parameter model taking into account the diode-external circuit in combination with the external circuit parameters, and use the AC small signal response curve to describe the plasma extraction transition oscillation characteristics. The lumped circuit modeling method proposed in the present invention takes into account the influence of device structure parameters-external circuit-operating conditions, can reproduce the diode plasma extraction transition oscillation phenomenon, and analyze the generation mechanism and influencing factors of the oscillation.

Description

Technical Field

[0001] The invention belongs to the field of power electronic devices, and in particular relates to a modeling method for high-voltage diode plasma extraction transition oscillation analysis. Background Art

[0002] The power module is the core component of new energy equipment, and the power module is the sub-component with the highest failure rate in the equipment. Therefore, improving the reliability of the power module is the key to ensuring the safe operation of new energy equipment. With the increase of module power density, the internal device layout is more compact. At the same time, in order to reduce the switching loss of power devices, the gate and longitudinal structure of the device are continuously optimized, the switching speed is continuously improved, and the oscillation phenomenon caused by parasitic parameters in the module is becoming increasingly obvious. The oscillation caused by parasitic parameters can be divided into LC oscillation and transit time oscillation. The LC oscillation frequency is affected by the packaging parasitic parameters and is about 10-100MHz. The oscillation amplitude is related to the switching speed of the device and can be adjusted by optimizing the driving scheme. At present, the research on LC oscillation is relatively mature. The plasma extraction transit time oscillation (PETT) oscillation occurs in the turn-off process of the bipolar device. It is determined by the hole transit frequency inside the device and the resonant frequency of the external parasitic parameters. Its oscillation frequency is about 100-1000MHz, forming electromagnetic waves in space. On the one hand, it affects the performance of the device drive, causing the device to malfunction and affect the safety of the device. On the other hand, it causes EMI interference to other sub-components in the device, affecting the normal operation of other sub-components and posing a threat to the safety of the system.

[0003] In recent years, relevant research at home and abroad has been conducted on the plasma extraction transition oscillation inside the oscillating power module: the existing research found the PETT oscillation phenomenon between the parallel IGBT chips in the process of the press-fit IGBT module, studied the relationship between the oscillation voltage range and the parasitic inductance based on different chip layout methods, and proposed to suppress the PETT oscillation by using Permalloy; the PETT oscillation phenomenon caused by IGBT and diode was found in the welded power module, and it was proposed that the welded module can suppress the PETT oscillation phenomenon by optimizing the packaging layout. Regarding the calculation method of the PETT oscillation frequency, the existing research has established a unified expression for the PETT oscillation frequency of silicon-based bipolar devices based on a large number of experimental results. However, the existing research on PETT oscillation is mainly based on experimental tests, and the oscillation characteristics are analyzed based on experimental results. The physical model describing the PETT oscillation has not yet been established from the mechanism level. Summary of the invention

[0004] In view of the above problems, the present invention proposes a modeling method for the analysis of plasma extraction transition oscillation of high-voltage diodes. According to the carrier operation characteristics of the diode in the PETT oscillation stage, the device is divided into three regions: plasma region, drift region and passive region, and each region is equivalent to lumped circuit parameters such as resistance, inductance and capacitance. The PETT oscillation lumped circuit model is constructed using the diode equivalent circuit and peripheral circuit parameters. The model can calculate the dynamic changes of each impedance of the loop in the oscillation stage and reproduce the PETT oscillation instability-self-stabilizing oscillation phenomenon.

[0005] The technical solution adopted by the present invention specifically includes the following steps:

[0006] A modeling method for high voltage diode plasma extraction transition oscillation analysis comprises the following steps:

[0007] S1: Determine the internal parameters of the diode device, and calculate the internal base carrier expression and space charge region width expression of the diode device in the reverse recovery phase according to the internal parameters;

[0008] S2: Extract the parasitic parameters of the diode's external circuit, including parasitic inductance, parasitic resistance, and parasitic capacitance, according to the module packaging structure of the diode;

[0009] S3: According to the carrier distribution inside the device, the inside of the device is divided into three regions: plasma region, drift region and passive region;

[0010] S4: According to the base region carrier expression, space charge region width expression, and the voltage-current relationship inside the diode device obtained in step S1, equivalent circuit parameters of the three regions are established respectively, including equivalent resistance of the plasma region, equivalent resistance of the drift region, equivalent inductance of the drift region, equivalent capacitance of the drift region, and equivalent resistance of the passive region, and the equivalent circuit parameters of the three regions are connected in series in sequence to obtain an equivalent lumped circuit model of the diode device;

[0011] S5: Connecting the parasitic parameters of the diode external circuit obtained in step S2 in series to the diode device equivalent lumped circuit model to obtain a loop lumped parameter model taking into account the diode-external circuit parameters; using an AC small signal response curve to represent the plasma extraction transition oscillation characteristics in the diode.

[0012] The excellent effects of the present invention are:

[0013] 1. The present invention proposes a modeling method for high-voltage diode plasma extraction transition oscillation analysis, which can reproduce the plasma extraction transition oscillation phenomenon in the diode.

[0014] 2. The present invention calculates the diode plasma extraction transition oscillation through mathematical analytical calculations, and has the advantages of high analysis efficiency, convenience, speed, and high accuracy.

[0015] 3. The plasma extraction transition oscillation model proposed in the present invention takes into account the influence of device structure parameters, external circuit parameters and operating conditions at the same time, and can be used to analyze the generation mechanism and influencing factors of plasma extraction transition oscillation. Based on the model, an oscillation suppression method and suppression parameter boundaries are proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart for modeling transition oscillations for high voltage diode plasma extraction;

[0017] Figure 2 The voltage and current waveforms of the diode turn-off process;

[0018] Figure 3 (a) shows the internal area distribution of diode 4 during the turn-off stage, and (b) shows the carrier change inside diode 4 during the turn-off stage.

[0019] Figure 4 (a) is the diagram of the current operation law inside the diode, (b) is the distribution diagram of holes and electric field inside the diode, (c) is the hole operation speed inside the diode, and (d) is the lumped circuit model of the diode;

[0020] Figure 5 It is the equivalent circuit diagram of the oscillation circuit;

[0021] Figure 6 It is the dynamic change diagram of loop impedance;

[0022] Figure 7 It is the AC small signal response diagram;

[0023] Figure 8 This is the measured near-field probe waveform. DETAILED DESCRIPTION

[0024] In order to explain the present invention in more detail, the present invention will be further described in detail below by taking a 1700V / 450A power semiconductor module as an example in conjunction with the accompanying drawings.

[0025] The lumped circuit modeling method for plasma extraction transition oscillation analysis in a high-voltage PiN diode proposed in the present invention specifically comprises the following steps:

[0026] S1: Determine the internal parameters of the device according to the diode data sheet, and obtain the operating rules of the internal carriers and space charge regions in the reverse recovery phase of the diode based on operating conditions such as voltage, temperature and commutation speed.

[0027] First, determine the device internal parameters according to the data sheet.

[0028] In order to prevent the voltage spikes caused by high di / dt from affecting the reliability of the device, high-voltage PiN diodes all adopt a non-punch-through structure. The relationship between its breakdown voltage and base doping concentration and base width is obtained based on the impact ionization integral of 1, and the rated voltage BV in the device data sheet is pp The base doping concentration N inside the device can be obtained D and base width w B .

[0029] BV pp (Si) = 5.34 × 10 13 N D -34 (1)

[0030] w B =2.67×10 10 N D -78 (2)

[0031] A margin is left for the breakdown voltage when the device is designed. Generally, the rated voltage in the data sheet is 85% of the device breakdown voltage.

[0032] In this embodiment, the rated voltage of the device is 1.7 kV, and the breakdown voltage of the device is 2 kV, so the base width w can be obtained. B =183μm, base doping concentration N D =8×10 13 cm -3 .

[0033] Afterwards, the analysis of the operation rules of the internal carriers and space charge regions of the diode during the reverse recovery phase is carried out. Before the reverse recovery of the diode, the diode works in the forward conduction state, and the carriers in the highly doped region of the diode are injected into the low-doped base region, producing a conductivity modulation effect. Since the base region needs to maintain electrical neutrality, the hole concentration in the base region is equal to the electron concentration, that is, n(x)≈p(x). The carrier concentration in the base region under the forward conduction condition is:

[0034]

[0035] In the formula, in order to facilitate the expression of the formula, the position coordinates are transformed, that is, x'=xw B / 2, p(x') is the carrier concentration at x' inside the base region, x is the distance from the inside of the diode device to the cathode; J is the on-state current density, J = I F / A, A is the chip active area, I F is the diode on-state current, τ HL is the injected carrier lifetime, q is the unit charge, L a is the bipolar diffusion length, that is D is the bipolar diffusion coefficient, wB is the base width, μ n represents electron mobility, μ p represents the hole mobility.

[0036] According to formula (3), the average carrier concentration in the base region under the on-state condition of the diode is:

[0037]

[0038] Where n a represents the average electron concentration inside the base region under the on-state condition, p a Represents the average hole concentration inside the base region under on-state conditions.

[0039] When the diode is turned off, the voltage and current waveforms are as follows: Figure 2 As shown, it can be divided into 4 stages:

[0040] Phase 1 (current drops from on-state to zero, t 0 ~t 1 ): The diode current begins to decrease, the number of carriers injected into the diode base region decreases, the carrier concentration near the p+n junction in the base region decreases, and the gradient decreases until t 1 At this moment, the carrier gradient at the p+n junction decreases to zero. Assume that the current slope is constant at this stage, s = di / dt and t 0 If time is zero, then t 1 =I F / s,I F Represents the diode on-state current.

[0041] Phase 2 (current is zero to voltage starts to rise, t 1 ~t 2 ): The carrier concentration in the diode base region continues to decrease, and the carrier gradient direction at the p+n junction becomes negative. The diode current direction is opposite. At this time, there are still a large number of excess carriers at the p+n junction, and the space charge region cannot be established inside the device, so the diode voltage drop is still low. 2 At the moment, the carrier concentration at the p+n junction decreases to zero. The current change slope in this stage is consistent with that in stage 1, both of which are s. According to the relationship between the amount of charge extracted from the diode base region and the device port current in this stage, t 2 The time expression is:

[0042]

[0043] In order to simplify the representation, the base width w is B The coefficient of is represented by K, and the expression is:

[0044]

[0045] Phase 3 (voltage starts to rise until current reaches the reverse recovery peak, t 2 ~t 3 ): t 2 At the moment, the excess carriers at the p+n junction decrease to zero, and the space charge region begins to be established. As the space charge region is established, the carriers stored in the base region are extracted, and the reverse recovery current continues to increase until t 3 At this moment, the voltage across the diode reaches the bus voltage, and the reverse recovery current reaches its peak value.

[0046] According to the relationship between the internal charge of the device and the width of the space charge region and the charge and the port current, the expression of the internal space charge region can be obtained as follows:

[0047]

[0048] Where W SC (t) represents the width of the space charge region at time t.

[0049] In this stage, the remaining holes passing through the space charge region will affect the electric field distribution inside the space charge region. Assuming that the holes move through the space charge region at a saturated drift velocity, the hole concentration inside the space charge region can be expressed as the current expression:

[0050]

[0051] In the formula, v s represents the hole saturation drift velocity, I RR (t) represents the reverse recovery current value at time t, and p(t) represents the hole concentration inside the space charge region at time t.

[0052] According to the electrostatic equation inside the device, the voltage across the device can be expressed by the width of the space charge region and the effective charge density:

[0053]

[0054] Where V R (t) represents the voltage across the device at time t, N D represents the base doping concentration, ε s represents the dielectric constant of vacuum.

[0055] t 3 The voltage across the device is V R (t 3 )=V DC , combining formulas (7) and (9), we can get t 3 The width of the space charge region at the moment is:

[0056]

[0057] Where WSC (t 3 ) indicates t 3 The width of the space charge region at that moment.

[0058] Phase 4 (current decreases from the reverse recovery peak to zero, t 3 ~t 4 ): The internal area distribution of the stage 4 device is as follows Figure 3 As shown in a in the figure, the carrier changes as Figure 3 As shown in b, the stored charge in the base region is extracted from the device. During this stage, the width of the space charge region remains unchanged, and the holes cross the space charge region to reach the p+ pole to generate a reverse recovery current. As the amount of residual charge inside the base region continues to decay, the reverse recovery current continues to decrease.

[0059] After the space charge region is established, the excess holes in the base region diffuse to the edge of the space charge region. It is assumed that the electric field in the undepleted region is very small when the excess carriers diffuse. Therefore, the drift current part of the excess carriers is ignored in the continuity equation. The expression of the excess carrier concentration in stage 4 is:

[0060]

[0061] In the formula, p re (x, t) represents the hole concentration at position x at time t, D p represents the hole diffusion coefficient.

[0062] From formula (11), the general solution of excess carriers in the base region can be obtained as:

[0063]

[0064] In the formula, A and B are the coefficients to be determined.

[0065] In stage 4, the excess carrier concentration at the edge of the space charge region is zero, and the excess carrier concentration at the center of the undepleted region is the largest. Therefore, the boundary condition of formula (12) is

[0066]

[0067] In the formula, x M Indicates t 3 The center position of the plasma region at time p a Represents the average hole concentration inside the base region under on-state conditions.

[0068] Substituting the boundary conditions into the general solution formula (12) for excess carriers, the excess carrier expression can be obtained as:

[0069]

[0070] In the formula, Δx is the distance from the inside of the plasma to x=x Mt represents any time in stage 4. L represents the distance from the center of the plasma region to the edge of the space charge region, L = 1 / 2·(w B -W SC (t 3 )).

[0071] Therefore, the reverse recovery current in stage 4 can be obtained by the excess carrier concentration:

[0072]

[0073] In the formula, J R (t) represents the reverse recovery current at time t.

[0074] According to the device data sheet, the IGBT parasitic capacitance C IGBT is 0.25nF.

[0075] S2: Extract the distributed parasitic parameters inside the module according to the module packaging structure.

[0076] The structural model of the module was constructed using Solidworks modeling software, and the distributed parasitic parameters inside the module were extracted using ANSYS Q3D Extractor software. The parasitic inductance and parasitic resistance between the cathode of the diode inside the module (the back of the chip) and the back of the parallel chip are 0.1nH and 10mΩ respectively; the parasitic inductance and parasitic resistance between the anode of the diode (the front of the chip) and the front of the parallel chip are 0.4nH and 40mΩ respectively.

[0077] S3: Using the carrier motion law in the reverse recovery phase of the diode, the device equivalent lumped circuit model is established according to the voltage-current relationship of each part inside the device, and the dynamic change law of each parameter in the equivalent lumped circuit model is obtained.

[0078] According to the carrier distribution inside the device, the device can be divided into three regions: plasma region, drift region and passive region. The current operation law inside the diode at this stage is as follows: Figure 4 As shown in a in the figure, the hole and electric field distribution are as follows Figure 4 As shown in b in the figure, the hole running speed is Figure 4 As shown in c in the figure, the equivalent circuit model is as follows Figure 4 As shown in d.

[0079] Plasma region: When the diode is forward-conducting, there is a conductivity modulation effect inside the device. There are a large number of electrons and holes in the base region. The excess carriers injected during the diode shutdown process are extracted from the base region. According to the current density equation, we can get:

[0080]

[0081] In the formula, J p(x, t) represents the hole current density at x at time t, J n (x, t) represents the hole current density at x at time t, p(x, t) represents the hole concentration at x at time t, n(x, t) represents the electron concentration at x at time t, E represents the electric field, D p represents the hole diffusion coefficient, D n represents the electron diffusion coefficient.

[0082] Reverse recovery stage 4 Due to the electric field inside the base region, the base region contains only hole current and the electron current is zero, that is:

[0083]

[0084] At the same time, the base region of the device is electrically neutral, so the concentrations of electrons and holes are equal, that is, n(x, t)≈p(x, t). Substituting formula (17) into formula (16), we can obtain:

[0085]

[0086] Where σ represents the conductivity of the plasma region.

[0087] From formula (18), the equivalent resistance inside the plasma zone can be expressed as:

[0088]

[0089] In the formula, R p Represents the equivalent resistance inside the plasma region. The hole concentration p can be obtained from the average value of the hole concentration in the plasma region, that is:

[0090]

[0091] Drift region: This region establishes a corresponding space charge region to bear the voltage at the end of the diode. No carriers are generated, and the holes injected from the plasma region cross the space charge region to reach the anode.

[0092] Point a is the boundary between the low field region and the saturation velocity region inside the device, that is, when E>E s When v = v s , the low field distance can be expressed as:

[0093]

[0094] Where a represents the boundary between the internal low field region and the saturation velocity region, ε s represents the vacuum dielectric constant, E s represents the critical field strength, N D Represents the base region doping concentration.

[0095] According to the hole drift velocity and the electric field distribution inside the device, the hole transit time in the drift region is:

[0096]

[0097] In the formula, τ d represents the hole transit time in the drift region, and E(x) represents the field strength at point x.

[0098] The corresponding equivalent circuit is established using a small signal model in the oscillation stage. In the following formulas, the subscript "0" represents a DC quantity, and "~" represents a small signal AC quantity. For physical quantities that contain both DC and AC components, neither the subscript "0" nor "~" is used.

[0099] Assuming that the plasma is thin enough, the conduction current in the plasma After entering the drift region, it reaches the anode without delay and conducts AC current in the drift region. Propagating as an undamped wave (changing phase only) at drift velocity, it is expressed as:

[0100]

[0101] The total AC current in the drift region is the sum of the conduction current and the displacement current:

[0102]

[0103] In the formula, the coefficient γ can be expressed as:

[0104]

[0105] From (24), the electric field in the drift region can be expressed as:

[0106]

[0107] Substitute (25) into (26) and in the drift region (0~W SC ) is integrated, the voltage across the drift region is obtained as:

[0108]

[0109] In the formula, represents the total AC current at the drift region x, is the AC conduction current at the drift region x, is the AC displacement current at the drift region x; γ is the ratio of the plasma conduction current to the total current, μ n is the electron mobility, represents the electric field at the drift region x, v s represents the hole saturation drift velocity, φ represents the injection delay, τ(x) represents the delay time at the drift region x, and wres The resonant frequency representing the device's external circuit parameters; Represents the voltage across the drift region;

[0110] The boundary conditions for integration are:

[0111]

[0112] θ d is the crossing angle in the drift region:

[0113]

[0114] θ 1 is a constant, expressed as:

[0115]

[0116] According to (27), the small signal impedance of the drift region is:

[0117]

[0118] C D =ε s / W SC Defined as the capacitance per unit area of ​​the drift region, the equivalent circuits of the drift region can be expressed as:

[0119]

[0120]

[0121]

[0122] Where, L d Represents the equivalent inductance of the drift region, C d Represents the equivalent capacitance of the drift region, R d Represents the equivalent resistance of the drift region.

[0123] Passive region: Power devices prepare ohmic contacts by depositing metal films on the surface of the semiconductor layer. Ohmic contacts produce contact resistance, which is expressed as resistance R s It means that the contact resistance per unit area is about 5×10 -2 Ω / cm 2 .

[0124] S4: A loop lumped parameter model taking into account the diode-external circuit parameters is established in combination with the diode external circuit parameters, and the AC small signal response curve is used to describe the plasma extraction transition oscillation characteristics in the diode.

[0125] Based on the diode lumped circuit parameters and external parasitic parameters, a loop circuit equivalent model is constructed. Figure 5 As shown, each subcomponent in the circuit can be expressed in the form of RLC. The internal parameters and packaging parameters of the diode device are shown in Table 1, where the conduction current ratio γ of the diode plasma region is 1, that is, the displacement current in the plasma region can be ignored, and the capacitance C can be ignored in the equivalent model of the plasma region. p , only the resistor R p Therefore, only the plasma resistance R is considered in the model. p .

[0126] Table 1 Diode device and packaging parameters

[0127]

[0128] According to the impedance transformation formula, the entire oscillation circuit can be lumped as R eq , L eq , C eq In the form of series connection, the dynamic changes of each impedance in the loop are calculated based on the internal and packaging parameters of the device. Figure 6 As shown. Therefore, the current small signal response in the PETT oscillation stage can be expressed as:

[0129]

[0130] In the formula, δ = R eq / 2L eq , represents the oscillation attenuation factor; Represents the oscillation frequency; R eq Represents the total resistance value in the loop circuit equivalent model, L eq represents the total inductance value in the loop circuit equivalent model, It represents the small signal response value of current in the PETT oscillation stage.

[0131] The current small signal response obtained in this embodiment is as follows Figure 7 As shown, when the loop resistance R eq When the loop resistance R is negative, the small signal current in the loop oscillates and diverges, and instability occurs. eq When it is positive, the small signal current oscillation of the loop converges and tends to be stable. Figure 8 The measured near-field probe waveform has consistent instability-self-stabilization characteristics, so the lumped circuit model can accurately reproduce the plasma extraction transition oscillation phenomenon.

[0132] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made to the present invention by those skilled in the art based on the disclosure of the present invention should be within the scope of protection of the present invention.

Claims

1. A modeling method for high voltage diode plasma extraction transition oscillation analysis, characterized in that: The steps include: S1: Determine the internal parameters of the diode device, and calculate the internal base carrier expression and space charge region width expression of the diode device in the reverse recovery phase according to the internal parameters; S2: Extract the parasitic parameters of the diode's external circuit, including parasitic inductance, parasitic resistance, and parasitic capacitance, according to the module packaging structure of the diode; S3: According to the carrier distribution inside the device, the inside of the device is divided into three regions: plasma region, drift region and passive region; S4: According to the base region carrier expression, space charge region width expression, and the voltage-current relationship inside the diode device obtained in step S1, equivalent circuit parameters of the three regions are established respectively, including plasma region equivalent resistance, drift region equivalent resistance, drift region equivalent inductance, drift region equivalent capacitance, and passive region equivalent resistance, and the equivalent circuit parameters of the three regions are connected in series in sequence to obtain an equivalent lumped circuit model of the diode device; S5: Connecting the parasitic parameters of the diode external circuit obtained in step S2 in series to the diode device equivalent lumped circuit model to obtain a loop lumped parameter model taking into account the diode-external circuit parameters; using an AC small signal response curve to represent the plasma extraction transition oscillation characteristics in the diode.

2. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 1, characterized in that: The internal base carrier expression of the diode device in the reverse recovery phase is: In the formula, p re (Δx,t) represents the distance from the plasma to x at time t M The distance, p a represents the average carrier concentration in the base region under the on-state condition of the diode, t3 represents the time when the current reaches the reverse recovery peak, x M Indicates the center position of the plasma zone at time t3, which is calculated based on the current change slope and the turn-on current; D p represents the hole diffusion coefficient; L represents the distance from the center of the plasma region to the edge of the space charge region, W SC (t3) represents the width of the space charge region; w B is the base width, x is the distance from the inside of the diode device to the cathode, Δx is the distance from the inside of the plasma region to x=x M distance.

3. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 2, characterized in that: The base width is calculated based on the breakdown voltage of the diode device, and the calculation formula is: BV pp =5.34×10 13 N D -34 w B =2.67×10 10 N D -78 Where BV pp Indicates the device breakdown voltage, N D Indicates the base doping concentration inside the diode device.

4. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 2, characterized in that: The space charge region width expression is: In the formula, J F represents the diode on-state current density, q is the unit charge, n a represents the average carrier concentration inside the base region; s represents the current change slope during the period from the current being zero to the voltage starting to rise during the diode shutdown process, W SC (t) represents the width of the space charge region at time t, t2≤t≤t3, t2 represents the moment when the voltage starts to rise from zero, and t3 represents the moment when the current reaches the reverse recovery peak, which is calculated based on the current change slope and the turn-on current; Calculate the voltage V across the device at time t R (t): Since V R (t3) = V DC , then the width of the space charge region W inside the device at time t3 is calculated SC (t3): In the formula, v s represents the hole saturation drift velocity, N D Indicates the base doping concentration inside the diode device, V DC represents the DC bus voltage, A represents the active area of ​​the diode chip, ε s represents the vacuum dielectric constant; p(t) represents the hole concentration inside the space charge region at time t.

5. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 4, characterized in that: The calculation process of the equivalent circuit parameters of the plasma zone is as follows: The excess carriers injected during the diode turn-off process are extracted from the base region. According to the current density equation, we get: In the formula, J p (x, t) represents the hole current at x at time t; J n (x, t) represents the electron current at time x at time t, p(x, t) and n(x, t) represent the hole and electron concentrations inside the base region of the diode device; μ p represents the hole mobility, μ n represents electron mobility; E represents the electric field inside the base region, D p , D n represents the hole diffusion coefficient and the electron diffusion coefficient; In the reverse recovery phase, the base region contains only hole current, and the electron current is zero. At the same time, the electron and hole concentrations in the base region of the diode device are equal, so: According to the expression of hole current, the equivalent resistance inside the plasma region is obtained as: Where p is the average hole concentration, σ represents the conductivity of the plasma region.

6. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 4, characterized in that: The calculation process of the equivalent circuit parameters of the drift region is as follows: The drift area is divided into two regions: the low field region and the saturation velocity region. The distance of the low field region is expressed as Where a represents the distance of the low field region, which is the boundary between the low field region and the saturation velocity region inside the device, and E s represents the critical electric field value, q represents the unit charge, ε s represents the dielectric constant of vacuum; The hole transit time τ in the drift region is calculated based on the hole saturation drift velocity, the electric field distribution inside the device, and the width of the space charge region inside the device. d for: Conduction current in plasma After entering the drift region, it reaches the anode without delay and conducts AC current in the drift region. The drift velocity is expressed as a non-attenuated wave propagation: Calculate the total AC current everywhere in the drift region: The electric field in the drift region and the voltage across the drift region are calculated based on the total AC current in each location in the drift region: In the formula, represents the total AC current at the drift region x, is the AC conduction current at the drift region x, is the AC displacement current at the drift region x; γ is the ratio of the base conduction current to the total current, μ n is the electron mobility, represents the electric field at the drift region x, v s represents the hole saturation drift velocity, φ represents the injection delay, τ(x) represents the delay time at the drift region x, and w res The resonant frequency representing the device's external circuit parameters; represents the voltage across the drift region, θ d is the crossing angle in the drift region, θ1 is a constant; W SC represents the width of the space charge region; E(x) represents the field strength at x; σ represents the conductivity of the plasma region; The small signal impedance of the drift region is calculated based on the voltage across the drift region: C D =ε s / W SC Defined as the capacitance per unit area of ​​the drift region, the equivalent circuits of the drift region are expressed as: In the formula, Represents the voltage across the drift region, L d Represents the equivalent inductance of the drift region, C d Represents the equivalent capacitance of the drift region, R d Represents the equivalent resistance of the drift region, C D Represents the capacitance per unit area of ​​the drift region; Passive region: The ohmic contact on the surface of the semiconductor layer of the power device will produce contact resistance, which is represented by the resistor R s It means that the contact resistance per unit area is about 5×10 -2 Ω / cm 2 .

7. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 6, characterized in that: The crossing angle in the drift region is: i d =w res t d 。 8. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 6, characterized in that: The equivalent circuit parameter of the passive region is expressed as the passive region equivalent resistance R s Indicates that the contact resistance per unit area is 5×10 -2 Ω / cm 2 .

9. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 1, characterized in that: The parasitic parameters include the parasitic capacitance of the IGBT connected in parallel with the diode, the parasitic inductance and parasitic resistance between the cathode of the diode and the back of the parallel chip, and the parasitic inductance and parasitic resistance between the anode of the diode and the front of the parallel chip.

10. The modeling method for high voltage diode plasma extraction transition oscillation analysis according to claim 1, characterized in that: The diode lumped circuit parameters and the external circuit parasitic parameters are connected in series to construct an equivalent model of the loop circuit and calculate the current small signal response in the PETT oscillation stage: In the formula, δ = R eq / 2L eq , represents the oscillation attenuation factor; Represents the oscillation frequency; R eq Represents the total resistance value in the loop circuit equivalent model, L eq represents the total inductance value in the loop circuit equivalent model, It represents the current small signal response value in the PETT oscillation stage; When the loop resistance R eq When the loop resistance R is negative, the small signal current in the loop oscillates and diverges, becoming unstable. eq When it is positive, the small signal current oscillation of the loop converges and tends to be stable.

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