Transistor and method of forming transistor

Abstract

A transistor is disclosed, comprising a top source / drain region, a bottom source / drain region, a channel region vertically located between the top source / drain region and the bottom source / drain region, and a gate laterally adjacent to the channel region in an operative manner. The channel region is crystalline and comprises a plurality of vertically elongated grains, each of which is directly adjacent to the top source / drain region and two of the bottom source / drain region. Other embodiments are disclosed, including methods.

Description

[0001] Related patent data

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 884,781, entitled “Transistor And Methods Of Forming Transistors,” filed on August 9, 2019, naming Manuj Nahar, Vassil N. Antonov, Kamal M. Karda, and Michael Mutch as inventors, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments disclosed herein relate to transistors and methods of forming transistors. Background Art

[0004] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (which may also be referred to as bit lines, data lines, sense lines) and access lines (which may also be referred to as word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0005] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally defined as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two information levels or states.

[0006] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and is separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region that is part of the gate structure between the gate insulator and the conductive gate. Field effect transistors are of course also used in integrated circuit systems other than memory circuit systems and / or external to memory circuit systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0008] Figure 2 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0009] Figure 3 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0010] Figure 4 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0011] Figure 5 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0012] Figure 6 is a schematic cross-sectional view of a portion of a substrate construction during a process according to an embodiment of the present invention.

[0013] Figure 7 and 8 In the process according to the embodiment of the present invention Figure 6 Schematic sequential cross-sectional views of the construction.

[0014] Fig. 9 is a schematic cross-sectional view of a portion of a substrate construction during a process according to an embodiment of the present invention.

[0015] Figures 10 to 12 In the process according to the embodiment of the present invention Fig. 9 Schematic sequential cross-sectional views of the construction.

[0016] Fig.13 is a schematic cross-sectional view of a portion of a substrate construction during a process according to an embodiment of the present invention.

[0017] Figures 14 to 18In the process according to the embodiment of the present invention Fig.13 Schematic sequential cross-sectional views of the construction. DETAILED DESCRIPTION

[0018] Embodiments of the invention encompass methods of forming one or more transistors and one or more transistors independent of the fabrication method. A transistor fabricated according to a method embodiment may have any of the properties as described herein in a structural embodiment. Figure 1 1 shows a first example transistor 14 according to an embodiment of the present invention as part of a construction 10. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting / semiconductive or insulating / insulator / insulating (i.e., electrical herein) material 12. Various materials have been formed vertically above base substrate 11. The materials may be Figure 1 Beside the material depicted, Figure 1 The material depicted is directed vertically inward or from Figure 1 The depicted material is vertically outward. For example, other parts or all of the fabricated components of the integrated circuit system may be disposed somewhere on, around, or within the base substrate 11. Only one transistor 14 is shown, although the construction 10 may include multiple transistors of the same or different constructions, such as fabricated into an array including one or more transistors according to the present invention.

[0019] Transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically located between the top source / drain region 16 and the bottom source / drain region 18, respectively, and a gate 22 (i.e., a conductive material) operatively laterally adjacent to the channel region 20. A gate insulator 24 (e.g., silicon dioxide and / or silicon nitride) is located between the gate 22 and the channel region 20. For simplicity and clarity, the example components depicted are only shown in FIG. Figure 1 For example, the source / drain regions and the channel region may extend in and out of the Figure 13. The source / drain regions 16 and the channel regions 20 may be in the form of coextensive longitudinal elongated lines in the plane of the page. Alternatively and by way of example only, the example source / drain regions and the channel regions may be circular, rectangular, elliptical, triangular, etc. in a horizontal cross section (not shown). The gate insulator 24 and / or the gate 22 may peripherally surround such structures, or alternatively, by way of example only, only partially surround such structures or on only one lateral side in a vertical cross section (not shown). The top source / drain regions 16 and the channel regions 20 may be considered to have a top interface 38, and the bottom source / drain regions 18 and the channel regions 20 may be considered to have a bottom interface 40. Interfaces 38 and / or 40 are shown as being flat and horizontal, although other oriented interfaces may be used, such as diagonal, jagged and / or wavy interfaces, combinations of straight and curved segments, etc. By way of example only, the regions 16, 18, and 20 may include one or more of silicon in elemental form, germanium in elemental form, a mixture of silicon and germanium, etc.

[0020] In one embodiment, the top source / drain region 16 and the bottom source / drain region 18 are each crystalline. In this document, "crystalline" not immediately preceded by a numerical percentage or other quantitative adjective refers to a material, region, and / or structure that is at least 90% crystalline by volume (i.e., having at least 90% grains by volume). The channel region 20 is crystalline and includes a plurality of vertically elongated grains 26 that are individually directly against two of the top source / drain region 16 and the bottom source / drain region 18. A channel region having a plurality of vertically elongated grains that are individually directly against two of the top source / drain region and the bottom source / drain region may exhibit a greater current flow between the top source / drain region and the bottom source / drain region than a channel region without such vertically elongated grains. In one embodiment, not all grains in channel region 20 are directly against both of top source / drain region 16 and bottom source / drain region 18, where example channel region 20 has example replacement grains 28. In one embodiment, at least 10% (at least 50% in one such embodiment and at least 90% in one such embodiment) of all grains in channel region 20 are directly against both of top source / drain region 16 and bottom source / drain region 18. In one embodiment, channel region 20 is polycrystalline.

[0021] In one embodiment, the top source / drain region 16 , the bottom source / drain region 18 , and the channel region 20 individually have an average grain size (i.e., volume), wherein the average grain size of the channel region 20 is different from the average grain size of at least one of the top source / drain region 16 and the bottom source / drain region 18 . Figure 1An example is shown where the average grain size of the channel region 20 is larger than the average grain size of at least one (and as shown, in one embodiment, both) of the top source / drain region 16 and the bottom source / drain region 18 . Figure 2 An example alternative transistor 14a of construction 10a is shown, in which the average grain size of the channel region 20 is larger than only one of the top source / drain region 16 and the bottom source / drain region 18a (e.g., the top source / drain region 16) (e.g., because the example grains 30a in the bottom source / drain region 18a are larger). The same numbering from the embodiments described above has been used in appropriate locations, with some of the construction differences being indicated by the suffix "a". Any other attribute or aspect as shown and / or described herein with respect to other embodiments may be used. A larger grain size in the channel region may provide a greater current than a channel region with a smaller grain size. In addition, providing a transistor having a channel region with an average grain size different from the average grain size of at least one of the top source / drain region and the bottom source / drain region may enable customization of certain operating characteristics of the transistor (e.g., current magnitude and / or other characteristics) compared to what may otherwise occur in the case where the channel region and the top source / drain region and the bottom source / drain region have the same average grain size.

[0022] In some embodiments, the top source / drain region 16 and the bottom source / drain region 18 include polycrystalline grains 30 and grain boundaries 32 between immediately adjacent polycrystalline grains 30, respectively. The vertically elongated grains 26 may be considered to include grain boundaries 34 between immediately adjacent vertically elongated grains 26 and grain boundaries 36 that are not between immediately adjacent vertically elongated grains 26 (e.g., grain boundaries between immediately adjacent grains 28 and grain boundaries between immediately adjacent grains 26 and 28). In one embodiment, at least 30% (at least 60% in one embodiment) of the grain boundaries 32 at the top interface 38 in the top source / drain region 16 are aligned with the grain boundaries 34 of the vertically elongated grains 26 at the top interface 38 in the channel region 20. In one embodiment, at least 30% (at least 60% in one embodiment) of the grain boundaries 32 at the bottom interface 40 in the bottom source / drain region 18 are aligned with the grain boundaries 34 of the vertically elongated grains 26 at the bottom interface 40 in the channel region 20. A greater amount of alignment of such grain boundaries at such interfaces can result in a greater current than would otherwise occur, compared to a lesser amount of alignment of such grain boundaries at such interfaces. Furthermore, a greater amount of alignment of such grain boundaries at such interfaces can enable tailoring of certain operating characteristics of the transistor (e.g., current magnitude and / or other characteristics) than would otherwise occur / exist, compared to a lesser amount of alignment of such grain boundaries at such interfaces.

[0023] In one embodiment, a transistor (e.g., 14) includes a top source / drain region (e.g., 16), a bottom source / drain region (e.g., 18), and a channel region (e.g., 20) vertically located between the top source / drain region and the bottom source / drain region, and a gate (e.g., 22) laterally adjacent to the channel region in an operative manner. The top source / drain region, the bottom source / drain region, and the channel region are crystalline and individually have an average grain size. The average grain size of the channel region is different from the average grain size of at least one of the top source / drain region and the bottom source / drain region (e.g., whether or not the channel region includes a plurality of vertically elongated grains, the vertically elongated grains individually directly abut two of the top source / drain region and the bottom source / drain region). In addition, a larger grain size in the channel region can provide a greater current than a channel region having a smaller grain size. Furthermore, providing a transistor having a channel region having an average grain size different from the average grain size of at least one of the top source / drain region and the bottom source / drain region may enable customization of certain operating characteristics of the transistor (e.g., current magnitude and / or other characteristics) as may otherwise occur if the channel region and the top and bottom source / drain regions have the same average grain size. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0024] Figure 3 and 4 Alternative embodiment transistors 14b and 14c of constructions 10b and 10c are shown, respectively. The same numbering from the embodiments described above has been used where appropriate, with some construction differences being indicated by the suffix "b" or suffix "c". The example channel region 20b of transistors 14b and 14c does not have vertically elongated grains that directly abut both of the top source / drain region and the bottom source / drain region, respectively. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0025] In one embodiment, the average grain size of the channel region (e.g., 20, 20b) is larger than the average grain size of at least one of the top source / drain region and the bottom source / drain region (e.g., transistors 14, 14a, 14b, 14c), in one embodiment is larger than both of the top source / drain region and the bottom source / drain region (e.g., transistors 14, 14b), and in another embodiment is larger than only one of the top source / drain region and the bottom source / drain region (e.g., transistors 14a, 14c). In one embodiment, the average grain size of the top source / drain region and the bottom source / drain region is the same (e.g., transistors 14, 14b). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0026] Figure 5An example of a configuration 10d having a top source / drain region 16d and a bottom source / drain region 18d is shown as an alternative transistor 14d. The same numbering from the embodiments described above has been used in appropriate locations, with some of the configuration differences being indicated by the suffix "d". In one embodiment, a transistor (e.g., 14d) includes a top source / drain region (e.g., 16d), a bottom source / drain region (e.g., 18d), a channel region (e.g., 20) vertically located between the top source / drain region and the bottom source / drain region, and a gate (e.g., 22) laterally adjacent to the channel region in an operational manner. The top source / drain region and the bottom source / drain region have polycrystalline grains (e.g., 30) and grain boundaries (e.g., 32) between closely adjacent polycrystalline grains in the polycrystalline grains. The channel region has channel grains (e.g., 26, 28), which include grain boundaries (e.g., 34, 36) between closely adjacent channel grains in the channel grains. The top source / drain region and the channel region have a top interface (e.g., 38), and the bottom source / drain region and the channel region have a bottom interface (e.g., 40). At least 50% (in one embodiment at least 75%, in one embodiment at least 85%) of the grain boundaries at the top interface in the top source / drain region are laterally offset from the grain boundaries of the channel grains at the top interface in the channel region (e.g., whether or not the channel region includes a plurality of vertically elongated grains that individually directly abut two of the top source / drain region and the bottom source / drain region). At least 50% (in one embodiment at least 75%, in one embodiment at least 85%) of the grain boundaries at the bottom interface in the bottom source / drain region are laterally offset from the grain boundaries of the channel grains at the bottom interface in the channel region (e.g., whether or not the channel region includes a plurality of vertically elongated grains that individually directly abut two of the top source / drain region and the bottom source / drain region). In one embodiment, a plurality of the channel grain boundaries are vertically elongated grains (e.g., 26) that are individually directly abutting two of the top source / drain region and the bottom source / drain region. The lateral offset of the grain boundaries can reduce the tendency of conductivity-modifying dopants to diffuse between the channel region and the immediately adjacent source / drain region. Any other attributes or aspects as shown and / or described herein with respect to other embodiments can be used.

[0027] Embodiments of the present invention include methods of forming transistors (e.g., 14, 14a, 14b, 14d). The transistor formed according to the method embodiment may have any of the properties described above with respect to the structural embodiment. The structural embodiment of the transistor may have any of the properties described below with respect to the method embodiment. In one method embodiment, this includes forming a bottom material (e.g., 50), a top material (e.g., 52), and an intermediate material (e.g., 54) between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region (e.g., 18, 18a, 18d), a top source / drain region (e.g., 16, 16d), and a channel region (e.g., 20, 20b) vertically located between the bottom source / drain region and the top source / drain region. In the finished structure of the transistor, at least the bottom material and the top material include a conductivity-enhancing dopant (e.g., ideally, at a concentration sufficient to make it conductive in the finished structure of the transistor, such as causing a region of the structure to have at least 10 19 atoms / cm 3 The annealing may form any one of the bottom material, the top material, and the intermediate material to have a maximum dopant concentration of 100%. Figures 1 to 5 The gate insulator (e.g., 24) and the gate (e.g., 22) are formed laterally adjacent to the intermediate material, for example, to form Figures 1 to 5 In one embodiment, the method includes annealing before forming the gate. In one embodiment, the annealing activates conductivity-enhancing dopants in at least one of the bottom material, the top material, and the intermediate material.

[0028] In one embodiment, at least two of the bottom material, the top material, and the intermediate material are amorphous immediately before annealing. In this document, a material, region, and / or structure is "amorphous" if it is at least 90% amorphous by volume. Alternatively, as an example, at least two of the bottom material, the top material, and the intermediate material may be crystalline immediately before annealing (e.g., one 3D lattice that is transformed into a different 3D lattice by annealing), or neither amorphous nor crystalline as defined herein (e.g., having grains greater than 10% by volume to less than 90% by volume). In one embodiment, the method includes annealing only two of the bottom material, the top material, and the intermediate material together, annealing the bottom material and the intermediate material together in one such embodiment and annealing the intermediate material and the top material together in another such embodiment.

[0029] In one embodiment, the annealing comprises laser annealing. By way of example only, laser annealing may use a wavelength between 200 and 700 nanometers, 0.1 to 2 J / cm 2 Power (ideally, 0.5 to 2 J / cm 2 ), a pulse width of 5 to 250 nanoseconds, a number of laser shots from 1 to 100, and a substrate temperature from room temperature to 450°C. The laser power for all anneals herein can be selected by a skilled artisan to control the surface roughness of the interface and the grain size of the layer being laser annealed. In addition, for different laser shots, the substrate temperature can be varied, and the laser power and / or pulse width can also be varied. In one embodiment, at least one of the at least two time-interval laser annealing steps uses only 1 laser shot. In another embodiment, at least one of the at least two time-interval laser annealing steps uses more than one (1) laser shot, and in one such embodiment no more than 1,000 laser shots are used. Alternatively, more than 1,000 laser shots may be used. In one embodiment, at least one of the at least two time-interval laser annealing steps uses multiple laser shots, and the earlier multiple laser shots form grains. The later multiple laser shots in the multiple laser shots after the earlier multiple laser shots increase the average grain size of the grains formed during the earlier multiple laser shots.

[0030] Alternatively, as an example, the annealing may include thermal annealing or microwave annealing. Example thermal annealing conditions include a substrate temperature of 450° C. to 1,000° C., an inert environment (e.g., N 2 , rare gases, etc.), pressures from 1 mTorr to atmospheric pressure, and times from 1 second to 12 hours. Example microwave annealing conditions include microwave power from 500 to 10,000 watts, substrate temperature at room temperature, an inert environment (e.g., N 2 , inert gas, etc.), pressures from 1 mTorr to atmospheric pressure, and times from 1 second to 12 hours. Annealing may include any two or more than two of the above-described example annealing methods, including any other existing or future developed annealing methods.

[0031] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] In one embodiment, a method of forming a transistor (e.g., 14, 14a, 14b, 14d) includes forming a bottom material (e.g., 50), a top material (e.g., 52), and an intermediate material (e.g., 54) located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region (e.g., 18, 18a, 18d), a top source / drain region (e.g., 16, 16d), and a channel region (e.g., 20, 20b) vertically located between the bottom source / drain region and the top source / drain region. Reference Figures 6 to 8 This example embodiment is further described. Figure 6 , which shows a precursor construction to any of the constructions 10, 10a, 10b, 10c, and 10d described above. The same numbering has been used where applicable to the precursor construction. Bottom material 50 (e.g., one or more of silicon in elemental form, germanium in elemental form, a mixture of silicon and germanium, etc.) has been formed to be amorphous and has a conductivity-enhancing dopant therein (e.g., to a concentration that will make bottom material 50 conductive in the finished construction of the transistor). Intermediate material 54 (e.g., one or more of silicon in elemental form, germanium in elemental form, a mixture of silicon and germanium, etc.) has been formed to be amorphous and, in one embodiment, at least initially undoped. In this document, "undoped" means any and all conductivity-modifying dopants (e.g., phosphorus, arsenic, etc.) from 0% up to no more than 0.1 molar percent, while "doped" means any and all conductivity-modifying dopants in excess of 0.1 molar percent. For convenience and ease of illustration only, materials 50 and 54 are shown as being patterned substantially into the final shape of the transistor being formed, although this may not yet have occurred at the time of processing.

[0033] refer to Figure 7 , the bottom material and the intermediate material, which have been made amorphous, are annealed together to crystallize the bottom material 50 and the intermediate material 54 into crystalline ones. In one embodiment, the annealing activates conductivity-enhancing dopants in the bottom material 50. Such annealing may also activate dopants that may be in the intermediate material 54 (if any). In one embodiment, the annealing comprises laser annealing, although one or more other annealing techniques may be used, including laser annealing in combination with one or more other annealing techniques.

[0034] refer to Figure 8 , top material 52 is formed after annealing bottom material 50 and intermediate material 54 together. In one such embodiment, top material 52 is formed by epitaxial growth from the uppermost surface of crystallized intermediate material 54, and in one such later embodiment is doped, and during such epitaxial growth, such conductivity-enhancing dopants therein are activated. In the context of this document, a "doped" material or region includes a material or region having a conductivity of at least 1×1014 atoms / cm 3 In another such embodiment, top material 52 is formed by a technique other than epitaxial growth, and in one such later embodiment is amorphous and subsequently annealed (e.g., by laser and / or other annealing). Prior to forming top material 52, the uppermost surface of intermediate material 54 may be polished (e.g., by CMP) and / or native oxide may be otherwise removed therefrom (e.g., by exposure to HF). Annealing may form any of the bottom material, top material, and intermediate material to have a Figures 1 to 5 The gate insulator and gate are finally formed laterally adjacent to the intermediate material (e.g., before or after any annealing described above), for example to form Figures 1 to 5 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] In one embodiment, a method of forming a transistor (e.g., 14, 14a, 14b, 14d) includes forming a bottom material (e.g., 50), a top material (e.g., 52), and an intermediate material (e.g., 54) located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region (e.g., 18, 18a, 18d), a top source / drain region (e.g., 16, 16d), and a channel region (e.g., 20, 20b) located vertically between the bottom source / drain region and the top source / drain region. In the finished structure of the transistor, at least the bottom material and the top material include therein a conductivity-enhancing dopant (e.g., ideally, at a concentration sufficient to make it conductive in the finished structure of the transistor). In a laser annealing step of at least two time intervals, at least two of the bottom material, the top material, and the intermediate material are laser annealed (separately or together) to melt such at least two of the bottom material, the top material, and the intermediate material and then crystallize them into crystals. At least one of the laser annealing steps activates conductivity-enhancing dopants in at least one of at least two of the bottom material, the top material, and the intermediate material. The annealing may form any of the bottom material, the top material, and the intermediate material to have Figures 1 to 5 The gate insulator (e.g., 24) and the gate (e.g., 22) are formed laterally adjacent to the intermediate material (e.g., before or after any annealing), for example to form Figures 1 to 5 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] refer to Figures 9 to 12 One such embodiment is described. Fig. 9 , which shows a precursor construction to any of the constructions 10, 10a, 10b, 10c, and 10d described above. Again, the same numbering has been used where applicable to the precursor construction. In one embodiment, bottom material 50 has been formed to be amorphous and to have therein a conductivity-enhancing dopant (e.g., to a concentration that would make bottom material 50 conductive in a finished construction of a transistor). Intermediate material 54 has been formed to be amorphous. In one embodiment, such intermediate material may be formed to be at least initially undoped.

[0037] refer to Fig.10 , the amorphous bottom material 50 and the amorphous intermediate material 54 have been annealed together to melt the amorphous bottom material and the intermediate material, and then crystallize them into crystalline ones. In one embodiment, such annealing includes laser annealing.

[0038] refer to Fig.11 , conductivity-enhancing dopant ions have been implanted into the uppermost portion UP of the intermediate material 54 (e.g., the portion that will become the top material 52) to render such uppermost portion amorphous. Ideally, the conductivity-enhancing implant is at a concentration sufficient to render it conductive in the finished configuration of the transistor.

[0039] refer to Fig.12 , the uppermost portion has been annealed to crystallize it into a crystalline state, activating conductivity-enhancing dopants therein and forming therefrom top source / drain regions 16. Ideally, the annealing comprises laser annealing, although one or more other annealing techniques may be used, including laser annealing in combination with one or more other annealing techniques.

[0040] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] In another alternative such embodiment, such a method includes melting and then crystallizing the bottom material, the top material, and the intermediate material individually using three time-spaced laser annealing steps, wherein the three time-spaced laser annealing steps individually activate any and all conductivity-enhancing dopants located in the respective bottom material, the top material, and the intermediate material. In one embodiment, the method includes melting and then crystallizing the bottom material, the top material, and the intermediate material using only two time-spaced laser annealing steps. In one such embodiment, each of the intermediate and bottom materials is melted and then crystallized using one of only two time-spaced laser annealing steps, and in one embodiment, each of the top and intermediate materials is melted and then crystallized using one of only two spaced laser annealing steps. In one embodiment, each of the bottom material, the top material, and the intermediate materials is formed amorphous immediately prior to any annealing at them.

[0042] In one embodiment, the intermediate material is formed to be crystalline prior to forming the top material, wherein forming the top material includes forming the top material to be amorphous, followed by annealing the amorphous top material to crystallize it and activate conductivity-enhancing dopants therein. In one embodiment, the method includes forming at least one of the bottom material, the top material, and the intermediate material to be from 25% crystalline to less than 90% crystalline by volume when initially formed, followed by annealing the initially formed at least one material to be at least 90% crystalline by volume. In one embodiment, at least two time-interval laser annealing steps are performed prior to forming the gate. In one embodiment, each of the bottom material, the top material, and the intermediate material includes at least one of silicon in elemental form, germanium in elemental form, or a mixture of silicon and germanium.

[0043] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0044] refer to Figures 13 to 18 Another such embodiment of an annealing step using at least two time intervals is described. Fig.13 , which again illustrates a precursor structure to any of the above-described structures 10, 10a, 10b, 10c, and 10d. The same numbering has been used where applicable to the precursor structure. The bottom material 50 has been formed to be amorphous. In a desirable embodiment, the bottom material 50 as initially formed has a conductivity-enhancing dopant therein at a concentration sufficient to make it conductive in the finished structure of the transistor.

[0045] refer to Fig.14 , the amorphous bottom material 50 has been annealed to melt the amorphous bottom material 50 and then crystallize it into a crystalline one. Ideally, the annealing comprises laser annealing, although one or more other annealing techniques may be used, including laser annealing in combination with one or more other annealing techniques.

[0046] refer to Fig.15 , the intermediate material 54 has been formed to be amorphous. In one embodiment, the intermediate material is undoped, at least as initially formed. Prior to forming the top material 52, the uppermost surface of the bottom material 50 may be polished (e.g., by CMP) and / or the native oxide may otherwise be removed therefrom (e.g., by exposure to HF).

[0047] refer to Fig.16, at least one of at least two time-spaced laser annealing steps has been used to melt the amorphous intermediate material 54 and crystallize it into a crystalline one. Such laser annealing steps are used to raise the temperature of the amorphous intermediate material 54 to at least its melting temperature and also below the melting temperature of the bottom material 50, so that the amorphous intermediate material 54, but not the bottom material 50, melts. For example, such a situation may occur even when materials 54 and 50 have the same composition but do not have the same conductivity dopant concentration, where the bottom material 50 is crystalline and the intermediate material 54 is amorphous at the start of the laser annealing, whereby the crystallized material has a higher melting temperature than the melting temperature of the amorphous material. Alternatively, such a situation may occur, for example, by using different compositions for materials 54 and 50 and selecting the composition for the bottom material 50 to have a higher melting temperature than the melting temperature of the amorphous intermediate material 54.

[0048] refer to Fig.17 , top material 52 has been formed to be amorphous. In one embodiment, top material 52 is undoped, at least as initially formed. In a desirable embodiment, bottom material 50 as initially formed has conductivity-enhancing dopants therein at a concentration sufficient to make it conductive in a finished configuration of a transistor. Prior to forming top material 52, the uppermost surface of intermediate material 54 may be polished (e.g., by CMP) and / or native oxide otherwise removed therefrom (e.g., by exposure to HF).

[0049] refer to Fig.18 , the latter of at least two time-spaced laser annealing steps has been used to melt the amorphous top material 52 and crystallize it into a crystalline one. Such a latter laser annealing step is used to raise the temperature of the amorphous top material 52 to at least its melting temperature and also below the melting temperature of the crystalline intermediate material 54, so that the amorphous top material 52, rather than the crystalline intermediate material 54, melts. According to the above, such a situation may occur even when the materials 52 and 54 have the same composition but do not have the same conductivity dopant concentration, wherein the intermediate material 54 is crystalline and the top material 52 is amorphous at the beginning of the laser annealing, whereby the crystalline material has a higher melting temperature than the melting temperature of the amorphous material. Alternatively, such a situation may occur, for example, by using different compositions for the materials 52 and 54 and selecting the composition for the intermediate material 54 to have a higher melting temperature than the melting temperature of the amorphous top material 52. In one embodiment, each of the intermediate material and the top material includes silicon in elemental form as originally formed.

[0050] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0051] In one embodiment, a method of forming a transistor (e.g., 14, 14a, 14b, 14d) includes forming a bottom material (e.g., 50), a top material (e.g., 52), and an intermediate material (e.g., 54) vertically located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material constitute a bottom source / drain region (e.g., 18, 18a, 18d), a top source / drain region (e.g., 16, 16d), and a channel region (e.g., 20, 20b) vertically located between the bottom source / drain region and the top source / drain region, respectively. At least one of the bottom material, the top material, and the intermediate material is initially formed to be from 25% crystalline to less than 90% crystalline by volume. The initially formed at least one material is annealed to be at least 90% crystalline by volume (i.e., crystalline as defined above). Ideally, the annealing comprises laser annealing, although one or more other annealing techniques may be used, including laser annealing in combination with one or more other annealing techniques. Annealing can form any of the bottom material, the top material, and the middle material to have Figures 1 to 5 The gate insulator (e.g., 24) and the gate (e.g., 22) are formed laterally adjacent to the intermediate material, for example, to form Figures 1 to 5 Any one of the structures.

[0052] In one embodiment, at least one of the bottom material, the top material, and the intermediate material is initially formed to be from 25% crystalline to 60% crystalline by volume. In one embodiment, at least the bottom material and the top material are formed to include conductivity enhancing dopants therein. In one embodiment, at least two of the bottom material, the top material, and the intermediate material are formed to be from 25% crystalline to less than 90% crystalline by volume as initially formed, wherein annealing is performed on such at least two of the bottom material, the top material, and the intermediate material. In one embodiment, at least two of the bottom material, the top material, and the intermediate material are formed to be from 25% crystalline to less than 60% crystalline by volume as initially formed. In one embodiment, all three of the bottom material, the top material, and the intermediate material are formed to be from 25% crystalline to less than 90% crystalline by volume as initially formed, wherein such annealing is performed on such all three of the bottom material, the top material, and the intermediate material.

[0053] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0054] In one embodiment, a method of forming a transistor (e.g., 14, 14a, 14b, 14d) includes forming a bottom material (e.g., 50), a top material (e.g., 52), and an intermediate material (e.g., 54) vertically located between the bottom material and the top material. In a finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region (e.g., 18, 18a, 18d), a top source / drain region (e.g., 16, 16d), and a channel region (e.g., 20, 20b) vertically located between the bottom source / drain region and the top source / drain region. In a finished structure of the transistor, at least the bottom material and the top material include therein a conductivity-enhancing dopant. In an unfinished structure of the transistor, at least one of the bottom material, the top material, and the intermediate material is amorphous. The power level (e.g., not greater than 0.35 J / cm2) is insufficient to crystallize more than 5% of the volume of at least one of the amorphous materials in the bottom material, the top material, and the intermediate material. 2 ), applying laser energy to at least one of the bottom material, the top material, and the amorphous of the intermediate material (e.g., as described above with respect to laser annealing). After applying the laser energy, annealing at least one of the bottom material, the top material, and the amorphous of the intermediate material to crystallize at least one of the bottom material, the top material, and the intermediate material to be crystalline. Forming the gate insulator (e.g., 24) and the gate (e.g., 22) laterally adjacent to the intermediate material, for example, to form Figures 1 to 5 Any one of the structures.

[0055] In one embodiment, the application of laser energy at least reduces impurities (e.g., one or both of hydrogen or argon) from at least one of the amorphous in the bottom material, the top material, and the intermediate material. In one embodiment, the power level crystallizes 0% to 3% (in one embodiment from 0% to 1%) by volume of at least one of the amorphous in the bottom material, the top material, and the intermediate material. In an ideal embodiment, the power level is insufficient to crystallize any of the amorphous in the bottom material, the top material, and the intermediate material. In one embodiment, the application of laser energy uses only 1 laser shot, and in another embodiment, more than 1 laser shot is used.

[0056] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0057] The method as described herein can reduce the intrusion of the top source / drain region downward into the channel region, and thereby achieve more precise control of the vertical thickness of the top source / drain region and the channel region. The method as described herein can result in an increase in the average grain size in the channel region and the ability to optimize the operating properties of one or more of the top source / drain region, the channel region, and the bottom source / drain region. The method as described herein, ideally laser annealing, can promote the formation of multiple vertically elongated grains, which are individually directly against two of the top source / drain region and the bottom source / drain region. The method as described herein can promote the formation of sharp and thin interfaces between the top source / drain region and the channel region and between the bottom source / drain region and the channel region. The method using laser annealing as described herein can reduce the thermal budget to which the structure is exposed during production.

[0058] The above-described processing or construction may be considered to be related to an array of components that is formed as a single stack or single layer of such components or is formed within a single stack or single layer of such components, which is located above or as part of a base substrate (although a single stack / layer may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the finished structure, and in some embodiments may be below the array (e.g., CMOS under the array). In any case, one or more additional such stacks / layers may be disposed or fabricated above and / or below those shown in the figure or described above. In addition, in different stacks / layers, the arrays of components may be the same or different relative to each other. Intermediate structures may be disposed between stacks / layers that are directly vertically adjacent (e.g., additional circuitry and / or dielectric layers). In addition, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one above another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0059] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0060] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "above", "bottom", "above", "below", "below", "under", "up", and "down" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the direction in which the substrate is handled during fabrication, and vertical is a direction generally orthogonal thereto. References to "completely horizontal" are directions along the surface of the main substrate (i.e., no angle thereto) and can be relative to the direction in which the substrate is handled during fabrication. Furthermore, as used herein, "vertical" and "horizontal" are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. Furthermore, "elevationally-extending" and "extend(ing) elevationally" refer to directions that are at an angle of at least 45° to completely horizontal. Furthermore, "extending vertically," "vertically extending," "extending horizontally," "extending horizontally," etc., with respect to field effect transistors, are orientations with reference to the channel length of the transistor along which current flows between source / drain regions in operation. For bipolar junction transistors, "extending vertically," "vertically extending," "extending horizontally," "extending horizontally," etc., are orientations with reference to the substrate length along which current flows between emitter and collector in operation. In some embodiments, any vertically extending components, features, and / or regions extend vertically or within 10° of vertical.

[0061] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two described regions / materials / components relative to each other. Furthermore, the use of "above" without being preceded by "directly" requires only that some portion of the described regions / materials / components that is above the other is vertically outward from the other (i.e., regardless of whether there is any lateral overlap of the two described regions / materials / components). Similarly, the use of "below" and "beneath" without being preceded by "directly" requires only that some portion of the described regions / materials / components that is below / beneath the other is vertically inward from the other (i.e., regardless of whether there is any lateral overlap of the two described regions / materials / components).

[0062] Any of the materials, regions, and / or structures described herein may be homogeneous or inhomogeneous, and in any event may be continuous or discontinuous over any material overlying such material. Where one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. Furthermore, unless otherwise stated, each material is formed using any suitable existing or yet to be developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0063] In addition, "thickness" itself (without a directional adjective in front) is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of the immediately adjacent material or immediately adjacent region of different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and since the thickness is variable, such materials or regions will have a minimum thickness and a maximum thickness. As used herein, "different compositions" only require that those parts of the two materials or regions that can be directly against each other are chemically and / or physically different (for example, when such materials or regions are not homogeneous). If the two materials or regions do not directly against each other, then "different compositions" only require that those parts of the two materials that are closest to each other are chemically and / or physically different (when such materials or regions are not homogeneous). In this document, when the materials, regions or structures are in at least some physical contact relative to each other, a material, region or structure "directly against" another material, region or structure. In contrast, the words “over,” “on,” “adjacent,” “along,” and “against” when not preceded by “directly” encompass “directly against” as well as configurations in which intermediate materials, regions, or structures result in no physical touching contact between the materials, regions, or structures relative to each other.

[0064] As used herein, regional material components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one regional material component to another and does so primarily due to the movement of subatomic positive and / or negative charges (if such charges are sufficiently generated). Another electronic component may be located between the regional material components and electrically coupled to the regional material components. In contrast, when the regional material components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled regional material components.

[0065] The composition of any one of the conductivity / conductor / conductive materials herein may be a metallic material and / or a conductively doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0066] As used herein, "selective" with respect to etching, etching, removing, removing, depositing, forming, and / or forming means such action that one material is so acted upon relative to another material(s) at a rate of at least 2:1 by volume. Additionally, selective deposition, selective growth, or selective formation means that for at least the first 75 angstroms of deposition, growth, or formation, one material is deposited, grown, or formed relative to another material(s) at a rate of at least 2:1 by volume.

[0067] As used herein, "or" includes either and both unless otherwise indicated.

[0068] in conclusion

[0069] In some embodiments, the transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top source / drain region and the bottom source / drain region, and a gate laterally adjacent to the channel region in an operative manner. The channel region is crystalline and includes a plurality of vertically elongated grains that are individually directly adjacent to the top source / drain region and two of the bottom source / drain regions.

[0070] In some embodiments, the transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top source / drain region and the bottom source / drain region, and a gate laterally adjacent to the channel region in an operative manner. The top source / drain region, the bottom source / drain region, and the channel region are crystalline and individually have an average grain size. The average grain size of the channel region is different from the average grain size of at least one of the top source / drain region and the bottom source / drain region.

[0071] In some embodiments, the transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top source / drain region and the bottom source / drain region, and a gate laterally adjacent to the channel region in an operational manner. The top source / drain region and the bottom source / drain region have polycrystalline grains and grain boundaries between immediately adjacent polycrystalline grains in the polycrystalline grains. The channel region has channel grains, and the channel grains include grain boundaries between immediately adjacent channel grains in the channel grains. The top source / drain region and the channel region have a top interface, and the bottom source / drain region and the channel region have a bottom interface. At least 50% of the grain boundaries at the top interface in the top source / drain region are laterally offset from the grain boundaries of the channel grains at the top interface in the channel region. At least 50% of the grain boundaries at the bottom interface in the bottom source / drain region are laterally offset from the grain boundaries of the channel grains at the bottom interface in the channel region.

[0072] In some embodiments, a method of forming a transistor includes forming a bottom material, a top material, and an intermediate material vertically located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom source / drain region and the top source / drain region. In the finished structure of the transistor, at least the bottom material and the top material include a dopant that improves conductivity. In at least two time interval laser annealing steps, at least two of the bottom material, the top material, and the intermediate material are laser annealed to melt at least two of the bottom material, the top material, and the intermediate material and then crystallize them into crystals. At least one of the laser annealing steps activates the dopant that improves conductivity in at least one of the at least two of the bottom material, the top material, and the intermediate material. A gate insulator and a gate are formed to be laterally adjacent to the intermediate material.

[0073] In some embodiments, a method of forming a transistor includes forming a bottom material, a top material, and an intermediate material vertically located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom source / drain region and the top source / drain region. In the finished structure of the transistor, at least the bottom material and the top material include a dopant that improves conductivity. At least two of the bottom material, the top material, and the intermediate material are annealed together to crystallize at least two of the bottom material, the top material, and the intermediate material. A gate insulator and a gate are formed to be laterally adjacent to the intermediate material.

[0074] In some embodiments, a method of forming a transistor includes forming a bottom material, a top material, and an intermediate material vertically located between the bottom material and the top material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material constitute a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom source / drain region and the top source / drain region, respectively. The bottom material is formed to be amorphous and has a dopant that improves conductivity, and the intermediate material is formed to be amorphous. The amorphous bottom material and the intermediate material are annealed together to crystallize the bottom material and the intermediate material into crystalline. The top material is formed by epitaxial growth after annealing the bottom material and the intermediate material together. The gate insulator and the gate are formed to be laterally adjacent to the intermediate material.

[0075] In some embodiments, a method of forming a transistor includes forming a bottom material, a top material, and an intermediate material vertically located between the top material and the bottom material. In the finished structure of the transistor, the bottom material, the top material, and the intermediate material constitute a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom source / drain region and the top source / drain region, respectively. At least one of the bottom material, the top material, and the intermediate material is initially formed to be crystalline from 25% to less than 90% by volume. At least one of the initially formed materials is annealed to be at least 90% crystalline by volume. A gate insulator and a gate are formed to be laterally adjacent to the intermediate material.

[0076] In some embodiments, a method of forming a transistor includes forming a bottom material, a top material, and an intermediate material vertically located between the bottom material and the top material. In a finished structure of the transistor, the bottom material, the top material, and the intermediate material respectively constitute a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom source / drain region and the top source / drain region. In a finished structure of the transistor, at least the bottom material and the top material include a conductivity-enhancing dopant therein. In an unfinished structure of the transistor, at least one of the bottom material, the top material, and the intermediate material is amorphous. Laser energy is applied to at least one of the bottom material, the top material, and the intermediate material at a power level insufficient to crystallize more than 5% of the volume of at least one of the amorphous in the bottom material, the top material, and the intermediate material. After applying the laser energy, at least one of the amorphous in the bottom material, the top material, and the intermediate material is annealed to crystallize at least one of the bottom material, the top material, and the intermediate material into a crystalline one. A gate insulator and a gate are formed to be laterally adjacent to the intermediate material.

Claims

1. A transistor, wherein include: a top source / drain region, a bottom source / drain region, a channel region vertically between the top source / drain region and the bottom source / drain region, and a gate operatively laterally adjacent to the channel region; and the channel region is crystalline and includes a plurality of vertically elongated grains that are individually directly against both the top source / drain region and the bottom source / drain region, The top source / drain region and the bottom source / drain region include polycrystalline grains and grain boundaries between immediately adjacent polycrystalline grains; The vertically elongated grains include grain boundaries between immediately adjacent grains in the vertically elongated grains; The top source / drain region and the channel region have a top interface, and the bottom source / drain region and the channel region have a bottom interface; at least 30% of the grain boundaries at the top interface in the top source / drain region are aligned with the grain boundaries of the vertically elongated grains at the top interface in the channel region; and At least 30% of the grain boundaries at the bottom interface in the bottom source / drain region are aligned with the grain boundaries of the vertically elongated grains at the bottom interface in the channel region. 2 . The transistor of claim 1 , wherein at least 10% of all grains in the channel region directly abut both of the top source / drain region and the bottom source / drain region. 3 . The transistor of claim 2 , wherein at least 50% of all grains in the channel region are directly against both the top source / drain region and the bottom source / drain region.

4. The transistor of claim 3, wherein no more than 90% of all grains in the channel region directly abut both of the top source / drain region and the bottom source / drain region. 5 . The transistor of claim 1 , wherein less than all grains in the channel region directly abut both the top source / drain region and the bottom source / drain region. The transistor of claim 1 , wherein the channel region is polycrystalline.

7. The transistor according to claim 1, in, at least 60% of the grain boundaries at the top interface in the top source / drain region are aligned with the grain boundaries of the vertically elongated grains at the top interface in the channel region; and At least 60% of the grain boundaries at the bottom interface in the bottom source / drain region are aligned with the grain boundaries of the vertically elongated grains at the bottom interface in the channel region.

8. A transistor, wherein include: a top source / drain region, a bottom source / drain region, a channel region vertically between the top source / drain region and the bottom source / drain region, and a gate operatively laterally adjacent to the channel region; and The top source / drain region, the bottom source / drain region, and the channel region are crystalline and individually have an average grain size; the average grain size of the channel region is different from the average grain size of at least one of the top source / drain region and the bottom source / drain region, The channel region includes a plurality of vertically elongated grains that are individually directly abutting both the top source / drain region and the bottom source / drain region; The top source / drain region and the bottom source / drain region include polycrystalline grains and grain boundaries between immediately adjacent polycrystalline grains; The vertically elongated grains include grain boundaries between immediately adjacent grains in the vertically elongated grains; The top source / drain region and the channel region have a top interface, and the bottom source / drain region and the channel region have a bottom interface; at least 30% of the grain boundaries at the top interface in the top source / drain region are aligned with the grain boundaries of the vertically elongated grains at the top interface in the channel region; and At least 30% of the grain boundaries at the bottom interface in the bottom source / drain region are aligned with the grain boundaries of the vertically elongated grains at the bottom interface in the channel region.

9. The transistor of claim 8, wherein the average grain size of the channel region is larger than the average grain size of the at least one of the top source / drain region and the bottom source / drain region.

10. The transistor of claim 9, wherein the average grain size of the channel region is larger than the average grain size of both the top source / drain region and the bottom source / drain region.

11. The transistor of claim 9, wherein the average grain size of the channel region is larger than only one of the top source / drain region and the bottom source / drain region.

12. The transistor of claim 8, wherein the average grain size of the top source / drain region and the bottom source / drain region are the same.

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