Integrated circuit life prediction method, device and computer readable storage medium

Abstract

The present application discloses a life prediction method, device and computer-readable storage medium for an integrated circuit. The method includes: obtaining an estimated life of a reference integrated circuit, and obtaining a first duration corresponding to the reference integrated circuit in a set aging stage; obtaining a second duration corresponding to the integrated circuit to be tested in the same aging stage; predicting the life of the integrated circuit to be tested based on the estimated life, the first duration and the second duration; wherein the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, the multiple aging stages of the reference integrated circuit correspond one-to-one to the multiple aging stages of the integrated circuit to be tested, and the maximum power supply voltage of the corresponding aging stages is the same. Through the above method, the present application can simplify the integrated circuit life prediction method and improve the accuracy of the prediction results.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method and device for predicting the life of an integrated circuit, and a computer-readable storage medium. Background Art

[0002] Integrated circuits are used everywhere in our lives. In the fields of civil, commercial, and military, integrated circuits are often key components to maintain the normal operation of various systems. As the market demand for high-performance chips has been greatly reduced, the role of integrated circuit aging mechanisms has been significantly enhanced, and the service life of digital integrated circuits produced below 65nm has been significantly reduced, which has led to severe challenges to the durability of integrated circuits.

[0003] Existing aging mechanism models predict the life of integrated circuits by assuming that they are used under specific conditions, but the actual operation of the circuit is often different from the preset conditions. The speed of circuit aging is determined by the operating temperature, duty cycle, voltage, component size, and operating time. Among them, the operating temperature and duty cycle are related to the operating temperature of the equipment and its environment, work intensity, and application field. These factors cannot be estimated before the equipment is put into use.

[0004] Therefore, the life prediction results without actual operating conditions can only be used as a reference standard when optimizing the circuit, and cannot be used to predict the life of specific equipment in need. However, adding temperature sensors specifically for circuit life prediction and statistics on the running programs and data will greatly increase the cost of integrated circuit manufacturing and waste huge computing resources. Therefore, it is impractical to use full real-time data to estimate the life of the circuit. Summary of the invention

[0005] The present application mainly provides a method, device and computer-readable storage medium for predicting the life of an integrated circuit, which solves the problem of low accuracy in predicting the life of an integrated circuit in the prior art.

[0006] To solve the above technical problems, the first aspect of the present application provides a method for predicting the life of an integrated circuit, comprising: obtaining an estimated life of a reference integrated circuit, and obtaining a first duration corresponding to the reference integrated circuit in a set aging stage; obtaining a second duration corresponding to the integrated circuit to be tested in the same aging stage; predicting the life of the integrated circuit to be tested based on the estimated life, the first duration and the second duration; wherein the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, the multiple aging stages of the reference integrated circuit correspond one-to-one to the multiple aging stages of the integrated circuit to be tested, and the maximum supply voltages of the corresponding aging stages are the same.

[0007] To solve the above technical problems, the second aspect of the present application provides an integrated circuit life prediction device, including: an acquisition module, used to obtain the estimated life of a reference integrated circuit, a first time length corresponding to the reference integrated circuit in a set aging stage, and a second time length corresponding to the integrated circuit to be tested in the same aging stage; a life prediction module, used to predict the life of the integrated circuit to be tested based on the estimated life, the first time length and the second time length.

[0008] To solve the above-mentioned technical problems, the third aspect of the present application provides an integrated circuit life prediction device, comprising a processor and a memory coupled to each other; a computer program is stored in the memory, and the processor is used to execute the computer program to implement the integrated circuit life prediction method provided in the above-mentioned first aspect.

[0009] In order to solve the above technical problems, the fourth aspect of the present application provides a computer-readable storage medium, which stores program data. When the program data is executed by a processor, the integrated circuit life prediction method provided by the first aspect is implemented.

[0010] The beneficial effects of the present application are as follows: Different from the prior art, the present application first obtains the estimated life of the reference integrated circuit, the first duration corresponding to the reference integrated circuit in the set aging stage, and the second duration corresponding to the integrated circuit to be tested in the same aging stage; then, based on the estimated life, the first duration and the second duration, the life of the integrated circuit to be tested is predicted; wherein, the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, the multiple aging stages of the reference integrated circuit correspond one to one with the multiple aging stages of the integrated circuit to be tested, and the maximum power supply voltages of the corresponding aging stages are the same. Since the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specification, the duration of the integrated circuit in the aging stage can indirectly reflect the actual operation status, and there is a certain relationship between the duration and life of the reference integrated circuit and the integrated circuit to be tested in the same aging stage, and the life of the integrated circuit to be tested can be predicted by the duration of the corresponding aging stages of the reference integrated circuit and the integrated circuit to be tested, and the estimated life of the reference integrated circuit. In this process, only a small amount of real-time information is used, which effectively simplifies the life prediction process and improves the accuracy of the prediction result. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 is a schematic diagram of soft errors occurring in the integrated circuit provided by the present application before and after aging;

[0013] Figure 2 It is a schematic flow chart of an embodiment of an integrated circuit life prediction method provided by the present application;

[0014] Figure 3 It is a structural block diagram of the voltage regulation system provided by the present application;

[0015] Figure 4 It is a schematic diagram of a mechanism for converting a supply voltage of an integrated circuit provided by the present application under a voltage regulation system;

[0016] Figure 5 It is a schematic diagram of supply voltage changes at different aging stages provided by the present application;

[0017] Figure 6 This is a schematic flow chart of an embodiment of step S11 provided by the present application;

[0018] Figure 7 It is a schematic structural block diagram of an embodiment of an integrated circuit life prediction device provided by the present application;

[0019] Figure 8 is a schematic structural block diagram of another embodiment of the integrated circuit life prediction device provided by the present application;

[0020] Fig. 9 It is a structural schematic block diagram of an embodiment of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] The terms "first" and "second" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0023] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] See also Figure 1 , Figure 1 This is a schematic diagram of soft errors caused by the aging effect of integrated circuits provided by the present application. Aging of integrated circuits will cause an increase in the propagation delay of the circuit. When the propagation delay of the circuit is greater than the system clock cycle, it will lead to incorrect sampling of registers in the circuit, and further cause the failure of the circuit. This application aims to predict the time required for the propagation delay of the integrated circuit to increase due to aging and cause the propagation delay to be greater than the system clock cycle. It is to predict the time required for the circuit to begin to fail due to soft errors caused by the aging effect of the circuit after the circuit begins to be used, that is, the life prediction of the integrated circuit.

[0025] See also Figure 2 , Figure 2 1 is a schematic flow chart of an embodiment of the integrated circuit life prediction method provided by the present application. It should be noted that if there are substantially the same results, this embodiment does not necessarily Figure 2 The process sequence shown is limited. This embodiment includes the following steps:

[0026] Step S11: Obtain an estimated life span of a reference integrated circuit, and obtain a first duration corresponding to a set aging stage of the reference integrated circuit.

[0027] Among them, the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specifications, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, the multiple aging stages of the reference integrated circuit correspond one-to-one to the multiple aging stages of the integrated circuit to be tested, and the maximum supply voltages of the corresponding aging stages are the same.

[0028] Specifically, the reference integrated circuit and the integrated circuit under test are both equipped with a voltage adjustment system and a soft error monitoring sensor, and the multiple aging stages are obtained according to the adjustment of the maximum supply voltage by the voltage adjustment system.

[0029] See also Figure 3 In pipeline digital integrated circuits, the critical paths in the two data processing stages are equipped with soft error monitoring sensors. After a soft error occurs in the system, the voltage adjustment system increases the supply voltage to shorten the propagation delay to avoid the occurrence of soft errors, such as Figure 4 shown.

[0030] Therefore, in an integrated circuit equipped with a voltage regulation system, the life cycle of the circuit can be divided into multiple aging stages using the period of maximum operating voltage. Figure 5 As shown in the figure, as the digital integrated circuit equipped with a voltage adjustment system is used for a longer time, the aging effect will slowly increase the propagation delay. When the condition that the propagation delay is less than the system clock cycle cannot be met under the maximum voltage, the maximum supply voltage is increased. Therefore, each maximum supply voltage can represent an aging stage. Figure 5 , ①, ②, ③, ④, and ⑤ respectively represent different aging stages of five different maximum supply voltages (V1, V2, V3, V4, and V5), and each aging stage of the integrated circuit corresponds to a duration.

[0031] The integrated circuit to be tested is the prediction object, and the ultimate purpose of this application is to predict the life of the integrated circuit to be tested.

[0032] Step S12: obtaining a second duration corresponding to the integrated circuit under test in the same aging stage.

[0033] In the same aging phase, ie, the aging phase of the integrated circuit under test, the maximum supply voltage is the same as the maximum supply voltage of the set aging phase selected in step S11.

[0034] Step S13: predicting the life of the integrated circuit to be tested according to the estimated life, the first time duration and the second time duration.

[0035] The life of the integrated circuit to be tested may be obtained based on the relationship that the ratio of the estimated life to the life of the integrated circuit to be tested is equal to the ratio of the first time length to the second time length.

[0036] Specifically, the life of the IC under test is calculated according to the following formula:

[0037]

[0038] Among them, LifeTime est LifeTime is the life of the IC under test. ref is the estimated lifespan, t est is the second duration, t ref For the first duration.

[0039] Specifically, the aging degree of the integrated circuit is determined by the average temperature of the chip during operation, the input duty cycle of each component, the voltage difference between the gate and the source, the component design size, and the total operating time. Among them, only the component size and voltage are determined under the preset operating conditions, and the temperature, duty cycle, and operating time are mostly related to the environment and user usage habits. The impact of the integrated circuit NBTI aging effect on the circuit propagation delay can be expressed as follows:

[0040] ΔD NBTI =K·D0α n t n

[0041] Where, ΔD NBTI represents the propagation delay increased by NBTI, K is a constant at a specific system voltage and temperature, D0 represents the propagation delay of the circuit when it is not aged at time zero, α represents the input duty cycle of a single component, t represents the total operating time of the integrated circuit, and n is a constant (usually 0.16). It can be seen that the effective information that can be extracted from the voltage adjustment system is the total operating time t of the integrated circuit and K that changes according to the voltage change.

[0042] The voltage adjustment system adjusts the supply voltage of the integrated circuit according to the actual operation of the integrated circuit, such as Figure 4 Therefore, the effective information that the voltage regulation system can provide is the voltage and the operating time. In addition, the parameters that determine the aging degree of the integrated circuit include the average temperature of the component operation, the duty cycle and the component design size.

[0043] This application uses a reference integrated circuit comparison method to offset the uncertainty of other influencing factors. Specifically, due to the influence of process deviations during the production of integrated circuits, the propagation delays of two integrated circuits of the same design will be different after production, so the safety margins reserved for the aging mechanism will also be different. Therefore, if the propagation delays of two identical integrated circuits (C1 and C2) in different environments and usage habits are compared due to NBTI, the results are:

[0044]

[0045] Among them, ConstantNBTI is the ratio of the safety margins between the two integrated circuits, which is a fixed constant after production. Similarly, the propagation delay of the two circuits at time zero is also a constant. In addition, the usage habits (α) and operating environment (K) of the same circuit itself are the same because the application scenario has not changed, that is:

[0046]

[0047]

[0048] Among them, K C1 , K C2 are the operating environment parameters of the two integrated circuits, D 0C1 , D 0C2 are the propagation delays of the two integrated circuits at time zero, They are the customary parameters of the two integrated circuits. are the operating time of the two integrated circuits respectively.

[0049] Therefore, the average temperature of circuit operation, duty cycle, and component design size can all be estimated using reference integrated circuit data with known lifespans, namely:

[0050]

[0051] Among them, t C1 With t C2 are the operating time of two integrated circuits with the same specifications, and A is a constant. Therefore, the time ratio of two integrated circuits in the same aging stage is also a constant A, that is:

[0052]

[0053] Among them, Δt C1 , Δt C2 They are the corresponding time durations of the two integrated circuits in the same aging stage.

[0054] Therefore, for an integrated circuit under test whose life span is unknown, a reference integrated circuit with a known life span can be used to predict the life span.

[0055] See also Figure 6 , Figure 6 is a flowchart of an embodiment of step S11 provided by the present application. It should be noted that if there are substantially the same results, this embodiment does not necessarily Figure 6 The process sequence shown is limited. This embodiment includes the following steps:

[0056] Step S111: Perform an aging test on the reference integrated circuit, record the duration corresponding to each aging stage, and record the total working time of the reference integrated circuit.

[0057] Specifically, a voltage adjustment system is configured for a reference integrated circuit, and an aging test is performed to obtain multiple aging stages, and the duration and maximum supply voltage of each aging stage can be recorded.

[0058] Step S112: selecting one of the aging stages as the set aging stage, taking the duration corresponding to the set aging stage as the first duration, and taking the total working duration as the estimated lifespan.

[0059] Among them, the choice of setting the aging stage can be selected according to the preset voltage, specifically, the aging stage corresponding to the maximum supply voltage and the preset voltage is selected as the preset aging stage, the duration corresponding to the preset aging stage is used as the first duration, and the total working time is used as the estimated life.

[0060] To obtain the second duration, an aging stage having the same maximum supply voltage as the set aging stage can be selected during the aging stage of the integrated circuit to be tested, and the duration of the aging stage is used as the second duration.

[0061] Different from the prior art, this application combines the integrated circuit life prediction technology with the voltage adjustment system, and compares and analyzes the operating time of the integrated circuit under test at the same aging stage using a reference integrated circuit with the same known aging detailed data as the integrated circuit under test, and then makes an accurate prediction of the life cycle of the integrated circuit through the limited real-time information provided by the voltage adjustment system. Compared with adding temperature sensors specifically for the life prediction of integrated circuits and the method of statistically analyzing the programs and data being run, this application greatly saves the manufacturing cost of integrated circuits and reduces the occupation of computing resources.

[0062] Therefore, while accurately predicting the life of an integrated circuit, the present application greatly reduces the cost and complexity of building an integrated circuit aging prediction system.

[0063] See also Figure 7 , Figure 7 It is a schematic block diagram of the structure of an embodiment of the integrated circuit life prediction device of the present application. The integrated circuit life prediction device 100 includes an acquisition module 110 and a life prediction module 120, wherein the acquisition module 110 is used to obtain the estimated life of the reference integrated circuit, the first duration corresponding to the reference integrated circuit in the set aging stage, and the second duration corresponding to the integrated circuit to be tested in the same aging stage, and the life prediction module 120 is used to predict the life of the integrated circuit to be tested based on the estimated life, the first duration and the second duration. Among them, multiple aging stages are obtained according to the adjustment of the maximum power supply voltage by the voltage adjustment system.

[0064] Among them, the integrated circuit life prediction device 100 may also include a test module (not shown in the figure), which is used to perform an aging test on the reference integrated circuit, record the duration corresponding to each aging stage, and record the total working time of the reference integrated circuit. The acquisition module 110 can also be used to select one of the aging stages as the set aging stage, obtain the events experienced in the set aging stage as the first duration, and obtain the total working time as the estimated life.

[0065] The life prediction module 120 is further used to obtain the life of the integrated circuit under test according to the relationship that the ratio of the estimated life to the life of the integrated circuit under test is equal to the ratio of the first time length to the second time length.

[0066] For the specific methods of each step executed by each module processing, please refer to the description of each step of the embodiment of the integrated circuit life prediction method of the present application, which will not be repeated here.

[0067] See also Figure 8 , Figure 8 The integrated circuit life prediction device 200 includes a processor 210 and a memory 220 coupled to each other, the memory 220 stores a computer program, and the processor 210 is used to execute the computer program to implement the integrated circuit life prediction method described in the above embodiments.

[0068] For the description of each step of the processing execution, please refer to the description of each step of the embodiment of the integrated circuit life prediction method of the present application, which will not be repeated here.

[0069] The memory 220 can be used to store program data and modules. The processor 210 executes various functional applications and data processing by running the program data and modules stored in the memory 220. The memory 220 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function (such as a data processing function), etc.; the data storage area may store data created according to the use of the integrated circuit life prediction device 200 (such as reference integrated circuit life data, reference integrated circuit maximum voltage number and corresponding duration data in each aging stage, aging stage data of the integrated circuit to be tested, etc.). In addition, the memory 220 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage device. Accordingly, the memory 220 may also include a memory controller to provide the processor 210 with access to the memory 220.

[0070] In each embodiment of the present application, the disclosed method and device can be implemented in other ways. For example, the embodiments of the integrated circuit life prediction device 200 described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0071] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0072] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0073] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium.

[0074] See also Fig. 9 , Fig. 9 This is a schematic block diagram of the structure of an embodiment of a computer-readable storage medium of the present application. The computer-readable storage medium 300 stores program data 310. When the program data 310 is executed, the steps of each embodiment of the integrated circuit life prediction method as described above are implemented.

[0075] For the description of each step of the processing execution, please refer to the description of each step of the embodiment of the integrated circuit life prediction method of the present application, which will not be repeated here.

[0076] The computer-readable storage medium 300 may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which may store program codes.

[0077] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for predicting the life of an integrated circuit, characterized in that: The method comprises: Obtaining an estimated life span of a reference integrated circuit, and obtaining a first duration corresponding to the reference integrated circuit in a set aging stage; Obtaining a second duration corresponding to the integrated circuit under test in the same aging stage; Predicting the life of the integrated circuit under test according to the estimated life, the first duration, and the second duration; Among them, the reference integrated circuit and the integrated circuit to be tested are integrated circuits of the same specifications, the reference integrated circuit and the integrated circuit to be tested include multiple aging stages, the multiple aging stages of the reference integrated circuit correspond one-to-one to the multiple aging stages of the integrated circuit to be tested, and the maximum supply voltages of the corresponding aging stages are the same.

2. The method according to claim 1, characterized in that The obtaining of the estimated life span of the reference integrated circuit and the obtaining of the first duration corresponding to the reference integrated circuit in the set aging stage include: Performing an aging test on the reference integrated circuit, recording the duration corresponding to each aging stage, and recording the total working time of the reference integrated circuit; One of the aging stages is selected as the set aging stage, the duration corresponding to the set aging stage is used as the first duration, and the total working time is used as the estimated lifespan.

3. The method according to claim 1, characterized in that The predicting the life of the integrated circuit under test according to the estimated life, the first duration, and the second duration includes: The life of the integrated circuit under test is obtained according to the relationship that the ratio of the estimated life to the life of the integrated circuit under test is equal to the ratio of the first time length to the second time length.

4. The method according to claim 3, characterized in that The obtaining of the life of the integrated circuit under test according to the relationship that the ratio of the estimated life to the life of the integrated circuit under test is equal to the ratio of the first time length to the second time length includes: The life of the integrated circuit under test is calculated according to the following formula: Among them, LifeTime est is the life of the IC under test, LifeTime ref is the estimated lifespan, t est is the second duration, t ref The first duration.

5. The method according to claim 1, characterized in that The plurality of aging stages are formed according to the adjustment of the maximum supply voltage by a voltage adjustment system.

6. An integrated circuit life prediction device, characterized in that: The device comprises: An acquisition module, configured to acquire an estimated life span of a reference integrated circuit, a first duration corresponding to the reference integrated circuit in a set aging stage, and a second duration corresponding to the integrated circuit to be tested in the same aging stage; The life prediction module is used to predict the life of the integrated circuit under test according to the estimated life, the first time period and the second time period.

7. The device according to claim 6, characterized in that The device also includes a test module for performing an aging test on the reference integrated circuit, recording the duration corresponding to each aging stage, and recording the total working duration of the reference integrated circuit; The acquisition module is also used to select one of the aging stages as the set aging stage, acquire the events experienced in the set aging stage as the first duration, and acquire the total working time as the estimated lifespan.

8. The device according to claim 6, characterized in that The life prediction module is further used to obtain the life of the integrated circuit under test according to the relationship that the ratio of the estimated life to the life of the integrated circuit under test is equal to the ratio of the first time length to the second time length.

9. An integrated circuit life prediction device, characterized in that: The integrated circuit life prediction device includes a processor and a memory coupled to each other; a computer program is stored in the memory, and the processor is used to execute the computer program to implement the steps of the method as described in any one of claims 1-5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program data, and when the program data is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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