Method, apparatus and system for wafer grounding

Abstract

Systems and methods for wafer grounding and wafer grounding position adjustment are disclosed. A first method may include: receiving a first value of an electrical characteristic associated with a wafer grounded by an electrical signal; determining a first control parameter using at least the first value; and controlling the characteristics of the electrical signal using the first control parameter and the first value. A second method for adjusting the grounding position of a wafer may include: terminating an electrical connection between the wafer and at least one grounding pin contacting the wafer; adjusting the relative position between the wafer and the grounding pin; and restoring the electrical connection between the grounding pin and the wafer. A third method may include: causing the grounding pin to penetrate a coating on the wafer by an impact; and establishing an electrical connection between the grounding pin and the wafer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 893,135 filed on August 28, 2019, U.S. Application No. 63 / 022,374 filed on May 8, 2020, and U.S. Application No. 63 / 068,839 filed on August 21, 2020, which are incorporated herein by reference in their entirety. Technical Field

[0003] The description herein relates to the field of charged particle beam equipment, and more particularly to wafer grounding and biasing for semiconductor wafer manufacturing. Background Art

[0004] Charged particle beam equipment can produce a two-dimensional image of a wafer substrate by detecting secondary electrons, backscattered electrons, mirror electrons or other types of electrons from the surface of the wafer substrate when struck by the charged particle beam generated by the charged particle beam equipment. Various charged particle beam equipment are used for various purposes on semiconductor wafers in the semiconductor industry, such as wafer processing (e.g., electron beam direct writing lithography system), process monitoring (e.g., critical dimension scanning electron microscope (CD-SEM)), wafer inspection (e.g., electron beam inspection system), defect analysis (e.g., defect review SEM, or DR-SEM and focused ion beam system, or FIB), etc. When such equipment performs its function, the potential of the wafer substrate can be maintained at a predetermined value or biased for better imaging. This can be achieved by electrically or more specifically connecting the target wafer substrate to a programmable DC voltage source (e.g., wafer bias power supply) when the wafer substrate interacts with the charged particle beam, in which process, excess charge is brought to the wafer substrate. This process can be called wafer biasing.

[0005] For wafer biasing, electrical contact from a wafer bias supply to the wafer substrate is typically made at the backside of the wafer substrate by using one or more electrical contacts pressed against the backside of the wafer substrate when the front surface of the wafer is not suitable for placement of electrical contacts. Summary of the invention

[0006] Embodiments of the present disclosure provide systems and methods for grounding a wafer. In some embodiments, a method for grounding a wafer may include receiving a first value of an electrical characteristic associated with a wafer grounded by an electrical signal. The method may also include determining a first control parameter using at least the first value. The method may also include controlling a characteristic of the electrical signal using the first control parameter and the first value.

[0007] In some embodiments, a system for grounding a wafer is disclosed. The system may include: a sensor configured to generate a first value of an electrical characteristic associated with the wafer being grounded by an electrical signal; an electrical signal generator configured to generate the electrical signal; and a controller including a circuit device for receiving the first value of the electrical characteristic, determining a first control parameter using at least the first value, and controlling the characteristic of the electrical signal using the first control parameter and the first value.

[0008] In some embodiments, a method for adjusting a grounding position of a wafer is disclosed. The method may include terminating an electrical connection between the wafer and a ground pin contacting the wafer. The method may also include adjusting a relative position between the wafer and the ground pin. The method may also include restoring an electrical connection between the ground pin and the wafer.

[0009] In some embodiments, a system for adjusting a grounding position of a wafer is disclosed. The inspection system may include a grounding pin configured to contact the wafer, and an actuator configured to terminate an electrical connection between the wafer and the grounding pin, adjust a relative position between the wafer and the grounding pin, and restore an electrical connection between the grounding pin and the wafer.

[0010] In some embodiments, a method for grounding a wafer is disclosed. The method may include establishing a set of contact points between a plurality of probes and the wafer. The method may also include applying a first set of electrical signals to the set of contact points via the plurality of probes to facilitate breakdown of a coating of the wafer. The method may also include: applying a second set of electrical signals to the set of contact points via the plurality of probes based on determining that a resistance of an electrical path between the plurality of probes via the wafer is greater than or equal to a predetermined threshold, wherein the second set of electrical signals is determined based on a value of an electrical characteristic associated with the wafer when the first set of electrical signals is applied.

[0011] In some embodiments, a method for grounding a wafer is disclosed. The method may include establishing a first set of contact points between a plurality of probes and the wafer. The method may also include applying a first set of electrical signals to the first set of contact points via the plurality of probes to facilitate breakdown of a coating of the wafer. The method may also include: when the resistance of an electrical path between the plurality of probes via the wafer is greater than or equal to a predetermined threshold, establishing a second set of contact points between the plurality of probes and the wafer. The method may also include applying a second set of electrical signals to the second set of contact points via the plurality of probes, wherein the second set of electrical signals is determined based on the value of an electrical characteristic associated with the wafer when the first set of electrical signals is applied.

[0012] In some embodiments, a method for grounding a wafer is disclosed. The method may include causing a ground pin to contact the wafer. The method may also include vibrating at least one of the ground pin or the wafer. The method may also include establishing an electrical connection between the ground pin and the wafer.

[0013] In some embodiments, a system is disclosed. The system may include a ground pin configured to contact a wafer. The system may also include a controller having circuitry for vibrating at least one of the ground pin or the wafer and establishing an electrical connection between the ground pin and the wafer.

[0014] In some embodiments, a method for grounding a wafer is disclosed. The method may include causing a ground pin to penetrate a coating on the wafer by impact. The method may also include establishing an electrical connection between the ground pin and the wafer.

[0015] In some embodiments, a system is disclosed. The system may include a ground pin and a controller having a circuit for controlling the ground pin to penetrate a coating on a wafer by striking and establish an electrical connection between the ground pin and the wafer.

[0016] In some embodiments, a non-transitory computer readable medium may store a set of instructions executable by at least one processor of a device to cause the device to perform a method. The method may include causing a ground pin to penetrate a coating on a wafer by impact. The method may also include establishing an electrical connection between the ground pin and the wafer.

[0017] In some embodiments, a system for wafer grounding is disclosed. The system may include a first ground pin. The system may also include an electrostatic keeper including a first electrode inside the electrostatic keeper. The system may also include a first overvoltage protection device electrically coupled between the first ground pin and the first electrode, wherein the first overvoltage protection device is configured to conduct power when a first voltage applied to the first overvoltage protection device exceeds a threshold voltage, and stop conducting power when the first voltage does not exceed the threshold voltage.

[0018] In some embodiments, a device for rapid ramping of high voltage is disclosed. The device may include an isolator disposed between a high voltage portion of the device and a ground portion of the device. The device may also include a first electrode electrically coupled to the high voltage portion. The device may also include a second electrode electrically coupled to the ground portion and not electrically conductive to the first electrode. The device may also include a dielectric layer covering the first electrode and the second electrode above the isolator. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram illustrating an example electron beam inspection (EBI) system consistent with some embodiments of the present disclosure.

[0020] Figure 2 is a schematic diagram showing an example electron beam tool consistent with some embodiments of the present disclosure, which may be Figure 1 An example of a portion of an electron beam inspection system.

[0021] Figure 3 is an illustration of an example system for wafer grounding consistent with some embodiments of the present disclosure.

[0022] Figure 4 is a diagram of an example multi-pin wafer grounding system consistent with some embodiments of the present disclosure.

[0023] Figure 5 is a flow chart illustrating an example method for wafer grounding consistent with some embodiments of the present disclosure.

[0024] Figure 6 is an illustration of an example system for wafer ground position adjustment consistent with some embodiments of the present disclosure.

[0025] Figure 7 is an illustration of an example system for wafer ground position adjustment consistent with some embodiments of the present disclosure.

[0026] Figure 8 is an illustration of example ground locations before and after adjustment consistent with some embodiments of the present disclosure.

[0027] Fig. 9 is an illustration of an example system for wafer ground position adjustment consistent with some embodiments of the present disclosure.

[0028] Fig.10 is a flow chart illustrating an example method of adjusting a grounding position of a wafer consistent with some embodiments of the present disclosure.

[0029] Fig.11 is a flow chart illustrating another example method for adjusting a grounding position of a wafer consistent with some embodiments of the present disclosure.

[0030] Fig.12 is a diagram of an example multi-pin wafer grounding system consistent with some embodiments of the present disclosure.

[0031] Fig.13 is a flow chart illustrating an example method for wafer grounding consistent with some embodiments of the present disclosure.

[0032] FIG. 14A to FIG. 14D Operational stages of an example system for wafer grounding consistent with some embodiments of the present disclosure are shown.

[0033] FIG. 15A to FIG. 15D Operational stages of another example system for wafer grounding consistent with some embodiments of the present disclosure are shown.

[0034] Fig.16is a flow chart illustrating an example method for wafer grounding consistent with some embodiments of the present disclosure.

[0035] Fig.17 is an illustration of an example wafer grounding system consistent with some embodiments of the present disclosure in which a voltage difference is instantaneously created between an electrode of an electrostatic holder and a ground pin.

[0036] Fig.18 is an illustration of an example wafer grounding system consistent with some embodiments of the present disclosure in which a voltage differential is prevented from forming between an electrode of an electrostatic holder and a ground pin.

[0037] FIG. 19A to FIG. 19C is an illustration of an example wafer grounding system consistent with some embodiments of the present disclosure in which a voltage differential is prevented from forming between an electrode of an electrostatic holder and a ground pin.

[0038] Fig. 20 A cross-sectional view of an example wafer inspection system consistent with some embodiments of the present disclosure is shown in which discharge may occur at a high voltage portion.

[0039] Fig.21 is an illustration of an example device for rapid ramping of high voltage without inducing discharge, consistent with some embodiments of the present disclosure.

[0040] Fig. 22 is an illustration of another example apparatus for rapid ramping of high voltage without causing discharge, consistent with some embodiments of the present disclosure.

[0041] Fig.23 is an illustration of yet another example apparatus for rapid ramping of high voltage without causing discharge, consistent with some embodiments of the present disclosure.

[0042] Fig.24 is an illustration of yet another example apparatus for rapid ramping of high voltage without causing discharge, consistent with some embodiments of the present disclosure.

[0043] Fig.25 is a cross-sectional view of an example wafer inspection system for rapid ramping of high voltage without causing discharge, consistent with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] Reference will now be made in detail to example embodiments, examples of which are shown in the accompanying drawings. The following description refers to the accompanying drawings, in which the same numbers in different drawings represent the same or similar elements, unless otherwise stated. The implementations set forth in the following description of the example embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with aspects related to the subject matter recorded in the appended claims. Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing a detection system and a detection method in a system utilizing an electron beam ("e-beam"). However, the present disclosure is not limited thereto. Other types of charged particle beams (e.g., including protons, ions, muons, or any other particles carrying an electric charge) may be similarly applied. In addition, the systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, X-ray detection, ion detection, and the like.

[0045] Electronic devices consist of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits may be formed together on the same piece of silicon and are called integrated circuits, or ICs. The size of these circuits has been reduced significantly so that more circuits can be mounted on a substrate. For example, an IC chip in a smartphone may be as small as a fingernail but may include more than 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0046] Manufacturing these ICs, which have extremely small structures or components, is a complex, time-consuming, and expensive process that typically involves hundreds of individual steps. An error in even one step can cause the finished IC to be defective, rendering it useless. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process; that is, to increase the overall yield of the process.

[0047] An integral part of improving yield is monitoring the chip manufacturing process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. This inspection can be performed using a scanning charged particle microscope ("SCPM"). For example, the SCPM can be a scanning electron microscope (SEM). The SCPM can be used to image these extremely small structures, in effect "taking a picture" of the structure of the wafer. The image can be used to determine whether the structure is correctly formed in the appropriate location. If the structure is defective, the process can be adjusted so the defect is less likely to occur again.

[0048] The working principle of SEM is similar to that of a camera. A camera takes a picture by receiving and recording the intensity of light reflected or emitted from a person or object. SEM takes a "picture" by receiving and recording the energy or number of electrons reflected or emitted from the structure of the wafer. Before taking such a "picture", an electron beam can be projected onto the structure, and when the electrons are reflected or emitted ("leave") from the structure (e.g., from the surface of the wafer, from the structure below the surface of the wafer, or both), the detector of the SEM can receive and record the energy or number of these electrons to generate an inspection image. In order to take such a "picture", the electron beam can scan the wafer (e.g., in a line-by-line or zigzag manner), and the detector can receive the outgoing electrons from the area below the electron beam projection (referred to as a "beam spot"). The detector can receive and record the outgoing electrons from each beam spot one at a time, and combine the information recorded for all beam spots to generate an inspection image. Some SEMs use a single electron beam (referred to as "single-beam SEM") to take a single "picture" to generate an inspection image, while some SEMs use multiple electron beams (referred to as "multi-beam SEM") to take multiple "sub-pictures" of the wafer in parallel and stitch them together to generate an inspection image. By using multiple electron beams, the SEM can provide more electron beams to the structure to obtain these multiple "sub-pictures", resulting in more electrons being emitted from the structure. Therefore, the detector can receive more emitted electrons at the same time, and generate inspection images of the wafer structure with higher efficiency and faster speed.

[0049] Typically, the structure is made on a substrate (e.g., a silicon substrate) that is placed on a platform called a stage for imaging. When the electron beams hit the structure, they may charge the substrate and make it no longer electrically neutral. The charged substrate can acquire voltage and affect the emitted electrons, which may affect the imaging quality. Therefore, in order to improve imaging, it may be advantageous to ground the substrate.

[0050] For grounding, the substrate can be electrically connected to a power source. The electrical connection between the power source and the substrate can be achieved by pressing one or more conductive ground pins or probes against the back side (i.e., the surface without structure) of the substrate. The back side of the substrate is usually covered with a thin layer of material ("backside film") that is created as a protective covering during the manufacturing process of the substrate.

[0051] However, the backside film is not conductive. Generally, two methods can be used to overcome this non-conductive backside film: penetration method and electrical breakdown method. In the penetration method, the ground pin can be pressed to penetrate the backside film and directly contact the substrate. However, this penetration method may cause damage to the backside film, which may cause damage to the substrate during the manufacturing process and also cause excessive particle generation, thereby contaminating the vacuum chamber of the SEM.

[0052] In the electrical breakdown method, the ground pin can press and partially penetrate, but not completely penetrate, the back film. The power supply can generate a high voltage (e.g., tens of kilovolts) electrical signal ("ground signal") between the ground pins to destroy the back film to establish an electrical connection between the ground pin and the wafer. The ground signal can cause electrical breakdown between the tip of the ground pin and the back film.

[0053] But the electrical breakdown method also has its challenges. The first challenge is that different types of substrates require different optimized voltages of the ground signal in order to break through the back film, and doing so will not cause excessive damage. That is, the voltage of the ground signal optimized for one type of substrate may not be able to break through the back film of another type of substrate, resulting in the inability to create an electrical connection between the ground pin and the wafer. The second challenge is that the voltage of the ground signal is too high and may cause excessive damage to the wafer around the tip of the ground pin (for example, a micro-explosion of the back film), resulting in the generation of particles that may contaminate the imaging environment (for example, the vacuum chamber of the SEM system). The third challenge is that the electrical breakdown may fail at certain grounding locations, but repeated breakdown at the same location may be undesirable because it may result in a shortened life of the ground pin or an excessive number of contaminating particles. Therefore, these two methods need to be improved.

[0054] Embodiments of the present disclosure can provide an improved wafer grounding system. Wafer grounding can be achieved by a penetration method or an electrical breakdown method. According to an embodiment of the electrical breakdown method of the present disclosure, the contact position of the grounding pin can be dynamically adjusted. If grounding is unsuccessful at the initial contact position, the probability of successful wafer grounding can be increased by dynamically adjusting the contact position and applying different grounding signals, while reducing contamination in the vacuum chamber and extending the life of the grounding pin (compared to the current method). In addition, according to an embodiment of the electrical breakdown method of the present disclosure, the electrical characteristics of the electrical signal used for wafer grounding can also be dynamically adjusted based on the measurement feedback of the grounding electrical path. By dynamically adjusting the electrical characteristics, the life of the grounding pin can be extended, the contamination in the detection vacuum chamber can be reduced, and the electrical signal can be conveniently adapted to ground different types of wafers. In addition, according to embodiments of the penetration method and the electrical breakdown method in the present disclosure, a vibrator can be provided for vibrating the grounding pin relative to the wafer to improve the contact between the grounding pin and the wafer. The vibrator can be used in a system using a penetration method, in which the explosion of the back film and the deposition of contaminant particles can be avoided, and the life of the grounding pin can be extended. The vibrator can also be used in a system using only the electrical breakdown method or a system combining the two methods, wherein the grounding position of the grounding pin can be provided with additional dimensions for adjustment and the success rate of wafer grounding can be increased.

[0055] Embodiments of the present disclosure include methods and systems for grounding a wafer and adjusting the grounding position of a wafer. For example, a wafer grounding system may receive a first value of an electrical characteristic associated with a wafer grounded by an electrical signal. The wafer grounding system may also determine a first control parameter using at least the first value. The wafer grounding system may also control the characteristics of the electrical signal using the first control parameter and the first value. For another example, the wafer grounding system may separate a wafer and a grounding pin. The wafer grounding system may also adjust the relative position between the wafer and the grounding pin. The wafer grounding system may also reattach the grounding pin and the wafer. Details of the embodiments are described below.

[0056] In addition, in some special cases, highly complex structures may be manufactured on the wafer, which may bring more challenges to wafer grounding. For example, some ICs may be manufactured to include a large number of layers. Such a multilayer structure may cause the tension on the surface of the wafer to be higher than normal. The high tension may cause the wafer to warp or bend, which may cause errors (e.g., blur) in the inspection image. In order to avoid wafer warping or bending due to such complex structures, some wafers used to manufacture such complex ICs may be coated with a thickened back film to enhance their mechanical strength. However, a thickened back film that is thick enough to prevent wafer warping may be too thick to make both the electrical breakdown method and the penetration method unusable for wafer grounding.

[0057] Embodiments of the present disclosure also include methods and systems for wafer grounding using a "pin-bumping" method. The wafer grounding system can actuate a grounding pin to bump the thickened backside film, thereby penetrating it in a fully penetrating or partially penetrating manner. After penetrating the thickened backside film by bumping, an electrical connection can be established between the grounding pin and the conductive surface of the wafer for wafer grounding.

[0058] Typically, the substrate is placed and fixed on the stage by an electrostatic holder (or "electrostatic chuck"). The electrostatic holder may include at least one electrode, and a non-conductive dielectric material may be provided between the electrode and the substrate. For example, the electrode may be disposed below the top surface of the stage. When a clamping voltage is applied, the electrode may attract and fix the substrate to the top surface of the stage via an electrostatic field. When the clamping voltage is turned off, the electrode may lose the electrostatic field and the substrate may detach from the stage.

[0059] However, in some cases, after the clamping voltage is turned off, residual charge may appear on the electrostatic holder, which may cause residual clamping force. The residual clamping force may make it difficult to release the substrate, and in some cases, the substrate may not be released at all. This "chip sticking" problem may affect the performance and utilization of the device. The residual charge may accumulate over a period of time or form instantaneously when the clamping voltage is applied. For example, during normal operation of the electrostatic holder, the ground pin may contact the substrate to provide a ground signal. The substrate may be biased with a voltage potential (e.g., 30 kilovolts). The electrodes of the electrostatic holder may be provided with a clamping voltage (e.g., +300 or -300 volts) floating on the voltage potential. When the clamping voltage is periodically turned on and off (e.g., for fixing and releasing multiple substrates), the residual charge may accumulate on the surface of the electrostatic holder over a period of time due to the voltage difference between the voltage potential and the clamping voltage causing the charge to be not completely neutralized. In the event of an arc in the circuit of the electrode, residual charge may be formed transiently when the clamping voltage is applied, where the transient voltage difference between the substrate and the electrode (e.g., 10 kilovolts) may significantly disturb the clamping voltage, while the voltage potential is not affected. This transient voltage difference may cause a strong electric field to be transiently formed between the substrate and the electrode, which may attract or repel charge in the substrate relative to the top surface of the electrostatic holder.

[0060] Several designs can be used to reduce the residual clamping force. In some cases, a first design can be used to deal with residual charge that accumulates over a period of time. For example, the electrostatic holder can be provided with lift pins that can be used to lift the substrate when the presence of residual clamping force is detected. As another example, an ion generator can be provided with the electrostatic holder, and if the residual clamping force is measured to be above a predetermined threshold, the ion generator can be used to neutralize (e.g., by emitting ions) the residual charge on the surface of the electrostatic holder.

[0061] However, in the case of transient residual charge formation, the first design may not be effective because the initial residual force cannot be measured. In these cases, the second design can be used. For example, a discharge controller can be provided for the electrostatic holder, which can control the discharge voltage of the electrostatic holder to temporarily neutralize the residual charge on the surface of the electrostatic holder until the residual clamping force is measured to be below a predetermined threshold so that the lifting pins can be used to lift the substrate, and the residual charge is completely neutralized after the substrate is released. However, the second design of the electrostatic holder relies on the discharge capability of the electrostatic holder rather than the discharge capability of the ion generator, which may not be able to effectively neutralize all residual charge.

[0062] Embodiments of the present disclosure also include devices and systems for preventing the formation of residual charge caused by the voltage difference formed instantaneously between the substrate and the electrostatic holder, which may include an overvoltage protection device that is communicatively coupled between the electrode of the electrostatic holder and the substrate. The overvoltage protection device may be conductive under an overvoltage and reset to be non-conductive when the overvoltage is removed. For example, when the voltage difference between the electrode and the substrate is lower than a threshold voltage, the overvoltage protection device may be conductive. When the voltage difference is higher than the threshold voltage (for example, caused by an arc discharge occurring in the circuit of the electrode), the overvoltage protection device may become conductive to conduct electricity between the electrode and the substrate so that the voltage difference between them can be reduced or eliminated. When the voltage difference drops below the threshold voltage again, the overvoltage protection device may become non-conductive again. By doing so, residual charge is not formed instantaneously on the substrate or the electrostatic holder.

[0063] In some cases, one reason for the voltage difference formed instantaneously between the substrate and the electrostatic holder may be a discharge near the electrostatic holder. Typically, the electrostatic holder can be placed on the top surface of the housing of the stage. In order to bias the substrate fixed on the electrostatic holder, the top surface of the housing can be conductive and a bias high voltage potential (e.g., -30 kV) is applied. The housing is grounded, such as by connecting the bottom surface of the housing to the ground. The top and bottom surfaces of the housing can be isolated by one or more isolators. For example, the isolator can be one or more walls of the housing.

[0064] One challenge of existing wafer grounding systems is that the isolator between the high voltage portion (e.g., the top surface of the housing) and the grounded portion (e.g., the bottom surface of the housing) of the system may be susceptible to undesirable discharges. When the electric field between the high voltage portion and the isolator is too strong, field emission of charge may begin between them, which may cause electrons to detach from the surface of the high voltage portion. If these field emission electrons have enough landing energy to release gas molecules adhering to the surface of the isolator, an avalanche effect may be triggered, which may eventually lead to dielectric breakdown between the high voltage portion and the isolator. For example, arc discharges may occur, which may release a large amount of charge near the high voltage portion. Such discharges may interfere with the clamping voltage of the electrostatic holder (e.g., by causing a voltage difference to be formed instantaneously between the substrate and the electrostatic holder) and cause residual charge to form on the electrostatic holder, which may cause wafer sticking problems as described herein. In addition, such discharges may attract unwanted particles (e.g., dust) from the environment, which may cause potential damage to the wafer grounding system.

[0065] During normal operation of the wafer grounding system, field emissions do not occur because the voltage of the high voltage portion of the system is stable. However, when the high voltage is switched on and off (e.g., for substrate replacement or repair service), the surface voltage of the isolator may respond capacitively to the ramping up or down of the high voltage (e.g., the isolator and the high voltage portion are the two terminals of an effective capacitor). In this case, the electric field between the high voltage portion and the isolator may become strong enough to cause field emissions and ultimately lead to undesirable discharges.

[0066] To prevent unwanted discharges, existing wafer grounding systems may have to ramp up or down high voltages at slow speeds. However, such slow ramping speeds may limit wafer inspection throughput, especially in multi-beam inspection systems.

[0067] Embodiments of the present disclosure also include devices and systems for rapid ramping of high voltage without causing discharge. For example, such a device may include an isolator arranged between a high voltage portion of the device and a ground portion of the device. The device may also include a first electrode electrically coupled to the high voltage portion and a second electrode electrically coupled to the ground portion and non-conductive with the first electrode. The device may also include a dielectric layer covering the first electrode and the second electrode on the isolator. By doing so, a strong electric field can be limited to be formed near the ends of the first electrode and the second electrode and near the surface of the isolator. In addition, a smooth sinking electric field can be formed between the first electrode and the second electrode, which can avoid a sudden change in the electric field gradient corresponding to a high electric field strength. In addition, by covering the first electrode and the second electrode, the surrounding environment may have a weaker effect on the electric field between them. In addition, even if the electric field between the first electrode and the second electrode becomes very strong, since the first electrode and the second electrode are covered by the dielectric layer and the isolator, field emission will not occur. In general, the provided device and system can provide rapid ramping of high voltage without causing any undesirable discharge, reducing the possibility of wafer adhesion problems, greatly improving the throughput of wafer inspection, and reducing environmental hazards caused by undesirable discharge.

[0068] For the sake of clarity, the relative sizes of components in the drawings may be exaggerated.In the following description of the figures, identical or similar reference numerals refer to identical or similar components or entities and only the differences with respect to individual embodiments are described.

[0069] As used herein, unless otherwise expressly stated, the term "or" encompasses all possible combinations unless not feasible. For example, if it is stated that a component may include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0070] Figure 1 An exemplary electron beam inspection (EBI) system 100 consistent with some embodiments of the present disclosure is shown. The EBI system 100 can be used for imaging. Figure 1 As shown, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. The beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first load port 106a and a second load port 106b. The EFEM 106 may include (multiple) additional load ports. The first load port 106a and the second load port 106b receive a wafer front opening pod (FOUP) that contains wafers to be inspected (e.g., semiconductor wafers or wafers made of (multiple) other materials) or samples to be inspected (wafers and samples may be used interchangeably). A "batch" is a plurality of wafers that can be loaded as a batch for processing.

[0071] One or more robots (not shown) in the EFEM 106 can transport the wafer to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) that removes gas molecules in the load / lock chamber 102 to reach a first pressure lower than atmospheric pressure. After reaching the first pressure, one or more robots (not shown) can transport the wafer from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules in the main chamber 101 to reach a second pressure lower than the first pressure. After reaching the second pressure, the wafer is subjected to inspection by the beam tool 104. The beam tool 104 can be a single beam system or a multi-beam system.

[0072] The controller 109 is electronically connected to the beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. Figure 1 106 , it is shown as being external to the structure including the main chamber 101 , the load / lock chamber 102 , and the EFEM 106 , it being understood that the controller 109 may be a part of the structure.

[0073] In some embodiments, the controller 109 may include one or more processors (not shown). The processor may be a general or specific electronic device capable of manipulating or processing information. For example, the processor may include any number of any combination of the following: a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a general array logic (GAL), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a system on a chip (SoC), an application specific integrated circuit (ASIC), and any type of circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed on multiple machines or devices coupled via a network.

[0074] In some embodiments, the controller 109 may also include one or more memories (not shown). The memory may be a general or specific electronic device capable of storing code and data that is accessible to the processor (e.g., via a bus). For example, the memory may include any number of any combination of the following: random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard drive, solid-state drive, flash drive, secure digital (SD) card, memory stick, compact flash (CF) card, or any type of storage device. The code may include an operating system (OS) and one or more applications (or "apps") for a specific task. The memory may also be a virtual memory that includes one or more memories distributed on multiple machines or devices coupled via a network.

[0075] Figure 2 An example imaging system 200 is shown in accordance with an embodiment of the present disclosure. Figure 2 The electron beam tool 104 can be configured for use with the EBI system 100. The electron beam tool 104 can be a single beam device or a multi-beam device. Figure 2As shown, the electron beam tool 104 includes a motorized sample stage 201, and a wafer holder 202 supported by the motorized sample stage 201 to hold a wafer 203 to be inspected. The electron beam tool 104 also includes an objective lens assembly 204, an electron detector 206 (which includes electron sensor surfaces 206a and 206b), an objective lens aperture 208, a condenser lens 210, a beam limiting aperture 212, a gun aperture 214, an anode 216, and a cathode 218. In some embodiments, the objective lens assembly 204 may include a modified swing objective delayed immersion lens (SORIL) including a pole piece 204a, a control electrode 204b, a deflector 204c, and an excitation coil 204d. The electron beam tool 104 may additionally include an energy dispersive X-ray spectrometer (EDS) detector (not shown) for characterizing materials on the wafer 203.

[0076] A primary electron beam 220 is emitted from the cathode 218 by applying an accelerating voltage between the anode 216 and the cathode 218. The primary electron beam 220 passes through the gun aperture 214 and the beam limiting aperture 212, both of which can determine the size of the electron beam entering the condenser lens 210, which is located below the beam limiting aperture 212. The condenser lens 210 focuses the primary electron beam 220 before the electron beam enters the objective lens aperture 208 to set the size of the electron beam before entering the objective lens assembly 204. The deflector 204c deflects the primary electron beam 220 to facilitate beam scanning on the wafer. For example, during the scanning process, the deflector 204c can be controlled to sequentially deflect the primary electron beam 220 to different locations on the top surface of the wafer 203 at different time points to provide data for image reconstruction of different parts of the wafer 203. In addition, the deflector 204c can also be controlled to deflect the primary electron beam 220 to different sides of the wafer 203 at a specific location at different time points to provide data for stereoscopic image reconstruction of the wafer structure at that location. In addition, in some embodiments, the anode 216 and the cathode 218 can generate multiple primary electron beams 220, and the electron beam tool 104 can include multiple deflectors 204c to project multiple primary electron beams 220 to different parts / sides of the wafer at the same time to provide data for image reconstruction of different parts of the wafer 203.

[0077] The excitation coil 204d and the pole piece 204a generate a magnetic field that starts at one end of the pole piece 204a and ends at the other end of the pole piece 204a. A portion of the wafer 203 scanned by the primary electron beam 220 can be immersed in the magnetic field and can be charged, which in turn generates an electric field. Before colliding with the wafer 203, the electric field reduces the energy of the primary electron beam 220 that strikes the wafer 203 near the surface. The control electrode 204b, which is electrically isolated from the pole piece 204a, controls the electric field on the wafer 203 to prevent micro-arcing of the wafer 203 and ensure proper beam focusing.

[0078] The secondary electron beam 222 can be emitted from a portion of the wafer 203 upon receiving the primary electron beam 220. The secondary electron beam 222 can form a beam spot on the sensor surfaces 206a and 206b of the electron detector 206. The electron detector 206 can generate a signal (e.g., voltage, current, etc.) representing the intensity of the beam spot and provide the signal to the image processing system 250. The intensity of the secondary electron beam 222 and the resulting beam spot can be changed according to the external or internal structure of the wafer 203. In addition, as described above, the primary electron beam 220 can be projected to different locations on the top surface of the wafer or specific locations on different sides of the wafer to generate secondary electron beams 222 (and the resulting beam spots) of different intensities. Therefore, by mapping the intensity of the beam spot to the position of the wafer 203, the processing system can reconstruct an image reflecting the internal or surface structure of the wafer 203.

[0079] The imaging system 200 can be used to inspect a wafer 203 on a motorized sample stage 201 and includes an electron beam tool 104, as described above. The imaging system 200 can also include an image processing system 250, which includes an image acquisition device 260, a storage device 270, and a controller 109. The image acquisition device 260 can include one or more processors. For example, the image acquisition device 260 can include a computer, a server, a mainframe, a terminal, a personal computer, any kind of mobile computing device, etc., or a combination thereof. The image acquisition device 260 can be connected to the detector 206 of the electron beam tool 104 through a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, radio, or a combination thereof. The image acquisition device 260 can receive a signal from the detector 206 and can construct an image. The image acquisition device 260 can therefore acquire an image of the wafer 203. The image acquisition device 260 can also perform various post-processing functions, such as generating a contour, superimposing an indicator on the acquired image, etc. The image acquisition device 260 can perform brightness and contrast adjustments, etc. on the acquired image. The storage device 270 may be a storage medium such as a hard disk, cloud storage, random access memory (RAM), other types of computer-readable memory, etc. The storage device 270 may be coupled to the image acquirer 260 and may be used to save the scanned raw image data as raw images and post-processed images. The image acquirer 260 and the storage device 270 may be connected to the controller 109. In some embodiments, the image acquirer 260, the storage device 270, and the controller 109 may be integrated together as a control unit.

[0080] In some embodiments, the image acquirer 260 can acquire one or more images of the sample based on the imaging signal received from the detector 206. The imaging signal can correspond to a scanning operation for performing charged particle imaging. The acquired image can be a single image including multiple imaging regions. The single image can be stored in the storage device 270. The single image can be an original image that can be divided into multiple regions. Each region can include an imaging region containing a feature of the wafer 203.

[0081] Wafer grounding can be achieved by conducting charge from wafer 203 to wafer holder 202 to cause wafer 203 to become electrically neutral. Wafer grounding can be performed using a penetration method or an electrical breakdown method. In these methods, a wafer can be placed on a wafer stage, and the back side of the wafer is supported by the wafer stage. A back film (e.g., a protective coating) can be present on the surface of the back side of the wafer substrate. The back film can be non-conductive. Two or more ground pins made of a conductive material (e.g., metal) can be pressed against the back film without completely piercing it.

[0082] In the electrical breakdown method, an electrical signal can enter the wafer from a first ground pin through the back film via a first dielectric breakdown, and leave the wafer through the back film to a second ground pin via a second dielectric breakdown. The dielectric breakdown may result in the formation of a stable electrical path (e.g., a direct current (DC) path) through the back film, which may be referred to as a "bias path". The bias path may have an effective resistance. For example, the resistance of the back film may contribute to the effective resistance.

[0083] During electrical breakdown, a sensor can be used to measure the effective resistance between the first ground pin and the second ground pin. A controller coupled to the wafer grounding system can determine whether a threshold condition is met (e.g., the effective resistance is less than or equal to a predetermined resistance). If the threshold condition is met, the controller can cause the electrical signal generator to stop generating a ground signal. Otherwise, the controller can cause the electrical signal generator to continue generating a ground signal for a predetermined duration (e.g., a few milliseconds to tens of milliseconds). Each of these comparisons of the effective resistance to the predetermined resistance can be referred to as a "cycle" of wafer grounding. Typically, several cycles may be required before the threshold condition is met.

[0084] When the effective resistance of the bias path is less than or equal to the predetermined resistance, the wafer grounding can be completed. The controller can then electrically disconnect the ground pins from the electrical signal generator and electrically connect them to the wafer bias power supply. The wafer bias power supply can provide a low voltage electrical signal to the wafer substrate through the bias path for wafer biasing.

[0085] The challenge of the electrical breakdown method is that, before completing the wafer grounding, the controller may cause the electrical signal generator to continue to generate the same ground signal, such as the same amplitude, the same frequency or within the same predetermined period. This electrical signal may not be optimized for the wafer grounding. For example, in order to cause dielectric breakdown, the amplitude may be higher than necessary, the frequency may be higher than necessary, or the duration may be longer than necessary. Unoptimized electrical signals may excite particles of the back film and release them from the surface of the back side. Particles may enter the vacuum chamber of the enclosed wafer and wafer stage, which may cause pollution and increase maintenance costs. In addition, unoptimized electrical signals may reduce the life of the ground pin, which may also increase maintenance costs.

[0086] Another challenge of the electrical breakdown method is that the ground signal may be unadjustable for different types of wafers. The ground signal may have a predetermined signal curve (e.g., a square wave). The predetermined signal curve may be applied with a predetermined amplitude, a predetermined frequency, or a predetermined duration. This characteristic of the predetermined signal curve may be unadjustable. However, different manufacturers may manufacture different types of wafers, and different types of wafers may have different types of back films. For example, different types of back films may have different materials, such as oxides, silicon nitride, or other materials. For another example, different types of back films may have different thicknesses, hardnesses, or electrical conductivity (e.g., insulation or high resistance). For different types of wafers, the characteristics of the optimized electrical signal may be different. For an unadjustable signal curve, it is unlikely that the signal curve of the electrical signal used for grounding is set to be optimized for different types of wafers, thereby causing the above-mentioned problems.

[0087] Another challenge of the electrical breakdown method is that the signal curve of the ground signal is usually a pulse, such as a square wave. Tests have shown that a pulse signal may cause a greater number of particles of the back film to be released into the vacuum chamber.

[0088] Another challenge of the electrical breakdown method is that the contact position ("grounding position") of the ground pin at the back film is usually fixed. When the ground pin is pressed against the wafer, the wafer may not be grounded due to poor contact or other reasons. However, it may be difficult to adjust the grounding position because the wafer stage may lack a mechanism for adjusting the position of the wafer. In order to increase the possibility of successful grounding of the wafer, the existing system may use multiple (e.g., more than two) grounding pins to press the back film. If any two of the multiple grounding pins form an electrical path, the wafer grounding can be completed using these two grounding pins. However, if no grounding pin can form an electrical path, the wafer may not be grounded and may be discarded as waste. This may reduce the productivity and efficiency of manufacturing. In addition, the use of multiple grounding pins may increase the complexity of the system.

[0089] Figure 3is a diagram of an example system 300 for grounding a wafer consistent with some embodiments of the present disclosure. The system 300 can be used to ground a wafer, which has various advantages, such as increasing the life of a ground pin or reducing sputtered particles. Figure 3 In the embodiment, the system 300 includes at least a subsystem 302 for holding a wafer, an electrical signal generator 314 , a sensor 316 , a controller 322 , and a control parameter optimizer 324 .

[0090] Subsystem 302 includes electrostatic holder 306 and wafer 304. In some embodiments, wafer 304 may be Figure 2 The wafer 203 in the embodiment of the present invention and the electrostatic holder 306 may be Figure 2 The wafer holder 202 in the embodiment of the present invention. The wafer 304 includes a back film 308. The back film 308 can be non-conductive. The electrostatic holder 306 can include at least one electrode 310. When powered, the electrode 310 can attract and fix the wafer 304 to the electrostatic holder 306 via an electrostatic field. The subsystem 302 also includes at least one ground pin (or "probe") 312. The ground pin 312 can be electrically connected between the electrical signal generator 314 and the wafer 304. In some embodiments, the ground pin 312 can be pressed against the back film 308 without completely penetrating the back film 308. The ground pin 312 can be electrically connected to the electrical signal generator 314 and the sensor 316.

[0091] The electrical signal generator 314 can generate a ground signal for grounding the wafer 304. In some embodiments, the electrical signal generator 314 is a driver. The ground signal can have a high voltage to cause dielectric breakdown between the ground pin 312 and the wafer 304 through the back film 308. The sensor 316 can be used to detect or measure an electrical characteristic 320 associated with electrical breakdown. For example, the electrical characteristic 320 can include at least one of impedance, resistance, capacitive reactance, admittance, conductance or accommodation. In some embodiments, the electrical characteristic 320 can be associated with an electrical path including the ground pin and the wafer. For example, the subsystem 302 can be a single-pin system that includes a single ground pin 312. In the single-pin system, the sensor 316 can be electrically connected to the wafer 304, and the electrical characteristic 320 of the electrical breakdown between the ground pin 312 and the wafer 304 through the back film 308 can be measured.

[0092] For another example, the subsystem 302 may be a multi-pin system that includes a plurality of ground pins 312 . Figure 43 is an illustration of an example multi-pin wafer grounding system 400 consistent with some embodiments of the present disclosure. System 400 includes wafer 304, electrostatic holder 306, backside film 308, electrode 310, and a plurality of ground pins 312. In some embodiments, subsystem 302 may be replaced by system 400. In a multi-pin system, for example, electrical signal generator 314 may be electrically connected to a first ground pin, and sensor 316 may be electrically connected to a second ground pin. A ground signal may enter wafer 304 through the first ground pin and exit through the second ground pin. Figure 3 The sensor 316 can measure the electrical characteristics 320 of a first electrical breakdown and a second electrical breakdown, the first electrical breakdown passing through the back film 308 between the first ground pin and the wafer 304, and the second electrical breakdown passing through the back film 308 between the wafer 304 and the first ground pin. In some embodiments, the wafer 304 and the conductor on the wafer stage ( Figure 3 A capacitive coupling may be formed between the electrostatic holder 306 or the electrode 310 in the wafer 304. For example, the wafer and the conductor on the wafer stage may form a capacitor. The capacitive coupling may be used as an electrical path ("return path") for a ground signal. The capacitively coupled electrical connection may be checked using an alternating current (AC) signal entering through at least one of the ground pins 312. When the AC signal flows through and forms a current loop, the controller 322 may determine that the capacitive coupling has been established. In some embodiments, the quality of the electrical connection between the ground pin 312 and the wafer 304 may be verified by measuring the AC signal.

[0093] Reference again Figure 3 , the controller 322 can be electrically connected to the electrical signal generator 314 and can control the electrical signal generator 314 to generate a ground signal and an AC signal. In some embodiments, the controller 322 can be implemented as Figure 1 to Figure 2322 is a part of the controller 109 in the back film 308. In some embodiments, the controller 322 can be implemented as a controller independent of the controller 109, such as a software module or a hardware module. The characteristics of the ground signal and the AC signal can be controlled by the control parameters output by the controller 322. The characteristics of the ground signal and the AC signal can include at least one of the following: voltage, current, curve of voltage or current, frequency of the curve, period of the curve, phase of the curve, amplitude of the curve, or duration of the voltage or current. In some embodiments, the curve of the ground signal can be a sinusoidal shape. Compared with a square wave signal, a sinusoidal signal (e.g., a sinusoidal high voltage signal) can significantly reduce the number of sputtered particles excited and released from the surface of the back film 308. Controlling the characteristics of the ground signal and the AC signal can optimize the performance of the grounding process, such as by generating a ground signal with a minimum voltage or duration required to cause dielectric breakdown. Depending on different types of wafers 304, the control parameters output by the controller 322 may be different. Therefore, the ground signal and the AC signal can be adjustable, and the life of the ground pin 312 can be improved.

[0094] The control parameter optimizer 324 may optimize the control parameters of the controller 322. In some embodiments, the controller 322 may use at least the electrical characteristic 320 to generate the real-time control parameter 326. For example, the controller 322 may receive the value of the electrical characteristic 320 and the target value 328 of the electrical characteristic 320 and generate the real-time control parameter 326. In some embodiments, the target value 328 may be stored in a database (e.g., in a memory accessible to the controller 322), and the controller 322 may retrieve the target value 328 from the database as needed. The target value 328 may be a value of the same type of electrical characteristic 320 and may be predetermined to indicate a grounding state. In some embodiments, the value of the electrical characteristic 320 may be compared with the target value 328 before the controller 322 determines the real-time control parameter 326. For example, when the electrical characteristic 320 is an effective resistance, the target value 328 may be a target effective resistance value. If the value of the electrical characteristic 320 is less than or equal to the target effective resistance value, the controller 322 may determine that dielectric breakdown has occurred and the wafer 304 is grounded and may control the electrical signal generator 314 to stop generating a grounding signal. If the value of the electrical characteristic 320 is higher than or equal to the target effective resistance value, the controller 322 may determine that dielectric breakdown has not occurred and generate a real-time control parameter 326 to be optimized by the control parameter optimizer 324. The control parameter optimizer 324 may optimize the real-time control parameter 326 and output the optimized control parameter 330 to the controller 322. The controller 322 may use the optimized control parameter 330 to control the electrical signal generator 314 to generate a ground signal having a desired characteristic.

[0095] The control parameter optimizer 324 can optimize the real-time control parameter 326 based on various inputs. The inputs can include at least the initial parameters 326, the value of the electrical characteristic 320, the target value 328, and the wafer type 332. In some embodiments, the wafer type 332 can be stored in a database, such as the same database that stores the target value 328. In some embodiments, the control parameter optimizer 324 can include other input data to optimize the real-time control parameter 326. The wafer type 332 can indicate the type of wafer 304. For example, the wafer type 332 can indicate the material type, thickness, hardness or conductivity of the back film 308, the electrical characteristics of the wafer 304, etc. In some embodiments, the control parameter optimizer 324 can use machine learning techniques to use the value of the electrical characteristic 320, the real-time control parameter 326, the target value 328, and the wafer type 332 as inputs to determine the optimization parameter 330. For example, the machine learning technique can include a neural network. The machine learning technique can be an unsupervised learning model or a supervised learning model.

[0096] In some embodiments, the machine learning technique may be a supervised learning model and may be trained to optimize real-time control parameters under conditions of various wafer types 332, measured values ​​of electrical characteristics 320, and target values ​​328 of electrical characteristics 320. In some embodiments, in order to train the supervised learning model, information of known parameters (e.g., tuning parameters without using machine learning techniques) corresponding to various wafer types 332, measured values ​​of electrical characteristics 320, and target values ​​328 of electrical characteristics 320 may be used as labels (“true labels”) indicating true or accurate classifications. For example, such information may be stored in a database as a log file. During training, initial control parameters may be generated and fed to the supervised learning model. The output of the supervised learning model may be compared with the true labels. If they are different, the parameters of the supervised learning model may be updated. If the accuracy of such comparison exceeds a predetermined level (e.g., 95%), it may be determined that the supervised learning model has been trained.

[0097] The trained supervised learning model can be used to determine optimized control parameters 330 based on various wafer types 332, measured values ​​of electrical characteristics 320, and target values ​​328 of electrical characteristics 320. For example, in a first cycle of wafer grounding, the controller 322 can receive optimized control parameters 330 to control the electrical signal generator 314 to generate a sinusoidal grounding signal with expected characteristics, such as an expected frequency of voltage or an expected amplitude of voltage. The sensor 316 can measure the first value of the electrical characteristic 320. The controller 322 can receive the first value of the electrical characteristic 320 and retrieve the target value 328 from the database. Based on the comparison that the first value of the electrical characteristic 320 is higher than the target value 328, the controller 322 can generate a real-time control parameter 326. The control parameter optimizer 324 can receive the real-time control parameter 326 and the first value of the electrical characteristic 320, and also retrieve the target value 328 and the wafer type 332 from the database. By inputting these into the trained supervised learning model, the control parameter optimizer 324 can output the optimized control parameter 330. The controller 322 may receive the optimized control parameter 330 to control the electrical signal generator 314 to change the characteristics of the ground signal during the second period of wafer grounding.

[0098] In some embodiments, the optimized control parameters 330 in different cycles of wafer grounding may be different. For example, the optimized control parameters 330 may depend on the value of the electrical characteristic 320 measured by the sensor 316. For example, in the second cycle of wafer grounding in the above example, after the controller 322 has controlled the electrical signal generator 314 to change the characteristic of the grounding signal, the sensor 316 may receive a second value of the electrical characteristic 320. The second value may be lower than the first value measured by the sensor 316 in the first cycle of wafer grounding, but still higher than the target value 328, which may indicate that dielectric breakdown has not yet completely occurred, but the controlled voltage of the grounding signal has increased the likelihood of it occurring. In this case, the voltage of the grounding signal may be reduced to ensure that dielectric breakdown occurs while protecting the life of the grounding pin from excessive voltage. The control parameter optimizer 324 may input the second value to determine the optimized control parameters 330 for the third cycle of wafer grounding, which may instruct the controller 322 to control the electrical signal generator 314 to reduce the amplitude of the voltage of the grounding signal compared to the amplitude in the second cycle of wafer grounding.

[0099] The optimized parameters can be different for each cycle of the grounding process. With the optimized grounding voltage curve, the life of the grounding pin is expected to be significantly improved.

[0100] In some embodiments, optimized control parameters 330 may differ according to wafer type 332. For example, after inspecting wafer 304, a new wafer with a new backside film may be placed on electrostatic holder 306. New backside film 308 may have different electrical characteristics than backside film 308. In this case, control parameter optimizer 324 may retrieve the corresponding wafer type from the database and optimize the real-time control parameters corresponding to the new wafer.

[0101] In some embodiments, the control parameter optimizer 324 may be implemented as a software module accessible and executable by the controller 322, such as an application or code stored in a memory accessible by the controller 322. In some embodiments, the control parameter optimizer 324 may be implemented as a hardware module storing executable program code, and the hardware module may communicate with the controller 322 for data input / output. For example, the hardware module may be an FPGA or an ASIC.

[0102] Figure 5 is a flow chart illustrating an example method 500 for wafer grounding consistent with some embodiments of the present disclosure. The method 500 may be performed by a controller that may be coupled to a charged particle beam device (eg, the EBI system 100). For example, the controller may be Figure 2 The controller 109 or Figure 3 The controller 322 in the embodiment of the present invention can be programmed to implement the method 500.

[0103] At step 502, the controller receives a first value of an electrical characteristic associated with a wafer grounded by an electrical signal. In some embodiments, the electrical characteristic may be Figure 3 The electrical characteristic 320 in. For example, the electrical characteristic may include at least one of impedance, resistance, capacitance, admittance, conductance, or accommodation.

[0104] The first value of the electrical characteristic may be the first value of the electrical characteristic 320 during the first period in which the wafer is grounded. The wafer may be Figure 3 The electrical signal can be generated by Figure 3 In some embodiments, the sensor (e.g., Figure 3 The sensor 316 in the embodiment may generate a first value after measuring the electrical characteristic. The controller may receive the first value from the sensor.

[0105] In some embodiments, the sensor may be placed in a portion of the electrical path that conducts the electrical signal away from the wafer (the "feedback portion"). In some embodiments, the electrical characteristic may be associated with the electrical path that includes the wafer and the wafer mount that supports the wafer. In some embodiments, the electrical characteristic may be associated with the electrical path that includes the wafer, the wafer mount that supports the wafer, and the ground pin. For example, the wafer mount may be Figure 3 The electrostatic retainer 306 in the embodiment of the present invention.

[0106] In some embodiments, the electrical characteristic may include one of a resistance between the wafer and the wafer mount or a capacitive reactance between the wafer and the wafer mount. For example, in a single-pin system, a ground signal may enter the wafer 304 through the ground pin 312 and leave the wafer 304 through capacitive coupling between the wafer 304 and the electrostatic holder 306. In this example, the electrical path may include, for example, electrical characteristics between the ground pin 312, the back film 308, and the wafer 304. The electrical characteristics may include the capacitive reactance of the capacitive coupling between the wafer 304 and the electrostatic holder 306. For another example, in a multi-pin system, a ground signal may enter the wafer 304 through a first ground pin and leave through a second ground pin. The electrical path may include, for example, electrical characteristics between the first ground pin 312, the back film 308, and the wafer 304 and the second ground pin. In this example, the electrical characteristic may include a resistance between the wafer and the wafer mount, such as an effective resistance of a first electrical breakdown and a second electrical breakdown, the first electrical breakdown being between the first ground pin and the wafer 304 through the back film 308, and the second electrical breakdown being between the wafer 304 and the second ground pin through the back film 308.

[0107] It should be noted that the present disclosure does not limit the types of electrical characteristics, and the electrical characteristics of a DC circuit or an AC circuit may be adopted in the present disclosure without exceeding the scope of the present disclosure.

[0108] Reference again Figure 5 In step 504, the controller determines a first control parameter using at least the first value. For example, the first control parameter may be an optimized control parameter 330 in a first cycle of wafer grounding, such as Figure 3 In some embodiments, the controller may determine the first control parameter based on a comparison between the first value and the target value of the electrical characteristic. For example, the target value of the electrical characteristic may be Figure 3 In some embodiments, in order to determine the first control parameter based on the comparison, the controller may determine whether the difference between the first value and the target value satisfies a threshold condition. The controller may also determine the first control parameter based on determining that the difference satisfies a threshold condition. In some embodiments, for example, when the electrical characteristic is resistance, the threshold condition may be that the first value is less than or equal to the target value. It should be noted that, depending on the type of electrical characteristic, the threshold condition between the first value and the target value may also change accordingly, without being limited to the examples listed herein.

[0109] In some embodiments, to determine the first control parameter, the controller may use at least the first value to determine an initial parameter. For example, the initial parameter may be Figure 3The controller may then determine the first control parameter based on at least the initial parameter, the first value, the target value, and the type of wafer. For example, the type of wafer may be Figure 3 In some embodiments, the controller may use a control parameter optimizer (such as Figure 3 The control parameter optimizer 324 in the control parameter optimizer 324 is used to determine the first control parameter.

[0110] In some embodiments, the control parameter optimizer may use machine learning techniques to determine the first control parameter. For example, the input of the machine learning technique may include at least the initial parameter, the first value, the target value, and the type of wafer. Figure 3 As shown, control parameter optimizer 324 may take as input real-time control parameter 326, first value of electrical characteristic 320, target value 328, and wafer type 332. Output of control parameter optimizer 324 may be optimized control parameter 330.

[0111] Reference again Figure 5 In step 506, the controller uses the first control parameter and the first value to control the characteristic of the electrical signal. Figure 3 As shown, the controller 322 can control the characteristics of the ground signal generated by the electrical signal generator 314 using the optimized control parameter 330 and the first value of the electrical characteristic 320. In some embodiments, the characteristics of the electrical signal include at least one of the following: voltage, current, a curve of the voltage or current, a frequency of the curve, a period of the curve, a phase of the curve, an amplitude of the curve, or a duration of the voltage or current.

[0112] In some embodiments, the curve of the electrical signal may be a sinusoidal shape. Compared to a square wave curve, the electrical signal having a sinusoidal curve may reduce the particles of the back film of the wafer (e.g., back film 308) from being sputtered into the vacuum chamber (e.g., Figure 3 The vacuum chamber enclosed subsystem 302 in the embodiment of the present invention.

[0113] In some embodiments, to control the characteristic of the electrical signal, the controller may use the first control parameter and the first value to change the value of the characteristic of the electrical signal. For example, the controller may change the amplitude, frequency, phase or duration of the voltage of the ground signal.

[0114] In some embodiments, during the grounding process of the same type of wafer, the voltage of the ground signal may decrease as the number of cycles of wafer grounding increases.For example, at step 506, the controller may use the first control parameter and the first value to decrease the voltage of the ground signal.

[0115] In some embodiments, steps 502 to 506 may be repeated until the wafer is grounded. For example, after performing step 506 in the first cycle of wafer grounding, the controller may receive a second value of the electrical characteristic. The controller may also use at least the second value to determine a second control parameter. The controller may also use the second control parameter and the second value to control the characteristic of the electrical signal. The controller may stop executing method 500 until a threshold condition is met, which is described in step 504. In some embodiments, the second control parameter and the first control parameter may have different values. Accordingly, the second control parameter and the first control parameter may have different values.

[0116] In some embodiments, the impedance (e.g., resistance) of the electrical path including the wafer and wafer mount described in step 502 may be greater than or equal to a predetermined threshold. When the impedance is greater than or equal to the predetermined threshold, the controller may determine that the electrical path is disconnected. For example, the predetermined threshold may include resistance values ​​of 100,000 ohms, 200,000 ohms, 300,000 ohms, or 350,000 ohms, etc. The predetermined threshold may be determined based on an estimated amount of current that may be required to meet the grounding requirements of the wafer. When the impedance is greater than or equal to the predetermined threshold, after the controller performs step 506, it may be determined that the electrical path is disconnected (e.g., almost no electrical signal can flow between the wafer and the wafer mount). When the impedance is greater than or equal to the predetermined threshold, the controller may use at least the first value to determine a third control parameter. For example, the first value may be data related to the electrical path after the controller applies an electrical signal while the electrical path is still disconnected. The third control parameter and the first control parameter may have different values. The controller may then use at least the third control parameter and the first value to control the characteristics of the electrical signal. In some embodiments, the controller may repeat such operations until the electrical path is closed.

[0117] In some embodiments, the controller may generate and optimize different types of control parameters in different cycles of the wafer grounding. For example, the aforementioned second control parameter and the first control parameter may be of different types. For example, the first control parameter may be one or more parameters for the controller to control the amplitude of the grounding signal, and the second control parameter may be one or more parameters for the controller to control the duration of the grounding signal.

[0118] Figure 6 6 is a diagram of an example system 600 for wafer grounding position adjustment consistent with some embodiments of the present disclosure. System 600 includes at least a subsystem 602 for holding a wafer, a wafer grounding subsystem 606, and a wafer grounding position adjustment subsystem 608. Subsystem 602 may be similar to Figure 3302 in the embodiment of the present invention, and includes a wafer 304, an electrostatic holder 306, a back film 308, an electrode 310, a ground pin 312, and a wafer stage 604. In some embodiments, the wafer stage 604 may be Figure 2 In some embodiments, subsystem 606 can be used to ground wafer 304 and can be similar to Figure 3 The system 300 in the embodiment of the present invention will not be described in detail below. In some embodiments, the subsystem 608 can adjust the position ("grounding position") of the ground pin 312 contacting the back film 308.

[0119] In some embodiments, when wafer 304 is mounted on top of electrostatic holder 306 and ground pin 312 contacts back film 308, subsystem 606 can test whether wafer 304 can be grounded, such as by using Figures 3 to 5 If the grounding is unsuccessful, subsystem 608 may receive a signal indicating this and generate a signal for adjusting the grounding position. The signal may drive one or more actuators of subsystem 602 to change the grounding position. When the grounding position is adjusted, subsystem 606 may continue to test whether wafer 304 can be grounded. The above process may be repeated until wafer 304 is successfully grounded. It should be noted that although subsystem 602 Figure 6 , but it can also be a single-pin system (e.g., similar to Figure 3 subsystem 302 in ), and the wafer ground position adjustment may still be effective.

[0120] Figure 7 7 is an illustration of an example system 700 for wafer grounding position adjustment consistent with some embodiments of the present disclosure. In some embodiments, system 700 may be an embodiment of subsystem 608. System 700 includes at least a subsystem 702 for holding a wafer, a controller 710, a sensor 712, and a target adjuster 714. Sensor 712 may measure a relative position (e.g., a rotational or translational position) between wafer 304 and grounding pin 312. In some embodiments, target adjustment 714 may include a parameter value to be used by controller 710 to control an actuator of subsystem 702 to adjust the grounding position to a target position. For example, the target position may include a rotational position or a translational position. In some embodiments, target adjustment 714 may be stored in a database (e.g., in Figure 1 Subsystem 702 may be similar to Figure 3 Subsystem 302 or Figure 6602 in the embodiment of the present invention and includes a wafer 304, an electrostatic holder 306, a backside film 308, an electrode 310, a ground pin 312, a top portion 704 of a wafer stage, a bottom portion 706 of a wafer stage, and an actuator including an elevator 708. The subsystem 702 in Figure 7 is shown as a multi-pin system. However, it can also be a single-pin system, such as Figure 3 The actuator may include an electric actuator, a magnetic actuator, an electromagnetic actuator, a hydraulic actuator, a mechanical actuator, or any suitable type of actuator. In some embodiments, the wafer stage (including the top portion 704 and the bottom portion 706) may be Figure 2 The motorized sample stage 201 in FIG.

[0121] The controller 710 can be electrically connected to the sensors 712 and actuators, including the lifter 708 and the actuator (not shown) that are mechanically connected to the top portion 704. The controller 710 can control various parts of the actuator movement subsystem 702, such as the lifter 708, the top portion 704, the ground pins 312, or other mechanical components (e.g., a robotic arm) for moving the wafer 304. For example, the dashed arrow between the controller 710 and the top portion 704 can indicate that the controller 710 can control the actuator (not shown) to move the top portion 704 horizontally, vertically, or both. The dashed arrow between the controller 710 and the lifter 708 can indicate that the controller 710 can control the lifter 708 to move the wafer 304 vertically. In some embodiments, the controller 710 can also be connected to a database to retrieve parameters for controlling the actuator or to store data received from the sensor 712. For example, the controller 710 can access a database that stores the target adjustment 714. In some embodiments, the controller 710 can be implemented as Figure 1 to Figure 2 In some embodiments, the controller 710 may be implemented as a controller independent of the controller 109, such as a software module or a hardware module.

[0122] In some embodiments, the bottom portion 706 can be stationary, while the top portion 704 can be movable. For example, the top portion 704 can be movable (e.g., vertically, horizontally, or both) or rotatable in the horizontal direction or both. In some embodiments, the electrostatic holder 306 can be fixed to the top portion 704 and can also be movable therewith. In some embodiments, the top portion 704 can support the wafer 304 via the electrostatic holder 306 and fix the ground pin 312. For example, one end of the ground pin can be fixed to the top portion 704 and can also be movable with the top portion 704. When the wafer 304 rests on the top portion 704 (e.g., on the electrostatic holder 306), the ground pin 312 can contact the bottom surface (e.g., back film 308) of the wafer 304.

[0123] In some embodiments, the actuator can move the top portion. For example, the actuator may include a rotating mechanism (not shown) to rotate the top portion 704 in a horizontal direction, such as rotating a certain azimuth angle. In some embodiments, the actuator may include a lifter 708. The first end of the lifter may be fixed to the bottom portion 706, and the second end of the lifter may be vertically movable. For example, the first end of the lifter may be horizontally fixed to the bottom portion 706 (e.g., by penetrating a hole in the bottom portion 706) and may be vertically movable. The second end of the lifter may be raised or lowered by a moving mechanism such as an electromagnetic actuator or a hydraulic actuator. The second end of the lifter may penetrate the top portion 704, the electrostatic holder 306, and the electrode 310, such as by penetrating a hole or groove therein. The second end of the lifter may move beyond the top surface of the electrostatic holder 306 and contact the bottom surface of the wafer 304. In the subsystem 702, by raising the lifter to a specific height (e.g., a few millimeters), the wafer 304 may be raised to leave the top surface of the electrostatic holder 306 and be separated from the ground pin 312.

[0124] In some embodiments, the lifter 708 may be fixed vertically and horizontally, and the top portion 704 may be vertically movable. When the top portion 704 is lowered, the ground pins 312 and the electrostatic holder 306 may also be lowered. However, the lifter 708 may support the wafer 304, and the wafer 304 may be vertically stationary. By lowering the top portion 704, the electrostatic holder 306 may be lowered to leave the bottom surface of the wafer 304, and the ground pins 312 may be separated from the bottom surface.

[0125] In some embodiments, to adjust the grounding position, the following process may be performed by the system 700 . Figure 6The subsystem 606 in can determine that the wafer 304 is not grounded and send a signal indicating this to the controller 710. The controller 710 can control the sensor 712 to measure the current rotation angle (e.g., azimuth) of the ground pin 312 relative to the wafer 304. The controller 710 can also retrieve the target adjustment 714 (e.g., the value of the target rotation angle). The controller 710 can compare the target angle with the current rotation angle, such as by determining the angular difference between them. The controller 710 can then send the angular difference to the actuator for adjusting the ground position. In some embodiments, the controller 710 can store computer-readable instructions in an accessible memory such as a software module, and execute such instructions to perform the above operations.

[0126] In some embodiments, adjusting the grounding position may include changing the relative rotation angle (e.g., azimuth angle) between the grounding pin 312 and the wafer 304. Changing the relative rotation angle may include at least one of: changing the rotation angle of the wafer 304 while keeping the grounding pin 312 rotationally stationary; changing the rotation angle of the grounding pin 312 while keeping the wafer 304 rotationally stationary; or changing the rotation angle of the grounding pin 312 and the wafer 304.

[0127] For example, in some embodiments, when the lifter 708 is horizontally fixed to the bottom portion 706 and vertically movable, the controller 710 can control the lifter 708 to lift the wafer 304, such as by keeping the top portion 704 vertically stationary. Because the ground pins 312 and the electrostatic holder 306 are fixed on the top portion 704, when the wafer 304 is lifted by the lifter 708, the back film 308 can be separated from the top surface of the ground pins 312 and the electrostatic holder 306. The controller 710 can also control the top portion 704 to rotate horizontally (e.g., in the azimuth direction) to an angle equal to the angle difference. The rotation direction can be clockwise or counterclockwise. In some embodiments, the rotation can be performed relative to the center of the top portion 704. Because the ground pins 312 are fixed on the top portion 704, they can also be rotated for the angle difference with the top portion 704. The controller 710 can control the bottom portion 706 to become rotationally stationary, and therefore the wafer 304 is also rotationally stationary. After performing such a rotation, the controller 710 may control the elevator 708 to lower the wafer 304 until the wafer 304 is positioned above the electrostatic holder 306 , at which point the ground pins 312 are reattached to the backside film 308 at a different location.

[0128] For another example, in some embodiments, when the lifter 708 is fixed to the bottom part 706 horizontally and vertically, the controller 710 can control the actuator (not shown) to lower the top part 704 to separate the ground pin 312 and the back film 308. The lifter 708 fixed to the bottom part 706 horizontally and vertically can also be called a "support". Because the ground pin 312 and the electrostatic holder 306 are fixed on the top part 704, when the top part 704 is lowered by the actuator, the back film 308 can be separated from the top surface of the ground pin 312 and the electrostatic holder 306. The controller 710 can also control the top part 704 to rotate horizontally (for example, in the azimuth direction) to an angle equal to the angle difference. The direction of rotation can be clockwise or counterclockwise. In some embodiments, the rotation can be performed relative to the center of the top part 704. Because the ground pin 312 is fixed on the top part 704, they can also be rotated for the angle difference with the top part 704. The controller 710 can control the bottom portion 706 to become rotationally stationary, and thus the wafer 304 is also rotationally stationary. After performing such a rotation, the controller 710 can control the actuator to lift the top portion 704 until the wafer 304 is located above the electrostatic holder 306, at which point the ground pins 312 are reattached to the back film 308 at a different location.

[0129] For another example, in some embodiments, the ground pin 312 may not be fixed on the top portion 704 but fixed on an independent actuator (not shown). In this example, the controller 710 can control the actuator to lower the ground pin 312 while keeping the top portion 704 and the wafer 304 vertically stationary, such as by keeping the lifter 708 vertically stationary. The ground pin 312 can then be separated from the back film 308, and the wafer 304 remains located on the electrostatic holder 306. The controller 710 can also control the independent actuator to horizontally (e.g., in the azimuth direction) rotate the ground pin 312 to an angle equal to the angle difference. The direction of rotation can be clockwise or counterclockwise. In some embodiments, the rotation can be performed relative to the center of the top portion 704. After performing such a rotation, the controller 710 can control the actuator to lift the ground pin 312 until they are reattached to the back film 308 at different positions.

[0130] In some embodiments, the controller 710 can adjust the translation position between the ground pin 312 and the wafer 304. For example, the controller 710 can control the separation of the ground pin 312 and the back film 308, and control the translation actuator (not shown) to adjust the horizontal position by a predetermined distance along a predetermined direction of at least one of the top portion 704, the ground pin 312, or the wafer 304, and then reattach the ground pin 312 and the back film 308 at a different position. In some embodiments, the controller 710 can adjust both the translation position and the rotation position between the ground pin 312 and the back film 308.

[0131] When the controller 710 completes the adjustment of the grounding position, the subsystem 606 can test again whether the wafer 304 can be grounded. If the wafer 304 can be successfully grounded, the adjustment process can be ended. Otherwise, the system 700 can be run again to perform another round of adjustments. The process can be repeated until the wafer 304 is successfully grounded. In some embodiments, the angle difference can be predetermined to a small value (e.g., one thousandth, one hundredth, or one tenth of a degree), and the system 700 can perform substantially any number of adjustments before successfully grounding the wafer 304, which can ensure that the wafer 304 is not wasted.

[0132] Figure 8 is an illustration of an example ground position before and after adjustment. Figure 8 yes Figure 7 A top view of a wafer 304 is provided in a subsystem 702 of FIG. Figure 8 In the embodiment, the subsystem 702 may include two ground pins 312. Figure 7 In accordance with the described example, the wafer 304 may be rotationally stationary. To adjust the ground rotation, the ground pins 312 may be separated from the back film 308, such as by lifting the wafer 304 or lowering the top portion 704. Figure 8 As shown, when the wafer 304 is stationary and the top portion 704 is rotated, the top portion 704 can be rotated in a clockwise direction 802 by an angle difference 808. Before such adjustment, the ground pin 312 can contact the back film 308 at a first grounding position 804, as shown by a black dot. After the adjustment, the ground pin 312 can contact the back film 308 at a grounding position 806, as shown by a circle.

[0133] By performing such an adjustment, the grounding position can be easily and effectively performed without discarding the wafer 304, and the possibility of grounding the wafer 304 can be conveniently increased, thereby improving production efficiency and manufacturing efficiency. In addition, by using such a grounding position adjustment design, the number of grounding pins can be reduced, and the complexity of the wafer grounding system can be reduced. In addition, by setting arbitrary values ​​of the angle difference and the predetermined distance, the grounding position can be adjusted with arbitrary accuracy and at any number of times as needed.

[0134] exist Figures 7 and 8 In some embodiments, when the ground pins 312 are reattached to the back film 308, they may be pressed against the back film 308 at a different pressure than before adjustment. For example, after adjustment, the ground pins 312 may be pressed against the back film 308 at a higher pressure. At a higher pressure, even if the angle difference is 0°, it may be possible in some cases for the wafer grounding subsystem (e.g., the wafer grounding subsystem 606) to ground the wafer 304 because the ground pins 312 may penetrate deeper into the back film 308. Changing the pressure may provide another independent aspect to adjust the grounding position. Position adjustment and pressure adjustment may be used by the system 702 alone or in combination.

[0135] Fig. 9 is a diagram of an example system 900 for wafer grounding position adjustment consistent with some embodiments of the present disclosure. System 900 includes at least a subsystem 602 for holding a wafer, a wafer grounding subsystem 606, and a wafer adjustment platform 902. Subsystems 602 and 606 have been described in Figure 6 Wafer conditioning platform 902 may be different from subsystems 608 and 702 and will be described in detail below.

[0136] In some embodiments, the wafer adjustment platform 902 may be a platform for rotating or translating the wafer 304. For example, the wafer adjustment platform 902 may include a controller, a sensor, and at least one actuator for rotating or translating the wafer 304. In some embodiments, the wafer adjustment platform 902 may be implemented as a component independent of the subsystem 602. For example, the wafer adjustment platform 902 may be located at a different position in the same vacuum chamber as the subsystem 602. In some embodiments, in order to adjust the grounding position, an unloading actuator (e.g., a robot arm) may unload the wafer 304 from the electrostatic holder 306 (e.g., by suction and lifting) onto the wafer adjustment platform 902. The wafer adjustment platform 902 may rotate the wafer 304 by a certain angle (e.g., an angle difference) or translate the wafer 304 by a certain distance. After rotating or translating the wafer 304, a loading actuator (e.g., a robot arm) can load the wafer 304 (e.g., by suction and lifting) from the wafer conditioning platform 902 back to the electrostatic holder 306, through which the ground pins 312 can be reattached to the backside film 308 at a different position. One benefit of using the design of system 900 can be that it can maximize the compatibility of the ground position adjustment system with existing designs of wafer stages by adding a component (wafer conditioning platform 902) without replacing the existing wafer stage (e.g., wafer stage 604) or substantially modifying the existing wafer stage (e.g., by adding elevator 708).

[0137] Figure 10 to Figure 11 1 shows an example flow chart of methods 1000 to 1100 consistent with some embodiments of the present disclosure. Methods 1000 to 1100 may be performed by a controller that may be coupled to a charged particle beam device (e.g., EBI system 100). For example, the controller may be Figure 2 The controller 109 or Figure 7 The controller 710 in the embodiment of the present invention can be programmed to implement methods 1000 to 1100.

[0138] Fig.10 is a flow chart illustrating an example method of adjusting a grounding position of a wafer consistent with some embodiments of the present disclosure.

[0139] At step 1002, the controller terminates the electrical connection between the wafer and the ground pins contacting the wafer. For example, the wafer may be Figures 6 to 9 The ground pin can be Figures 6 to 9 In some embodiments, the controller can control the actuator to use a lifter (e.g., Figure 7 The lifter 708 in the embodiment of the present invention can be used to lift the wafer from the wafer mounting base (e.g., Figures 6 to 9 The lifter can be in contact with the bottom surface of the wafer (e.g., Figures 6 to 9 The back side film 308 of the wafer mount contacts and is fixed to the bottom portion of the wafer mount (eg, Figure 7 In some embodiments, the ground pins may be secured to the top portion of the wafer mount (e.g., Figure 7 , and when the wafer rests on the top portion, the ground pins may contact the bottom surface of the wafer.

[0140] In some embodiments, the controller may control the actuator to lower the ground pin from the bottom surface of the wafer resting on the wafer mount to separate the wafer and the ground pin. The ground pin may be vertically movable in the wafer mount, such as Figure 7 The controller can be controlled to keep the wafer vertically stationary. For example, the ground pin can be connected to a separate actuator that can vertically lower and raise the ground pin without lowering or raising the wafer mount, such as Figure 7 As shown and described in .

[0141] In some embodiments, the controller can control the actuator to lower the top portion of the wafer mount to separate the ground pin and the wafer. In some embodiments, the ground pin can be fixed to the top portion of the wafer mount, such as Figure 7The bottom surface of the wafer may contact an immovable support member fixed to the bottom portion of the wafer mount (eg, when the lifter 708 is held vertically fixed), such as Figure 7 When the top portion is not lowered, the ground pins may contact the bottom surface of the wafer, such as Figure 7 As shown and described in .

[0142] In some embodiments, the controller may control the actuator to remove the wafer from the wafer mount to the platform, such as Fig. 9 In some embodiments, the ground pins may be secured to the wafer mount and contact the wafer when the wafer rests on the wafer mount, such as Fig. 9 As shown and described in .

[0143] In step 1004, the controller adjusts the relative position between the wafer and the ground pin. In some embodiments, the relative position may include a relative rotational position, a relative translational position, or a combination thereof. In some embodiments, the controller may control the actuator to adjust the relative azimuth angle between the wafer and the ground pin to a predetermined angle, such as Figures 6 to 9 In some embodiments, the predetermined angle may be the difference between the current relative azimuth and the target relative angle. The current relative azimuth may be between the wafer and the ground pin. The target relative azimuth may be between the wafer and the ground pin. For example, the predetermined angle may be Figure 8 The angle difference is 808.

[0144] In some embodiments, if the wafer is separated from the ground pin by lifting the wafer from the wafer mount using a lifter or by lowering the top portion of the wafer mount, the controller may adjust the relative position by rotating the top portion of the wafer mount relative to the bottom portion of the wafer mount by a predetermined angle. In some embodiments, if the wafer is separated from the ground pin by lowering the ground pin from the bottom surface of the wafer, the controller may adjust the relative position by rotating the ground pin relative to the wafer mount by a predetermined angle when the ground pin is rotationally movable relative to the wafer mount. In some embodiments, if the wafer is separated from the ground pin by removing the wafer from the wafer mount to the platform, the controller may adjust the relative position by causing the platform to rotate the wafer by a predetermined angle.

[0145] In some embodiments, if the wafer is separated from the ground pin by translation, the controller may control the actuator to adjust the relative translation distance between the wafer and the ground pin by a predetermined distance, such as Figure 7 Described in .

[0146] At step 1006, the controller restores the electrical connection between the ground pin and the wafer. In some embodiments, if the wafer is separated from the ground pin by lifting the wafer from the wafer mount using a lifter, the controller may reattach the ground pin and the wafer by lowering the wafer onto the top portion of the wafer mount using the lifter, such as Figure 7 In some embodiments, if the wafer is separated from the ground pins by lowering the ground pins from the bottom surface of the wafer, the controller can reattach the ground pins and the wafer by lifting the ground pins to contact the bottom surface of the wafer, such as Figure 7 In some embodiments, if the wafer is separated from the ground pins by lowering the top portion of the wafer mount, the controller can reattach the ground pins and the wafer by lifting the top portion of the wafer mount, such as Figure 7 As shown and described in .

[0147] In some embodiments, if the wafer is detached from the ground pins by removing the wafer from the wafer mount to the platform, the controller may reattach the ground pins and the wafer by moving the wafer from the platform to the wafer mount, such as Fig. 9 As shown and described in .

[0148] In some embodiments, when the controller signals to reattach the ground pins and the wafer, the ground pins may contact the bottom surface of the wafer at a pressure different from the pressure between the ground pins and the bottom surface before the wafer and the ground pins were separated. In some embodiments, the ground pins may contact the bottom surface of the wafer at a location different from the location where the ground pins contacted the bottom surface before the wafer and the ground pins were separated, such as Figure 8 In some embodiments, the ground pins may contact the bottom surface of the wafer at the same relative position.

[0149] In some embodiments, steps 1002 to 1006 may be repeated until the wafer is successfully grounded.

[0150] Fig.11 1 is a flow chart illustrating another example method 1100 for adjusting a grounding position of a wafer consistent with some embodiments of the present disclosure. The method 1100 includes steps 1102 to 1108. The controller may perform steps 1102 to 1106 in a manner similar to steps 1002 to 1006, respectively.

[0151] At step 1108, another controller (e.g., Figure 3 Controller 322, or Figure 6 and Fig. 9A controller in subsystem 606 in ) can determine whether an electrical path for grounding the wafer is formed (or substantially broken). If the electrical path is not formed (or substantially broken), the controller can return to perform steps 1102 to 1106. If the electrical path is formed (or closed), the controller can stop executing method 1100, where it can be determined that the wafer is successfully grounded. In the present disclosure, if the impedance (e.g., resistance) of the electrical path is greater than or equal to a predetermined threshold, the electrical path is considered "substantially broken". When the impedance is greater than or equal to the predetermined threshold, the controller can determine that the electrical path is broken. In some embodiments, the predetermined threshold may include a resistance value of 100,000 ohms.

[0152] The present disclosure also provides methods and systems for grounding a wafer using a vibrator to adjust a ground pin.In some embodiments, a vibrator can be used in a system to support electrical breakdown, penetration, or both for wafer grounding. Fig.12 1 is a diagram of an example multi-pin wafer grounding system 1200 consistent with some embodiments of the present disclosure. System 1200 is similar to system 400 and includes a wafer 304, an electrostatic holder 306, a back film 308, an electrode 310, a plurality of ground pins 312, and a plurality of vibrators 1202 coupled (e.g., fixed) to the ground pins 312. In some embodiments, each ground pin of the ground pins 312 can be coupled to a single vibrator. In some embodiments, each vibrator of the vibrator 1202 can be coupled to two or more ground pins, or each ground pin can be coupled to two or more vibrators 1202. The vibrator can vibrate the ground pin 312 in any direction (e.g., horizontal, vertical, circular, elliptical, or any direction) along any number of dimensions (e.g., ID, 2D, or 3D). In some embodiments, the vibrator 1202 can be integrated with an actuator (e.g., lifter 708) of the ground pin 312. In some embodiments, the vibrator 1202 can include a piezoelectric actuator.

[0153] In some embodiments, the vibrator 1202 can be powered by a power source. For example, the power source can be the same as or different from the electrical signal generator 314. The controller 322 can control the output of the power source. For example, the controller 322 can control the output to be an electrical signal or pulse of any shape to drive the vibrator 1202 to vibrate.

[0154] In some embodiments, the controller 322 can control the vibration of the vibrator 1202 for wafer grounding. For example, in a system using the penetration method, the ground pin 312 can penetrate the back film 308 and directly contact the wafer 304 at the initial grounding position. If an electrical path is not formed to allow the ground signal to flow between the wafer 304 and the ground pin 312 (for example, one or more ground pins 312 fail to completely penetrate the back film 308, or the ground pin 312 has deposited contamination particles), the controller 322 can control the vibrator 1202 or the wafer 304 to vibrate, such as to make the ground pin 312 better contact the wafer 304 or shake off particles deposited on the ground pin 312. For another example, in a system using the electrical breakdown method, in addition to using an actuator (for example, a lifter 708 or a top portion 708) to adjust the grounding position of the ground pin 312, the vibrator 1202 can also provide another dimension of control to achieve better grounding at the same or adjusted grounding position. It should be noted that by providing the vibrator 1202, the wafer grounding system can be enabled to use both the penetration method and the electrical breakdown method for wafer grounding. In other words, the wafer grounding system with the vibrator 1202 can have two wafer grounding "modes": a mechanical mode (using the penetration method) and an electrical mode (using the electrical breakdown method).

[0155] In some embodiments, when the wafer 304 is stationary, the controller 322 can control the vibrator 1202 to vibrate. Figure 7 312. When the top portion 708 in the embodiment or the top portion 708 is used as a vibrator for the ground pin 312, the controller 322 can control the top portion 708 to vibrate. For another example, when the vibrator 1202 is independent of the top portion 704, the controller 322 can control the vibrator 1202 to vibrate independently of the movement of the top portion 708. In some embodiments, when the wafer 304 is not stationary, the controller 322 can control the wafer 304 to vibrate. For example, the controller 322 can control the electrode 310 to vibrate, thereby causing the wafer 304 to vibrate. It should be noted that the vibrator 1202 is not limited to the examples disclosed herein, and can be implemented in any suitable method to vibrate the ground pin 312 relative to the wafer 304.

[0156] In some embodiments, the controller 322 can control the vibrator 1202 to vibrate periodically. In some embodiments, the controller 322 can control the vibrator 1202 to vibrate "on demand", such as when a failure in the electrical connection between the die 304 and the ground pin 312 is detected.

[0157] Fig.131 is a flow chart illustrating an example method 1300 for wafer grounding consistent with some embodiments of the present disclosure. The method 1300 may be performed by a controller that may be coupled to a charged particle beam device (eg, the EBI system 100). For example, the controller may be Figure 3 Controller 322 or Figure 7 The controller 710 in FIG. 1300 can be programmed to implement the method 1300 .

[0158] At step 1302, the controller causes the ground pin to contact the wafer. The controller may perform step 1302 in a manner similar to step 1002 or 1102. In some embodiments, before performing step 1302, the controller may determine whether an electrical path is formed for grounding the wafer. If an electrical path is not formed, the controller may perform step 1302.

[0159] At step 1304, the controller causes at least one of the ground pin or the wafer to vibrate. In some embodiments, the controller causes a ground pin (e.g., Fig.12 In some embodiments, the controller can vibrate a ground pin 312 in the wafer and a vibrator in a top portion of a wafer mount (e.g., top portion 704) that supports the wafer. In some embodiments, the vibrator can be the top portion. In some embodiments, the controller can vibrate a wafer mount (e.g., electrostatic holder 306 or electrode 310), wherein the wafer holder holds the wafer on the wafer mount. In some embodiments, the controller can vibrate at least one of the ground pin or the wafer in at least one of a direction perpendicular to a surface of the wafer or a direction parallel to the surface. For example, Fig.12 As shown, the controller may cause at least one of the ground pin or the wafer to vibrate in a horizontal direction, a vertical direction, a circular direction, or a 3D direction.

[0160] In step 1306, the controller establishes an electrical connection between the ground pin and the wafer. The controller may perform step 1306 in a manner similar to step 1006 or 1106. In some embodiments, the controller may use a penetration method to restore electrical connection. For example, the controller may press the ground pin against the surface of the wafer through a coating (e.g., back film 308) on the surface to directly contact the wafer. In some embodiments, the controller may use an electrical breakdown method to restore electrical connection. For example, the controller may press the ground pin against the wafer surface through a coating (e.g., back film 308), wherein the ground pin does not completely penetrate the coating.

[0161] In some embodiments, after step 1306, another controller (e.g., Figure 3 Controller 322, or Figure 6 and Fig. 9A controller in the subsystem 606 in the method 1300 may determine whether an electrical path for grounding the wafer is formed (or substantially broken). If the electrical path is not formed (or substantially broken), the controller may return to perform steps 1302 to 1306. If the electrical path is formed, the controller may stop performing the method 1300, where it may be determined that the wafer is successfully grounded.

[0162] The present disclosure also provides methods and systems for grounding a wafer having a thickened backside film. In some embodiments, highly complex structures are fabricated on the wafer. Such complex structures may include a large number of layers. For example, a complex structure may include a three-dimensional circuit, such as a NAND flash memory circuit, that includes one or more NOT-AND ("NAND") gates. Multilayer complex structures may generate higher tension on the surface of the wafer than other structures, which may cause the wafer to warp or bend. A warped wafer may cause problems during inspection, such that portions of the wafer may deviate from the primary electron beam (e.g., Figure 2 These problems may result in a decrease in the quality of the inspection image (e.g., out of focus, blur, distortion, etc.).

[0163] In order to avoid the wafer from warping or bending due to this complex structure, in some embodiments, the wafer can be coated with a thickened back film to enhance its mechanical strength. For example, under normal circumstances, the thickness of the back film can be 0.1-0.3 μm. In order to avoid the wafer from warping or bending, the thickness of the back film can be increased (for example, increased to 1.4-2.2 μm). However, the thickened back film may be too thick so that both the electrical breakdown method and the penetration method cannot be used for wafer grounding. For example, the thickened back film may be so thick that there is no dielectric breakdown in the electrical breakdown method to break through it. In another example, the thickened back film may be so thick that there is no ground pin in the penetration method that can be pressed to penetrate it.

[0164] To ground the wafer with the thickened backside film, a "pin bumping method" can be used. FIG. 14A to FIG. 14D 1400 is a system for grounding a wafer in accordance with some embodiments of the present disclosure. The system 1400 may implement a pin-bumping method. The system 1400 may be any system for grounding a wafer (e.g., Figure 3 , Figure 6 , Figure 7 or Fig. 9 300, 600, 700 or 900). Although FIG. 14A to FIG. 14D Only one ground pin is shown, but it should be noted that any single-pin system (e.g. Figure 3 subsystem 302 in) or a multi-pin system (e.g., Figure 4 System 400, Figure 6 to Figure 7 and Fig. 9 Subsystem 602 or 702 or Fig.12 The system 1200 in FIG. 1 can be configured to compatibly implement the pin-bumping method. For example, in a multi-pin system, the pin-bumping method can be compatibly implemented on one or more of its multiple ground pins.

[0165] exist FIG. 14A to FIG. 14D In FIG. 1 , system 1400 includes wafer 304, backside film 1402, ground pins 312, and an actuator (not shown). Backside film 1402 may be similar to Figure 3 to Figure 4 , Figure 6 to Figure 7 , Fig. 9 and Fig.12 In some embodiments, the back film 1402 can be thickened. For example, the thickness of the back film 1402 can exceed 0.3 μm (e.g., 1.4-2.2 μm). In some embodiments, the actuator can be coupled to a wafer stage (e.g., Figure 6 or Fig. 9 For example, the actuator may be coupled to a portion of the wafer stage (e.g., Figure 7 In some embodiments, the actuator can include one of an electric actuator (e.g., an electromechanical actuator such as an electric motor, or an electrohydraulic actuator including a hydraulic accumulator), a magnetic actuator (e.g., an electric motor), a spring (e.g., a coil spring or a coiled polymer), a pneumatic actuator, or a hydraulic actuator.

[0166] Fig.14A An initial stage of the system 1400 is shown, in which the ground pin 312 may be controlled (e.g., by Figure 3 Controller 322 or Figure 7 Controller 710 in the system 1400) to contact the back film 1402. For example, the actuator may be disabled in the initial stage. In other words, the ground pin 312 may be in a default position in the initial stage, wherein the default position causes the ground pin 312 to contact the back film 1402. This configuration in the initial stage can ensure that the system 1400 has compatibility for grounding a wafer without a thickened back film. For example, when a wafer without a thickened back film is placed in the system 1400, by setting Fig.14A In the initial stage shown, the system 1400 may perform other methods (e.g., Figure 5 , Fig.10 , Fig.11 ,or Fig.13 Method 500, 1000, 1100 or 1300) in order to ground the chip without invoking the pin-bumping method.

[0167] Fig. 14BThe first stage of the system 1400 for implementing the pin-impact method is shown, wherein the ground pin 312 is moved away (as shown by the arrow) a distance from the back film 1402. In some embodiments, the actuator can move the ground pin 312 away from the back film 1402. In some embodiments, the ground pin 312 can be moved away from the back film 1402 so that the distance between the ground pin 312 (e.g., measured from the tip of the ground pin 312) and the back film 1402 can exceed 100 microns. For example, the distance can exceed 1 millimeter. In some embodiments, by moving the ground pin 312 away from the back film 1402, the ground pin 312 can have enough space for acceleration, as described below.

[0168] Fig. 14C The second stage of the system 1400 implementing the pin-impacting method is shown, in which an actuator (not shown) can actuate (e.g., accelerate) the ground pin 312 toward the back film 1402 (as shown by the arrow). In some embodiments, the acceleration can end before the ground pin 312 hits the back film 1402. In some embodiments, the actuator can actuate the ground pin 312 so that the kinetic energy of the ground pin 312 before hitting the back film 1402 can exceed, for example, 0.0002 joules (e.g., when the maximum travel distance of the ground pin 312 is 3 mm). It should be noted that the kinetic energy of the ground pin before hitting the back film 1402 can depend on its travel distance under the actuation of the actuator, and is not limited to the above example.

[0169] Fig.14D The final stage of the system 1400 implementing the pin-bumping method is shown, where the ground pin 312 is Fig. 14C In some embodiments, the ground pin 312 may penetrate the back film 1402 completely and directly contact the wafer 304 without drilling into it. In this case, the ground pin 312 may be electrically connected to the wafer 304 using the penetration method of wafer grounding to ground the wafer 304. In some embodiments, the ground pin 312 may not be fully penetrated by the back film 1402, so that the distance between the tip of the ground pin 312 and the surface (e.g., conductive surface) of the wafer 304 may be less than or equal to 0.3 microns. In this case, the electrical breakdown method of wafer grounding may be used to establish an electrical connection between the ground pin 312 and the wafer 304 to ground the wafer 304.

[0170] In some embodiments of the pin-impact method described above, the kinetic energy of the ground pin 312 may depend on the distance between the ground pin 312 and the back film 1402, such as Fig. 14BFor example, if the actuator is a spring-based actuator, the ground pin 312 can be pulled away from the back film 1402 to compress the spring of the actuator. The greater the distance between the ground pin 312 and the back film 1402, the greater the elastic energy that the ground pin 312 can obtain by compressing the spring. The elastic energy obtained by the ground pin 312 can determine the kinetic energy it obtains in the second stage, such as Fig. 14C In another example, if the actuator is an electric actuator, the distance between the ground pin 312 and the back film 1402 can determine the space that allows the electric actuator to work on the ground pin 312 in the second stage, such as Fig. 14C For a particular type of actuator, different types of wafers, different types of backside films, and different thicknesses of backside films 1402 may determine the distance in the first stage, such as Fig. 14B As described in.

[0171] In some embodiments, the distance may be determined based on at least one of the wafer type, the backside film type, or the backside film thickness (e.g., by Figure 3 Controller 322 or Figure 7 For example, for a specific type of wafer with a specific type of backside film of a specific thickness, an experiment can be performed outside the grounding process, where a corresponding distance can be obtained, such as a distance that ensures direct contact between the grounding pin 312 and the wafer 304 without drilling, or a distance that ensures dielectric breakdown between the grounding pin 312 and the wafer 304. The wafer type information can be stored in a wafer grounding system including the system 1400 (e.g., in a Figure 3 332), and the corresponding distances may also be stored in the wafer grounding system (e.g., in a database storing wafer types 332 as shown). Figure 3 Target value 328 is also stored in the database shown.) When executing the second phase, system 1400 can determine the wafer type information and retrieve the corresponding distance before moving ground pin 312 away from backside film 1402.

[0172] In some embodiments, system 1400 can be based on determining from the electrical connection (e.g., by Figure 3 The electrical characteristics of the sensor 316 in Figure 3 For example, if the ground pin 312 hits the back film 1402 but the electrical connection cannot be established or the quality of the electrical connection does not meet the needs of wafer grounding, the system 1400 can determine a new distance for moving the ground pin 312 away from the back film 1402 based on the electrical characteristics determined from the electrical connection, and repeat the process. FIG. 14B to FIG. 14CIn some embodiments, when repeating the pin-bumping method, the system 1400 can also optimize other parameters besides the distance, such as the target kinetic energy to be applied to the ground pin 312 by the actuator.

[0173] In some embodiments, if Fig.14D If electrical connection cannot be established at the final stage as described in the previous section, the wafer grounding system including system 1400 can adjust the location on the wafer where the pin bumping method is implemented. For example, the location can be Figures 6 to 11 Adjusted as described in .

[0174] FIG. 15A to FIG. 15D 1 shows stages of operation of an example system 1500 for wafer grounding consistent with some embodiments of the present disclosure. System 1500 may implement a pin-bumping method. System 1500 may be any system for wafer grounding (e.g., Figure 3 , Figure 6 , Figure 7 or Fig. 9 300, 600, 700 or 900). Although FIG. 15A to FIG. 15D Only one ground pin is shown, but it should be noted that any single-pin system (e.g. Figure 3 subsystem 302 in) or a multi-pin system (e.g., Figure 4 System 400, Figure 6 to Figure 7 and Fig. 9 Subsystem 602 or 702 or Fig.12 The system 1200 in FIG. 1 can be configured to compatibly implement the pin-bumping method. For example, in a multi-pin system, the pin-bumping method can be compatibly implemented on one or more of its multiple ground pins.

[0175] exist FIG. 15A to FIG. 15D In FIG. 1 , system 1500 includes wafer 304, backside film 1402, ground pin 312, mass 1502, and an actuator (not shown). The actuator in system 1500 may be similar to FIG. 14A to FIG. 14D The actuator in the system 1400 described in . The mass 1502 can be a solid object with mass. In some embodiments, the mass 1502 can be a hammer or a ram.

[0176] Fig.15A An initial stage of the system 1500 is shown, in which the ground pin 312 may be controlled (e.g., by Figure 3 Controller 322 or Figure 7 Controller 710 in ) to contact backside film 1402 and mass 1502 can be controlled to contact ground pin 312. Similar to the initial stage of system 1400, such a configuration can ensure that system 1500 has compatibility for grounding a wafer without a thickened backside film.

[0177] Fig. 15B The first stage of the system 1500 implementing the pin-impact method is shown, where the mass 1502 is moved away from the ground pin 312 (as shown by the arrow) by a distance. In some embodiments, the actuator can move the mass 1502 away from the back film 1402. In some embodiments, the mass 1502 can be moved away from the ground pin 312 so that the distance between the mass 1502 (e.g., measured from the top surface of the mass 1502) and the ground pin 312 can exceed 100 microns. For example, the distance can exceed 1 mm. In some embodiments, by moving the mass 1502 away from the ground pin 312, the mass 1502 can have enough space for acceleration, as described below.

[0178] Fig. 15C A second stage of the system 1500 implementing the pin-bumping method is shown, in which an actuator (not shown) may actuate (e.g., accelerate) a mass 1502 (as indicated by the arrow) toward the ground pin 312. In some embodiments, the acceleration may end before the mass 1502 strikes the ground pin 312. In some embodiments, the actuator may actuate the mass 1502 such that the kinetic energy of the mass 1502 before striking or impacting the ground pin 312 may exceed, for example, 0.0002 joules.

[0179] Fig.15D The final stage of the system 1500 implementing the pin-impacting method is shown, in which the ground pin 312 penetrates the back film 1402 by impact due to the force applied to the ground pin 312 by the mass 1502. Similar to the final stage of the system 1400, in the final stage of the system 1500, the ground pin 312 may or may not fully penetrate the back film 1402, and an electrical connection may be established between the ground pin 312 and the wafer 304 using the penetration method or the electrical breakdown method, respectively.

[0180] exist FIG. 15A to FIG. 15D In some embodiments of the pin impact method described in , the kinetic energy of the mass block 1502 when impacting the ground pin 312 may depend on the distance between the mass block 1502 and the ground pin 312, such as Fig. 15B As described in. Fig. 15C The kinetic energy of the mass block 1502 to be obtained is Fig. 15B The relationship between the distance between the middle mass 1502 and the ground pin 312 may be similar to Fig. 14C The kinetic energy of the ground pin 312 to be obtained is Fig. 14B The relationship between the distance between the ground pin 312 and the back film 1402 is not described here. In addition, in some embodiments, Fig. 15BThe distance in the range may be based on at least one of the type of wafer, the type of coating on the wafer, or the thickness of the coating. FIG. 14A to FIG. 14C In addition, in some embodiments, the system 1500 can be determined based on the electrical connection (for example, by Figure 3 The electrical characteristics of the sensor 316 in Figure 3 The electrical characteristics 320 in the example are used to optimize the distance, or to FIG. 14A to FIG. 14C The position of the pin bumping method on the chip is adjusted in a similar manner as described in , which will not be repeated here.

[0181] and FIG. 14A to FIG. 14B Compared to the pin-bumping method described in FIG. 15A to FIG. 15B The pin impact method described in the embodiment of the present invention can have more degrees of freedom to design the system 1500. For example, the material and mass of the mass 1502 can be selected with more degrees of freedom. FIG. 15A to FIG. 15B Compared to the pin-bumping method described in FIG. 14A to FIG. 14B The pin-bumping method described in may be more straightforward and require fewer components to implement.

[0182] Fig.16 1 is a flow chart illustrating an example method 1600 for wafer grounding consistent with some embodiments of the present disclosure. The method 1600 may be performed by a controller that may be coupled to a charged particle beam device (e.g., the EBI system 100). For example, the controller may be Figure 3 Controller 322 or Figure 7 The controller 710 in FIG. 1600 can be programmed to implement the method 1600 .

[0183] At step 1602, the controller causes a ground pin (eg, FIG. 14A to FIG. 14D or FIG. 15A to FIG. 15D ground pin 312 in the wafer (eg, FIG. 14A to FIG. 14D or FIG. 15A to FIG. 15D In step 1604, the controller establishes an electrical connection between the ground pin and the chip.

[0184] In some embodiments of step 1602, the controller may cause the ground pin to penetrate a coating on the wafer by striking the ground pin (e.g., FIG. 14A to FIG. 14D or FIG. 15A to FIG. 15DThe back film 1402 in the wafer can be used as the back film 1402 in the wafer. For example, the coating can have a thickness of more than 0.3 microns. In some embodiments, the controller can cause the ground pin to penetrate the coating via impact to directly contact the wafer. In some embodiments, the controller can cause the ground pin to penetrate the coating via impact, wherein the ground pin does not completely penetrate the coating. For example, when the ground pin does not completely penetrate the coating, the distance between the tip of the ground pin and the wafer surface after the ground pin penetrates the coating by impact can be less than or equal to 0.3 microns. In some embodiments, such as when the above distance is less than or equal to 0.3 microns, the wafer can still be grounded by electrical breakdown.

[0185] In some embodiments of step 1602, the controller may actuate toward the wafer (e.g., using a FIG. 14A to FIG. 14D In some embodiments, when the ground pin is actuated toward the wafer, the controller can control the ground pin to move a distance away from the wafer (e.g., Fig. 14B ) and accelerating the ground pin toward the wafer (e.g., as shown and described in Fig. 14C In some embodiments, the distance may exceed 100 microns. For example, the distance may exceed 1 millimeter. In some embodiments, the controller may determine the distance based on at least one of the type of wafer, the type of coating on the wafer, or the thickness of the coating (e.g., FIG. 14A to FIG. 14D In some embodiments, the controller may cause the ground pin to contact the wafer before moving the ground pin away from the wafer, such as by Fig.14A The method shown.

[0186] In some embodiments of step 1602, the controller may cause the mass (e.g., FIG. 15A to FIG. 15D In some embodiments, the controller can actuate (e.g., using a controller such as a controller that moves the wafer toward the ground pin) to strike the ground pin toward the wafer. FIG. 15A to FIG. 15D The controller may control the mass block to move a distance (e.g., such as 0.0002 joules) away from the ground pin. Fig. 15B ) and accelerates the mass toward the ground pin (e.g., as shown and described in Fig. 15C In some embodiments, the distance may exceed 100 microns. For example, the distance may exceed 1 millimeter. In some embodiments, the controller may determine the distance based on at least one of the type of wafer, the type of coating on the wafer, or the thickness of the coating (e.g., FIG. 15A to FIG. 15D In some embodiments, the controller may cause the mass to contact the ground pin before moving the mass away from the ground pin, such as by Fig.15A In some embodiments, in addition to causing the proof mass to contact the ground pin before moving the proof mass away from the ground pin, the controller may also cause the ground pin to contact the wafer, such as in Fig.15A The method shown.

[0187] As an example, Fig.17 is a diagram of an example wafer grounding system 1700 consistent with some embodiments of the present disclosure, wherein a voltage difference is instantaneously present between an electrode of an electrostatic holder and a ground pin. In some embodiments, the system 1700 may include Figure 3 System 300, Figure 4 System 400, Figure 6 System 600, Figure 7 System 700, Fig. 9 System 900, Fig.12 System 1200, FIG. 14A to FIG. 14D System 1400 or FIG. 15A to FIG. 15D The system 1500 may have the same components or more components or fewer components. Fig.17 In the embodiment, system 1700 includes a chip 304, an electrostatic holder 306, one or more ground pins (including a ground pin 312), multiple electrodes (including a first electrode 1702 and a second electrode 1704), a first wiring 1706 connected to the first electrode 1702, a second wiring 1708 connected to the second electrode 1704, a ground wiring 1710 connected to the ground pin 312, a ground power source 1712 connected to the ground wiring 1710, and a voltage source 1714 connected to the first wiring 1706 and the second wiring 1708.

[0188] For example, the first electrode 1702 can withstand a positive clamping voltage provided by the voltage source 1714 via the first wiring 1706 (indicated by the positive sign "+" inside the first electrode 1702), and the second electrode 1704 can withstand a negative clamping voltage provided by the voltage source 1714 via the second wiring 1708 (indicated by the negative sign "-" inside the second electrode 1704). The "wiring" or "cabling" described herein may include any number of wires, cables, cords, interfaces, connectors, conductors, insulators, semiconductors, or any power distribution components. Fig.17 As shown, the first electrode 1702 and the second electrode 1704 can be included below the top surface of the electrostatic holder 306. The electrostatic holder 306 can include a non-conductive dielectric material between the wafer 304 and the first electrode 1702 and the second electrode 1704. It should be noted that although Fig.17 Only one ground pin and two electrodes are shown, but system 1700 may include any number of ground pins and electrodes.

[0189] During operation of system 1700, ground pin 312 may be electrically connected to die 304 to provide a ground signal, such as Fig.17 For example, the ground pin 312 can be formed on the back surface of the through-wafer 304 ( Fig.17 1710 and the ground pin 312 may be connected to the wafer 304 via dielectric breakdown, such as by the electrical breakdown method described herein. The ground power supply 1712 may provide a ground signal and a wafer bias potential (e.g., a negative voltage potential) to the wafer 304 via the ground wiring 1710 and the ground pin 312. For example, the ground power supply 1712 may include Figure 3 The ground power source 1712 may be a device different from the voltage source 1714.

[0190] During operation of the system 1700, a clamping voltage may be provided to the electrodes of the electrostatic holder 306 for securing the wafer 304 on the top surface of the electrostatic holder 306. The clamping voltage may float on a voltage potential provided to the wafer 304 by the floating voltage. For example, the floating voltage may be 300 volts, wherein the first electrode 1702 may be provided with a positive clamping voltage of 30 kV + 300 volts, and the second electrode 1704 may be provided with a negative clamping voltage of 30 kV - 300 volts. Consistent with some embodiments of the present disclosure, as Fig.17 As shown, the first electrode 1702 and the second electrode 1704 can be provided with a positive clamping voltage and a negative clamping voltage, respectively. In response to the clamping voltage, opposite charges can be formed at the bottom surface of the wafer 304 (indicated by the positive sign "+" and the negative sign "-" inside the wafer 304). If the absolute values ​​of the clamping voltages of the first electrode 1702 and the second electrode 1704 are equal, the opposite charges generated at the bottom surface of the wafer 304 may not affect the total charge carried by the wafer 304. For example, the wafer 304 can be biased (e.g., with a voltage potential of 30 kV) and maintained electrically neutral (e.g., the total charge carried is zero), and the charge distribution inside the wafer 304 can be as shown. Fig.17 Opposite charges formed at the bottom surface of wafer 304 may be attracted by the corresponding electrode, wherein wafer 304 may be fixed to the top surface of electrostatic holder 306 .

[0191] In some cases, arcing may occur in the circuit arrangement of the electrode. Fig.17As shown, an arc 1716 may occur in the first wiring 1706, which may momentarily cause a voltage difference (e.g., 10 kV) to form between the wafer 304 and the electrode of the electrostatic holder 306 (e.g., the first electrode 1702). This voltage difference may significantly interfere with the clamping voltage, while the bias voltage potential (e.g., 30 kV) provided to the wafer 304 may not be affected. For example, the clamping voltage of the first electrode 1702 may drop from 30 kV + 300 V to 20 kV + 300 V. As another example, if the first wiring 1708 ( Fig.17 If an arc occurs in the wafer 304 (not shown), the clamping voltage of the second electrode 1704 may also change due to the voltage difference. This instantaneously formed voltage difference can generate a strong electric field between the wafer 304 and the electrodes of the electrostatic holder 306 (e.g., the first electrode 1702 and the second electrode 1704). The strong electric field can attract or repel the charges in the wafer 304 relative to the top surface of the electrostatic holder 306. The attracted or repelled charges can further form residual charges on the wafer 304 or the electrostatic holder 306.

[0192] The present disclosure provides a device and system for preventing the formation of residual charge caused by the voltage difference formed instantaneously between the substrate and the electrostatic retainer. Consistent with some embodiments of the present disclosure, the device or system may include a ground pin, an electrostatic retainer including an electrode inside the electrostatic retainer, and an overvoltage protection device electrically coupled (e.g., conductively connected) between the ground pin and the electrode. The overvoltage protection device may be configured to conduct electricity when the voltage applied to the overvoltage protection device exceeds a threshold voltage, and stop conducting electricity when the voltage does not exceed the threshold voltage. In some embodiments, the overvoltage protection device may allow power to be conducted in multiple directions. In some embodiments, the threshold voltage may be an electrical characteristic (e.g., parameter) of the overvoltage protection device. In some embodiments, the threshold voltage may be adjustable (e.g., configurable to have any value in response to different applications of the device and system).

[0193] In some embodiments, the overvoltage protection device may include at least one of the following: a transient voltage suppression (TVS) diode, a Zener diode, a varistor (or referred to as a "voltage dependent resistor"), or a silicon diode for alternating current (SIDAC), or any active crossbar device that becomes conductive under an overvoltage and resets to non-conductive when the overvoltage is removed. For example, if the overvoltage protection device includes a TVS diode, the threshold voltage may be the reverse breakdown voltage of the TVS diode. When the voltage applied to the TVS diode exceeds the reverse breakdown voltage, the TVS diode may operate in an avalanche mode that provides a low impedance path to ground for the overvoltage. After the overvoltage drops below its reverse breakdown voltage, the TVS diode may return to a high impedance state.

[0194] In some embodiments, the overvoltage protection device may include at least one of a thyristor surge protection device (Trisil), a diode alternating current (DIAC), and a bidirectional triode thyristor (TRIAC).

[0195] In accordance with some embodiments of the present disclosure, the device and system may include multiple ground pins, and the electrostatic holder may include multiple electrodes. The device and system may include multiple overvoltage protection devices, each of which may be electrically coupled between a ground pin and an electrode. That is, there is an overvoltage protection device electrically coupled between each ground pin and each electrode. The multiple overvoltage protection devices may be configured to become conductive under an overvoltage and reset to non-conductive when the overvoltage is removed.

[0196] In accordance with some embodiments of the present disclosure, the device and system may further include a housing. The housing may include a concave surface surrounding the electrostatic retainer and the ground pin. The housing may further include at least one of a first interface or a second interface. The first interface may be on the concave surface and cooperate with the wiring of the electrode. The second interface may be on the concave surface and cooperate with the wiring of the ground pin. The overvoltage protection device may be disposed inside or outside the housing.

[0197] By using an overvoltage protection device, the above-mentioned apparatus and system can transfer charge between the electrode and the ground pin instantaneously through the overvoltage protection device in a low impedance state when an overvoltage is instantaneously formed between the electrode and the ground pin (for example, when an arc occurs in the wiring of the electrode). When the overvoltage subsides, the overvoltage protection device can be restored to a high impedance state. Such a technical solution can reduce or eliminate the formation of residual charge.

[0198] As an example, Fig.18 is a diagram of an example wafer grounding system 1800 consistent with some embodiments of the present disclosure in which a voltage difference is prevented from forming between an electrode of an electrostatic holder and a ground pin. The system 1800 may be similar to Fig.17 The system 1700 includes a chip 304, an electrostatic holder 306, a ground pin 312, a first electrode 1702, a second electrode 1704, a first wiring 1706, a second wiring 1708, a ground wiring 1710, a ground power supply 1712, a voltage source 1714, a first overvoltage protection device 1802 electrically coupled between the ground wiring 1710 and the first wiring 1706, and a second overvoltage protection device 1804 electrically coupled between the ground wiring 1710 and the second wiring 1708.

[0199] The first overvoltage protection device 1802 and the second overvoltage protection device 1804 may respectively shunt overvoltage between the ground wiring 1710 (and substantially the wafer 304) and the first wiring 1706 and the second wiring 1708. For example, when the voltage difference between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708) is lower than a threshold voltage (e.g., a breakdown voltage), the first overvoltage protection device 1802 (or the second overvoltage protection device 1804) may be non-conductive (e.g., functioning as a high impedance capacitor) and prevent charges from flowing between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708). When the voltage difference between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708) is equal to or higher than the threshold voltage, the first overvoltage protection device 1802 (or the second overvoltage protection device 1804) can become conductive (for example, by significantly reducing its impedance) and allow charge to flow between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708), which can instantaneously reduce or eliminate the voltage difference. When the voltage difference between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708) is reduced below the threshold voltage again, the first overvoltage protection device 1802 (or the second overvoltage protection device 1804) can automatically reset to become non-conductive again.

[0200] The first overvoltage protection device 1802 or the second overvoltage protection device 1804 may have a direction along which charge is allowed to flow. In some embodiments, the first overvoltage protection device 1802 or the second overvoltage protection device 1804 may be "bidirectional" such that charge is allowed to flow in either direction along them. For example, when the absolute value of the voltage difference between the ground wiring 1710 and the first wiring 1706 (or the second wiring 1708) is equal to or higher than the threshold voltage, if the voltage of the chip 304 is higher than the first electrode 1702 (or the second electrode 1704), the first overvoltage protection device 1802 (or the second overvoltage protection device 1804) may allow charge to flow from the ground wiring 1710 to the first wiring 1706 (or the second wiring 1708), or if the voltage of the chip 304 is lower than the first electrode 1702 (or the second electrode 1704), the first overvoltage protection device 1802 (or the second overvoltage protection device 1804) may allow charge to flow from the first wiring 1706 (or the second wiring 1708) to the ground wiring 1710.

[0201] In some embodiments, the first overvoltage protection device 1802 or the second overvoltage protection device 1804 may be "unidirectional" so that charge is only allowed to flow in a single direction thereof. For example, if the first overvoltage protection device 1802 has a conductive direction from the ground wiring 1710 to the first wiring 1706, it may allow charge to flow from the ground wiring 1710 to the first wiring 1706 only when the voltage of the wafer 304 exceeds the voltage of the first electrode by a threshold voltage, and may prevent charge from flowing from the first wiring 1706 to the ground wiring 1710 even when the voltage of the first electrode 1702 exceeds the voltage of the wafer 304 by a threshold voltage.

[0202] As an example, FIG. 19A to FIG. 19C is a diagram of an example wafer grounding system 1900A-1900C consistent with some embodiments of the present disclosure in which a voltage difference is prevented from forming between an electrode of an electrostatic holder and a ground pin. The systems 1900A-1900C may be similar to Fig.18 The system 1800 in FIG. 1800 includes an electrostatic holder 306, a ground pin 312, a first electrode 1702, a second electrode 1704, a first wiring 1706, a second wiring 1708, a ground wiring 1710, a ground power source 1712, a voltage source 1714, a first overvoltage protection device 1802, and a second overvoltage protection device 1804. The system 1900A-1900C also includes a housing 1902, which includes a concave surface 1904 (by FIG. 19A to FIG. 19C ), a first interface 1906 on the concave surface 1904, a second interface 1908 on the concave surface 1904, a ground interface 1910 on the concave surface 1904, a first cable 1912 electrically coupled between the first electrode 1702 and the first interface 1906, a second cable 1914 electrically coupled between the second electrode 1704 and the second interface 1908, and a ground cable 1916 electrically coupled between the ground pin 312 and the ground interface 1910. The "interface" described herein may include a position or terminal at which two or more electrical components are connected or interact with each other. In some embodiments, the interface described herein may include a mating portion (e.g., a convex or concave portion). For example, the first interface 1906, the second interface 1908, and the ground interface 1910 may include a connector, a plug, a screw, a fixture, a pin, a socket, or any device for electrically coupling two or more electrical components.

[0203] The first wiring 1706 may include a first interface 1906 and a first cable 1912. For example, the first interface 1906 may cooperate with one or more portions of the first wiring 1706 (e.g., the first cable 1912). The second wiring 1708 may include a second interface 1908 and a second cable 1914. For example, the second interface 1908 may cooperate with one or more portions of the second wiring 1708 (e.g., the second wiring 1914). The ground wiring 1710 may include a ground interface 1910 and a ground cable 1916. For example, the ground interface 1910 may cooperate with one or more portions of the ground wiring 1710 (e.g., the ground wiring 1916).

[0204] The concave surface 1904 may surround the electrical retainer 306 and the ground pin 312, such as FIG. 19A to FIG. 19C It should be noted that the concave surface 1904 can be any shape, not limited to FIG. 19A to FIG. 19C Example shapes shown.

[0205] Consistent with the embodiments of the present disclosure, the first overvoltage protection device 1802 may be disposed anywhere as long as it is electrically coupled between the ground pin 312 and the first electrode 1702, and the second overvoltage protection device 1804 may be disposed anywhere as long as it is electrically coupled between the ground pin 312 and the second electrode 1704. As an example, Fig.19A As shown, the first overvoltage protection device 1802 and the second overvoltage protection device 1804 are arranged inside the housing 1902. FIG. 19B to FIG. 19C As shown, the first overvoltage protection device 1802 and the second overvoltage protection device 1804 are arranged outside the housing 1902. Fig.19B In FIG. 1 , the first overvoltage protection device 1802 is electrically coupled between the first interface 1906 and the ground interface 1910, and the second overvoltage protection device 1804 is electrically coupled between the second interface 1908 and the ground interface 1910. As another example, in Fig.19C , the first overvoltage protection device 1802 is electrically coupled between the first cable 1912 and the ground cable 1916, and the second overvoltage protection device 1804 is electrically coupled between the second cable 1914 and the ground cable 1916. In some embodiments, in order to further reduce their impedance, the first overvoltage protection device 1802 and the second overvoltage protection device 1804 can be arranged at positions close to the first electrode 1702 and the second electrode 1704, respectively. It should be noted that the present disclosure does not limit the position of the first overvoltage protection device 1802 or the position of the second overvoltage protection device 1804 to such positions. FIG. 19A to FIG. 19C Examples shown and described in .

[0206] In some cases, one reason for the voltage difference that is formed momentarily between the wafer and the electrostatic holder may be a discharge that occurs near the electrostatic holder. As an example, Fig. 20 A cross-sectional view of an example wafer inspection system 2000 is shown, consistent with some embodiments of the present disclosure, where discharge may occur at a high voltage portion. Fig. 20 In the embodiment, the system 2000 includes an electrostatic holder 306, a wafer 304 fixed on the electrostatic holder 306, a housing 1902 supporting the electrostatic holder 306, and a primary electron beam 220 projected onto the wafer 304 through a hole (indicated by an inner dashed line) in the shielding plate 2002. The housing 1902 includes a cavity 2004, which can be used to place a stage (e.g., Figure 2 The motorized sample stage 201 shown and described in FIG. 2 ). An electrostatic holder 306 may be mounted to the stage and may be controlled to move with the stage.

[0207] The housing 1902 includes a top surface 2006 (indicated by a bold line), a bottom surface 2008 (indicated by a bold line), and a side surface 2010. In some embodiments, the side surface 210 may also be used as a reflector for positioning purposes. For inspection operations, the top surface 2006 and the wafer 304 may be biased by a high voltage (e.g., -30 kV). In order to avoid deflection of the primary electron beam 220, the shielding plate 2002 may also be biased by a bias voltage (e.g., -30 kV). The bottom surface 2008 may be grounded. In the system 2000, the top surface 2006 may be referred to as a high voltage portion, and the bottom surface 2008 may be referred to as a grounding portion. An isolation layer may be applied to the side surface 2010 to isolate the top surface 2006 and the bottom surface 2008. Therefore, in the present disclosure, the side surface 2010 may also be referred to as an isolation surface 2010.

[0208] In an ideal case, there is no electric field below the bottom surface 2008 due to its grounding or above the top surface 2006 due to the shielding plate 2002, and the electric field will only exist between the top surface 2006 and the bottom surface 2008. In such an ideal case, the high voltage of the top surface 2006 can drop from the top surface 2006 to the bottom surface 2008 along the isolation surface 2010.

[0209] However, in actual scenarios, when the electric field near the top surface 2006 is too strong, field emission may be generated between the top surface 2006 and the isolation surface 2010. Since the top surface 2006 is conductive and connected to a power source, it can basically be used as a charge source that can provide a large amount of charge (e.g., electrons). The charges generated due to field emission (referred to as "field emission charges") may detach from the top surface 2006 and reach the isolation surface 2010. If the landing energy of the field emission charges is high enough, they may release gas molecules that adhere to the isolation surface 2010 and may further trigger an avalanche effect. The avalanche effect may cause a large current to generate an arc between the top surface 2006 and the isolation surface 2010, thereby releasing a large amount of charge into the environment near the electrostatic holder 306. This discharge may interfere with the clamping voltage of the electrostatic holder 306 and cause residual charge to be formed thereon, which may cause wafer sticking problems. In addition, this discharge may attract undesirable particles (e.g., dust) from the environment, which may interfere with the primary electron beam 220 used for wafer inspection.

[0210] The high voltage (i.e., bias voltage) of the top surface 2006 may be turned on and off in some cases, such as for wafer replacement or shutting down the system 2000 for maintenance. In these cases, to prevent the above-mentioned discharge, the ramp-up or ramp-down of the high voltage may be limited to a slow rate, which may limit the throughput of wafer inspection of the system 2000, especially when the system 2000 is a multi-beam inspection system.

[0211] In accordance with some embodiments of the present disclosure, a device and system for rapid ramping of high voltage without causing discharge is provided. Such a device may include an isolator arranged between a high voltage portion of the device and a grounded portion of the device. A high voltage may be applied to the high voltage portion. The grounded portion may be grounded by being electrically connected to the ground. The isolator may insulate the high voltage portion from the grounded portion. The device may also include a first electrode electrically coupled to the high voltage portion, and a second electrode electrically coupled to the grounded portion and non-conductive with the first electrode. The device may also include a dielectric layer covering the first electrode and the second electrode on the isolator. As used herein, "covering" may include enclosing, encapsulating, burying, wrapping, embedding, covering, coating, or any action of insulating or isolating an object from another object or the environment. For example, the dielectric layer may be made of glass, ceramic, or a dielectric constant of at least 3×10 -11 Farads per meter of any material.

[0212] In some embodiments, the high voltage portion may include a first surface (e.g., an anode plate). The ground portion may include a second surface (e.g., a cathode plate) parallel to the first surface. The separator may include a vertical surface (e.g., a sidewall) between the first surface and the second surface.

[0213] In some embodiments, the dielectric layer may be adhered to the surface of the isolator. In this case, the first electrode and the second electrode may be covered between the dielectric layer and the surface of the isolator. For example, a glass or ceramic layer may be glued to the surface of the isolator, wherein the first electrode and the second electrode may be glued between the layer and the surface.

[0214] In some embodiments, the separator may include a dielectric layer. In this case, the first electrode and the second electrode may be embedded inside the separator. For example, the dielectric layer may be a homogenous portion of the separator. For example, the first electrode and the second electrode may be embedded in clay and fired together into a single ceramic body.

[0215] In some embodiments, the separator may embed the first electrode and the second electrode, and an additional dielectric layer may be adhered to the surface of the separator. It should be noted that covering the first electrode and the second electrode on the separator may also be achieved in other ways, and the present disclosure is not limited to the above embodiments.

[0216] In accordance with some embodiments of the present disclosure, the device may further include a first conductive portion and a second conductive portion. The first conductive portion may be electrically coupled to the high voltage portion of the device and capacitively coupled to the first electrode. For example, the first conductive portion may be a plate extending from the high voltage portion and parallel to the first electrode. The second conductive portion may be electrically coupled to the ground portion of the device and capacitively coupled to the second electrode. For example, the second conductive portion may be a plate extending from the ground portion and parallel to the second electrode.

[0217] The dielectric layer can help form a capacitor on the surface of the isolator. For example, the first conductive portion, the dielectric layer, and the first electrode can form a first capacitor. As another example, the second conductive portion, the dielectric layer, and the second electrode can form a second capacitor. The capacitor can mitigate capacitive coupling between the device and objects in its surrounding environment (e.g., adjacent components of the device or building structures) to prevent the formation of concentrated electric fields that can cause field emissions. The larger the capacitance of the capacitor, the better the mitigation it can provide. If the capacitance of the capacitor is high enough, it can be considered that its high capacitance can effectively place the device in a vacuum, thereby greatly mitigating or even eliminating the effects of environmental capacitive coupling.

[0218] The capacitance of a capacitor may be proportional to the overlapping area of ​​its terminals and inversely proportional to the distance between the two terminals. That is, the capacitance of a capacitor may be proportional to the ratio of the overlapping area to the distance (referred to as the "overlapping distance ratio"). For example, a first capacitor may have a first conductive portion and a first electrode as its two terminals, which are spaced apart by the thickness of the dielectric layer and have a first overlapping area. A second capacitor may have a second conductive portion and a second electrode as its two terminals, which are spaced apart by the thickness of the dielectric layer and have a second overlapping area.

[0219] In some embodiments, the thickness of the dielectric layer may be equal to or less than one tenth (i.e., 1 / 10) of the smaller overlap region of the first overlap region between the first conductive portion and the first electrode and the second overlap region between the second conductive portion and the second electrode. In this case, the overlap distance ratio of the first capacitor and the second capacitor may both be at least 10, which may help increase their capacitance.

[0220] In some embodiments, the thickness of the dielectric layer can be equal to or less than one-fiftieth (e.g., 1 / 50) of the distance between the surface of the dielectric layer and an object that is capacitively coupled to the device and is not part of the device. For example, the object can be an object in the surrounding environment of the device. The object and the first conductive portion (or the second conductive portion) can form an effective capacitor, where the object and the first conductive portion (or the second conductive portion) are its two terminals and all the material therebetween (e.g., air) is a dielectric material. In this case, the capacitance of the first capacitor (or the second capacitor) may exceed the capacitance of the effective capacitor because the terminal-to-terminal distance of the first capacitor (or the second capacitor) is much smaller (e.g., at most 1 / 50) than the terminal-to-terminal distance of the effective capacitor, which can help reduce the capacitive coupling between the object and the device.

[0221] In accordance with some embodiments of the present disclosure, the apparatus may further include a housing. The housing may be configured to enclose a stage of the wafer inspection system. The high voltage portion may include a top surface of the housing. The ground portion may include a bottom surface of the housing. The isolator may include a wall of the housing. For example, in addition to enclosing the platform, the housing may also be used to support an electrostatic holder.

[0222] In accordance with some embodiments of the present disclosure, the device may include a plurality of electrodes covered by a dielectric layer on top of the isolator. For example, the number of covered electrodes may depend on the value of the high voltage. In some embodiments, the number of covered electrodes may be a ratio of the value of the high voltage. By doing so, the surface voltage of the isolator may be configured during ramp-up or ramp-down of the high voltage.

[0223] As an example, Fig.21 is a diagram of an example device 2100 for rapid ramping of high voltage without causing discharge consistent with some embodiments of the present disclosure. The device 2100 may include Fig. 20 Some components of system 2000 in FIG. 2004 include top surface 2006, bottom surface 2008, and isolation surface 2010. Fig. 202008. The high voltage portion of the device 2100 may include a top surface 2006 and the grounded portion of the device 2100 may include a bottom surface 2008. The top surface 2006 may be parallel to the bottom surface 2008. The isolator of the device 2100 may include an isolation surface 2010 perpendicular to the top surface 2006 and the bottom surface 2008. Fig.21 As shown, isolation surface 2010 can serve as an isolator between top surface 2006 and bottom surface 2008 of device 2100. Device 2100 also includes a first electrode 2102 electrically coupled to top surface 2006 and a second electrode 2104 electrically coupled to bottom surface 2008 and in electrical non-conductivity with first electrode 2102.

[0224] The first electrode 2102 and the second electrode 2104 may be fixed on the isolation surface 2010. By introducing the first electrode 2102 and the second electrode 2104 on the isolation surface 2010, the voltage difference between the top surface 2006 and the bottom surface 2008 may decrease at a constant rate. Fig.21 As shown, the value of the voltage difference between point 2106 and point 2108 decreases along the x direction and substantially reaches zero potential (because the second electrode 2104 is grounded), represented by voltage curve 2110. Point 2106 may be at the end of the first electrode 2102, and point 2108 may be at the end of the second electrode 2104. Fig.21 As shown, voltage curve 2110 has a constant slope without abrupt changes. In this case, the electric field between point 2106 and point 2108 can have a constant intensity, and the gradient of the electric field can be smooth, which can prevent the formation of a concentrated electric field that may cause field emission.

[0225] Fig.21 An ideal situation is shown in which the effects of the environment surrounding the device 2100 are not considered. In a practical scenario, environmental objects or even air may interact with the device 2100, such as via capacitive coupling. For example, if the environment includes conductive objects (e.g., Fig. 20 If there are adjacent components or building structures of the system 2000), there may be capacitance between these objects and the isolation surface 2010, the first electrode 2102 or the second electrode 2104, which can be represented as one or more effective capacitors.

[0226] As an example, Fig. 22 is an illustration of an example device 2200 for rapid ramping of high voltage without causing discharge, consistent with some embodiments of the present disclosure. Fig. 22A practical case is shown in which the influence of the environment on the device 2200 is considered. The device 2200 may be similar to the device 2100 and include a top surface 2006, a bottom surface 2008, an isolation surface 2010, a first electrode 2102, and a second electrode 2104. The value of the voltage difference between the point 2106 and the point 2108 decreases along the x-direction and reaches substantially zero potential (because the second electrode 2104 is grounded), represented by the voltage curve 2204.

[0227] Device 2200 also includes an effective capacitor bank 2202, which includes one or more effective capacitors representing the capacitance formed between device 2200 and objects in its surroundings. The effective capacitors represent only capacitive coupling, not actual capacitors. Under the influence of effective capacitor bank 2202, Fig.21 Compared with the voltage curve 2110 in FIG. 2 , the voltage curve 2204 may be changed to a different shape and include a mutation point 2206, which indicates that the electric field near the point 2106 may be concentrated and have a high intensity. In this case, there is a risk that field emission may occur near the point 2106.

[0228] As an example, Fig.23 2004 is a diagram of an example device 2300 for rapid ramping of high voltage without causing discharge consistent with some embodiments of the present disclosure. Device 2300 can be similar to device 2100 and includes a top surface 2006, a bottom surface 2008, an isolation surface 2010, a first electrode 2102, and a second electrode 2104. In order to mitigate or eliminate the effects of capacitive coupling from the environment (e.g., Fig. 22 ), the device 2300 further includes a dielectric layer 2306 (shown as a dotted area) covering the first electrode 2102 and the second electrode 2104 on the isolation surface 2010. Fig.23 In FIG. 2 , dielectric layer 2306 may be adhered (eg, via glue 2308, shown as a shaded area) to isolation surface 2010. Fig.23 , the first electrode 2102 and the second electrode 2104 are covered between the dielectric layer 2306 and the isolation surface 2010. For example, the dielectric layer 2306 can be a glass or ceramic layer.

[0229] Similar to Fig. 22 In the device 2200, the device 2300 can be capacitively coupled to objects in its surrounding environment. Fig.23 Three effective capacitors reflecting this capacitive coupling are shown, including a first effective capacitor 2310 formed between the environment and the first conductive portion 2302, a second effective capacitor 2316 formed between the environment and the second conductive portion 2304, and a third effective capacitor 2318 formed between the environment and the dielectric layer 2306.

[0230] Device 2300 also includes a first conductive portion 2302 and a second conductive portion 2304. First conductive portion 2302 can be electrically coupled to top surface 2006 and capacitively coupled to first electrode 2102. For example, Fig.23 As shown, the first conductive portion 2302 can be a plate extending from the top surface 2006 and parallel to the first electrode 2102. The material of the first conductive portion 2302, the first electrode 2102, and the dielectric layer 2306 therebetween can form a first capacitor 2312. The second conductive portion 2304 can be electrically coupled to the bottom surface 2008 and capacitively coupled to the second electrode 2104. For example, Fig.23 As shown, the second conductive portion 2304 can be a plate extending from the bottom surface 2008 and parallel to the second electrode 2104. The material of the second conductive portion 2304, the second electrode 2104, and the dielectric layer 2306 therebetween can form a second capacitor 2314. The first capacitor 2312 and the second capacitor 2314 can mitigate capacitive coupling between the device and the environment (e.g., represented by the first effective capacitor 2310, the second effective capacitor 2316, and the third effective capacitor 2318) to prevent the formation of a concentrated electric field that may cause field emission.

[0231] One way to effectively mitigate the capacitive coupling between the device 2300 and its surroundings is to increase the capacitance of the first capacitor 2312 and the second capacitor 2314 to a level much higher than the capacitance of these capacitive couplings (e.g., the capacitance of the first effective capacitor 2310, the second effective capacitor 2316, and the third effective capacitor 2318). For example, the first capacitor 2312 can have the first conductive portion 2302 and the first electrode 2102 as its two terminals, which are separated by the thickness of the dielectric layer 2306 and have a first overlap area. The second capacitor 2314 can have the second conductive portion 2304 and the second electrode 2104 as its two terminals, which are separated by the thickness of the dielectric layer 2306 and have a second overlap area. Because the capacitance of a capacitor is proportional to its overlap distance ratio, the device can be configured so that the first capacitor 2312 and the second capacitor 2314 have a high overlap distance ratio. In some embodiments, the thickness of dielectric layer 2306 may be equal to or less than one tenth (i.e., 1 / 10) of the smaller of the first overlapping region of first capacitor 2312 and the second overlapping region of second capacitor 2314. In such a case, the overlapping distance ratio of first capacitor 2312 and second capacitor 2314 may both be at least 10, which may help increase their capacitance.

[0232] In order to increase the capacitance of the first capacitor 2312 and the second capacitor 2314 to a level much higher than the capacitance of these capacitive couplings, the device 2300 may also be configured such that the overlap distance ratios of the first capacitor 2312 and the second capacitor 2314 are both higher than the overlap distance ratios of the first effective capacitor 2310, the second effective capacitor 2316, and the third effective capacitor 2318. In some embodiments, the thickness of the dielectric layer 2306 may be equal to or less than one-fiftieth (e.g., 1 / 50) of the distance between the surface of the dielectric layer 2306 and an object that is capacitively coupled to the device 2300 and is not part of the device 2300. For example, the object may be the nearest object in the surrounding environment of the device 2300. In this case, the capacitance of both the first capacitor 2312 and the second capacitor 2314 can exceed the capacitance of the first effective capacitor 2310, the second effective capacitor 2316, and the third effective capacitor 2318 because the terminal-to-terminal distance of both the first capacitor 2312 and the second capacitor 2314 is much smaller than (e.g., at most 1 / 50) the terminal-to-terminal distance of the first effective capacitor 2310, the second effective capacitor 2316, and the third effective capacitor 2318, which can help reduce capacitive coupling between the device 2300 and its environment.

[0233] like Fig.23 As shown, the value of the voltage difference between point 2106 and point 2108 decreases along the x direction and substantially reaches zero potential (because the second electrode 2104 is grounded), as represented by voltage curve 2320. Fig.23 Compared with the voltage curve 2204 in FIG. 21 , the voltage curve 2320 has a smooth slope without a sudden change. In this case, a concentrated electric field is not formed between the point 2106 and the point 2108, and thus field emission can be prevented.

[0234] In some embodiments, the dielectric layer may internally embed the first electrode 2102 and the second electrode 2104. As an example, Fig.24 is a diagram of an example device 2400 for rapid ramping of high voltage without causing discharge consistent with some embodiments of the present disclosure. Device 2400 may be similar to Fig.23 2300 and includes a top surface 2006, a bottom surface 2008, a first electrode 2102, a second electrode 2104, a first conductive portion 2302, a second conductive portion 2304, a first capacitor 2312, a second capacitor 2314, a first effective capacitor 2310, a second effective capacitor 2316, and a third effective capacitor 2318. In contrast to device 2300, device 2400 does not include an isolation surface 2010, a dielectric layer 2306, or a glue 2308. Instead, device 2400 includes an isolator 2402 as a single dielectric body (e.g., a ceramic body or a glass body), such as Fig.24 The dotted area is shown in .

[0235] Isolator 2402 may include surface layer 2404, which may be considered equivalent to dielectric layer 2306 in device 2300. Fig.24 As shown, the first electrode 2102 and the second electrode 2104 can be embedded inside the separator 2402. As an example, to make the separator 2402, the first electrode 2102 and the second electrode 2104 can be embedded in clay, and the clay in which the electrodes are embedded can be co-fired into a single ceramic body.

[0236] like Fig.24 As shown, the value of the voltage difference between point 2106 and point 2108 decreases along the x direction and substantially reaches zero potential (because the second electrode 2104 is grounded), represented by voltage curve 2406, which has a smooth slope without abrupt changes. Voltage curve 2406 can be similar to Fig.23 2204 in the voltage curve. In this case, no concentrated electric field is formed between the point 2106 and the point 2108, and thus field emission can be prevented.

[0237] As an example, Fig.25 is a cross-sectional view of an example wafer inspection system 2500 for rapid ramping of high voltage without causing discharge consistent with some embodiments of the present disclosure. The system 2500 may be similar to Fig. 20 System 2000, Fig.23 Device 2300 and Fig.24 The system 2500 includes the electrostatic holder 306, the wafer 304, the housing 1902, the primary electron beam 220, the shielding plate 2002, the cavity 2004, the top surface 2006, the bottom surface 2008, and the isolation surface 2010. Compared with the system 2000, the system 2500 also includes the first electrode 2102, the second electrode 2104, the first conductive portion 2302, the second conductive portion 2304, and the isolator 2502. In some embodiments, the isolator 2502 can be similar to Fig.23 In some embodiments, the isolator 2502 may be similar to Fig.24 This is accomplished by isolator 2402 in FIG. Fig.25 , the isolator 2502 is shown as a set of symbols between the first electrode 2102 and the second electrode 2104, which represents the effective capacitive coupling and resistive coupling caused by the dielectric material of the isolator 2502.

[0238] As Figure 20 to Figure 25As shown and described in association, the device and system provided in the present disclosure can prevent the formation of strong electric fields. The device and system introduce electrodes for forming a smoothly sinking electric field between them, which can avoid sudden changes in the electric field that may cause field emission. In addition, by covering the first electrode and the second electrode on the isolation surface, the capacitive coupling between the device or system and the surrounding environment can be reduced. In general, the device and system can provide rapid ramping of high voltage without causing any undesirable discharges, can reduce the possibility of wafer sticking problems, greatly improve the throughput of wafer inspection, and can reduce environmental hazards caused by undesirable discharges.

[0239] It should be noted that, in addition to using an isolator with covered electrodes, other means can be used to achieve rapid ramping of high voltage without causing discharge. For example, the isolator can be replaced with a resistive surface, where the covered electrodes can reduce the voltage difference through resistive coupling between them provided by the resistive surface. However, heat dissipation may occur in the resistive surface, which may cause deformation of the surrounding parts.

[0240] It should also be noted that Figure 20 to Figure 25 The devices and systems described in association are not limited to use for wafer grounding or wafer detection. Instead, they can be used for any system or device that includes a high voltage section and a ground section and requires a fast ramp-up or ramp-down. For example, such a system or device may include, but is not limited to, a SEM, a transmission electron microscope (TEM), or an X-ray machine.

[0241] Further embodiments may be described in the following clauses:

[0242] 1. A method for grounding a wafer, the method comprising:

[0243] receiving a first value of an electrical characteristic associated with a wafer grounded by an electrical signal;

[0244] determining a first control parameter using at least the first value; and

[0245] A characteristic of the electrical signal is controlled using the first control parameter and the first value.

[0246] 2. The method of clause 1, wherein the electrical characteristic is associated with an electrical path including the wafer and a wafer mount supporting the wafer.

[0247] 3. The method according to clause 2, further comprising:

[0248] determining a second control parameter using at least the first value based on determining that the resistance of the electrical path is greater than or equal to a predetermined threshold, wherein the second control parameter and the first control parameter have different values; and

[0249] The characteristic of the electrical signal is controlled using the second control parameter and the first value.

[0250] 4. The method of clause 3, wherein the predetermined threshold is 100,000 ohms.

[0251] 5. The method according to any of the preceding clauses, wherein determining the first control parameter comprises:

[0252] The first control parameter is determined based on a comparison of the first value and a target value of the electrical characteristic.

[0253] 6. The method according to any of the preceding clauses, wherein determining the first control parameter comprises:

[0254] determining whether a difference between the first value and the target value satisfies a threshold condition; and

[0255] The first control parameter is determined based on determining that the difference satisfies the threshold condition.

[0256] 7. A method according to any of the preceding clauses, wherein the electrical characteristic comprises at least one of impedance, resistance, capacitance, admittance, conductance or accommodation.

[0257] 8. The method of clause 7, wherein the electrical characteristic comprises one of a resistance between the die and the die mount or a capacitive reactance between the die and the die mount.

[0258] 9. The method of clause 8, wherein the threshold condition comprises the first value being less than or equal to the target value.

[0259] 10. The method according to any of the preceding clauses, wherein determining the first control parameter comprises:

[0260] determining an initial parameter using at least the first value; and

[0261] The first control parameter is determined based on at least the initial parameter, the first value, the target value, and the type of the wafer.

[0262] 11. The method of clause 10, wherein determining the first control parameter comprises:

[0263] The first control parameter is determined using a machine learning technique, wherein inputs to the machine learning technique include the initial parameter, the first value, the target value, and the type of wafer.

[0264] 12. A method according to any of the preceding clauses, wherein the characteristic of the electrical signal includes at least one of the following items: voltage, current, a curve of the voltage or the current, a frequency of the curve, a period of the curve, a phase of the curve, an amplitude of the curve, or a duration of the voltage or the current.

[0265] 13. A method according to any of the preceding clauses, wherein the curve comprises a sinusoidal shape.

[0266] 14. The method of any of the preceding clauses, wherein controlling the characteristic of the electrical signal using the first control parameter and the first value comprises:

[0267] The value of the characteristic of the electrical signal is changed using the first control parameter and the first value.

[0268] 15. The method of any preceding clause, wherein controlling the characteristic of the electrical signal comprises:

[0269] The voltage of the electrical signal is reduced.

[0270] 16. A method according to any of the preceding clauses, further comprising:

[0271] receiving a second value of the electrical characteristic after controlling the characteristic of the electrical signal using the first control parameter and the first value;

[0272] determining a third control parameter using at least the second value, wherein the third control parameter and the first control parameter have different values; and

[0273] The characteristic of the electrical signal is controlled using the third control parameter and the second value.

[0274] 17. The method of clause 16, wherein the third control parameter and the first control parameter are of different types.

[0275] 18. A system for grounding a wafer, the system comprising:

[0276] a sensor configured to generate a first value of an electrical characteristic associated with the wafer grounded by an electrical signal;

[0277] an electrical signal generator configured to generate the electrical signal; and

[0278] A controller includes circuitry for receiving the first value of the electrical characteristic, determining a first control parameter using at least the first value, and controlling the characteristic of the electrical signal using the first control parameter and the first value.

[0279] 19. The system according to clause 18, further comprising:

[0280] A ground pin is electrically connected between the electrical signal generator and the chip.

[0281] 20. The system of any of clauses 18 to 19, wherein the electrical characteristic is associated with an electrical path including the wafer, a wafer mount supporting the wafer, and the ground pin.

[0282] 21. The system of clause 20, wherein the controller comprises circuit means for:

[0283] determining a second control parameter using at least the first value based on determining that the resistance of the electrical path is greater than or equal to a predetermined threshold, wherein the second control parameter and the first control parameter have different values; and

[0284] The characteristic of the electrical signal is controlled using the second control parameter and the first value.

[0285] 22. The system of clause 21, wherein the predetermined threshold is 100,000 ohms.

[0286] 23. The system of any of clauses 18 to 22, wherein determining the first control parameter comprises:

[0287] The first control parameter is determined based on a comparison of the first value and a target value of the electrical characteristic.

[0288] 24. The system of any of clauses 18 to 23, wherein determining the first control parameter comprises:

[0289] determining whether a difference between the first value and the target value satisfies a threshold condition; and

[0290] The first control parameter is determined based on determining that the difference satisfies the threshold condition.

[0291] 25. The system of any of clauses 18 to 24, wherein the electrical characteristic comprises at least one of impedance, resistance, capacitance, admittance, conductance or accommodation.

[0292] 26. The system of clause 25, wherein the electrical characteristic comprises one of a resistance between the wafer and the wafer mount or a capacitive reactance between the wafer and the wafer mount.

[0293] 27. The system of clause 26, wherein the threshold condition comprises the first value being less than or equal to the target value.

[0294] 28. The system of any of clauses 18 to 27, wherein determining the first control parameter comprises:

[0295] determining an initial parameter using at least the first value; and

[0296] The first control parameter is determined based on at least the initial parameter, the first value, the target value, and the type of the wafer.

[0297] 29. The system of clause 28, wherein determining the first control parameter comprises:

[0298] The first control parameter is determined using a machine learning technique, wherein inputs to the machine learning technique include the initial parameter, the first value, the target value, and the type of wafer.

[0299] 30. A system according to any one of clauses 18 to 29, wherein the characteristic of the electrical signal comprises at least one of: a voltage, a current, a curve of the voltage or the current, a frequency of the curve, a period of the curve, a phase of the curve, an amplitude of the curve, or a duration of the voltage or the current.

[0300] 31. A system according to any of clauses 18 to 30, wherein the curve comprises a sinusoidal shape.

[0301] 32. The system of any of clauses 18 to 31, wherein controlling the characteristic of the electrical signal comprises:

[0302] The voltage of the electrical signal is reduced.

[0303] 33. A system according to any one of clauses 18 to 32, wherein the controller comprises circuit means for:

[0304] receiving a second value of the electrical characteristic from the sensor after controlling the characteristic of the electrical signal using the first control parameter and the first value;

[0305] determining a third control parameter using at least the second value, wherein the third control parameter and the first control parameter have different values; and

[0306] The characteristic of the electrical signal is controlled using the second control parameter and the second value.

[0307] 34. The system of clause 33, wherein the third control parameter and the first control parameter are of different types.

[0308] 35. A method for adjusting a grounding position of a wafer, the method comprising:

[0309] terminating an electrical connection between the wafer and a ground pin contacting the wafer;

[0310] adjusting the relative position between the chip and the ground pin; and

[0311] The electrical connection between the ground pin and the die is restored.

[0312] 36. The method of clause 35, wherein terminating the electrical connection between the die and the ground pin comprises:

[0313] lifting the wafer from the wafer mount supporting the wafer using a lifter that contacts a bottom surface of the wafer and is secured to a bottom portion of the wafer mount,

[0314] Wherein the ground pins are fixed to the top portion of the wafer mount, and when the wafer rests on the top portion, the ground pins contact the bottom surface of the wafer.

[0315] 37. The method of clause 36, wherein restoring the electrical connection between the ground pin and the die comprises:

[0316] The wafer is lowered onto the top portion of the wafer mount using the lifter.

[0317] 38. The method of clause 35, wherein terminating the electrical connection between the die and the ground pin comprises:

[0318] The ground pin is lowered from a bottom surface of the wafer resting on a wafer mount, wherein the ground pin is vertically movable in the wafer mount.

[0319] 39. The method of clause 38, wherein restoring the electrical connection between the ground pin and the die comprises:

[0320] The ground pins are lifted to contact the bottom surface of the wafer.

[0321] 40. The method of clause 35, wherein terminating the electrical connection between the die and the ground pin comprises:

[0322] A top portion of a wafer mount supporting the wafer is lowered, wherein the grounding pin is fixed to the top portion of the wafer mount, a bottom surface of the wafer contacts an immovable support fixed to the bottom portion of the wafer mount, and the grounding pin contacts the bottom surface of the wafer when the top portion is not lowered.

[0323] 41. The method of clause 40, wherein restoring the electrical connection between the ground pin and the die comprises:

[0324] The top portion of the wafer mount is raised.

[0325] 42. The method of clause 35, wherein terminating the electrical connection between the die and the ground pin comprises:

[0326] The wafer is removed from the wafer mount to a platform, wherein the ground pins are secured to the wafer mount and contact the wafer while the wafer rests on the wafer mount.

[0327] 43. The method of clause 42, wherein restoring the electrical connection between the ground pin and the die comprises:

[0328] The wafer is moved from the platform to the wafer mount.

[0329] 44. A method according to any one of clauses 35 to 43, wherein before terminating the electrical connection between the chip and the ground pin, the ground pin contacts the bottom surface of the chip with a pressure different from the pressure between the ground pin and the bottom surface.

[0330] 45. A method according to any of clauses 35 to 44, wherein the ground pins contact the bottom surface of the wafer at the same relative position.

[0331] 46. ​​The method of any of clauses 35 to 45, wherein adjusting the relative position between the wafer and the ground pin comprises:

[0332] The relative azimuth angle between the ground pin and the chip is adjusted to a predetermined angle.

[0333] 47. The method of clause 46, wherein the predetermined angle is a difference between a current relative azimuth angle between the wafer and the ground pin and a target relative azimuth angle between the wafer and the ground pin.

[0334] 48. The method of any one of clauses 46 to 47, wherein adjusting the relative azimuth angle comprises:

[0335] The top portion of the wafer mount is rotated relative to the bottom portion of the wafer mount by the predetermined angle.

[0336] 49. The method of any of clauses 46 to 47, wherein adjusting the relative azimuth angle comprises:

[0337] The ground pin is rotated relative to the wafer mount by the predetermined angle, wherein the ground pin is rotatably movable relative to the wafer mount.

[0338] 50. The method of any of clauses 46 to 47, wherein adjusting the relative azimuth angle comprises:

[0339] The platform is caused to rotate the wafer by the predetermined angle.

[0340] 51. The method of any one of clauses 35 to 45, wherein adjusting the relative position between the wafer and the ground pin comprises:

[0341] The relative translation distance between the wafer and the ground pin is adjusted by a predetermined distance.

[0342] 52. The method according to any one of clauses 35 to 51, further comprising:

[0343] determining whether an electrical path for grounding the wafer is formed;

[0344] Based on determining that the electrical path is not formed, the electrical connection between the die and the ground pin is terminated.

[0345] 53. A system for adjusting a grounding position of a wafer, the system comprising:

[0346] a ground pin configured to contact the wafer; and

[0347] An actuator is configured to terminate the electrical connection between the wafer and the ground pin, adjust the relative position between the wafer and the ground pin, and restore the electrical connection between the ground pin and the wafer.

[0348] 54. The system according to clause 53, further comprising:

[0349] A wafer mount includes a bottom portion and a top portion, wherein the top portion is configured to support the wafer and fix the ground pin, the actuator is further configured to move the top portion, and when the wafer rests on the top portion, the ground pin contacts the bottom surface of the wafer.

[0350] 55. The system of clause 54, wherein the actuator comprises a lifter in contact with the bottom surface and secured to the bottom portion,

[0351] The ground pin is fixed to the top portion, and

[0352] The lifter is configured to lift the wafer off the top portion.

[0353] 56. The system of clause 55, wherein the elevator is configured to lower the wafer onto the top portion.

[0354] 57. The system of clause 55, wherein the actuator further comprises a non-movable support in contact with the bottom surface and secured to the bottom portion, and the lifter is configured to lower the top portion.

[0355] 58. The system of clause 57, wherein the lifter is configured to raise the top portion.

[0356] 59. The system of clause 54, wherein the ground pin is vertically movable in the wafer mount,

[0357] the bottom surface rests on the top portion, and

[0358] The actuator configured to separate the wafer and the ground pin is also configured to lower the ground pin from the bottom surface.

[0359] 60. The system of clause 59, wherein the actuator configured to separate the die and the ground pin is further configured to:

[0360] The ground pin is lifted to contact the bottom surface.

[0361] 61. The system according to clause 54, further comprising:

[0362] a platform configured to rotate the wafer; and

[0363] The actuator configured to separate the wafer and the ground pin is also configured to remove the wafer from the wafer mount to the platform.

[0364] 62. The system of clause 61, wherein the actuator configured to reattach the ground pin and the wafer is further configured to move the wafer from the platform to the wafer mount.

[0365] 63. A system according to any of clauses 53 to 62, wherein before terminating the electrical connection between the wafer and the ground pin, the ground pin contacts the bottom surface with a pressure different from the pressure between the ground pin and the bottom surface.

[0366] 64. A system according to any of clauses 53 to 63, wherein the ground pins contact the bottom surface at the same relative position.

[0367] 65. The system of any of clauses 54 to 64, wherein the actuator configured to adjust the relative position between the wafer and the ground pin is further configured to:

[0368] The relative azimuth angle between the ground pin and the chip is adjusted to a predetermined angle.

[0369] 66. The system of clause 65, wherein the predetermined angle is a difference between a current relative azimuth angle between the wafer and the ground pin and a target relative azimuth angle between the wafer and the ground pin.

[0370] 67. A system according to any of clauses 65 to 66, wherein the actuator configured to adjust the relative azimuth angle is also configured to rotate the top portion relative to the bottom portion by the predetermined angle.

[0371] 68. A system according to any of clauses 65 to 66, wherein the ground pin is rotationally movable relative to the top portion, and

[0372] The actuator configured to adjust the relative azimuth angle is further configured to rotate the ground pin by the predetermined angle relative to the top portion.

[0373] 69. The system of any one of clauses 65 to 66, wherein the platform is further configured to rotate the wafer by the predetermined angle.

[0374] 70. The system of any of clauses 53 to 69, wherein the actuator configured to adjust the relative position between the wafer and the ground pin is further configured to:

[0375] The relative translation distance between the wafer and the ground pin is adjusted by a predetermined distance.

[0376] 71. The system of any one of clauses 53 to 70, wherein the actuator is further configured to:

[0377] Based on determining that an electrical path for grounding the die is not formed, the electrical connection between the die and the ground pin is terminated.

[0378] 72. A method of grounding a wafer, the method comprising:

[0379] establishing a set of contact points between a plurality of probes and the wafer;

[0380] applying a first set of electrical signals to the set of contact points via the plurality of probes to facilitate breakdown of a coating of the wafer; and

[0381] Based on determining that the resistance of the electrical paths between the plurality of probes through the wafer is greater than or equal to a predetermined threshold, applying a second set of electrical signals to the set of contact points through the plurality of probes, wherein the second set of electrical signals is determined based on a value of an electrical characteristic associated with the wafer when the first set of electrical signals is applied.

[0382] 73. The method of clause 72, wherein the probe comprises a ground pin.

[0383] 74. A method according to any one of clauses 72 to 73, wherein the first set of electrical signals comprises a set of voltage pulses.

[0384] 75. A method according to any of clauses 72 to 74, wherein the breakdown comprises dielectric breakdown.

[0385] 76. A method according to any of clauses 72 to 75, wherein the predetermined threshold is 100,000 Ohms.

[0386] 77. A method of grounding a wafer, the method comprising:

[0387] establishing a first set of contact points between a plurality of probes and the wafer;

[0388] applying a first set of electrical signals to the first set of contact points via the plurality of probes to facilitate breakdown of a coating of the wafer;

[0389] When the resistance of the electrical paths between the plurality of probes through the wafer is greater than or equal to a predetermined threshold, establishing a second set of contact points between the plurality of probes and the wafer; and

[0390] A second set of electrical signals is applied to the second set of contact points via the plurality of probes, wherein the second set of electrical signals is determined based on a value of an electrical characteristic associated with the wafer when the first set of electrical signals is applied.

[0391] 78. The method of clause 77, wherein the probe comprises a ground pin.

[0392] 79. A method according to any one of clauses 77 to 78, wherein the first set of electrical signals comprises a set of voltage pulses.

[0393] 80. A method according to any of clauses 77 to 79, wherein the breakdown comprises dielectric breakdown.

[0394] 81. A method according to any of clauses 77 to 80, wherein the predetermined threshold is 100,000 Ohms.

[0395] 82. A method of grounding a wafer, the method comprising:

[0396] causing a ground pin to contact the wafer;

[0397] vibrating at least one of the ground pin or the wafer; and

[0398] An electrical connection is established between the ground pin and the die.

[0399] 83. The method of clause 82, wherein vibrating at least one of the ground pin or the wafer comprises:

[0400] A vibrator is vibrated, the vibrator being coupled to the ground pin and a top portion of a wafer mount supporting the wafer.

[0401] 84. The method of clause 83, wherein the vibrator is the top portion.

[0402] 85. The method of any of clauses 82 to 84, wherein vibrating at least one of the ground pin or the wafer comprises:

[0403] A wafer holder is vibrated, the wafer holder securing the wafer to a wafer mount supporting the wafer.

[0404] 86. The method of any of clauses 82 to 85, wherein vibrating at least one of the ground pin or the wafer comprises:

[0405] At least one of the ground pin or the wafer is vibrated in at least one of a direction perpendicular to a surface of the wafer or a direction parallel to the surface.

[0406] 87. The method of any of clauses 82 to 86, wherein establishing the electrical connection between the ground pins or the die comprises:

[0407] The ground pins are pressed against the surface of the wafer through the coating on the surface to make direct contact with the wafer.

[0408] 88. The method of any of clauses 82 to 87, wherein establishing the electrical connection between the ground pins or the die comprises:

[0409] The ground pin is pressed against the surface of the wafer through the coating of the surface, wherein the ground pin does not fully penetrate the coating.

[0410] 89. A system comprising:

[0411] a ground pin configured to contact the wafer; and

[0412] A controller having a circuit arrangement for:

[0413] vibrating at least one of the ground pin or the wafer; and

[0414] An electrical connection is established between the ground pin and the die.

[0415] 90. The system according to clause 89, further comprising:

[0416] A vibrator, coupled to the ground pin and a top portion of a wafer mount supporting the wafer, is configured to vibrate at least one of the ground pin or the wafer.

[0417] 91. The system of clause 90, wherein the vibrator is the top portion.

[0418] 92. The system of any of clauses 89 to 91, wherein vibrating at least one of the ground pin or the wafer comprises:

[0419] A wafer holder is vibrated, the wafer holder securing the wafer to a wafer mount supporting the wafer.

[0420] 93. The system of any of clauses 89 to 92, wherein vibrating at least one of the ground pin or the wafer comprises:

[0421] At least one of the ground pin or the wafer is vibrated in at least one of a direction perpendicular to a surface of the wafer or a direction parallel to the surface.

[0422] 94. The system of any of clauses 89 to 93, wherein establishing the electrical connection between the ground pins or the die comprises:

[0423] The ground pins are pressed against the surface of the wafer through the coating on the surface to make direct contact with the wafer.

[0424] 95. The system of any of clauses 89 to 94, wherein establishing the electrical connection between the ground pins or the die comprises:

[0425] The ground pin is pressed against the surface of the wafer through the coating of the surface, wherein the ground pin does not fully penetrate the coating.

[0426] 96. A method of grounding a wafer, the method comprising:

[0427] causing the ground pin to penetrate the coating on the wafer by impact; and

[0428] An electrical connection is established between the ground pin and the die.

[0429] 97. A method according to clause 96, wherein the coating has a thickness greater than 0.3 microns.

[0430] 98. The method of clause 96 or 97, wherein causing the ground pin to penetrate the coating on the wafer by the striking comprises:

[0431] The ground pin is caused to penetrate the coating by the impact to come into direct contact with the wafer.

[0432] 99. The method of clause 96 or 97, wherein causing the ground pin to penetrate the coating on the wafer by the striking comprises:

[0433] The ground pin is caused to penetrate the coating by the impact, wherein the ground pin does not completely penetrate the coating.

[0434] 100. The method of clause 99, wherein the distance between the tip of the ground pin and the surface of the wafer after the ground pin penetrates the coating by impact is less than or equal to 0.3 microns.

[0435] 101. The method of any of clauses 96-100, wherein causing the ground pin to penetrate the coating on the wafer by impact comprises:

[0436] The ground pin is actuated toward the wafer.

[0437] 102. The method of clause 101, wherein actuating the ground pin toward the wafer comprises:

[0438] moving the ground pin a distance away from the wafer; and

[0439] The ground pin is accelerated toward the wafer.

[0440] 103. A method according to clause 101 or 102, wherein

[0441] Actuating the ground pin toward the wafer is configured to cause a kinetic energy of the ground pin to exceed 0.0002 joules.

[0442] 104. A method according to clause 102 or 103, wherein the distance exceeds 100 microns or 1 mm.

[0443] 105. A method according to any of clauses 102-104, further comprising:

[0444] The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

[0445] 106. A method according to any of clauses 102-104, further comprising:

[0446] The ground pin is caused to contact the wafer before the ground pin is removed from the wafer.

[0447] 107. The method of any of clauses 96-106, wherein causing the ground pin to penetrate the coating on the wafer by impact comprises:

[0448] A mass is caused to strike the ground pin toward the wafer.

[0449] 108. The method of clause 107, wherein causing the proof mass to strike the ground pin toward the wafer comprises:

[0450] The mass is actuated toward the ground pin.

[0451] 109. The method of clause 108, wherein actuating the mass toward the ground pin comprises:

[0452] moving the mass away from the ground pin; and

[0453] The mass is accelerated toward the ground pin.

[0454] 110. The method of clause 108 or 109, wherein actuating the mass toward the ground pin is configured to cause a kinetic energy of the mass to exceed 0.0002 Joules.

[0455] 111. A method according to clause 109 or 110, wherein the distance exceeds 100 microns or 1 mm.

[0456] 112. A method according to any of clauses 109-111, further comprising:

[0457] The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

[0458] 113. A method according to any of clauses 109-112, further comprising:

[0459] Prior to moving the proof mass away from the ground pin, the proof mass is caused to contact the ground pin.

[0460] 114. A method according to any of clauses 109-112, further comprising:

[0461] Prior to moving the proof mass away from the ground pin, the ground pin is caused to contact the wafer.

[0462] 115. A system comprising:

[0463] a ground pin; and

[0464] A controller having a circuit arrangement for:

[0465] Controlling the ground pin to penetrate the coating on the wafer by impact; and

[0466] An electrical connection is established between the ground pin and the die.

[0467] 116. The system according to clause 115, further comprising:

[0468] An actuator is coupled to a wafer stage supporting the wafer.

[0469] 117. The system of clause 116, wherein the actuator comprises one of an electric actuator, a magnetic actuator, an electromagnetic actuator, a spring, a pneumatic actuator, or a hydraulic actuator.

[0470] 118. The system of any of clauses 116-117, wherein the actuator is configured to actuate the ground pin.

[0471] 119. A system according to clause 115, wherein the coating has a thickness greater than 0.3 microns.

[0472] 120. The system of clause 115 or 119, wherein the controller having circuit means for causing the ground pin to penetrate the coating on the wafer by impact comprises:

[0473] A circuit arrangement for causing the ground pin to penetrate the coating by the striking, wherein the ground pin is in direct contact with the wafer or the ground pin does not fully penetrate the coating.

[0474] 121. The system of clause 120, wherein the distance between the tip of the ground pin and the surface of the wafer after the ground pin penetrates the coating by impact is less than or equal to 0.3 microns.

[0475] 122. The system of any of clauses 115-121, wherein the controller having circuit means for controlling the ground pin to penetrate the coating on the wafer by impact comprises:

[0476] Circuit means for actuating the ground pin toward the wafer.

[0477] 123. The system of clause 122, wherein the controller having circuitry for actuating the ground pin toward the wafer comprises circuitry for:

[0478] moving the ground pin a distance away from the wafer; and

[0479] The ground pin is accelerated toward the wafer.

[0480] 124. A system according to clause 122 or 123, wherein the circuit device for actuating the ground pin toward the wafer is configured to cause a kinetic energy of the ground pin to exceed 0.0002 joules.

[0481] 125. A system according to clause 123 or 124, wherein the distance exceeds 100 microns or 1 mm.

[0482] 126. A system according to any of clauses 123-125, wherein the controller having the circuit arrangement is further configured to:

[0483] The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

[0484] 127. A system according to any of clauses 123-126, wherein the controller having the circuit arrangement is further configured to:

[0485] The ground pin is controlled to contact the wafer before the ground pin is moved away from the wafer.

[0486] 128. A system according to any of clauses 115-127, further comprising:

[0487] A mass, wherein the actuator is configured to actuate the mass.

[0488] 129. The system of clause 128, wherein the controller having circuit means for controlling the ground pin to penetrate the coating on the wafer by impact comprises:

[0489] Circuit means for actuating the proof mass to strike the ground pin toward the wafer.

[0490] 130. The system of clause 129, wherein the controller having circuit means for actuating the proof mass to strike the ground pin toward the wafer comprises:

[0491] Circuit means for actuating the proof mass toward the ground pin.

[0492] 131. The system of clause 130, wherein the controller having circuit means for actuating the mass toward the ground pin comprises circuit means for:

[0493] moving the mass away from the ground pin; and

[0494] The mass is accelerated toward the ground pin.

[0495] 132. The system of clause 130 or 131, wherein the circuit means for actuating the mass toward the ground pin to cause a kinetic energy of the mass to exceed 0.0002 joules.

[0496] 133. A system according to clause 131 or 132, wherein the distance exceeds 100 microns or 1 mm.

[0497] 134. A system according to any of clauses 131-133, wherein the controller having the circuit arrangement is further configured to:

[0498] The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

[0499] 135. A system according to any of clauses 131-134, wherein the controller having the circuit arrangement is further configured to:

[0500] Before the mass is moved away from the ground pin, the mass is controlled to contact the ground pin.

[0501] 136. A system according to any of clauses 131-134, wherein the controller having the circuit arrangement is further configured to:

[0502] The ground pin is controlled to contact the wafer before the proof mass is moved away from the ground pin.

[0503] 137. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method comprising:

[0504] causing the ground pin to penetrate the coating on the wafer by impact; and

[0505] An electrical connection is established between the ground pin and the die.

[0506] 138. A system for grounding a wafer, comprising:

[0507] a first ground pin;

[0508] an electrostatic holder, comprising a first electrode located inside the electrostatic holder; and

[0509] A first overvoltage protection device is electrically coupled between the first ground pin and the first electrode, wherein the first overvoltage protection device is configured to:

[0510] conducting power when a first voltage applied to the first overvoltage protection device exceeds a threshold voltage; and

[0511] When the first voltage does not exceed the threshold voltage, conducting power is stopped.

[0512] 139. The system of clause 138, wherein the first overvoltage protection device is configured to allow conduction of the electrical power in multiple directions.

[0513] 140. The system of any of clauses 138-139, wherein the threshold voltage is an electrical characteristic of the first overvoltage protection device.

[0514] 141. The system of any of clauses 138-140, wherein the threshold voltage is adjustable.

[0515] 142. The system of any of clauses 138-141, wherein the first overvoltage protection device comprises at least one of a transient voltage suppression (TVS) diode, a Zener diode, a varistor, or a silicon diode for alternating current (SIDAC).

[0516] 143. A system according to any of clauses 138-142, further comprising:

[0517] A shell includes a concave surface configured to surround the electrostatic retainer and the first ground pin, and at least one of a first interface on the concave surface and a second interface on the concave surface, wherein the first interface is configured to cooperate with the wiring of the first electrode and the second interface is configured to cooperate with the wiring of the first ground pin.

[0518] 144. A system according to clause 143, wherein the first overvoltage protection device is inside the housing.

[0519] 145. A system as described in clause 143, wherein the first overvoltage protection device is external to the housing.

[0520] 146. A system according to any of clauses 138-145, wherein the electrostatic holder includes a second electrode within the electrostatic holder.

[0521] 147. The system according to clause 146, further comprising:

[0522] A second overvoltage protection device is electrically coupled between the first ground pin and the second electrode, wherein the second overvoltage protection device is configured to:

[0523] conducting power when a second voltage applied to the second overvoltage protection device exceeds the threshold voltage; and

[0524] When the second voltage does not exceed the threshold voltage, conducting power is stopped.

[0525] 148. A system according to any of clauses 138-147, further comprising:

[0526] a second ground pin;

[0527] A third overvoltage protection device is electrically coupled between the second ground pin and the first electrode, wherein the third overvoltage protection device is configured as:

[0528] conducting power when a third voltage applied to the third overvoltage protection device exceeds the threshold voltage; and

[0529] When the third voltage does not exceed the threshold voltage, conducting power is stopped.

[0530] 149. An apparatus for rapid ramping of high voltage, comprising:

[0531] an isolator disposed between a high voltage portion of the device and a grounded portion of the device;

[0532] a first electrode electrically coupled to the high voltage portion;

[0533] a second electrode electrically coupled to the ground portion and in electrical non-conductivity with the first electrode; and

[0534] A dielectric layer covers the first electrode and the second electrode on the separator.

[0535] 150. The apparatus of clause 149, wherein the dielectric layer is adhered to a surface of the isolator, and the first electrode and the second electrode are covered between the dielectric layer and the surface of the isolator.

[0536] 151. The apparatus of clause 149, wherein the isolator comprises the dielectric layer, and the first electrode and the second electrode are embedded within the isolator.

[0537] 152. The apparatus of any of clauses 149-151, further comprising:

[0538] a first conductive portion electrically coupled to the high voltage portion of the device and capacitively coupled to the first electrode; and

[0539] A second conductive portion is electrically coupled to the ground portion of the device and capacitively coupled to the second electrode.

[0540] 153. An apparatus according to clause 152, wherein the thickness of the dielectric layer is equal to or less than one-tenth of the smaller overlap area of ​​a first overlap area between the first conductive portion and the first electrode and a second overlap area between the second conductive portion and the second electrode.

[0541] 154. A device according to any of clauses 149-153, wherein the thickness of the dielectric layer is equal to or less than one-fiftieth of the distance between a surface of the dielectric layer and an object that is capacitively coupled to the device and is not part of the device.

[0542] 155. A device according to any of clauses 149-154, wherein the material of the dielectric layer has a dielectric constant greater than or equal to 3×10 -11 The dielectric constant in farads per meter.

[0543] 156. An apparatus according to clause 155, wherein the material comprises glass or ceramic.

[0544] 157. An apparatus as described in any of clauses 149-156, wherein the high voltage portion includes a first surface, the grounded portion includes a second surface parallel to the first surface, and the isolator includes a surface perpendicular to the first surface and the second surface.

[0545] 158. The apparatus of any of clauses 149-157, further comprising:

[0546] A housing is configured to enclose a platform supporting a wafer, wherein the high voltage portion comprises a top surface of the housing, the ground portion comprises a bottom surface of the housing, and the isolator comprises a wall of the housing.

[0547] A non-transitory computer-readable medium may be provided that stores a processor (eg, Figure 1The processor of the controller 109 of the embodiment of the present invention executes instructions for the following: image processing, data processing, database management, graphic display, operation of charged particle beam equipment or other imaging devices, control chip grounding, control chip grounding position adjustment, implement pin impact method, etc. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with hole patterns, RAM, PROM and EPROM, FLASH-EPROM or any other flash memory, NVRAM, cache, registers, any other memory chip or cartridge memory, and network versions of the above.

[0548] The block diagram in the figure shows the possible architecture, function and operation of the system, method and computer hardware or software product according to various example embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a code module, segment or part, which includes one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the function indicated in the box may not appear in the order indicated in the figure. For example, the two boxes shown in succession can be performed or implemented substantially at the same time, or the two boxes can sometimes be performed in reverse order, depending on the functions involved. Some boxes can also be omitted. It should also be understood that each box of the block diagram and the combination of boxes can be implemented by a system based on special-purpose hardware that performs a specified function or action, or by a combination of special-purpose hardware and computer instructions.

[0549] It should be understood that the embodiments of the present disclosure are not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A system for wafer grounding, comprising: Ground pin; as well as A controller having a circuit arrangement for: Controlling the ground pin to penetrate the coating on the wafer by impact; establishing an electrical connection between the ground pin and the wafer; as well as an actuator coupled to a wafer stage supporting the wafer, wherein the actuator is configured to actuate the ground pin The controller having a circuit device for controlling the ground pin to penetrate the coating on the wafer by impact includes: circuit means for actuating the ground pin towards the wafer, and wherein the controller having the circuit means for actuating the ground pin towards the wafer comprises circuit means for: moving the ground pin a distance away from the wafer; and The ground pin is accelerated toward the wafer.

2. The system of claim 1, wherein the controller having circuit means for causing the ground pin to penetrate the coating on the wafer by the striking comprises: A circuit arrangement for causing the ground pin to penetrate the coating by the striking, wherein the ground pin is in direct contact with the wafer or the ground pin does not fully penetrate the coating.

3. The system of claim 1 , wherein the controller having the circuit arrangement is further configured to: The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

4. The system of claim 1, wherein the controller having the circuit arrangement is further configured to: The ground pin is controlled to contact the wafer before the ground pin is moved away from the wafer.

5. The system according to claim 1, further comprising: A mass, wherein the actuator is configured to actuate the mass.

6. The system of claim 5, wherein the controller having circuit means for controlling the ground pin to penetrate the coating on the wafer by striking comprises: Circuit means for actuating the proof mass to strike the ground pin toward the wafer.

7. The system of claim 6, wherein the controller having circuit means for actuating the proof mass to strike the ground pin toward the wafer comprises: Circuit means for actuating the proof mass toward the ground pin.

8. The system of claim 7, wherein the controller having circuit means for actuating the mass toward the ground pin comprises circuit means for: moving the mass away from the ground pin; and The mass is accelerated toward the ground pin.

9. The system of claim 8, wherein the controller having the circuit arrangement is further configured to: The distance is determined based on at least one of a type of the wafer, a type of coating of the wafer, or a thickness of the coating.

10. The system of claim 8, wherein the controller having the circuit arrangement is further configured to: Before the mass is moved away from the ground pin, the mass is controlled to contact the ground pin.

11. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method comprising: The ground pin is moved away from the wafer by an actuator of the device, accelerating the ground pin toward the wafer via the actuator to penetrate a coating on the wafer; as well as An electrical connection is established between the ground pin and the die.

Images