Small-area and multiple-column redundancy replacement method for Norflash

Abstract

The application discloses a small-area and multiple-column redundancy replacement method for Norflash, and belongs to the technical field of semiconductor storage. A replacement address is first processed by two-stage selector grading splitting, then whether the address of the second selector is replaced twice is judged at the error position of the main storage area. Considering that the two-time error will probably become a bad area after being unified, if the address is the same, the replacement is skipped, then whether the one-to-one allocated redundancy area is available is judged, if the redundancy area is not available, other redundancy resources are called to replace the redundancy area, if an error is detected in the redundancy area, the record information can be transferred to other latches, and multiple opportunities are provided. The small-area and multiple-column redundancy replacement method can improve the device yield and the consistency of chip performance on the basis of small cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor storage, and particularly relates to a small-area and multiple-column-redundancy replacement method for Nor flash. BACKGROUND

[0002] With the increasingly shrinking of semiconductor chip manufacturing processes, the characteristics of storage units in non-volatile memory chips are more and more difficult to control, and defects are more likely to be introduced in the chip manufacturing process to cause the characteristics of the storage units to be poor. Although only a small number of storage units have poor characteristics, in order to ensure the reliability and durability of the memory chip, as long as a storage unit with a risk of write performance or reliability is found in the wafer test and packaging test process, the chip is screened out, but this results in a loss of test yield and increases the cost of the chip.

[0003] In order to reduce the proportion of screening out the entire chip due to the poor write performance or reliability of a small number of storage units (improve the yield of chip testing and reduce the cost of the chip), column redundancy replacement is the main solution of the current mainstream non-volatile memory manufacturers. The main storage area with poor write performance or reliability of the storage unit is replaced by column redundancy, so as to improve the yield, but the circuit design of column redundancy replacement also increases the area of the chip. If the circuit design of column redundancy replacement is unreasonable, it will increase the chip area too much. Even if the yield of the non-volatile memory chip is improved through column redundancy replacement, if the proportion of yield improvement is lower than the proportion of chip area increase due to the addition of column redundancy replacement circuit design, the cost of non-volatile memory chip will be further increased. Therefore, it is necessary to reduce the area of column redundancy replacement circuit, which is very valuable to reduce the cost of non-volatile memory chip.

[0004] In order to save the performance of part of the storage units (cells) caused by defects in the chip manufacturing process, and the cells that are difficult to erase or program in the chip, redundancy replacement is usually added in the design to improve the yield of the device and the consistency of the chip performance.

[0005] And the redundancy replacement mainly includes row redundancy and column redundancy. Since the probability of error of word line (WL) of Nor flash is almost 0, and row redundancy is usually replaced at the sector level, the area required for deploying row redundancy replacement is large. Therefore, for Nor flash devices, redundancy replacement mainly uses column redundancy.

[0006] In the prior art, column redundancy replacement is mainly one-to-one corresponding forced allocation, which is divided into only replacing the error column according to the size of redundancy replacement, and first dividing a cell, and if an error occurs in a column in the cell, redundancy replacement is performed on the cell. The former can avoid waste, and the latter considers that the probability of error in the column next to the error column will increase, which can save time to some extent. However, this scheme needs to reserve about 2% of the area of the chip to ensure the coverage rate of redundancy replacement, that is, about every array column. Therefore, the disadvantages of this scheme are that a large area is needed to record the error address, and the flexibility is not enough, that is, each column has only one opportunity to be replaced by redundancy after an error occurs.

[0007] Therefore, it is desirable to provide a method with small area and ensuring redundancy replacement coverage. SUMMARY

[0008] In order to solve the technical problem that in the prior art, column redundancy replacement is mainly one-to-one corresponding forced allocation, which is divided into only replacing the error column according to the size of redundancy replacement, and first dividing a cell, and if an error occurs in a column in the cell, redundancy replacement is performed on the cell. The former can avoid waste, and the latter considers that the probability of error in the column next to the error column will increase, which can save time to some extent. However, this scheme needs to reserve about 2% of the area of the chip to ensure the coverage rate of redundancy replacement, that is, about every array column. Therefore, the disadvantages of this scheme are that a large area is needed to record the error address, and the flexibility is not enough, that is, each column has only one opportunity to be replaced by redundancy after an error occurs, the present application provides a small-area and multiple-column redundancy replacement method for Norflash.

[0009] A small-area and multiple-column redundancy replacement method for Norflash, the specific steps are as follows,

[0010] S1, selecting a storage unit by level;

[0011] S2, performing multiple column redundancy replacement on the error address after level selection.

[0012] Further, the level selection is specifically:

[0013] S1-1, differentiating the addresses of the bit lines of the main area and the redundancy area through YMUX1 and YMUX2 respectively to obtain SA_main sensitive amplifiers of the main area and SA_redun sensitive amplifiers of the redundancy area;

[0014] S1-2, recording the addresses of YMUX2_main and SA_main.

[0015] Further wherein YMUX2_redun / YMUX2_main =1:2.

[0016] Further: the multiple column redundancy replacement is:

[0017] S2-1, first record 2bit information for each YMUX2_redun, namely 1bit flag information of good and bad of redundancy and 1bit flag information of whether Latch replacement is used;

[0018] S2-2, the main area is an error area, and whether YMUX2 in the error address is repeated with the previous YMUX2 is judged, if repeated, the next address data is checked;

[0019] S2-3, if not the same, whether the Latch corresponding to the redundancy area of the main area is available is judged, if available, direct replacement is performed;

[0020] S2-4, if not available, traversal selection is performed from 1-YMUX2 in the redundancy area, if available, direct replacement is performed, if all Latch replacement resources of the redundancy area are used, traversal selection is performed from 1-YMUX2 again, if still error, the area is marked as a bad area.

[0021] Further: the S2-3, after replacement, the redundancy area is error, the redundancy error is recorded first, then whether the Latch corresponding to the redundancy is used is judged, if used, the recorded information is transferred to other Latch, if not used, the checking is returned.

[0022] Further: the YMUX1 and YMUX2 are both eight-to-one selectors.

[0023] The application has the advantages that:

[0024] The application can realize multiple opportunity redundancy replacement through two paths, and has smaller area, and the scheme is also applicable to nand flash, thereby providing a good redundancy replacement scheme for the whole non-volatile memory device, and greatly improving the device yield and the consistency of chip performance.

[0025] The application solves the problem of large area required for recording error addresses, records information resources about 8% of the prior art, and changes YMUX2_redun / YMUX2_main from 1:1 to 1:2 to further save area.

[0026] This invention first performs hierarchical splitting of the replacement address using a two-level selector. Then, for errors in the main memory area, it checks whether the address of the second selector has been replaced twice. Considering that two errors would likely result in a bad area, if they are the same, it skips the process. Next, it checks whether the allocated redundant areas are available. If they are unavailable, it calls other redundant resources to replace them. If an error is detected in the redundant area, the recorded information can be transferred to other latches, and there are multiple opportunities. In summary, this invention can achieve both small area and multiple column redundancy replacements, thereby greatly improving device yield and chip performance consistency at a low cost. However, due to the excessive area consumed by recording error addresses and other information, and the poor flexibility of redundancy replacement, it is impossible to balance the contradiction between high chip yield and low cost. Attached Figure Description

[0027] Figure 1 This is a schematic diagram illustrating the hierarchical selection implementation of a small-area, multiple-column redundancy replacement method for Norflash according to the present invention.

[0028] Figure 2 This is a schematic diagram illustrating the implementation of multiple redundancy replacement in a small-area, multiple-column redundancy replacement method for Norflash according to the present invention. Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that the various installation methods and technical terms mentioned in this invention are all well-known technical terms in the relevant technical field, and therefore will not be explained further. Furthermore, the same reference numerals are used for the same components, but this does not affect, nor should it constitute, an accurate understanding of the technical solution by those skilled in the art.

[0031] Examples and combinations Figures 1-2 Explanation:

[0032] A method for small-area, multiple-column redundancy replacement in Norflash is described below, with the following specific steps.

[0033] S1, hierarchical selection is performed on the storage unit; the hierarchical selection is specifically as follows: S1-1, the bit lines of the main area and the redundancy area are respectively subjected to address difference through YMUX1 and YMUX2 to obtain main area SA_main sensitive amplifiers and redundancy area SA_redun sensitive amplifiers;

[0034] S1-2, addresses of YMUX2_main and SA_main are recorded. YMUX2_redun / YMUX2_main = 1:2. S2, after the hierarchical selection, multiple column redundancy replacement is performed on the error address, and the multiple column redundancy replacement is as follows:

[0035] S2-1, 2bit information is recorded for each YMUX2_redun, that is, 1bit flag information of flag information of whether the Latch is used for replacement and 1bit flag information of whether the redundancy is good or bad;

[0036] S2-2, the main area is an error area, and it is judged whether the YMUX2 in the error address is repeated with the previous YMUX2, if not, the next address data is checked;

[0037] S2-3, if not the same, it is judged whether the Latch corresponding to the redundancy area of the main area is available, if available, the replacement is directly performed; after the replacement of S2-3, the redundancy area is error, the error of the redundancy is recorded first, and then it is judged whether the Latch corresponding to the redundancy is used, if used, the recorded information is stored in other Latch, if not used, the checking is continued. The YMUX1 and the YMUX2 are both eight-to-one selectors.

[0038] S2-4, if not available, the traversal selection is performed from the 1-YMUX2 of the redundancy area, if available, the replacement is directly performed, if all the Latch replacement resources of the redundancy area are used, the traversal selection is performed from the 1-YMUX2 again, if still error, the area is marked as a bad area.

[0039] For the small area problem, one is to perform hierarchical selection, for example, the hierarchical selection is performed on the storage unit, and the hierarchical selection is specifically as follows: Figure 1The schematic diagram of hierarchical selection implementation is shown, that is, the bit line (Bit line, BL) of the main area and the redundancy area is obtained through two-stage selector to obtain main area SA_main sense amplifier (sense amplify, SA) and redundancy area SA_redun SA, wherein SA_redun is usually 1, at this time, SA_main in the main area performs redundancy replacement of SA_redun units, only the addresses of YMUX2_main and SA_main need to be recorded, the hierarchical recording scheme solves the problem that a large area is required to record the error address, the recording information resource is about 8% of the prior art, but the flexibility problem is not solved. Two is further based on the hierarchical basis, through Figure 2 The flowchart algorithm is shown, only 2bit information needs to be recorded for each YMUX2_redun, that is, 1bit flag information (good_flag) indicating whether the redundancy is good or bad and 1bit flag information (monitor_flag) indicating whether the Latch is replaced, to ensure one-to-one correspondence (to ensure the fastest redundancy replacement, the idea of the prior art), and multiple opportunities are increased. Compared with the prior art scheme, the scheme of the present application increases YMUX2_redun-1 opportunity for the first time redundancy replacement, increases YMUX2_redun-2 opportunity for the second time, and only when the first YMUX2_redun redundancy replacement occurs, the opportunity is consistent with the prior art scheme. If further area saving is required, YMUX2_redun / YMUX2_main can be changed from 1:1 to 1:2, which will cause the redundancy replacement opportunity to be half less than that when YMUX2_redun / YMUX2_main = 1:1. In addition, by judging whether the address under the YMUX2 in the main area appears error, it is found that this place cannot be saved, so as to avoid wasting the redundancy resource, the algorithm of the present application will discard this part, and will not record and replace it twice.

[0040] For the redundancy replacement coverage problem, the present application mainly has two ways to improve the coverage of redundancy, one is that after the redundancy replacement, the error occurs in the redundancy used for replacement, which is judged by BIST data check, and is transferred to other latches (Latch) through the selector, two is that on the basis of one-to-one correspondence, if the error bit corresponds to the Latch of the redundancy replacement, other Latch can be called through the selector to record the address and other information required for redundancy replacement.

[0041] In this embodiment, if an error occurs in the main area, such as... Figure 2 As shown in the right-hand line, the system first checks whether the redundant area corresponding to the main area is available. If it is available, it directly replaces the redundant area, which is the fastest way. If it is not available, it iterates through 1-YMUX2 to select the redundant area. This is one of the core mechanisms that increases the chances of redundant replacement in the main area. Only after all the redundant replacement resources have been used, when performing Bist data check again, if there is still an error, there is no redundant replacement action, and it will be recorded as a bad area.

[0042] In this embodiment, if an error occurs in the redundancy region, such as Figure 2 As shown on the left, if an error occurs in the redundancy area, the error is first recorded. Then, it is determined whether the latch corresponding to this redundancy is being used. If it is being used, the recorded information is transferred to another latch. If it is not being used, the process returns to continue checking.

[0043] In summary, the solution proposed in this invention, namely through... Figure 2 The two paths shown allow for multiple opportunities for redundancy replacement while using a smaller area. This approach is also applicable to NAND flash, providing a good redundancy replacement solution for the entire non-volatile memory device, thereby greatly improving device yield and chip performance consistency.

[0044] For those skilled in the art, the present invention is not limited to the details of the exemplary embodiments described above, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention; therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Therefore, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent substitutions, and improvements made to the above embodiments based on the technical essence of the present invention should be included within the protection scope of the present invention.

Claims

1. A small area, multiple column redundancy replacement method for Norflash, characterized in that, The specific steps are as follows, S1, hierarchical selection is performed on the storage unit; S2, after hierarchical selection, multiple column redundancy replacement is performed on the error address; The hierarchical selection is specifically as follows: S1-1, the bit lines of the main area and the redundancy area are respectively subjected to address difference through YMUX1 and YMUX2 to obtain SA_main sensitive amplifiers of the main area and SA_redun sensitive amplifiers of the redundancy area; S1-2, the addresses of YMUX2_main and SA_main are recorded; The multiple column redundancy replacement is as follows: S2-1, first, 2bit information is recorded for each YMUX2_redun, that is, 1bit flag information indicating whether the redundancy is good or bad and 1bit flag information indicating whether the Latch is used for replacement; S2-2, the main area is an error area, and it is judged whether YMUX2 in the error address is repeated with the previous YMUX2, if not, the next address data is checked; S2-3, if not the same, it is judged whether the Latch corresponding to the main area in the redundancy area is available, if available, it is directly replaced; S2-4, if not available, selection is performed from 1-YMUX2 in the redundancy area, if available, it is directly replaced, if all the Latch replacement resources of the redundancy area are used, selection is again performed from 1-YMUX2, if still error, it is marked as a bad area.

2. The small area, multiple column redundancy replacement method for Norflash according to claim 1, characterized in that: Wherein YMUX2_redun / YMUX2_main=1:

2.

3. The small area, multiple column redundancy replacement method for Norflash according to claim 1, characterized in that: S2-3, after replacement, the redundancy area is error, the error of the redundancy is recorded first, and then it is judged whether the Latch corresponding to the redundancy is used, if used, the recorded information is transferred to other Latch, if not used, it is returned to continue checking.

4. The small area, multiple column redundancy replacement method for Norflash according to claim 1, characterized in that: The YMUX1 and YMUX2 are both eight-to-one selectors.

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