A method for manufacturing a SiC power device and a SiC power device

Abstract

The application relates to a preparation method of a SiC power device and the SiC power device in the field of semiconductor technology, and comprises the following steps: using a cleaning gas to clean the crystal face defects of a SiC substrate layer; growing an oxide solid solution film on the SiC substrate layer through a PECVD method, and the thickness of the oxide solid solution film is 20-50 nm; performing fine layering on the oxide solid solution film in a nitrogen environment to obtain a phase separation layer, wherein the temperature of the fine layering is 500-900 DEG C; using a cleaning gas two to clean the dangling bond passivation and dangling bond defects of the phase separation layer; and depositing a first electrode layer on the phase separation layer and a second electrode layer on the SiC substrate layer by adopting a magnetron sputtering method, so that the SiC power device has the advantages of high channel mobility, low static power consumption and high reliability, and the bottleneck of large energy loss at the gate caused by excessive tunneling current is broken.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of SiC power device and SiC power device. BACKGROUND

[0002] SiC power device benefits from the superior physical properties of SiC material, such as wide band gap, high breakdown field strength, high thermal conductivity, etc., and has great prospects in the fields of power grid, high-speed rail, electric vehicles and aerospace, etc. which have significant demand for high power.

[0003] In the preparation process of SiC power device, especially metal-oxide-semiconductor field-effect transistor, a mature silicon thermal oxidation process is often used to prepare SiO2 oxide insulating layer. However, for the SiO2 layer grown by thermal oxidation, there will inevitably be many interface defects such as Si-Si and C-C at the interface, which will cause a significant decrease in channel mobility, and the channel mobility is far from the theoretical electron mobility of SiC. In addition, the dielectric constant of SiO2 is only 3.9. In order to ensure the working current of the power device, the thickness of SiO2 needs to be thinned, which will cause the static power consumption to increase sharply. According to Gauss theorem, the smaller dielectric constant will also increase the electric field at the gate oxide material when the power device is working, which will pose a challenge to the reliability of the power device.

[0004] On the other hand, gate oxide materials represented by Al2O3 and HfO2 have been widely studied in recent years. However, compared with SiO2, although these materials have a larger dielectric constant, their band gap is not as wide as that of SiO2. In the process of matching with SiC, since the difference between the conduction band and the valence band of these materials is small, electrons can easily cross the barrier under the action of gate voltage, which will generate a large tunneling current and cause a large energy loss at the gate. SUMMARY

[0005] The present application provides a preparation method of SiC power device and SiC power device, which has the advantages of high channel mobility, low static power consumption and high reliability, and breaks through the bottleneck of large energy loss at the gate caused by excessive tunneling current.

[0006] In order to solve the above technical problems, the present application solves the problems by the following technical solutions:

[0007] A preparation method of SiC power device, comprising the following steps:

[0008] cleaning the crystal surface defects of the SiC substrate layer with a cleaning gas;

[0009] growing an oxide solid solution film on the SiC substrate layer by PECVD method, and the thickness of the oxide solid solution film is 20-50 nm.

[0010] The oxide solid solution film is finely layered under nitrogen environment to obtain a phase-separated layer, wherein the temperature of the fine layering is 500-900℃;

[0011] The dangling bonds of the phase-separated layer are passivated and the dangling bond defects are cleaned using a cleaning gas;

[0012] A first electrode layer is deposited on the phase-separated layer by a magnetron sputtering method, and a second electrode layer is deposited on the SiC substrate layer.

[0013] Optionally, the oxide solid solution film is A x SiO y film, wherein A is an a-valent element, and 4+ax=2y is satisfied.

[0014] Optionally, when X is Al element, the oxide solid solution film is an Al2(SiO3)3 film, and the temperature of the fine layering is controlled to be 525-575℃, and the thickness of the fine layering is controlled to be 20-30nm, and the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer and a second SiO2 layer.

[0015] Optionally, when A is Al element, the oxide solid solution film is an Al2(SiO3)3 film, and the temperature of the fine layering is controlled to be 600-700℃, and the thickness of the fine layering is controlled to be 20-30nm, and the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer, a third SiO2 layer and a second Al2O3 layer.

[0016] Optionally, when A is Al element, the oxide solid solution film is an Al2(SiO3)3 film, and the temperature of the fine layering is controlled to be 600-700℃, and the thickness of the fine layering is controlled to be 35-45nm, and the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer, a second SiO2 layer and a second Al2O3 layer.

[0017] Optionally, when A is Zr element, the oxide solid solution film is a ZrSiO4 film, and the temperature of the fine layering is controlled to be 600-800℃, and the thickness of the fine layering is controlled to be 20-35nm, and the ZrSiO4 film is finely layered into a first SiO2 layer, a ZrO2 layer and a second SiO2 layer.

[0018] Optionally, when A is Hf element, the oxide solid solution thin film is HfSiO4 thin film, and the temperature of the fine layering is controlled at 700-900 DEG C, and the thickness of the fine layering is controlled at 20-35 nm, and the HfSiO4 thin film is finely layered into a first SiO2 layer, a HfO2 layer and a second SiO2 layer.

[0019] Optionally, the oxygen pressure of the fine layering is controlled at 1.5-2.5 Pa.

[0020] A SiC power device includes a first electrode layer, a second electrode layer, a SiC substrate layer and a phase separation layer, the phase separation layer is arranged on the SiC substrate layer, the second electrode layer is arranged on an end surface of the SiC substrate layer away from the phase separation layer, and the first electrode layer is arranged on an end surface of the phase separation layer away from the SiC substrate layer.

[0021] Optionally, the first electrode layer is a polysilicon material or a metal material, and the second electrode layer is a metal material.

[0022] Compared with the prior art, the technical scheme provided in the application has the following beneficial effects:

[0023] By fine layering the oxide solid solution thin film at a set temperature range and oxygen pressure, a phase separation layer is obtained, and by the contact between the phase separation layer and the SiC substrate layer, the interface valence band difference and the conduction band difference of the SiC substrate layer are increased, thereby suppressing the leakage current, reducing the energy loss, preventing the electrons from crossing the barrier under the action of the gate voltage to generate a large tunneling current and cause a large energy loss, and the temperature setting of 500-900 DEG C is lower than the conventional annealing temperature setting, thereby preventing the formation of carbon clusters such as Si-Si bonds and C-C bonds at the interface of the SiC substrate layer, and further increasing the mobility of the interface carriers. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme in the embodiments of the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 A flow chart of a preparation method of a SiC power device is provided in the application;

[0026] Figure 2 A structure diagram of a SiC power device obtained by a preparation method of a SiC power device provided in the first embodiment is provided;

[0027] Figure 3The diagrams show the band structure of the SiC power device proposed in this embodiment and the band structure of a conventional SiC power device.

[0028] Figure 4 This is a structural diagram of a SiC power device obtained by the fabrication method of the SiC power device proposed in this embodiment 2;

[0029] Figure 5 This is a structural diagram of a SiC power device obtained by the fabrication method of the SiC power device proposed in this embodiment 3;

[0030] Figure 6 This is a structural diagram of a SiC power device obtained by the fabrication method of the SiC power device proposed in Embodiment 4.

[0031] Figure 7 This is a structural diagram of a SiC power device obtained by the fabrication method of the SiC power device proposed in this embodiment five. Detailed Implementation

[0032] The present application will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present application, but the present application is not limited to the following embodiments.

[0033] Example 1

[0034] like Figure 1 As shown, a method for fabricating a SiC power device includes the following steps: firstly, a cleaning gas is used to clean the crystal plane defects of the SiC substrate; wherein the cleaning gas can be hydrogen, and the cleaning temperature is set to 500℃ when cleaning the SiC substrate.

[0035] After cleaning the crystal plane defects on the SiC substrate surface, an oxide solid solution film is grown on the SiC substrate using plasma-enhanced atomic layer deposition (PECVD). The thickness of the oxide solid solution film is 20–50 nm. The oxide solid solution film is composed of A... x SiO y In a thin film, element A is an element with a valence of α and satisfies 4 + ax = 2y. A can be elements such as Al, Zr, Hf, Y, Ta, or La.

[0036] Considering that the dielectric constant of high dielectric materials is relatively large compared to SiO2, and the equivalent thickness of SiO2 obtained is about 1 to 10 nm, and based on the relative dielectric constants of Al2O3, ZrO2 and HfO2 being 9.0, 25 and 25 respectively, their physical thickness can be 2 to 6 times that of the equivalent thickness of SiO2. Therefore, the overall thickness of the oxide solid solution film is set to 20 to 50 nm.

[0037] Based on the different crystallization temperatures of Al2O3, ZrO2 and HfO2, the oxide solid solution film is finely layered in a nitrogen environment to obtain a phase separation layer, and the temperature and oxygen pressure of the fine layering are adjusted during the fine layering process, so that the oxide solid solution film self-assembles and crystallizes to form a separate film at different temperature ranges, and the phase separation layer has different film layer thicknesses near the SiC substrate layer under the oxygen pressure, wherein the fine layering temperature is 500-900°C, and the fine layering oxygen pressure is 1.5-2.5 Pa.

[0038] Among them, Al2O3, ZrO2 and HfO2 can also be called high-dielectric oxide. Since the energy band gap of Al2O3, ZrO2 and HfO2 is 8.7 eV, 7.8 eV and 5.7 eV respectively, the valence band difference and the conduction band difference are obviously smaller than the energy band gap of 8.9 eV of SiO2 in the process of forming an interface with 4H-SiC with an energy band gap of 3.3 eV, which can easily cause a large leakage current. Through calculation, it is found that when a layer of SiO2 is inserted between the high-dielectric oxide and SiC, the overall valence band difference and conduction band difference will be significantly increased. However, considering that the equivalent thickness of SiO2 is large, its physical thickness should be as small as possible. Therefore, in order to achieve the purpose of reducing static power consumption, the physical thickness of the first SiO2 layer closest to the SiC substrate layer needs to be controlled to within 1-5 nm, taking into account the effectiveness of SiO2 and the suppression of gate leakage current.

[0039] As shown in Figure 2 When A is Al element, the oxide solid solution film selects Al2(SiO3)3 film, at this time, Al2(SiO3)3 film is grown on SiC substrate layer, and the fine layering temperature is controlled at 525-575°C, the fine layering thickness is controlled at 20-30 nm, and the fine layering oxygen pressure is controlled at 1.5-2.5 Pa, so that the Al2(SiO3)3 film is finely divided into a first SiO2 layer, a first Al2O3 layer and a second SiO2 layer. Specifically, the thickness of the Al2(SiO3)3 film is 30 nm, the fine layering temperature is controlled at 550°C, and the fine layering oxygen pressure is controlled at 1.5 Pa. At this time, the phase separation layer is obtained after fine layering, and the phase separation layer has three layers, i.e. the Al2(SiO3)3 film is finely divided into a first SiO2 layer, a first Al2O3 layer and a second SiO2 layer. The first SiO2 layer is close to the SiC substrate layer, and the thickness of the phase separation layer is 2 nm, which meets the requirement of 1-5 nm and achieves the purpose of reducing static power consumption. The thickness of the obtained first Al2O3 layer is 20 nm, and the thickness of the obtained second SiO2 layer is 20 nm.

[0040] In one aspect, since in the fine delamination process, no direct oxidation of the SiC substrate layer is involved, and the annealing temperature is controlled at 600-900℃, the temperature is relatively low, thus carbon clusters, such as Si-Si bond and C-C bond, are not easily formed at the interface of the SiC substrate layer, so that the interface carriers have a higher mobility, and meanwhile, the first SiO2 layer obtained after fine delamination and in contact with the SiC substrate layer can also increase the interface valence band gap and the conduction band gap of the SiC substrate layer, thereby inhibiting the leakage current and preventing the electrons from crossing the barrier under the action of the gate voltage to generate a large tunneling current and cause a large energy loss.

[0041] As shown in Figure 3 , ΔEv represents the valence band gap, and ΔEc represents the conduction band gap. As can be seen from the figure, the valence band gap measured by the SiC / SiO2 / High-k structure obtained after fine delamination is larger than that measured by the SiC / High-k structure, and similarly, the conduction band gap measured by the SiC / SiO2 / High-k structure is larger than that measured by the SiC / High-k structure, wherein High-k is a high-k metal gate material, thereby proving in actual detection that the purpose of increasing the interface valence band and conduction band gap achieved by the embodiment is achieved, and thereby the leakage current is inhibited.

[0042] On the other hand, by controlling the temperature and oxygen pressure of the growth process of the oxide solid solution film, and controlling the thickness ratio of the high-dielectric oxide and SiO2 generated after phase separation, the overall dielectric constant is greater than 8, thereby reducing the electric field and making the overall structure more reliable.

[0043] After obtaining the first SiO2 layer, the first Al2O3 layer and the second SiO2 layer, a cleaning gas is used to clean the dangling bonds and dangling bond defects of the phase separation layer, wherein the cleaning gas can be nitrous oxide, and the cleaning temperature is set to 500℃, and finally a first electrode layer is deposited on the phase separation layer by a magnetron sputtering method, and a second electrode layer is deposited on the SiC substrate layer.

[0044] Example Two

[0045] As shown in Figure 4The embodiment is different from the embodiment one in that, when the Al2(SiO3)3 film with a thickness of 30 nm is finely layered, the temperature of the fine layering is controlled at 600-700°C, so that the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer, a third SiO2 layer and a second Al2O3 layer. Preferably, the temperature of the fine layering is controlled at 600°C, and the oxygen pressure of the fine layering is also selected as 1.5 Pa. At this time, the phase-separated layers after the fine layering are four layers, i.e. the Al2(SiO3)3 film is finely layered into a first SiO2 layer with a thickness of 2 nm, a first Al2O3 layer with a thickness of 20 nm, a third SiO2 layer with a thickness of 10 nm and a second Al2O3 layer with a thickness of 10 nm.

[0046] At this time, the purpose of periodically alternating the high dielectric constant material layer and the SiO2 layer is achieved, i.e. starting from the SiC substrate layer, the layers are sequentially the SiO2 material, the Al2O3 material, the SiO2 material and the Al2O3 material. The first SiO2 layer is inserted between the first Al2O3 layer and the SiC substrate layer, so that the thickness of the first SiO2 layer closest to the SiC substrate layer is controlled within 1-5 nm, thereby achieving the purpose of reducing the static power consumption. In the process of forming the interface between the Al2O3 with a band gap of 8.7 eV and the 4H-SiC with a band gap of 3.3 eV, the valence band difference and the conduction band difference are too small, which leads to a large leakage current. Since the temperature of the fine layering in the embodiment is low, i.e. 600°C, carbon clusters such as Si-Si bond and C-C bond are not easily formed at the interface of the SiC substrate layer, so that the interface carrier has a high mobility.

[0047] The same as the embodiment one is that, since the temperature and the oxygen pressure of the growth process of the Al2(SiO3)3 film are controlled, the thickness ratio of the high dielectric oxide and the SiO2 after the phase separation is controlled, so that the overall dielectric constant of the gate oxide structure obtained in the embodiment is greater than 8, thereby reducing the electric field and making the overall structure more reliable. On the other hand, the 2 nm first SiO2 layer obtained after the fine layering of the Al2(SiO3)3 film is in contact with the SiC substrate layer, which increases the interface valence band difference and the conduction band difference of the SiC substrate layer, thereby suppressing the leakage current and preventing the electrons from crossing the barrier under the action of the gate voltage, thereby generating a large tunneling current and causing a large energy loss.

[0048] Embodiment three

[0049] As Figure 5The embodiment is different from the first embodiment in that the temperature of the fine layering is controlled to be 600-700°C and the thickness of the fine layering is controlled to be 35-45 nm, so that the Al2(SiO3)3 film is finely divided into a first SiO2 layer, a first Al2O3 layer, a second SiO3 layer and a second Al2O3 layer. In this case, the temperature of the fine layering is preferably controlled to be 600°C and the oxygen pressure of the fine layering is preferably controlled to be 1.5 Pa. In this case, the fine layering is divided into four layers, i.e., the Al2(SiO3)3 film is finely divided into a 2-nm first SiO2 layer, a 20-nm first Al2O3 layer, a 20-nm second SiO2 layer and a 10-nm second Al2O3 layer.

[0050] In this case, the high dielectric constant material layer and the SiO2 layer are periodically arranged, i.e., the layers are arranged in the order of SiO2 material, Al2O3 material, SiO2 material and Al2O3 material from the SiC substrate layer. In this case, the first SiO2 layer is inserted between the first Al2O3 layer and the SiC substrate layer, so that the thickness of the first SiO2 layer closest to the SiC substrate layer is controlled to be 2 nm or less than 5 nm, thereby reducing the static power consumption. In the case of the conventional Al2O3 material having a band gap of 8.7 eV and the 4H-SiC material having a band gap of 3.3 eV, the band gap difference is too small to prevent a large leakage current. In this embodiment, the temperature of the fine layering is controlled to be 600°C, so that carbon clusters such as Si-Si bonds and C-C bonds are not formed at the interface of the SiC substrate layer, thereby increasing the mobility of the interface carriers.

[0051] In this embodiment, the temperature and the oxygen pressure of the Al2(SiO3)3 film are controlled, so that the thickness ratio of the high dielectric oxide and the SiO2 is controlled. In this case, the dielectric constant of the final gate oxide structure is greater than 8, thereby reducing the electric field and increasing the reliability of the structure. In addition, the first SiO2 layer having a thickness of 2 nm is in contact with the SiC substrate layer, thereby increasing the band gap difference of the interface of the SiC substrate layer and suppressing the leakage current. In this case, the electrons are prevented from crossing the barrier under the gate voltage, thereby preventing a large tunneling current and energy loss.

[0052] Embodiment Four

[0053] As Figure 6As shown, when A is Zr element, the oxide solid solution film is selected as ZrSiO4 film, and the temperature for fine layering is controlled at 600-800°C, and the thickness for fine layering is controlled at 20-35 nm, so that the ZrSiO4 film is finely layered into a first SiO2 layer, a ZrO2 layer and a second SiO2 layer. Preferably, the thickness of the ZrSiO4 film is controlled at 30 nm, and the temperature for fine layering is controlled at 700°C, and the oxygen pressure for fine layering is also selected as 1.5 Pa. In this case, the phase-separated layer is three layers, i.e. the ZrSiO4 film is finely layered into a 2 nm first SiO2 layer, a 20 nm ZrO2 layer and a 20 nm second SiO2 layer.

[0054] In this case, the first SiO2 layer is inserted between the ZrO2 layer and the SiC substrate layer to ensure that the overall valence band difference and the conduction band difference are significantly increased, and the thickness of the first SiO2 layer closest to the SiC substrate layer is controlled to be within 1-5 nm, so that the purpose of reducing static power consumption is achieved, and the phenomenon of large leakage current caused by too small valence band difference and conduction band difference in the process of forming the interface of ZrO2 with a band gap of 7.8 eV and 4H-SiC with a band gap of 3.3 eV is avoided. Since the temperature for fine layering used in the embodiment is low, i.e. 700°C, carbon clusters such as Si-Si bond and C-C bond are not easily formed at the interface of the SiC substrate layer, so that the interface carriers have a high mobility.

[0055] As in the first embodiment, the temperature and oxygen pressure during the growth of the ZrSiO4 film are controlled, so that the thickness ratio of the high dielectric oxide ZrO2 and SiO2 generated after phase separation is controlled, and the overall dielectric constant of the gate oxide structure obtained in the embodiment is greater than 8, so that the electric field is reduced and the overall structure is more reliable. On the other hand, the 2 nm first SiO2 layer obtained after fine layering of the ZrSiO4 film is in contact with the SiC substrate layer, which also increases the interface valence band difference and conduction band difference of the SiC substrate layer, thereby suppressing the leakage current and preventing the electrons from crossing the barrier under the action of the gate voltage to generate large tunneling current and cause large energy loss.

[0056] Example Five

[0057] As Figure 7As shown, when A is Hf element, the oxide solid solution film is selected as HfSiO4 film, so that the temperature of fine layering is controlled at 700-900℃, and the thickness of fine layering is controlled at 20-35nm, so that the HfSiO4 film is finely divided into a first SiO2 layer, a HfO2 layer and a second SiO2 layer. Preferably, the thickness of the HfSiO4 film is controlled at 30nm, at this time, the temperature of fine layering is controlled at 850℃, and the oxygen pressure of fine layering is also selected as 1.5Pa, at this time, the phase separation layer after fine layering is three layers, i.e. the HfSiO4 film is finely divided into a 2nm first SiO2 layer, a 20nm HfO2 layer and a 20nm second SiO2 layer.

[0058] In the embodiment, the first SiO2 layer is inserted between the HfO2 layer and the SiC substrate layer, so that the thickness of the first SiO2 layer closest to the SiC substrate layer is controlled within 1-5nm, so as to reduce the static power consumption, and avoid the phenomenon that the valence band difference and the conduction band difference are too small to cause large leakage current in the process of forming the interface between the HfO2 with a band gap of 5.7eV and the 4H-SiC with a band gap of 3.3eV. Since the temperature of fine layering used in the embodiment is low, i.e. 850℃, carbon clusters such as Si-Si bond and C-C bond are not easily formed at the interface of the SiC substrate layer, so that the interface carrier has high mobility.

[0059] In the embodiment, the temperature and the oxygen pressure in the growth process of the HfSiO4 film are controlled, so as to control the thickness ratio of the high dielectric oxide HfO2 and SiO2 after phase separation, so that the overall dielectric constant of the gate oxide structure obtained in the embodiment is greater than 8, so as to reduce the electric field and make the overall structure more reliable. On the other hand, the 2nm first SiO2 layer obtained after fine layering of the HfSiO4 film is in contact with the SiC substrate layer, so as to increase the interface valence band difference and the conduction band difference of the SiC substrate layer, so as to suppress the leakage current and prevent the electrons from crossing the potential barrier under the action of the gate voltage, so as to prevent large tunneling current and cause large energy loss.

[0060] Embodiment six

[0061] A SiC power device includes a first electrode layer, a second electrode layer, a SiC substrate layer and a phase separation layer, the phase separation layer is arranged on the SiC substrate layer, the second electrode layer is arranged on one end surface of the SiC substrate layer away from the phase separation layer, and the first electrode layer is arranged on one end surface of the phase separation layer away from the SiC substrate layer, wherein the first electrode layer is a polycrystalline silicon material or a metal material, the second electrode layer is a metal material, and the metal material can be nickel or aluminum.

[0062] By setting the phase separation layer and making the phase separation layer contact with the SiC substrate layer, the interface valence band gap and the conduction band gap of the SiC substrate layer are increased, so that the leakage current is inhibited, the energy loss is reduced, and the energy loss caused by the larger tunneling current generated by the electrons crossing the barrier under the action of the gate voltage is prevented.

[0063] In addition, it should be noted that the specific embodiments described in the specification, the shape of the zero, the components, the name taken, etc. can be different. Any equivalent or simple change made in accordance with the configuration, features and principles described in the patent concept of the present application is included in the protection scope of the present application. Those skilled in the art of the present application can make various modifications or supplements to the described specific embodiments or use similar ways to replace, as long as it does not deviate from the structure of the present application or exceed the scope defined by the present claims, which shall belong to the protection scope of the present application.

Claims

1. A method of fabricating a SiC power device, characterized by, The method comprises the following steps: cleaning the crystal face defects of the SiC substrate layer at a cleaning temperature of 500 DEG C by using a cleaning gas I, wherein the cleaning gas I is hydrogen; growing an oxide solid solution film on the SiC substrate layer by a PECVD method, wherein the thickness of the oxide solid solution film is 20-50 nm, and the oxide solid solution film is any one of an Al2(SiO3)3 film, a ZrSiO4 film or a HfSiO4 film; finely layering the oxide solid solution film in a nitrogen environment to obtain a phase separation layer, wherein the phase separation layer refers to a structure formed by periodically and alternately arranging a high dielectric constant material layer and a SiO2 layer, the high dielectric constant material layer includes any one of an Al2O3 layer, a ZrO2 layer and a HfO2 layer, the SiO2 layer is close to the SiC substrate layer in the phase separation layer, the thickness of the SiO2 layer is 1-5 nm, the temperature of the fine layering is 500-900 DEG C, and the oxygen pressure of the fine layering is 1.5-2.5 Pa; cleaning the dangling bonds and dangling bond defects of the phase separation layer at a cleaning temperature of 500 DEG C by using a cleaning gas II, wherein the cleaning gas II is nitrous oxide; depositing a first electrode layer on the phase separation layer and a second electrode layer on the SiC substrate layer by a magnetron sputtering method.

2. The method of claim 1, wherein the SiC power device is a vertical SiC power device. The oxide solid solution film is an Al2(SiO3)3 film, the temperature of the fine layering is controlled to be 525-575 DEG C, and the thickness of the fine layering is controlled to be 20-30 nm, so that the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer and a second SiO2 layer.

3. The method of claim 1, wherein the SiC power device is a Schottky barrier diode. The oxide solid solution film is an Al2(SiO3)3 film, the temperature of the fine layering is controlled to be 600-700 DEG C, and the thickness of the fine layering is controlled to be 20-30 nm, so that the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer, a second SiO2 layer and a second Al2O3 layer.

4. The method of claim 1, wherein the SiC power device is a Schottky barrier diode. The oxide solid solution film is an Al2(SiO3)3 film, the temperature of the fine layering is controlled to be 600-700 DEG C, and the thickness of the fine layering is controlled to be 35-45 nm, so that the Al2(SiO3)3 film is finely layered into a first SiO2 layer, a first Al2O3 layer, a second SiO2 layer and a second Al2O3 layer.

5. The method of claim 1, wherein the SiC power device is a Schottky barrier diode. The oxide solid solution film is a ZrSiO4 film, the temperature of the fine layering is controlled to be 600-800 DEG C, and the thickness of the fine layering is controlled to be 20-35 nm, so that the ZrSiO4 film is finely layered into a first SiO2 layer, a ZrO2 layer and a second SiO2 layer.

6. The method of claim 1, wherein the SiC power device is a Schottky barrier diode. The oxide solid solution film is a HfSiO4 film, the temperature of the fine layering is controlled to be 700-900 DEG C, and the thickness of the fine layering is controlled to be 20-35 nm, so that the HfSiO4 film is finely layered into a first SiO2 layer, a HfO2 layer and a second SiO2 layer.

7. A SiC power device, characterized by, The SiC power device is prepared by the preparation method as claimed in claims 1-6, comprising a first electrode layer, a second electrode layer, a SiC substrate layer and a phase separation layer, the phase separation layer is arranged on the SiC substrate layer, the second electrode layer is arranged on an end surface of the SiC substrate layer away from the phase separation layer, and the first electrode layer is arranged on an end surface of the phase separation layer away from the SiC substrate layer.

8. The SiC power device of claim 7, wherein, The first electrode layer is a polysilicon material or a metal material, and the second electrode layer is a metal material.

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