A positive and negative three-value latch circuit based on binary memristor

Abstract

The invention discloses a positive and negative three-value latch circuit based on a binary memristor. The invention comprises three identical basic logic gates and three identical composite logic gates, and a corresponding basic logic gate and a composite logic gate constitute a group of logic units. In each logic unit, the basic logic gate comprises two memristors, the negative pole serves as the input end of the basic logic gate, and the positive pole is connected as the output end of the basic logic gate. The composite logic gate comprises four memristors and two MOS tubes, the positive pole of a memristor is connected to the output end of the basic logic gate, the negative pole is connected to the negative pole of another memristor and then connected to the gates of two MOS tubes, the drain of one MOS tube is connected to a power supply through a memristor, the source is connected to the drain of another MOS tube, and is grounded through a memristor. The circuit model structure of the invention is clear and simple, easy to implement, and has important significance for application research in many fields such as multi-value digital logic circuit design.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, relates to a three-value digital logic circuit structure, and specifically relates to a positive and negative three-value latch circuit based on a binary memristor. Background Art

[0002] Memristor was proposed by Professor Shao-Tang Tsai in 1971 and first developed as a physical device by HP Labs in 2008. It has now become one of the measures to cope with the continuous shrinking of modern electronic circuits. As the fourth basic passive circuit element, memristor has been widely studied in digital logic circuits, nonlinear circuits, neuromorphic networks and other fields due to its advantages such as nanometer size, non-volatility and compatibility with CMOS technology.

[0003] At present, most of the research on digital logic circuits is based on binary logic. Compared with binary signals, multi-valued signals carry more information, which can improve the information density of transmission signal lines and integrated circuits and the time and space utilization of information processing. As a multi-valued logic, three-valued logic has more logical possibilities and can meet various different logic requirements. Therefore, the three-valued logic system has gradually become a substitute for the binary logic system, used to realize high-density logic systems, with higher computing speed, smaller computing level and smaller chip area, and is widely used in the design of various algorithms and logic applications.

[0004] As a representative of multi-valued logic, three-valued logic was first proposed by Thomas Fowler in 1840. However, due to the lack of corresponding actual three-valued devices, the research on three-valued logic has been stagnant. Therefore, the research on multi-valued logic circuits based on memristors has great development prospects. In three-valued logic, using memristors to replace traditional CMOS integrated circuits can better reduce the complexity of the circuit and has higher precision, providing a new direction for the development of three-valued logic circuits.

[0005] In digital logic systems, the output of a sequential logic circuit at any time depends not only on the input at that time, but also on the circuit's past output. As a basic element of a sequential logic circuit, storage elements play an important role. Traditional latch designs are based on gate circuits composed of MOS tubes, while ternary latches based on memristor designs have great advantages in reducing power consumption and circuit integration. Summary of the invention

[0006] The invention aims to provide a positive and negative three-value latch circuit based on a binary memristor, which is suitable for positive three-value and negative three-value universal latch circuits.

[0007] The technical solution of the present invention is as follows:

[0008] It includes three identical basic logic gates and three identical compound logic gates, and a corresponding basic logic gate and a compound logic gate constitute a group of logic units.

[0009] In each logic unit, the basic logic gate includes two memristors, the negative electrode of the first memristor M1 and the negative electrode of the second memristor M2 are respectively used as the input end of the basic logic gate, and the positive electrode of the first memristor M1 is connected to the positive electrode of the second memristor M2 as the output end of the basic logic gate. The composite logic gate includes four memristors and two MOS tubes, the positive electrode of the third memristor M3 is connected to the output end of the basic logic gate, the negative electrode of the third memristor M3 and the negative electrode of the fourth memristor M4 are connected and then connected to the gate of the first MOS tube T1 and the gate of the second MOS tube T2, the drain of the first MOS tube T1 is connected to the negative electrode of the fifth memristor M5, the positive electrode of the fifth memristor M5 is connected to the power supply, the source of the first MOS tube T1 is connected to the drain of the second MOS tube T2 and the positive electrode of the sixth memristor M6, and the source of the second MOS tube T2 and the negative electrode of the sixth memristor M6 are grounded.

[0010] The positive electrode of the fourth memristor M4 of the first group of logic units is used as the high input terminal S2 of the latch circuit, and the fourth memristor M 10 The positive electrode of is used as the secondary input terminal S1 of the latch circuit, and the fourth memristor M of the third group of logic units 16 The positive electrode of the latch circuit is used as the low input terminal S0 of the latch circuit; the negative electrode of the fifth memristor M5 of the first group of logic units, the negative electrode of the first memristor M7 of the second group of logic units, and the negative electrode of the first memristor M 13 The negative electrode of the first memristor M1 of the first group of logic units and the negative electrode of the fifth memristor M2 of the second group of logic units are connected as the high output terminal Q2 of the latch circuit; 11 The negative electrode, the second memristor M of the third group of logic units 14 The negative electrode of the second memristor M2 of the first group of logic units, the negative electrode of the second memristor M8 of the second group of logic units, and the negative electrode of the fifth memristor M of the third group of logic units are connected as the secondary output terminal Q1 of the latch circuit; the negative electrode of the second memristor M2 of the first group of logic units, the negative electrode of the second memristor M8 of the second group of logic units, and the negative electrode of the fifth memristor M 17 The negative pole of is connected as the low output terminal Q0 of the latch circuit.

[0011] The three-valued NOR gate and the NAND gate of the present invention are both cascaded by a three-valued OR gate and a standard three-valued inverter (STI), and the circuit is composed of four memristors and two PMOS tubes. Taking the NOR gate as an example, when the input is obtained by the OR gate and different outputs "-2", "-1", and "0" are obtained, different outputs can be obtained through the STI, and logic "-2" obtains logic "0", logic "-1" obtains logic "-1", and logic "0" obtains logic "-2".

[0012] The present invention takes a negative three-value latch as an example to provide a specific circuit design and analysis process. The positive three-value latch only needs to replace the basic logic AND gate in the negative three-value latch circuit with an OR gate, and the composite logic NOR gate with a NAND gate.

[0013] In this three-value latch circuit, outputs Q1 and Q0 are connected to the negative three-value AND gate, and then connected to the negative three-value NOR gate together with input S2 to obtain output Q2; outputs Q2 and Q0 are connected to the negative three-value AND gate, and then connected to the negative three-value NOR gate together with input S1 to obtain output Q1; outputs Q2 and Q1 are connected to the negative three-value AND gate, and connected to the negative three-value NOR gate together with input S0 to obtain output Q0. At this time, the current output signal in the circuit will be controlled by the previous output, and when there is only one zero input signal "0" in S2, S1, and S0 of the input signal, and the rest of the bits are non-zero input signals "-2", the circuit will set the output to the state corresponding to the zero bit of the input signal, and when the input signals S2, S1, and S0 are all "-2", the circuit will store the previous output signal.

[0014] The circuit model of the present invention has a clear and simple structure, is easy to implement, and has storage characteristics, which not only reduces the power consumption of the circuit, but also reduces the complexity of the circuit. The three-value latch circuit is a basic component of various three-value trigger circuits. It has both a stable state that can be maintained by itself and three states that can be set according to input signals. It lays a foundation for the subsequent realization of three-value trigger circuits and more complex digital sequential logic circuits, and is of great significance to the application research in many fields such as multi-value digital logic circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit block diagram of the present invention;

[0016] Figure 2 It is a schematic diagram of a negative three-value latch circuit based on a binary memristor according to the present invention. DETAILED DESCRIPTION

[0017] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0018] The positive and negative three-value latch circuit model based on the binary memristor designed by the present invention has a negative three-value latch circuit block diagram as shown in FIG. Figure 1 As shown, it is composed of three TAND gates U1, U2, U3 and three TNOR gates P1, P2, P3, and is implemented by utilizing the resistance switching characteristics and memory characteristics of the memristor.

[0019] The logic state in a circuit is a voltage value, where voltage is defined as -V DD is -3.3V, corresponding to logic "-2"; -V DD / 2 is -1.65V, corresponding to logic "-1"; GND is 0V, corresponding to logic "0". The truth table of the negative three-value latch designed by the present invention is shown in the following table:

[0020] <![CDATA[S2]]> <![CDATA[S1]]> <![CDATA[S0]]> <![CDATA[Q2]]> <![CDATA[Q1]]> <![CDATA[Q0]]> Q 0 0 0 -2 -2 -2 × 0 0 -2 -2 -2 0 × 0 -2 0 -2 0 -2 × 0 -2 -2 -2 0 0 -2 -2 0 0 0 -2 -2 × -2 0 -2 0 -2 0 -1 -2 -2 0 0 0 -2 0 -2 -2 -2 Keep Keep Keep Keep

[0021] According to the truth table of the negative three-value latch, the three input signals S2, S1, and S0 all take values ​​of "-2" or "0", and the output of the negative three-value latch is three bits, using (Q2, Q1, Q0) = (-2, 0, 0), (Q2, Q1, Q0) = (0, -2, 0) and (Q2, Q1, Q0) = (0, 0, -2) to represent the "-2", "-1" and "0" in the negative three-value signal.

[0022] When the input signal (S2, S1, S0) = (0, -2, -2), the output of the three-value NOR gate P1 is "-2", which is not affected by the output of the three-value AND gate U1, that is, the output signal Q2 is "-2"; the outputs of the three-value AND gates U2 and U3 are both "-2", and after being connected to the negative three-value NOR gates P2 and P3 together with the input signals S1 and S0, the output signals Q1 and Q0 are both "0". The output signal (Q2, Q1, Q0) = (-2, 0, 0) can be obtained, that is, Q = "-2", completing the "-2" function of the negative three-value latch circuit.

[0023] When the input signal (S2, S1, S0) = (-2, 0, -2), the output Q1 of the negative three-valued NOR gate P2 connected to S1 is "-2", that is, the output of the three-valued AND gates U1 and U3 is "-2", and the outputs of the two negative three-valued NOR gates P1 and P3 are "0", that is, Q2 = Q0 = "0". The output signal (Q2, Q1, Q0) that can be obtained is (0, -2, 0), that is, Q = "-1", completing the "-1" function of the negative three-valued latch circuit.

[0024] When the input signal (S2, S1, S0) = (-2, -2, 0), the output Q0 of the negative three-valued NOR gate P3 connected to S0 is "-2", that is, the output of the three-valued AND gates U1 and U2 is "-2", and the outputs of the two negative three-valued NOR gates P1 and P2 are "0", that is, Q2 = Q1 = "0". The output signal (Q2, Q1, Q0) in the circuit is (0, 0, -2), that is, Q = "0", completing the "0" function of the negative three-valued latch circuit.

[0025] When the input signal (S2, S1, S0) = (-2, -2, -2), the outputs of the negative three-valued NOR gates P1, P2, and P3 in the circuit depend on the outputs of the negative three-valued AND gates U1, U2, and U3, and the inputs of the three AND gates U1, U2, and U3 are controlled by the outputs Q2, Q1, and Q0. For example, when the output of the last circuit (Q2, Q1, Q0) = (0, 0, -2), the output of the three-valued AND gate U3 in the circuit is "0", and the other two outputs are both "-2". After being connected to the three-valued NOR gates with the input signals S2, S1, and S0 respectively, the output of the circuit is (Q2, Q1, Q0) = (0, 0, -2), and the output of the negative three-valued latch circuit remains unchanged.

[0026] The outputs obtained in the other cases cannot determine whether the latch will return to the "-2", "-1" or "0" state. Therefore, when the circuit is working normally, the input signal should comply with the constraint that only one of the three input signals is "0" and the rest are "-2" or all are "-2".

[0027] The positive three-value latch circuit can obtain an output signal (Q2, Q1, Q0) = (2, 0, 0) when the input signal (S2, S1, S0) = (0, 2, 2), that is, Q = "2", completing the setting "2" function of the positive three-value latch circuit.

[0028] When the input signal (S2, S1, S0) = (2, 0, 2), the output signal (Q2, Q1, Q0) = (0, 2, 0) can be obtained, that is, Q = "1", completing the setting "1" function of the positive three-value latch circuit.

[0029] When the input signal (S2, S1, S0) = (2, 2, 0), the output signal (Q2, Q1, Q0) = (0, 0, 2) can be obtained, that is, Q = "0", completing the "0" function of the positive three-value latch circuit.

[0030] When the input signal (S2, S1, S0) = (2, 2, 2), taking the output of the previous circuit (Q2, Q1, Q0) = (0, 0, 2) as an example, the output of the circuit is (Q2, Q1, Q0) = (0, 0, 2), and the output of the positive three-value latch circuit remains unchanged.

[0031] According to the relationship between the input and output of the above negative three-value latch truth table, we can construct the following Figure 1 The detailed circuit structure of the negative three-value latch circuit block diagram is shown in FIG. Figure 2 shown.

[0032] The cathodes of the first memristor M1 and the second memristor M2 are connected to the output terminals Q1 and Q0 respectively, the anodes of the first memristor M1 and the second memristor M2 are connected to the anode of the third memristor M3, the anode of the fourth memristor M4 is connected to the input terminal S2, the cathodes of the third memristor M3 and the fourth memristor M4 are connected to the gates of the first PMOS tube T1 and the second PMOS tube T2, the anode of the fifth memristor M5 is connected to the power supply -V DD The cathode of the fifth memristor M5 is connected to the drain of the first PMOS tube T1 and serves as the output terminal Q2. The source of the first PMOS tube T1 is connected to the anode of the sixth memristor M6 and the drain of the second PMOS tube T2. The source of the second PMOS tube T2 and the cathode of the sixth memristor M6 are connected to GND.

[0033] The cathodes of the seventh memristor M7 and the eighth memristor M8 are connected to the output terminals Q2 and Q0 respectively, the anodes of the seventh memristor M7 and the eighth memristor M8 are connected to the anode of the ninth memristor M9, and the cathodes of the tenth memristor M 10 The positive electrode of the ninth memristor M9 and the tenth memristor M 10 The cathode of the eleventh memristor M is connected to the gates of the third PMOS tube T3 and the fourth PMOS tube T4. 11 The positive terminal of the power supply -V DD connected, the eleventh memristor M 11 The cathode of the third PMOS tube T3 is connected to the drain of the third PMOS tube T3 and serves as the output terminal Q1. The source of the third PMOS tube T3 is connected to the twelfth memristor M 12 The positive electrode of the fourth PMOS tube T4 is connected to the drain of the fourth PMOS tube T4, and the source of the fourth PMOS tube T4 is connected to the twelfth memristor M 12 The negative terminal is connected to GND.

[0034] Thirteenth memristor M 13 and the fourteenth memristor M 14 The negative electrodes of the thirteenth memristor M are connected to the output terminals Q2 and Q1 respectively. 13 and the fourteenth memristor M 14 The positive electrode of the fifteenth memristor M 15 The positive electrode of the sixteenth memristor M 16 The positive electrode of the fifteenth memristor M is connected to the input terminal S0. 15 and the sixteenth memristor M 16 The negative electrode of the seventeenth memristor M is connected to the gate of the fifth PMOS tube T5 and the sixth PMOS tube T6. 17 The positive terminal of the power supply -V DD Connected, the seventeenth memristor M 17 The cathode of the fifth PMOS transistor T5 is connected to the drain of the fifth PMOS transistor T5 and serves as the output terminal Q0. The source of the fifth PMOS transistor T5 is connected to the eighteenth memristor M18 The positive electrode of the sixth PMOS tube T6 is connected to the drain of the sixth PMOS tube T6, and the source of the sixth PMOS tube T6 is connected to the eighteenth memristor M 18 The negative terminal is connected to GND.

[0035] For a positive three-value latch circuit, Figure 1 The negative three-value AND gates of the negative three-value latch circuit U1, U2, and U3 are replaced with positive three-value OR gates, and the negative three-value NOR gates of the P1, P2, and P3 parts are replaced with positive three-value NAND gates. The connection method of the positive three-value latch circuit schematic is the same as that of the negative three-value latch, and the present invention will not be described in detail.

[0036] Those skilled in the art should realize that the above embodiments are only used to verify the present invention, and are not intended to limit the present invention. As long as they are within the scope of the present invention, any changes or modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. A positive and negative three-value latch circuit based on a binary memristor, characterized in that: It includes three identical basic logic gates and three identical compound logic gates, and a corresponding basic logic gate and a compound logic gate constitute a group of logic units; In each logic unit, the basic logic gate includes two memristors, the negative electrode of the first memristor M1 and the negative electrode of the second memristor M2 are respectively used as the input end of the basic logic gate, the positive electrode of the first memristor M1 is connected to the positive electrode of the second memristor M2, and serves as the output end of the basic logic gate; the composite logic gate includes four memristors and two MOS tubes, the positive electrode of the third memristor M3 is connected to the output end of the basic logic gate, the negative electrode of the third memristor M3 is connected to the negative electrode of the fourth memristor M4, and then connected to the gate of the first MOS tube T1 and the gate of the second MOS tube T2, the drain of the first MOS tube T1 is connected to the negative electrode of the fifth memristor M5, the positive electrode of the fifth memristor M5 is connected to the power supply, the source of the first MOS tube T1 is connected to the drain of the second MOS tube T2 and the positive electrode of the sixth memristor M6, and the source of the second MOS tube T2 and the negative electrode of the sixth memristor M6 are grounded; The positive electrode of the fourth memristor M4 of the first group of logic units is used as the high input terminal S2 of the latch circuit, and the fourth memristor M 10 The positive electrode of is used as the secondary input terminal S1 of the latch circuit, and the fourth memristor M of the third group of logic units 16 The positive electrode of the latch circuit is used as the low input terminal S0 of the latch circuit; the negative electrode of the fifth memristor M5 of the first group of logic units, the negative electrode of the first memristor M7 of the second group of logic units, and the negative electrode of the first memristor M 13 The negative electrode of the first memristor M1 of the first group of logic units and the negative electrode of the fifth memristor M2 of the second group of logic units are connected as the high output terminal Q2 of the latch circuit; 11 The negative electrode, the second memristor M of the third group of logic units 14 The negative electrode of the second memristor M2 of the first group of logic units, the negative electrode of the second memristor M8 of the second group of logic units, and the negative electrode of the fifth memristor M of the third group of logic units are connected as the secondary output terminal Q1 of the latch circuit; the negative electrode of the second memristor M2 of the first group of logic units, the negative electrode of the second memristor M8 of the second group of logic units, and the negative electrode of the fifth memristor M 17 The negative pole of is connected as the low output terminal Q0 of the latch circuit.

Images