Method, terminal device and storage medium for successive cancellation list (scl) decoding

Abstract

Embodiments of the application disclose a method for continuous SCL decoding, a terminal device and a storage medium, which are used for saving most area resources occupied by a lazy copy and meeting requirements of high work frequency. The embodiments of the application are applied to a terminal device, the terminal device comprises a plurality of pointer register groups, a plurality of multiplexers (MUXs) and a plurality of state registers, and the method comprises the following steps: recording corresponding binary tree level pointers through the corresponding pointer register groups of each layer of a deep binary tree, wherein the binary tree level pointers are obtained through a shift method; recording a decoding list sorting index after decoding of each information node is completed through the plurality of state registers; and obtaining an output pointer register through the plurality of MUXs according to the binary tree level pointers and the decoding list sorting index.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular to a method, terminal device, and storage medium for continuous elimination list (SCL) decoding. Background Technology

[0002] In Successive Cancellation List (SCL) decoding, as the number of decoding lists and codeword lengths increase, a large number of multiplexers (MUXs) will degrade the decoder's timing and introduce an increase in area. The numerous MUX logic selections increase computational latency, forcing a reduction in the SCL decoder's master clock frequency, directly and adversely affecting the SCL decoder's performance. Summary of the Invention

[0003] This application provides a method, terminal device, and storage medium for continuously eliminating list SCL decoding, which saves most of the area resources occupied by Lazy Copy and meets the requirements of high workload frequency.

[0004] The first aspect of this application provides a method for decoding a continuous elimination list (SCL), applied to a terminal device. The terminal device includes multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers. The method may include: recording the corresponding binary tree level pointers through the pointer register groups corresponding to each level of a depth-first binary tree, wherein the binary tree level pointers are obtained by a shifting method; recording the decoding list sorting index after decoding of each information node is completed through the set of status registers; and calculating the output pointer register through the set of MUXs based on the binary tree level pointers and the decoding list sorting index.

[0005] A second aspect of this application provides a terminal device, including multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers, and may further include:

[0006] The recording module is used to record the corresponding binary tree level pointers through the pointer register group corresponding to each level of the deep binary tree, and the binary tree level pointers are obtained by shifting; the set of status registers records the sorting index of the decoding list after the decoding of each information node is completed;

[0007] The calculation module is used to calculate the output pointer register based on the binary tree level pointer and the sorting index of the decoding list, through the set of MUXs.

[0008] A third aspect of this application provides a terminal device, including multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers, and may further include:

[0009] Memory containing executable program code;

[0010] A processor coupled to the memory;

[0011] The processor is configured to record the corresponding binary tree level pointers through the pointer register group corresponding to each level of the deep binary tree, the binary tree level pointers being obtained through a shifting method; record the decoding list sorting index after each information node is decoded through the set of status registers; and calculate the output pointer register through the set of MUXs based on the binary tree level pointers and the decoding list sorting indexes.

[0012] A fourth aspect of this application provides a computer-readable storage medium including instructions that, when executed on a processor, cause the processor to perform the method described in the first aspect of this application.

[0013] Another aspect of this invention discloses a computer program product that, when run on a computer, causes the computer to execute the method described in the first aspect of this application.

[0014] Another aspect of this invention discloses an application publishing platform for publishing computer program products, wherein when the computer program product is run on a computer, the computer executes the method described in the first aspect of this application.

[0015] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0016] In this embodiment, the method is applied to a terminal device, which includes multiple pointer register groups, a set of multiplexer (MUX) units, and a set of status registers. The method comprises: recording the corresponding binary tree level pointers through the pointer register groups corresponding to each level of a deep binary tree, wherein the binary tree level pointers are obtained through a shifting method; recording the decoding list sorting index after decoding each information node is completed through the set of status registers; and calculating the output pointer register based on the binary tree level pointers and the decoding list sorting index, using the set of MUX units. Compared to existing technologies that require a corresponding MUX unit for each pointer register group and a separate MUX unit for the output pointer register group interface, this application can calculate the output pointer register using only one MUX unit and one set of status registers, saving a significant portion of the area resources occupied by the lazy copy and meeting the requirements of high workload and frequency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments and the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and other drawings can be obtained based on these drawings.

[0018] Figure 1A A schematic diagram of a depth binary tree for Polar code decoding;

[0019] Figure 1B A diagram illustrating the replacement of the decoding list;

[0020] Figure 1C This is a diagram illustrating the replacement of the decoding list using Lazy Copy.

[0021] Figure 1D A schematic diagram of traditional Lazy Copy;

[0022] Figure 2 This is a schematic diagram of an embodiment of the method for decoding the continuous elimination list (SCL) in this application.

[0023] Figure 3A This is a schematic diagram illustrating the convenient copying of Lazy Copy in an embodiment of this application;

[0024] Figure 3B This is a schematic diagram of the corresponding binary tree level pointer recorded in an embodiment of this application;

[0025] Figure 3C This is a schematic diagram of the output pointer register calculated in an embodiment of this application;

[0026] Figure 4A This is a schematic diagram of a terminal device in an embodiment of this application;

[0027] Figure 4B This is another schematic diagram of the terminal device in the embodiments of this application;

[0028] Figure 5 This is another schematic diagram of the terminal device in the embodiments of this application;

[0029] Figure 6 This is a schematic diagram of another embodiment of the terminal device in this application. Detailed Implementation

[0030] This application provides a method, terminal device, and storage medium for continuously eliminating list SCL decoding, which saves most of the area resources occupied by Lazy Copy and meets the requirements of high workload frequency.

[0031] To enable those skilled in the art to better understand the present application, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All embodiments based on the present application should fall within the scope of protection of the present application.

[0032] The following is a brief explanation of the terminology used in this application:

[0033] Polar codes are a forward error correction coding scheme used for signal transmission. The core of their construction is channel polarization. On the coding side, methods are employed to make each sub-channel exhibit different reliability. As the code length continuously increases, some channels tend towards a perfect channel (error-free) with a capacity close to 1, while others tend towards a pure noise channel with a capacity close to 0. Directly transmitting information on channels with a capacity close to 1 to approximate the channel capacity is the only method that can be rigorously proven to reach the Shannon limit. On the decoding side, the polarized channels can be decoded using a simple successive interference cancellation method, achieving performance similar to maximum likelihood decoding with lower complexity.

[0034] Polar codes are a linear channel coding method based on channel polarization theory. This codeword is the only known coding method to date that can reach the Shannon limit and has low encoding / decoding complexity; when the code length is N, the complexity is O(NlogN). The theoretical basis of Polar codes is channel polarization, which includes channel combination and channel decomposition. When the number of combined channels approaches infinity, polarization occurs: some channels tend to become noiseless, while others tend to become noisy. This phenomenon is called channel polarization. The transmission rate of a noiseless channel will reach the channel capacity I(W), while the transmission rate of a noisy channel tends to zero. The Polar code coding strategy utilizes this characteristic, using noiseless channels to transmit useful information and noisy channels to transmit agreed-upon information or no information at all.

[0035] In 5G wireless communication systems, Polar codes are chosen as the encoding scheme for control information in New Radio (NR) and for broadcast information carried by physical broadcast channels due to their excellent coding performance and simple decoding algorithm. This allows for higher data rates, energy efficiency, and spectral efficiency in practical terminal applications. In real-world systems, most manufacturers and research institutions employ Successive Cancellation List (SCL) decoding algorithms to achieve strong error correction capabilities and decoding performance.

[0036] The choice of the number of decoder lists is determined by the bit error rate requirements of the application scenario. A specific decoder list size (e.g., L = 2, 4, 8, 16, etc.) is used to trade off performance and complexity, because SCL decoding evolved from Successive Cancellation (SC), and the logic for calculating the F&G function and return partial sums in the deep binary tree is consistent. During SC decoding, many Loglikelihood Ratio (LLR) quantization values ​​and partial sum return values ​​are generated. These values ​​are crucial intermediate variables in the decoding process, requiring significant storage resources to cache them during decoding iterations. When the number of decoder lists in SCL is 1, SCL decoding is equivalent to SC decoding. However, when the number of decoder lists exceeds 1, the number of intermediate variables in the decoding iterations increases exponentially. For example, if the number of decoder lists is 4, the decoder's storage resources increase fourfold, and these intermediate variables are pruned and replaced. If registers are used as storage resources, the design complexity of replacement between different decoder lists is relatively small, but the chip area will increase exponentially. Compared to using Static Random-Access Memory (SRAM) as storage resources, the design complexity of replacement between different decoder lists will increase slightly. For the replacement technique implementation in SCL, most designs are based on the sorting result of each iteration being calculated and updated by a multiplexer (MUX), then stored in the corresponding pointer register, and finally the corresponding value is selected according to the level of the binary tree. This replacement structure introduces a large number of MUXs. As the codeword length and the number of decoder lists increase, the area of ​​these MUXs will increase rapidly, and the original timing will be degraded.

[0037] To optimize area, the intermediate LLR variables of each decoder list in the SCL decoder are stored using SRAM, such as... Figure 1AThe image shown is a schematic diagram of a depth binary tree for Polar code decoding. Figure 1A In the diagram, [a0, a1, a2, ..., a7] represent LLR variables, [u0, u1, u2, ..., u7] represent partial sum variables, leaf nodes 0, 1, 2, and 3 are information bit nodes, and 4 is a frozen bit node. When the depth-first binary tree calculates to a leaf node (the node at the bottom level of the binary tree), if the node is not a frozen bit node but an information bit node, then based on the cumulative sorting result of the path metric values ​​of each decode list, the decode list will undergo replacement and pruning.

[0038] The forward left branch message is the F function: outputf = sign(LLR(a)) * sign(LLR(b)) * min(|LLR(a), LLR(b)|);

[0039] The forward right branch message is the G function: outputg = (-1)u^*LLR(a) + LLR(b);

[0040] LLR(a) is the likelihood ratio of signal a, LLR(b) is the likelihood ratio of signal b, sign(LLR(a)) is the sign of LLR(a), sign(LLR(b)) is the sign of LLR(b), min is the minimum value, and u^ represents the return value of the partial sum of the G function.

[0041] Assuming the SCL decoder has 4 decoding lists, after decoding a certain information bit node, such as... Figure 1B The diagram illustrates the replacement of a decoding list. Decoding list 2 is replaced by decoding list 0. At this point, the intermediate LLR variable stored in decoding list 2 is replaced by the intermediate LLR variable in decoding list 0. Since SRAM is used to store the intermediate LLR variable, using a read-write method to replace it would incur a significant latency penalty, making the decoding performance unacceptable. From the perspective of binary tree traversal calculation, calculating the LLR input to each level of the F&G function is the result of the previous level. Therefore, a scheme can be used to replace the intermediate LLR variable by changing the SRAM address via a pointer, such as... Figure 1C The diagram illustrates a method for replacing the decoder list using Lazy Copy. This method of replacing the LLR using pointers is called Lazy Copy.

[0042] The design architecture for generating pointers in the SCL decoder directly determines the timing and area performance of the decode list replacement. In other words, the efficiency and energy consumption of Lazy Copy are crucial for decode list replacement. In most current designs, the LazyCopy pointer architecture uses a traditional register set combined with a MUX. Each intermediate layer of the deep binary tree has a set of registers to store the pointers for that layer, and each set has L registers (the maximum value is set for the decode list). When a certain information bit node is decoded and sorted, the pointer values ​​in the register set are updated. When the deep binary tree traverses to an intermediate layer to calculate the F&G function, Lazy Copy outputs the corresponding set of pointer registers, such as... Figure 1D The diagram illustrates a traditional Lazy Copy architecture. For example, when the codeword length is 8 and the number of decoder lists is 4, the Lazy Copy structure has two sets of registers corresponding to the first and second levels of the depth-first binary tree. Each set contains four pointer registers corresponding to the number of decoder lists. Each register has 2 bits as a pointer to indicate the SRAM address for reading different decoder lists. Before each pointer register are L*log2(L) MUXs. The Lazy Copy interface for selecting the output pointer register set has (n-1)*L*log2(L) MUXs, where n-1 is the number of levels in the depth-first binary tree. Figure 1D In the diagram, log2(L)bit represents the bit of the register, and FF represents the flip-flop, which is a type of register.

[0043] As the number of decoder lists increases and the codeword length increases, a large number of MUXs will degrade the decoder's timing and introduce an increase in area. When the number of decoder lists increases to 16 and the codeword length becomes 2... 16 At that time, the number of MUXs will become 16384, including those containing Figure 1D Each update of the MUX in the pointer register group and the MUX in the output pointer register group interface, along with numerous MUX logic selections, increases the computation delay, forcing the SCL decoder's main clock frequency to decrease, directly and adversely affecting the SCL decoder's performance.

[0044] To address the low efficiency of Lazy Copy in SCL decoders as code length and decoder list size increase, this application provides a high-efficiency replacement technique. This replacement architecture also uses a register set and MUX, but through optimization, it significantly reduces the number of MUXs, achieving a codeword length of 2 under the same conditions. 16 With a decoder list size of 16, the number of MUXs is reduced to 1024. From... Figure 1DAnalysis of the structure reveals that traditional Lazy Copy mainly consists of two MUXs. The first part involves selecting different levels of pointer register groups during the deep binary tree traversal. The second part involves updating the corresponding pointer registers through a set of MUXs after each information node completes decoding.

[0045] In the embodiments of this application, the terminal device can be deployed on land, including indoor or outdoor, handheld, wearable or vehicle-mounted; it can also be deployed on water (such as ships); and it can also be deployed in the air (such as airplanes, balloons and satellites).

[0046] In the embodiments of this application, the terminal device may be a mobile phone, a tablet computer, a computer with wireless transceiver capabilities, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal device in industrial control, a wireless terminal device in self-driving, a wireless terminal device in remote medical care, a wireless terminal device in a smart grid, a wireless terminal device in transportation safety, a wireless terminal device in a smart city, or a wireless terminal device in a smart home, etc.

[0047] By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those with comprehensive functions, large size, and the ability to achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0048] The technical solution of this application will be further described below by way of embodiments, such as... Figure 2The diagram shown is an embodiment of the method for decoding the continuous elimination list (SCL) in this application, applied to a terminal device. The terminal device includes multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers. The method is characterized by including:

[0049] 201. The corresponding binary tree level pointer is recorded through the pointer register group corresponding to each level of the depth binary tree. The binary tree level pointer is obtained by shifting.

[0050] It should be noted that the number of pointer register sets is the same as the number of levels in the depth binary tree.

[0051] Optionally, the binary tree level pointers recorded in the plurality of pointer register groups are used to point to the channel likelihood ratio (LLR) variable and the partial return variable.

[0052] Optionally, the number of registers in each group is L, where L is the maximum value of the set decode list, and L is an integer greater than 0.

[0053] Optionally, the hierarchical jumps of the binary tree correspond to the number of decoding nodes.

[0054] Optionally, the terminal device records the corresponding binary tree level pointer through the pointer register group corresponding to each level of the deep binary tree. This may include: the terminal device using a shift method to record the corresponding binary tree level pointer through the pointer register group corresponding to each level of the deep binary tree.

[0055] It's understandable that the pointer register in the pointer register group is a shift register. In digital circuits, a shift register is a flip-flop-based device that operates under several identical time pulses. Data is input into the device in parallel or serial mode, and then shifts one bit to the left or right sequentially with each time pulse, outputting the result at the output terminal. This type of shift register is one-dimensional. In fact, there are also multi-dimensional shift registers, where the input and output data themselves are sequences of bits. One way to implement such a multi-dimensional shift register is to connect several shift registers with the same number of bits in parallel.

[0056] like Figure 3A The image shown is a schematic diagram illustrating a convenient Lazy Copy implementation in an embodiment of this application. Figure 3A As shown, shift register technology is used to... Figure 1D The first part of MUX mentioned above has been optimized. Analysis of the algorithm for depth-first traversal of the binary tree in the SCL decoder reveals a clear correspondence between the level jumps in the binary tree and the number of decoder nodes; the number of nodes with a counter of 0 from right to left determines the level of the binary tree jump.

[0057] For example, with a codeword length of 8 and a decoding list of 4, when the decoding node count is 1, 3, 5, 7, the binary tree jumps to level 1; when the decoding node count is 2, 6, it jumps to level 2; and when the decoding node count is 4, it jumps to level 3. After a node is decoded, the pointer register set shifts one group to the left. When the binary tree updates an intermediate level from top to bottom, the pointer register set shifts to the right with the initial pointer register value. This ensures the correct correspondence of LLR data in each decoding list. For example, when the binary tree calculation is passed from level 2 to level 1, and the pointers in level 2 are 0, 0, 1, 0, then the pointers shifted in from level 1 will become 0, 1, 2, 3. This is because the LLR value read from the computation layer may be stored in other decoding lists, but the storage layer of the output calculation result must be the level corresponding to that decoding list.

[0058] For example, such as Figure 3B The diagram shown is a schematic of the corresponding binary tree level pointer recorded in an embodiment of this application. For example, there are two sets of pointer registers, corresponding to the middle levels 1 and 2 of the depth binary tree, respectively. Each set has L = 4 pointer registers. When decoding begins, the initial value of the pointer register set is [0, 1, 2, 3]. After decoding the first information bit node (decoding node 0), the sort result is [0, 1, 0, 3] (the sort result is [0 10 3]). According to the MUX calculation, the registers for both sets of pointers will be updated to [0, 1, 0, 3]. Then the binary tree will jump to the first level, and the Lazy Copy will shift left out of the first set of pointer registers [0, 1, 0, 3] (left shift pointer to stage 1). Next, the second information bit node (decoding node 1) will be decoded, and the sort result is [0, 0, 1, 2] (the sort result is [0 0 1 2]). According to the MUX calculation, the registers for the second set of pointers will be updated to [0, 0, 1, 0] (the second pointer changes to [0 0 1 0]). The binary tree will jump to the second level, and the Lazy Copy will shift left out of the second set of pointer registers [0, 0, 1, 0] (left shift pointer to stage 2). At this point, the binary tree will calculate from the second level back to the first level. Copy right-shifts the default pointer value from stage 2 to stage 1.

[0059] 202. The set of status registers records the sorting index of the decoding list after each information node has been decoded.

[0060] Understandably, for Figure 1D The second part of the MUX mentioned above is optimized by introducing a set of pointer status registers. The status registers record the sorted index of the decoding list after each information node is decoded, while the pointer register set still stores the corresponding binary tree level pointers. However, it does not need to be updated with the MUX for each decoding; it only needs to be calculated once by the MUX set when the output pointer register is accessed. The sorted list index in this application can be understood as the sorting result.

[0061] Optionally, the method further includes: during the continuous elimination list SCL decoding process, the terminal device obtains L decoding lists, where L is the maximum number of decoding lists and L is an integer greater than 0.

[0062] Optionally, the terminal device obtaining L decoding lists during the continuous elimination list (SCL) decoding process may include: the terminal device obtaining M decoding lists during the continuous elimination list (SCL) decoding process; the terminal device replacing and trimming the M decoding lists according to the path metric value to obtain L decoding lists, where M > L. M are integers greater than 0, and L is the maximum value set for the decoding lists.

[0063] Optionally, the terminal device may replace and trim the M decoding lists according to the path metric value to obtain L decoding lists, which may include: the terminal device selecting the L decoding lists with the smallest path metric value from the M decoding lists.

[0064] Understandably, the terminal device, through the Polar decoder, simultaneously searches several lists and prunes and replaces some of these lists, retaining only the L lists with the best performance. This can significantly improve the performance of Polar codes, making their decoding performance approach maximum likelihood. Assuming the maximum number of decoding lists is set to 8, when the number of decoding lists exceeds 8, the decoding lists can be replaced and pruned based on the path metric value.

[0065] The LLR path metric of the decoding list is an indicator of whether the decoding list has survived. When the actual value and the decision value are the same, the path metric is approximately zero. When the actual value and the decision value are opposite, the path metric is approximately the LLR of that node. The path metric of each list is the cumulative value of the path metrics of each node in the decoding list. The smaller the path metric, the more reliable the decoding list is. The SCL decoder sorts the decoding lists according to the path metric of each decoding list, and then selects the L best decoding lists, that is, the L decoding lists with the smallest path metric values, based on the sorting results.

[0066] 203. Based on the binary tree level pointer and the sorting index of the decoding list, the output pointer register is calculated using the set of MUXs.

[0067] Optionally, the terminal device calculates the output pointer register based on the binary tree level pointer and the decoding list sorting index using the set of MUXs. This may include: when traversing the deep binary tree from top to bottom, the terminal device calculates the output pointer register based on the binary tree level pointer and the decoding list sorting index using the set of MUXs.

[0068] Optionally, the terminal device's calculation of the output pointer register based on the binary tree level pointer and the decoding list sorting index through the set of MUXs may include: the terminal device selecting the pointer corresponding to each index in the decoding list sorting index from the binary tree level pointer through the set of multiplexers to obtain the output pointer register.

[0069] It is understood that the terminal device sequentially selects each index in the sorted index of the decoding list through the set of multiplexers, pointing to the corresponding pointer in the binary tree level pointer, thereby obtaining the output pointer register.

[0070] For example, after the second node is decoded, the depth binary tree will jump to the second level. At this time, the decoding list sorting index in the status register is [0, 0, 1, 2], and the binary tree level pointer in the register to be shifted left is [0, 1, 0, 3]. Then, through a set of selectors, based on the first index in the sorting list being "0", the first pointer in the binary tree level pointer is selected, corresponding to pointer "0". Based on the second index in the sorting list being "0", the first pointer in the binary tree level pointer is selected, corresponding to pointer "0". Based on the third index in the sorting list being "1", the second pointer in the binary tree level pointer is selected, corresponding to pointer "1". Based on the fourth index in the sorting list being "2", the third pointer in the binary tree level pointer is selected, corresponding to pointer "0". Thus, the output pointer register of Lazy Copy is calculated to be [0, 0, 1, 0].

[0071] like Figure 3CThe diagram illustrates the calculation of the output pointer register in an embodiment of this application. For example, the initial values ​​of the two sets of pointer registers are [0, 1, 2, 3]. After decoding the first information bit node (decoding node 0), the value in the state register group is updated to [0, 1, 0, 3]. A set of pointer registers is shifted left and calculated with the state register using a multi-selector (MUX) to obtain the output pointer register [0, 1, 0, 3] to the first level of the binary tree. When calculating the G function at the first level of the binary tree, the pointer register [0, 1, 0, 3] is shifted right into the pointer register group. After decoding the second information bit node (decoding node 1), the value in the state register group is updated to [0, 0, 1, 2] (the state register updates as [0, 0, 1, 2]). 2), a set of pointer registers and state registers are shifted to the left and calculated by a set of multiplexers (MUX) to get the output pointer register [0, 0, 1, 0] to the second level of the binary tree (left shift pointer calculate with state register to get [0 0 10] to stage 2); then the second level of the binary tree performs G function calculation to the first level, and the pointer register is shifted to the right to enter the register initial value [0, 1, 2, 3] (right shift default pointer value from stage 2 to stage 1).

[0072] 204. Obtain the address of the static random access memory (SRAM) based on the output pointer register.

[0073] The terminal device can obtain the address of the static random access memory (SRAM) based on the output pointer register.

[0074] 205. Read the corresponding data according to the address of the SRAM.

[0075] The terminal device reads the corresponding data based on the address in the SRAM. This is the actual value pointed to by the pointer register of the current level.

[0076] It should be noted that steps 204 and 205 are optional.

[0077] Understandably, in SCL decoders, as the code length increases, the number of decoder lists increases, resulting in better decoding performance. However, to balance resources and performance, in practical applications, a maximum number of decoder lists and a maximum code length are set based on algorithm simulation results. Once the number of decoder lists and the code length are determined, different requirements are placed on decoder list replacement techniques. For high-performance consumer electronic devices, the area must be as small as possible, and the performance must be as high as possible. When using traditional replacement techniques, SCL decoders not only cannot meet the requirements of high operating frequencies, but also a large number of MUXs occupy most of the area resources of the Lazy Copy.

[0078] According to the formula ∏(∏(x, p), q)=∏(x, ∏(p, q)) (Formula 1), we can know that... Figure 1D and Figure 3A The design can achieve the same effect. But... Figure 3A In the design, namely the efficient replacement technology in this application, based on current nanotechnology processes, it can meet the operating frequency of 1GHz, for example: for a code length of 2 16 For an SCL decoder with a decoder list of 16, the number of MUXs is reduced to 1 / 16 of the original. The left side of Equation 1 represents... Figure 1D The effect shown requires selection via MUX every time the pointer register group is updated. The right side of Equation 1 represents... Figure 3A As shown, the multi-selector MUX only needs to be selected once.

[0079] In the above formula, x represents the current level of the depth-based binary tree, p represents the value recorded in the status register, q represents the value recorded in the pointer register group (i.e., the LLR variable and the partial return variable it points to), and ∏ represents product. That is, the value recorded in the status register is the decoding list sort index, and the value recorded in the pointer register group is the binary tree level pointer.

[0080] The following is a detailed explanation of Formula 1 above:

[0081]

[0082]

[0083]

[0084]

[0085] in,[*] TLet L represent the transpose, and L represent the decoding list. In summary, we can conclude that ∏(∏(x, p), q) = ∏(x, ∏(p, q)).

[0086] In this embodiment, a pointer register group corresponding to each level of the deep binary tree records the corresponding binary tree level pointer, which is obtained through a shifting method. A set of status registers records the decoding list sorting index after each information node is decoded. Based on the binary tree level pointer and the decoding list sorting index, the output pointer register is calculated using a set of MUXs. Compared to existing technologies that require a corresponding MUX for each pointer register group and a MUX for the output pointer register group interface, this application can calculate the output pointer register using only one MUX and one set of status registers. This saves a significant portion of the Lazy Copy area resources and meets the requirements of high workload and frequency.

[0087] like Figure 4A The diagram shown is a schematic of a device for calculating the pointer register in SCL decoding according to an embodiment of this application. This device is applied to a terminal device, which includes multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers. It may also include:

[0088] The recording module 401 is used to record the corresponding binary tree level pointer through the pointer register group corresponding to each level of the deep binary tree, wherein the binary tree level pointer is obtained by a shift method; and to record the sorting index of the decoding list after the decoding of each information node is completed through the set of status registers.

[0089] The calculation module 402 is used to calculate the output pointer register based on the binary tree level pointer and the decoding list sorting index, through the set of MUXs.

[0090] Optionally, the calculation module 402 is specifically used to calculate the output pointer register based on the binary tree level pointer and the decoding list sorting index, through the set of MUXs, when traversing the depth binary tree from top to bottom.

[0091] Optionally, the calculation module 402 is specifically used to select the pointer corresponding to each index in the sorted index of the decoding list from the binary tree level pointers through the set of multiplexers, and obtain the output pointer register.

[0092] Optionally, the recording module 401 is specifically used to record the corresponding binary tree level pointer by using a shift method for the pointer register group corresponding to each level of the depth binary tree.

[0093] Optional, such as Figure 4BThe diagram shown is another schematic representation of the apparatus for calculating the pointer register in SCL decoding according to an embodiment of this application. It also includes an acquisition module 403;

[0094] The acquisition module 403 is used to acquire the address of the static random access memory (SRAM) according to the output pointer register;

[0095] The calculation module 402 is also used to read the corresponding data according to the address of the SRAM.

[0096] Optionally, the binary tree level pointers recorded in the plurality of pointer register groups are used to point to the channel likelihood ratio (LLR) variable and the partial return variable.

[0097] Optionally, the number of registers in each group is L, where L is the maximum value of the set decoding list, and L is a positive integer.

[0098] like Figure 5 The diagram shown is a schematic diagram of another embodiment of the terminal device in this application, including multiple pointer register groups 501, a set of multiplexers MUX 502, and a set of status registers 503, and may also include:

[0099] A processor 504 coupled with multiple pointer register groups 501, a set of multiplexers MUX 502, and a set of status registers 503;

[0100] The processor 504 is used to record the corresponding binary tree level pointer through the pointer register group corresponding to each level of the deep binary tree, the binary tree level pointer being obtained by a shift method; to record the decoding list sorting index after the decoding of each information node is completed through the set of status registers; and to calculate the output pointer register through the set of MUXs based on the binary tree level pointer and the decoding list sorting index.

[0101] Optionally, the processor 504 is specifically configured to calculate the output pointer register based on the binary tree level pointer and the decoding list sorting index, through the set of MUXs, when traversing the deep binary tree from top to bottom.

[0102] Optionally, the processor 504 is specifically configured to select, from the binary tree level pointers, the pointer corresponding to each index in the sorted index of the decoding list, to obtain the output pointer register.

[0103] Optionally, processor 504 is specifically used to record the corresponding binary tree level pointers by using a shift method for the pointer register group corresponding to each level of the deep binary tree.

[0104] Optionally, the processor 504 is further configured to obtain the address of the static random access memory (SRAM) according to the output pointer register; and read the corresponding data according to the address of the SRAM.

[0105] Optionally, the binary tree level pointers recorded in the plurality of pointer register groups are used to point to the channel likelihood ratio (LLR) variable and the partial return variable.

[0106] Optionally, the number of registers in each group is L, where L is the maximum value of the set decoding list, and L is a positive integer.

[0107] like Figure 6 The diagram shown is a schematic diagram of another embodiment of the terminal device in this application. Figure 6 This is a block diagram illustrating a portion of the structure of a mobile phone related to the terminal device provided in an embodiment of the present invention. (Reference) Figure 6 The mobile phone includes: multiple pointer register groups 601, a multi-selector MUX 602, a status register 603, a radio frequency (RF) circuit 610, a memory 620, an input unit 630, a display unit 640, a sensor 650, an audio circuit 660, a wireless fidelity (Wi-Fi) module 670, a processor 680, and a power supply 690, etc. Those skilled in the art will understand that... Figure 6 The mobile phone structure shown does not constitute a limitation on the mobile phone and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0108] The following is combined Figure 6 A detailed introduction to each component of a mobile phone:

[0109] RF circuit 610 can be used for receiving and transmitting signals during information transmission or calls. Specifically, it receives downlink information from the base station and processes it with processor 680; additionally, it transmits uplink data to the base station. Typically, RF circuit 610 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, RF circuit 610 can also communicate wirelessly with networks and other devices. The aforementioned wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0110] The memory 620 can be used to store software programs and modules. The processor 680 executes various functions and data processing of the mobile phone by running the software programs and modules stored in the memory 620. The memory 620 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 620 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0111] The input unit 630 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the mobile phone. Specifically, the input unit 630 may include a touch panel 631 and other input devices 632. The touch panel 631, also known as a touch screen, can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch panel 631), and drive the corresponding connection devices according to a pre-set program. Optionally, the touch panel 631 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends it to the processor 680, and can also receive and execute commands sent by the processor 680. In addition, the touch panel 631 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 631, the input unit 630 may also include other input devices 632. Specifically, other input devices 632 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons, power buttons, etc.), trackball, mouse, joystick, etc.

[0112] The display unit 640 can be used to display information input by the user or information provided to the user, as well as various menus of the mobile phone. The display unit 640 may include a display panel 641, which may optionally be configured as a Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED), or similar display panel. Further, a touch panel 631 may cover the display panel 641. When the touch panel 631 detects a touch operation on or near it, it transmits the information to the processor 680 to determine the type of touch event. Subsequently, the processor 680 provides corresponding visual output on the display panel 641 based on the type of touch event. Although in Figure 6 In this embodiment, the touch panel 631 and the display panel 641 are two separate components to realize the input and output functions of the mobile phone. However, in some embodiments, the touch panel 631 and the display panel 641 can be integrated to realize the input and output functions of the mobile phone.

[0113] The mobile phone may also include at least one sensor 650, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel 641 according to the ambient light level, and the proximity sensor can turn off the display panel 641 and / or backlight when the phone is moved to the ear. As a type of motion sensor, an accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity, and can be used for applications that recognize the phone's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition-related functions (such as pedometer, taps), etc. Other sensors that may be configured in the mobile phone, such as gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, will not be described in detail here.

[0114] Audio circuit 660, speaker 661, and microphone 662 provide an audio interface between the user and the mobile phone. Audio circuit 660 converts received audio data into electrical signals and transmits them to speaker 661, where speaker 661 converts them into sound signals for output. On the other hand, microphone 662 converts collected sound signals into electrical signals, which are received by audio circuit 660, converted into audio data, and then output to processor 680 for processing. The audio data is then transmitted via RF circuit 610 to, for example, another mobile phone, or output to memory 620 for further processing.

[0115] Wi-Fi is a short-range wireless transmission technology. Through the Wi-Fi module 670, mobile phones can help users send and receive emails, browse web pages, and access streaming media, providing users with wireless broadband internet access. Although Figure 6 Wi-Fi module 670 is shown, but it is understood that it is not an essential component of a mobile phone and can be omitted as needed without changing the essence of the invention.

[0116] The processor 680 is the control center of the mobile phone, connecting various parts of the phone through various interfaces and lines. It performs various functions and processes data by running or executing software programs and / or modules stored in the memory 620, and by calling data stored in the memory 620, thereby providing overall monitoring of the phone. Optionally, the processor 680 may include one or more processing units; preferably, the processor 680 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into the processor 680.

[0117] The mobile phone also includes a power supply 690 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 680 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0118] Although not shown, mobile phones may also include a camera, Bluetooth module, etc., which will not be described in detail here.

[0119] In this embodiment of the invention, the processor 680 is configured to record the corresponding binary tree level pointers through the pointer register group corresponding to each level of the deep binary tree, wherein the binary tree level pointers are obtained by a shift method; record the decoding list sorting index after the decoding of each information node is completed through the set of status registers; and calculate the output pointer register through the set of MUXs based on the binary tree level pointers and the decoding list sorting indexes.

[0120] Optionally, the processor 680 is specifically configured to calculate the output pointer register based on the binary tree level pointer and the decoding list sorting index, through the set of MUXs, when traversing the deep binary tree from top to bottom.

[0121] Optionally, the processor 680 is specifically configured to select, from the binary tree level pointers, the pointer corresponding to each index in the sorted index of the decoding list to obtain the output pointer register.

[0122] Optionally, the processor 680 is used to record the corresponding binary tree level pointers by using a shift method for the pointer register group corresponding to each level of the deep binary tree.

[0123] Optionally, the processor 680 is further configured to obtain the address of the static random access memory (SRAM) according to the output pointer register; and read the corresponding data according to the address of the SRAM.

[0124] Optionally, the binary tree level pointers recorded in the plurality of pointer register groups are used to point to the channel likelihood ratio (LLR) variable and the partial return variable.

[0125] Optionally, the number of registers in each group is L, where L is the maximum value of the set decoding list, and L is a positive integer.

[0126] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0127] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0128] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0129] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0130] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0131] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0132] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for decoding a continuous elimination list (SCL), applied to a terminal device, the terminal device comprising multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers, characterized in that, The method includes: The corresponding binary tree level pointer is recorded through the pointer register group corresponding to each level of the depth binary tree, and the binary tree level pointer is obtained by a shifting method; The set of status registers records the sorting index of the decoding list after each information node has been decoded; The output pointer register is obtained by selecting the pointer corresponding to each index in the sorted index of the decoding list from the binary tree level pointers using the set of multiplexers (MUX).

2. The method according to claim 1, characterized in that, The step of selecting the pointer corresponding to each index in the sorted index of the decoding list from the binary tree level pointers using the set of multiplexers (MUX) to obtain the output pointer register includes: When traversing the depth binary tree from top to bottom, the output pointer register is obtained by selecting the pointer corresponding to each index in the sorted index of the decoding list from the binary tree level pointers through the set of multiplexers (MUX).

3. The method according to claim 1 or 2, characterized in that, The method of recording the corresponding binary tree level pointers through the pointer register group corresponding to each level of the depth-first binary tree includes: For each level of the deep binary tree, a shift method is used to record the corresponding binary tree level pointer.

4. The method according to claim 1 or 2, characterized in that, The method further includes: The address of the static random access memory (SRAM) is obtained from the output pointer register. Read the corresponding data based on the address of the SRAM.

5. The method according to claim 1 or 2, characterized in that, The binary tree level pointers recorded in the multiple pointer register groups are used to point to the channel likelihood ratio (LLR) variable and the partial return variable.

6. The method according to claim 1 or 2, characterized in that, The number of registers in each group is L, where L is the maximum value of the decode list and L is a positive integer.

7. A terminal device, comprising multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers, characterized in that, Also includes: The recording module is used to record the corresponding binary tree level pointer through the pointer register group corresponding to each level of the deep binary tree, and the binary tree level pointer is obtained by shifting; the set of status registers records the sorting index of the decoding list after the decoding of each information node is completed; The calculation module is used to select the pointer corresponding to each index in the sorted index of the decoding list from the binary tree level pointers through the set of multiplexers (MUX) to obtain the output pointer register.

8. A terminal device, comprising multiple pointer register groups, a set of multiplexers (MUX), and a set of status registers, characterized in that, Also includes: Memory containing executable program code; A processor coupled to the memory; The processor is configured to record the corresponding binary tree level pointers through the pointer register group corresponding to each level of the deep binary tree, the binary tree level pointers being obtained through a shifting method; record the decoding list sorting index after each information node is decoded through the set of status registers; and select the pointers corresponding to each index in the decoding list sorting index from the binary tree level pointers through the set of multiplexers (MUX) to obtain the output pointer register.

9. A computer-readable storage medium comprising instructions that, when executed on a processor, cause the processor to perform the method as described in any one of claims 1-6.

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